Fault detection method and apparatus for memory, chip, medium, and program product

Abstract

The present disclosure provides a fault detection method for a memory. The method comprises: generating expected data on the basis of a preset mode, wherein the preset mode represents a test dimension of the memory, and the memory comprises a double data rate synchronous dynamic random access memory DDR subsystem and a dynamic random access memory (DRAM) subsystem; writing the expected data into the DRAM subsystem by means of the DDR subsystem; reading read-back data from the DRAM subsystem; and when the read-back data is not matched with the expected data, determining that the memory has a fault. The present disclosure further provides a fault detection apparatus for a memory, a chip, a computer readable medium, and a computer program product.

Description

Fault detection methods, devices, chips, media, and software products for memory.

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410681480.6, filed on May 28, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to the field of chip technology, and in particular to a method for detecting memory faults, a device for detecting memory faults, a chip, a computer-readable medium, and a computer program product. Background Technology

[0004] The development of automotive electronic systems has transformed vehicles from mere means of transportation into intelligent mobile platforms. With this trend, the stability of automotive electronic data storage has become paramount, profoundly impacting driving safety, vehicle performance monitoring, and the overall driving experience.

[0005] DDR SRAM (Double Data Rate Synchronous Dynamic Random Access Memory) technology (hereinafter referred to as DDR technology) plays a crucial role in vehicle electronic systems. However, DDR systems may face various failures during long-term operation, such as data transmission errors, timing misalignments, memory failures, and signal integrity issues. These failures can lead to performance degradation and data loss in automotive electronic systems, and may even cause the entire automotive electronic system to collapse, seriously affecting the reliability and stability of automotive electronic systems, and impacting vehicle safety, performance, and user experience. Summary of the Invention

[0006] This disclosure provides a method for detecting memory faults, a device for detecting memory faults, a chip, a computer-readable medium, and a computer program product.

[0007] In a first aspect, embodiments of this disclosure provide a method for detecting memory faults, comprising: generating expected data according to a preset mode; wherein the preset mode represents a test dimension of the memory, the memory including a Double Data Rate Synchronous Dynamic Random Access Memory (DDR) subsystem and a Dynamic Random Access Memory (DRAM) subsystem; writing the expected data into the DRAM subsystem through the DDR subsystem; reading back data from the DRAM subsystem; and determining that the memory has failed if the back data and the expected data do not match.

[0008] Secondly, embodiments of this disclosure provide a memory fault detection device, comprising: a test sequence generation module configured to: generate expected data according to a preset mode, wherein the preset mode represents a test dimension of the memory, the memory including a Double Data Rate Synchronous Dynamic Random Access Memory (DDR) subsystem and a Dynamic Random Access Memory (DRAM) subsystem; and write the expected data into the DRAM subsystem through the DDR subsystem; and a data comparison module configured to: read back data from the DRAM subsystem, and determine that the memory has failed if the read back data and the expected data do not match.

[0009] Thirdly, embodiments of this disclosure provide a chip including a memory and a processor; the memory stores a computer program executable by the processor, and when the computer program is executed by the processor, it implements the method described in the first aspect.

[0010] Fourthly, embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements the method described in the first aspect.

[0011] Fifthly, embodiments of this disclosure provide a computer program product comprising a computer program that, when executed by a processor, implements the method described in the first aspect. Attached Figure Description

[0012] In the accompanying drawings of this disclosure:

[0013] Figure 1 is a schematic flowchart of a memory fault detection method according to an embodiment of the present disclosure;

[0014] Figure 2 is a schematic diagram of the structure of a fault detection device for a memory according to an embodiment of the present disclosure;

[0015] Figure 3 is a schematic diagram of a PCB for fault detection of a memory according to Example 1 of this disclosure;

[0016] Figure 4 is a flowchart illustrating a memory fault detection method according to Example 2 of this disclosure;

[0017] Figure 5 is a flowchart illustrating a fault detection method for a memory according to Example 3 of this disclosure;

[0018] Figure 6 is a flowchart illustrating a memory fault detection method according to Example 4 of this disclosure. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions of this disclosure, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0020] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments and examples set forth below. Rather, these embodiments and examples are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0021] The accompanying drawings are provided to further illustrate this disclosure and form part of the specification. They are used together with the embodiments and examples to explain this disclosure and do not constitute a limitation thereof. These and other features and advantages will become more apparent to those skilled in the art from the description of the embodiments and examples with reference to the accompanying drawings.

[0022] This disclosure may be described with reference to plan and / or cross-sectional views using the ideal schematic diagrams of this disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances.

[0023] Where there is no conflict, the various embodiments / examples and features in the embodiments / examples of this disclosure may be combined with each other.

[0024] The terminology used in this disclosure is for describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising" or "including" as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0025] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0026] DDR technology is widely used in vehicle electronic systems. These systems can include infotainment systems, driver assistance systems, engine or motor control modules, vehicle communication networks, and software update and maintenance modules. Infotainment systems, such as those providing audio, video, and navigation, require the storage or caching of data from these functions. Driver assistance systems include various sensors and devices for perception processing, decision-making algorithms, data processing, and data communication, requiring extensive real-time processing and analysis of sensor, algorithm, and communication data. Engine or motor control modules in vehicle electronic systems are used for engine control, motor control, and vehicle performance optimization. Vehicle communication networks include Controller Area Networks (CAN) and Ethernet. Software update and maintenance modules are used for periodic software updates in vehicle electronic systems to improve software performance and fix vulnerabilities. DDR technology and DDR systems can be used in many or all of these electronic systems for long-term or temporary data storage.

[0027] During prolonged operation of vehicle electronic systems, DDR systems may encounter various malfunctions, significantly impacting the safety, stability, and reliability of these systems. The safety of the vehicle's electronic systems directly affects overall vehicle safety; any safety-related malfunction can render the driver unable to effectively control the vehicle, increasing the risk of accidents. The stability of the electronic systems impacts overall vehicle performance; poor stability, such as system crashes, freezes, or errors, reduces data processing efficiency and response speed. The reliability of the electronic systems affects the user experience; frequent malfunctions or instability prevent users from flexibly using various vehicle functions, such as navigation, entertainment, and communication, leading to a poor user experience and reduced product satisfaction. Therefore, fault detection and localization of the DDR system within vehicle electronic systems are essential.

[0028] In some related technologies, memory testing tools are used to detect whether the DDR system in the vehicle's electronic system is faulty. This fault detection method not only requires a lot of testing resources in the vehicle's electronic system, but also has limited testing coverage. In addition, it often takes a lot of time to detect faults.

[0029] In other related technologies, hardware testing and analysis tools (such as logic analyzers and oscilloscopes) are used to locate and diagnose faults in the DDR system of vehicle electronic systems. However, this method of fault location usually has various limitations, such as the need to reserve signal measurement points and the inability to measure transient faults.

[0030] In addition, this fault detection method cannot effectively detect latent faults in vehicles, nor can it detect transient single-point or multi-point faults during vehicle operation.

[0031] In view of this, in a first aspect, embodiments of the present disclosure provide a method for detecting faults in a memory, the method comprising the steps S1 to S4.

[0032] In step S1, expected data is generated according to a preset mode, wherein the preset mode represents the test dimension of the memory, and the memory includes a Double Data Rate Synchronous Dynamic Random Access Memory (DDR) subsystem and a Dynamic Random Access Memory (DRAM) subsystem.

[0033] In step S2, the expected data is written to the DRAM subsystem through the DDR subsystem.

[0034] In step S3, readback data is read from the DRAM subsystem.

[0035] In step S4, if the readback data and the expected data do not match, it is determined that the memory has failed.

[0036] As described above, the preset mode represents the testing dimension of the memory. In some embodiments, the preset mode includes a data mode (Data_mode) and a command mode (Cmd_mode), where the command mode refers to the permutation and combination of different read and write null commands; the data mode is linear, pseudo-random, or other predefined patterns.

[0037] The expected data generated according to the preset mode can be used to conduct targeted tests on the memory according to the test dimensions. The test results can reflect whether the memory has a fault in that test dimension. The DDR subsystem is responsible for ensuring data transmission between the chip and the DRAM subsystem. Therefore, reading and writing expected data in the DRAM subsystem through the DDR subsystem, and then comparing whether the expected data and the read-back data match, can quickly diagnose memory faults, improve memory reliability and maintenance efficiency, and reduce labor costs and time consumption.

[0038] It is worth noting that the present disclosure does not impose special limitations on the application scenarios of the memory fault detection method. For example, as described below, it can be applied during the startup, shutdown, or operation of the vehicle system to detect latent faults as well as transient single-point and multi-point faults.

[0039] The embodiments disclosed herein do not impose any special restrictions on the type of memory. It may be a DDR subsystem, a DRAM subsystem, or other types of memory and combinations thereof.

[0040] Furthermore, it is worth noting that the process of writing expected data to the DRAM subsystem via the DDR subsystem and reading back data from the DRAM subsystem can either cover the entire storable address space of the memory to achieve comprehensive memory detection, or it can cover only a portion of the storable address space of the memory to achieve partial memory detection; this disclosure is not limited to this. For example, in the case of periodically performing fault detection during the operation of the vehicle infotainment system, since some memory address space may be occupied during operation, the process of writing data from the DDR subsystem to the DRAM subsystem and reading back data from the DRAM subsystem can cover the unoccupied storable address space in the memory to avoid affecting the vehicle infotainment system.

[0041] In some embodiments, the testing dimensions of the memory include at least one of the following: the DDR subsystem, the DRAM subsystem, and the pathway between the DDR subsystem and the DRAM subsystem.

[0042] As one embodiment of this disclosure, for the test dimension being the DDR subsystem, the expected mode of the test dimension can be used to test whether the DDR subsystem can correctly read back data and write expected data at the correct timing when the parameters are at critical values, i.e., to test whether the Training value is critical; the expected mode can also be used to test whether the JESD timing meets the expected standard.

[0043] As another embodiment of this disclosure, for the DRAM subsystem as the test dimension, the expected mode can be used to detect whether there are faults such as bad line, bad cell, address errors and data corruption inside the DRAM memory.

[0044] As another embodiment of this disclosure, for the test dimension being the path between the DDR subsystem and the DRAM subsystem, the expected mode can be used to detect whether there is an impedance continuity problem between the chip, the DDR subsystem and the DRAM subsystem, and can also be used to detect whether there is an open circuit or short circuit problem in the path between the chip, the DDR subsystem and the DRAM subsystem.

[0045] The fault detection triggering method of the memory in this embodiment can be applied to various application scenarios, such as power-on / off detection mode, periodic detection mode, and fault location mode.

[0046] In some embodiments, step S1 includes: upon receiving a power-on command and / or a power-off command, generating expected data according to a preset mode.

[0047] In this embodiment, the power-on command can refer to the vehicle's infotainment system startup command, and the power-off command can refer to the vehicle's infotainment system shutdown command. Performing memory fault detection during vehicle startup and shutdown can detect latent faults.

[0048] In some embodiments, step S1 includes: determining the current period count value; and generating expected data according to a preset mode when the current period count value reaches a preset count threshold.

[0049] By comparing the current cycle count value with the preset count threshold, periodic fault detection can be achieved when the vehicle system is running. This can be used to detect transient single-point and multi-point faults in the memory.

[0050] As one embodiment of this disclosure, expected data is generated during the vehicle's startup and shutdown process to detect memory faults. When the vehicle is in the startup state, memory fault detection is performed according to a preset cycle, and the frequency of vehicle failures within a certain period of time is statistically analyzed to determine whether the vehicle meets the requirements of FTTI (Frequency of Time to Failure Interval).

[0051] In some embodiments, step S1 includes: generating expected data according to a preset mode when the chip to which the memory belongs is in a fault location mode.

[0052] The fault location mode is applicable to offline scenarios such as maintenance: first, the memory is tested for faults, and then the fault is located if a fault is detected in the memory.

[0053] Since fault location often consumes a lot of resources, in some embodiments, it may be difficult to achieve online fault location in online scenarios (such as receiving power-on and / or power-off commands, or periodically performing memory fault detection). When a memory fault is detected, fault reporting can be performed without fault location, thereby reducing the problem of high resource consumption caused by fault detection during vehicle system operation and improving user experience.

[0054] In some embodiments, if the readback data and the expected data do not match, the method further includes: storing the readback data that does not match the expected data and its corresponding storage address and the expected data.

[0055] In cases where a memory failure is confirmed, the readback data that does not match the expected data, the expected data, and the storage address of the readback data are recorded and saved; this is known as fault logging. This fault log can be used for subsequent analysis and location of the cause of the memory failure.

[0056] This disclosure does not impose special restrictions on the content stored when the readback data and the expected data do not match, and can also record and store expected patterns, fault detection times, etc.

[0057] In some embodiments, since there is an upper limit to the capacity of the readback data with storage errors and its corresponding storage address compared with the expected data, the method may further include: comparing the total number of readback data and expected data mismatches with a preset number to effectively prevent excessive error accumulation from affecting system performance, ensuring timely error detection and correction, thereby maintaining the reliability of the storage system.

[0058] In some embodiments, the method further includes: determining the cause and / or type of the memory failure based on the readback data and the storage address.

[0059] In this embodiment of the disclosure, the cause, type, and location of the memory failure can be determined by analyzing the readback data and storage address, which helps to repair and report the failure online, thereby improving the efficiency of fault repair.

[0060] In the memory fault detection method disclosed in the above embodiments of this disclosure, expected data is read and written in the DRAM subsystem through the DDR subsystem, and then the expected data and readback data are compared to see if they match. This allows for rapid diagnosis of memory faults. Recording and analyzing the faults effectively improves the efficiency of memory maintenance. The memory detection process does not rely on manual labor, effectively reducing labor costs and time consumption. Furthermore, the above fault detection method can be applied in various application scenarios (e.g., during the startup, shutdown, or operation of an in-vehicle infotainment system), enabling the detection of latent faults and transient single-point and multi-point faults in the memory of the in-vehicle infotainment system.

[0061] As shown in Figure 2, in a second aspect, embodiments of this disclosure provide a memory fault detection device 300, which includes a test sequence generation module 201 and a data comparison module 202.

[0062] The test sequence generation module 201 is configured to: generate expected data according to a preset mode, wherein the preset mode represents the test dimension of the memory, the memory includes a Double Data Rate Synchronous Dynamic Random Access Memory (DDR) subsystem and a Dynamic Random Access Memory (DRAM) subsystem; and write the expected data into the DRAM subsystem through the DDR subsystem.

[0063] The data comparison module 202 is configured to read back data from the DRAM subsystem and determine that the memory has failed if the back data and the expected data do not match.

[0064] It should be noted that this device is the same as the fault detection method for the memory described above. All implementations in the above method embodiments are applicable to the embodiments of this device and can achieve the same technical effect.

[0065] Thirdly, embodiments of this disclosure provide a chip including a memory and a processor; the memory stores a computer program executable by the processor, and when the computer program is executed by the processor, it implements any memory fault detection method of embodiments of this disclosure.

[0066] Fourthly, embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any memory fault detection method of embodiments of this disclosure.

[0067] Fifthly, embodiments of this disclosure provide a computer program product comprising a computer program that, when executed by a processor, implements any one of the memory fault detection methods of embodiments of this disclosure.

[0068] To enable those skilled in the art to more clearly understand the technical solutions provided by the embodiments of this disclosure, the technical solutions provided by the embodiments of this disclosure will be described in detail below through specific embodiments:

[0069] Example 1:

[0070] As an example, as a specific embodiment of this disclosure, referring to FIG3, a chip ASIC (Application Specific Integrated Circuit) is disposed on the PCB (Printed Circuit Board), and a DRAM subsystem is also disposed on the PCB. The ASIC includes a configuration module CGF (Configuration), a self-check module, and a DDR subsystem. The self-check module includes a data comparator, an error data storage unit, and a test sequence generator. The DDR subsystem is responsible for ensuring data transmission between the self-check module and the DRAM subsystem.

[0071] The configuration module is used to configure and view key parameters in the self-test module, such as setting preset modes, customizing test sequences, and viewing error messages.

[0072] The test sequence generator of the self-test module generates test sequences and comparison data (i.e., expected data) according to a preset pattern. It writes the comparison data to the DRAM subsystem via the DDR subsystem and transmits the comparison data to the data comparator. The data comparator reads readback data from the DRAM subsystem via the DDR subsystem and then matches the readback data with the expected data. If the readback data and the comparison data differ, it identifies potential faults in the memory. The error data storage unit in the self-test module can store the error address, expected data, and erroneous readback data corresponding to the fault.

[0073] When this PCB is applied to an in-vehicle infotainment system, it can provide support for the safety, reliability, and stability of the vehicle in various aspects such as vehicle operation, maintenance, and remote monitoring.

[0074] During vehicle operation, the PCB can detect and diagnose faults in the vehicle's memory, detect latent faults when the vehicle starts and stops, periodically detect and diagnose faults in the vehicle's memory while the vehicle is running, detect whether there are transient faults in the vehicle, and promptly issue an alarm to the driver when a fault is found, ensuring vehicle safety.

[0075] During vehicle maintenance, this PCB can help maintenance personnel quickly and accurately detect and locate memory faults. It can also further analyze information such as the cause and type of the fault, providing accurate diagnostic results and thus quickly generating accurate repair plans for rapid vehicle repair.

[0076] During remote vehicle monitoring, this PCB enables remote monitoring and maintenance of the vehicle. By uploading the detection results to the cloud platform through the vehicle communication system, the vehicle's operating status can be remotely monitored. When a vehicle malfunction is detected, remote diagnosis and maintenance can be performed to reduce vehicle repair time and costs.

[0077] Example 2:

[0078] For example, as a specific form of the embodiment of this disclosure, referring to FIG4, the PCB of Example 1 is applied to the vehicle infotainment system to detect whether the memory is faulty when the vehicle is powered on or off. The detection process includes the following steps 401 to 4011.

[0079] In step 401, the configuration module is set to power-on / off test mode.

[0080] In step 402, upon receiving a power-on or power-off command, the configuration module generates parameters such as a preset mode and test clock frequency for the self-test module. The configuration module then sends these parameters to the self-test module.

[0081] In step 403, the test sequence generator in the self-test module generates the expected data according to a preset mode.

[0082] In step 404, the test sequence generator in the self-test module writes the expected data into the DRAM subsystem through the DDR subsystem, and the data comparator in the self-test module reads the readback data corresponding to the expected data from the DRAM subsystem through the DDR subsystem.

[0083] In step 405, the data comparator in the self-test module matches the readback data of the DRAM subsystem read from the DDR subsystem with the expected data obtained from the test sequence generator. If the readback data does not match the expected data, step 406 is executed. If the readback data matches the expected data, step 408 is executed.

[0084] In step 406, if the readback data does not match the expected data, it indicates an anomaly. The error data storage unit in the self-test module stores the mismatched readback data, the error address corresponding to the readback data, and the expected data corresponding to the readback data. The stored data (i.e., the mismatched readback data, the error address corresponding to the readback data, and the expected data corresponding to the readback data) can be used to determine the fault type, fault location, fault cause, etc., which helps to further adjust and repair the faulty memory, thereby improving the reliability, safety, and user experience of the vehicle.

[0085] In step 407, the data comparator determines whether the number of errors where the readback data does not match the expected data has reached a preset number. This preset number refers to the upper limit of errors that can occur under this preset mode. If the number of errors reaches the preset number, step 409 is executed; if the number of errors does not reach the preset number, step 403 is executed, that is, the fault test continues using the expected data.

[0086] In step 408, the self-test module determines whether all expected data has been transmitted from the DDR subsystem to the DRAM subsystem. If all expected data has been transmitted, step 409 is executed; otherwise, step 403 is executed, i.e., the fault test continues to be performed using the expected data.

[0087] In step 409, all expected data is transmitted from the DDR subsystem to the DRAM subsystem, and the test is completed for the test dimensions corresponding to the preset mode.

[0088] In step 4010, it is determined whether the test of all preset modes has been completed. If the test of all preset modes has been completed, step 4011 is executed; otherwise, step 403 is executed, that is, the fault test is continued using the expected data.

[0089] In step 4011, the test results are generated.

[0090] The testing process described above in this example allows for the rapid and accurate detection of potential malfunctions during vehicle startup and shutdown.

[0091] Example 3:

[0092] For example, as a specific form of the embodiment of this disclosure, referring to FIG5, the PCB of Example 1 is applied to the vehicle infotainment system to perform periodic memory fault detection during vehicle operation. The detection process includes the following steps 501 to 5013.

[0093] In step 501, the configuration module is set to periodic test mode.

[0094] In step 502, it is determined whether the periodic timer has reached the preset counting threshold. If the periodic timer has reached the preset counting threshold, step 503 is executed. If the periodic timer has not reached the preset counting threshold, step 502 is repeated.

[0095] In step 503, when the periodic timer reaches a preset counting threshold, the configuration module generates parameters such as a preset mode and test clock frequency for the self-test module. The configuration module then sends these parameters to the self-test module.

[0096] In step 504, the test sequence generator in the self-test module generates the expected data according to a preset mode.

[0097] In step 505, the test sequence generator in the self-test module writes the expected data into the DRAM subsystem through the DDR subsystem, and the data comparator in the self-test module reads the readback data corresponding to the expected data from the DRAM subsystem through the DDR subsystem.

[0098] In step 506, the data comparator in the self-test module matches the readback data of the DRAM subsystem read from the DDR subsystem with the expected data obtained from the test sequence generator. If the readback data does not match the expected data, step 509 is executed. If the readback data matches the expected data, step 507 is executed.

[0099] In step 507, it is determined whether all expected data has been transmitted from the DDR subsystem to the DRAM subsystem. If all expected data has been transmitted, step 508 is executed; otherwise, step 504 is executed, i.e., the fault test continues to be performed using the expected data.

[0100] In step 508, after all expected data is transmitted from the DDR subsystem to the DRAM subsystem, the test is completed for the test dimension corresponding to the preset mode, and then step 5011 is executed.

[0101] In step 509, if the readback data does not match the expected data, it indicates an anomaly. The error data storage unit in the self-test module stores the mismatched readback data, the error address corresponding to the readback data, and the expected data corresponding to the readback data. The stored data (i.e., the mismatched readback data, the error address corresponding to the readback data, and the expected data corresponding to the readback data) can be used to determine the fault type, fault location, fault cause, etc., which helps to further adjust and repair the faulty memory, thereby improving the reliability, safety, and user experience of the vehicle.

[0102] In step 5010, the data comparator determines whether the number of errors where the readback data does not match the expected data has reached a preset number. This preset number refers to the upper limit of errors that can occur under this preset mode. If the number of errors reaches the preset number, step 508 is executed; if the number of errors does not reach the preset number, step 504 is executed, that is, the fault test continues using the expected data.

[0103] In step 5011, it is determined whether the test of all preset modes has been completed. If the test of all preset modes has been completed, step 5012 is executed; otherwise, step 504 is executed, that is, the fault test is continued using the expected data.

[0104] In step 5012, the test results are generated.

[0105] In step 5013, the counter is cleared, and step 502 is repeated.

[0106] The testing process described above in this example allows for the periodic detection of transient single-point and multi-point faults during vehicle operation.

[0107] Example 4:

[0108] For example, as a specific form of the embodiment of this disclosure, referring to FIG6, the PCB of Example 1 is applied to the vehicle infotainment system to perform fault detection during vehicle maintenance. The detection process includes the following steps 601 to 6013.

[0109] In step 601, the configuration module is set to fault location mode.

[0110] In step 602, the configuration module generates preset modes, test clock frequencies, and other parameters for the self-test module. The configuration module then sends these parameters to the self-test module.

[0111] In step 603, the test sequence generator in the self-test module generates the expected data according to a preset mode.

[0112] In step 604, the test sequence generator in the self-test module writes the expected data into the DRAM subsystem through the DDR subsystem, and the data comparator in the self-test module reads the readback data corresponding to the expected data from the DRAM subsystem through the DDR subsystem.

[0113] In step 605, the data comparator in the self-test module matches the readback data of the DRAM subsystem read from the DDR subsystem with the expected data obtained from the test sequence generator. If the readback data does not match the expected data, step 608 is executed. If the readback data matches the expected data, step 606 is executed.

[0114] In step 606, it is determined whether all expected data has been transmitted from the DDR subsystem to the DRAM subsystem. If all expected data has been transmitted, step 607 is executed; otherwise, step 603 is executed, i.e., the fault test continues to be performed using the expected data.

[0115] In step 607, after all expected data is transmitted from the DDR subsystem to the DRAM subsystem, the test is completed for the test dimensions corresponding to the preset mode, and then step 6010 is executed.

[0116] In step 608, if the readback data does not match the expected data, it indicates an anomaly. The error data storage unit in the self-test module stores the mismatched readback data, the error address corresponding to the readback data, and the expected data corresponding to the readback data. The stored data (i.e., the mismatched readback data, the error address corresponding to the readback data, and the expected data corresponding to the readback data) can be used to determine the fault type, fault location, fault cause, etc., which helps to further adjust and repair the faulty memory, thereby improving the reliability, safety, and user experience of the vehicle.

[0117] In step 609, the data comparator determines whether the number of errors where the readback data does not match the expected data has reached a preset number. This preset number refers to the upper limit of errors that can occur under this preset mode. If the number of errors reaches the preset number, step 607 is executed; if the number of errors does not reach the preset number, step 603 is executed, that is, the fault test continues using the expected data.

[0118] In step 6010, it is determined whether the test of all preset modes has been completed. If the test of all preset modes has been completed, step 6011 is executed; otherwise, step 603 is executed, that is, the fault test is continued using the expected data.

[0119] In step 6011, the test results are generated.

[0120] In step 6012, the test results are analyzed to determine the cause, location, and type of the fault, and a fault analysis result is generated. It is then determined whether the fault analysis is complete. If the analysis is complete, the memory test is terminated. If the fault analysis is not complete, step 6013 is executed.

[0121] In step 6013, based on the fault analysis results, the preset test mode and test timing parameters are adjusted, and step 602 is re-executed, i.e., the test is re-tested.

[0122] The testing process described in this example enables rapid identification and location of memory faults during vehicle maintenance and inspection, reducing labor costs and time consumption. Furthermore, storing mismatched readback data, the corresponding error addresses, and the expected data when a fault occurs helps provide diagnostic results and repair suggestions during maintenance, allowing technicians to perform timely repairs and improving efficiency.

[0123] In this disclosure, the processor is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read-write interface) is connected between the processor and the memory, enabling information exchange between the memory and the processor, including but not limited to a data bus (Bus).

[0124] Those skilled in the art will understand that all or some of the steps, systems, and devices disclosed above, as functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0125] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0126] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technique for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only optical disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cartridges, magnetic tapes, disk storage or other magnetic storage; and any other media that can be used to store desired information and can be accessed by a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0127] This disclosure has disclosed exemplary embodiments, and although specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A method for detecting a fault of a memory, comprising: generating expected data according to a preset pattern, wherein the preset pattern represents a test dimension of the memory, and the memory comprises a double data rate synchronous dynamic random access memory (DDR) subsystem and a dynamic random access memory (DRAM) subsystem; writing the expected data to the DRAM subsystem through the DDR subsystem; reading back read data from the DRAM subsystem; and determining that a fault of the memory occurs in a case where the back read data does not match the expected data.

2. The method of claim 1, wherein, The test dimension of the memory comprises at least one of the following: the DDR subsystem, the DRAM subsystem, and a path between the DDR subsystem and the DRAM subsystem.

3. The method of claim 1, wherein, The generating of the expected data according to the preset pattern comprises: generating the expected data according to the preset pattern in a case where a power-on instruction and / or a power-off instruction is received.

4. The method of claim 1, wherein, The generating of the expected data according to the preset pattern comprises: determining a current cycle count value; generating the expected data according to the preset pattern in a case where the current cycle count value reaches a preset threshold.

5. The method of claim 1, wherein, The generating of the expected data according to the preset pattern comprises: generating the expected data according to the preset pattern in a case where a chip to which the memory belongs is in a fault locating mode.

6. The method of claim 1, wherein, In the case where the back read data does not match the expected data, the method further comprises: storing the back read data that does not match the expected data and a storage address corresponding to the back read data and the expected data.

7. The method of claim 6, wherein, The method further comprises: determining a fault cause and / or a fault type of the memory according to the back read data and the storage address. 8.A device for detecting a fault of a memory, comprising: a test sequence generation module configured to: generate expected data according to a preset pattern, wherein the preset pattern represents a test dimension of the memory, and the memory comprises a double data rate synchronous dynamic random access memory (DDR) subsystem and a dynamic random access memory (DRAM) subsystem; and write the expected data to the DRAM subsystem through the DDR subsystem; a data comparison module configured to: read back read data from the DRAM subsystem; and determine that a fault of the memory occurs in a case where the back read data does not match the expected data. 9.A chip comprising a memory and a processor, wherein the memory stores a computer program executable by the processor, and the computer program, when executed by the processor, implements the method of any one of claims 1 to 7. 10.A computer readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method of any one of claims 1 to 7. 11.A computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the method of any one of claims 1 to 7.

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