Display panel and display apparatus

Abstract

A display panel and a display apparatus, relating to the technical field of display. The display panel comprises a base substrate, a driving circuit layer provided on the base substrate, and a plurality of light-emitting elements provided on the side of the driving circuit layer away from the base substrate; the driving circuit layer comprises at least a first conductive layer (101) and a second conductive layer (102), a first insulating layer (301) being provided between the first conductive layer (101) and the second conductive layer (102); the first insulating layer (301) comprises a first via (K1); a second insulating layer (302) is provided between the driving circuit layer and a first anode (2011) of a first light-emitting element (201); the first insulating layer (301) and / or the second insulating layer (302) is provided with a first recessed region (K2); a first orthographic projection of the first anode (2011) on the base substrate and a second orthographic projection of the first via (K1) on the base substrate have a first overlapping region (J1), and the first orthographic projection and a third orthographic projection of the first recessed region (K2) on the base substrate have a second overlapping region (J2), the second orthographic projection and the third orthographic projection having no overlapping region.

Description

Display panel and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410705654.8, filed on May 31, 2024, entitled “A Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0004] Organic light-emitting diodes (OLEDs) are widely used in the field of display technology due to their advantages such as thinness, high brightness, low power consumption, fast response, high definition, good flexibility, and high luminous efficiency.

[0005] Overview

[0006] This application provides a display panel and a display device.

[0007] In a first aspect, this application provides a display panel, the display panel comprising: a substrate, a driving circuit layer located on the substrate, and a plurality of light-emitting elements located on the driving circuit layer on a side away from the substrate;

[0008] The driving circuit layer includes at least a first conductive layer and a second conductive layer;

[0009] A first insulating layer is disposed between the first conductive layer and the second conductive layer;

[0010] The first insulating layer includes a first via;

[0011] The first conductive layer is electrically connected to the second conductive layer through the first via;

[0012] The plurality of light-emitting elements includes at least a first light-emitting element;

[0013] A second insulating layer is provided between the driving circuit layer and the first anode of the first light-emitting element;

[0014] The first insulating layer and / or the second insulating layer are provided with a first recessed area;

[0015] At the first recessed area, the first conductive layer and the second conductive layer are isolated by the first insulating layer, and the driving circuit layer is isolated from the first anode by the second insulating layer;

[0016] The first orthographic projection of the first anode on the substrate has a first overlapping region with the second orthographic projection of the first via on the substrate.

[0017] The first orthographic projection and the third orthographic projection of the first recessed area on the substrate have a second overlapping region; and

[0018] The second orthographic projection and the third orthographic projection have no overlapping area.

[0019] Optionally, the first recessed area is disposed on the first insulating layer; and

[0020] At the first recessed area, the thickness of the first insulating layer is greater than zero and less than the first target thickness;

[0021] The first target thickness is the thickness of the first insulating layer corresponding to the surrounding area of ​​the first recessed region.

[0022] Optionally, the first insulating layer includes a first planarization layer and a passivation layer located on the first planarization layer on the side away from the substrate; and

[0023] The first recessed area is disposed on the first planarization layer and / or the passivation layer.

[0024] Optionally, the first recessed area is disposed on the first planarization layer; and

[0025] At the first recessed region, the first conductive layer and the second conductive layer are isolated by the passivation layer.

[0026] Optionally, the first recessed area is a first through-hole on the first planarization layer.

[0027] Optionally, the first recessed region is disposed on the passivation layer; and

[0028] At the first recessed region, the first conductive layer and the second conductive layer are isolated by the first planarization layer.

[0029] Optionally, the first recessed area is a second via on the passivation layer.

[0030] Optionally, the first recessed area includes a first recessed portion and a second recessed portion;

[0031] The first recessed portion is disposed on the first planarization layer, and the second recessed portion is disposed on the passivation layer; and

[0032] The orthographic projection of the first recessed portion on the substrate and the orthographic projection of the second recessed portion on the substrate at least partially overlap.

[0033] Optionally, the first recessed area is disposed on the second insulating layer; and

[0034] At the first recessed area, the thickness of the second insulating layer is greater than zero and less than the second target thickness;

[0035] The second target thickness is the thickness of the second insulating layer corresponding to the surrounding area of ​​the first recessed region.

[0036] Optionally, the second insulating layer includes a second planarization layer;

[0037] The first recessed area is disposed on the second planarization layer; and

[0038] At the first recessed area, the thickness of the second flattening layer is greater than zero and less than the second target thickness.

[0039] Optionally, the first recessed area includes a third recessed portion and a fourth recessed portion;

[0040] The third recessed portion is disposed on the first insulating layer, and the fourth recessed portion is disposed on the second insulating layer;

[0041] The orthographic projection of the third recessed portion on the substrate and the orthographic projection of the fourth recessed portion on the substrate at least partially overlap;

[0042] At the third recessed portion, the thickness of the first insulating layer is greater than zero;

[0043] At the fourth recessed portion, the thickness of the second insulating layer is greater than zero; and

[0044] In the first recessed area, the total thickness of the driving circuit layer is less than the thickness of the driving circuit layer corresponding to the peripheral area of ​​the first recessed area.

[0045] Optionally, the plurality of light-emitting elements are arranged along a first direction to form a plurality of light-emitting element rows;

[0046] The plurality of light-emitting elements are arranged along the second direction to form a plurality of light-emitting element columns;

[0047] The first overlapping region and the second overlapping region are located in the first direction or the second direction; and

[0048] The area of ​​the first overlapping region is approximately equal to the area of ​​the second overlapping region.

[0049] Optionally, the first anode includes a first edge and a second edge disposed opposite to each other along the first direction or the second direction;

[0050] The first overlapping region is close to the first edge, and the vertical distance between the center of the first overlapping region and the first edge is the first distance;

[0051] The second overlapping region is close to the second edge, and the vertical distance between the center of the second overlapping region and the second edge is the second distance; and

[0052] The first distance is approximately equal to the second distance.

[0053] Optionally, the vertical distance between the center of the first overlapping region and the first straight line is the third distance;

[0054] The perpendicular distance between the center of the second overlapping region and the second straight line is the fourth distance; and

[0055] The third distance is approximately equal to the fourth distance;

[0056] The first straight line is a straight line perpendicular to the first direction and passing through the center of the first orthographic projection, or the first straight line is a straight line perpendicular to the second direction and passing through the center of the first orthographic projection.

[0057] Optionally, the plurality of light-emitting elements further includes a second light-emitting element;

[0058] The first insulating layer also includes a second via and a third via;

[0059] The first conductive layer is electrically connected to the second conductive layer through the second via and the third via, respectively;

[0060] The second anode of the second light-emitting element has a third overlapping region with the fifth orthographic projection of the second via on the substrate, and the fourth orthographic projection of the second anode on the substrate has a fourth overlapping region with the sixth orthographic projection of the third via on the substrate; and

[0061] The areas of the third overlapping region and the fourth overlapping region are approximately equal.

[0062] Optionally, the third overlapping region and the fourth overlapping region are symmetrically distributed within the fourth orthographic projection.

[0063] Optionally, the display panel includes a display area and a bonding area located on one side of the display area;

[0064] The display panel includes multiple data signal lines, multiple first connection lines, and multiple second connection lines;

[0065] The plurality of first connecting lines are disposed in the first conductive layer;

[0066] The plurality of data signal lines and the plurality of second connection lines are disposed in the second conductive layer;

[0067] The plurality of first connection lines, the plurality of second connection lines, and the plurality of data signal lines are located in the display area;

[0068] The first connecting line is electrically connected to the data signal line through the first connecting hole, and the first connecting line is electrically connected to the second connecting line through the second connecting hole;

[0069] The second connecting line is also electrically connected to the lead wire of the bonding area; and

[0070] The first via includes the first connecting hole and / or the second connecting hole.

[0071] Optionally, the driving circuit layer includes a sub-pixel driving circuit, wherein the transistors of the sub-pixel driving circuit are thin-film transistors made of low-temperature polycrystalline silicon.

[0072] Optionally, the second overlapping region is located on the side of the first overlapping region that is close to the center of the first orthographic projection.

[0073] Optionally, in the first recessed region, the total thickness of the first planarization layer and the passivation layer is greater than zero and less than the first target thickness.

[0074] Secondly, this application provides a display device, the display device including a display panel as described in the first aspect.

[0075] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application.

[0076] Brief description of the attached diagram

[0077] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0078] Figure 1 illustrates, by way of example, a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0079] Figure 2 illustrates, exemplarily, a wiring diagram of a display panel in the related art;

[0080] Figure 3 illustrates, exemplarily, a wiring diagram of another display panel in the related art;

[0081] Figure 4 illustrates, exemplarily, a wiring diagram of another display panel in the related art;

[0082] Figure 5 illustrates, exemplarily, a wiring diagram of another display panel in the related art;

[0083] Figure 6 illustrates, exemplarily, a schematic diagram of the positional relationship between the sub-pixel anode and the via in the relevant technology;

[0084] Figure 7 illustrates, by way of example, a schematic diagram of the microstructure of an anode edge in the related art;

[0085] Figure 8 illustrates, exemplarily, a light emission schematic diagram under the condition of high anode flatness in the related art;

[0086] Figure 9 illustrates, exemplarily, a schematic diagram of light emission when the anode is tilted to one side in the related art;

[0087] Figure 10 illustrates, by way of example, one of the microscopic topographic diagrams of the anode edge of a display panel provided in an embodiment of this application;

[0088] Figure 11 illustrates, by way of example, a second schematic diagram of the microstructure of the anode edge of a display panel according to an embodiment of this application;

[0089] Figure 12 illustrates, by way of example, a third schematic diagram of the microstructure of the anode edge of a display panel according to an embodiment of this application;

[0090] Figure 13 illustrates, exemplarily, a fourth schematic diagram of the microstructure of the anode edge of a display panel according to an embodiment of this application;

[0091] Figure 14 exemplarily illustrates one of the schematic diagrams showing the anode and via positions of a display panel according to an embodiment of this application;

[0092] Figure 15 exemplarily illustrates a second schematic diagram of the anode and via positions of a display panel provided in an embodiment of this application;

[0093] Figure 16 exemplarily illustrates the fifth of the microscopic morphology diagrams of the anode edge of a display panel provided in an embodiment of this application; and

[0094] Figure 17 illustrates, exemplarily, a display device provided in an embodiment of this application.

[0095] Detailed description

[0096] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0097] In related technologies, OLED display panels include structures such as a substrate, a driving circuit layer, and light-emitting elements. The driving circuit layer includes conductive layers, which can be multi-layered. Insulating layers are placed between different conductive layers of the driving circuit layer, and between the driving circuit layer and the anode of the light-emitting element, which can serve to insulate and planarize the surface, improving the surface flatness of the film structure.

[0098] Due to the dense wiring in display panels, numerous vias are placed on the insulating layers between different conductive layers to connect the conductive layers on both sides of the vias. However, some light-emitting elements have vias on one side of the anode and not on the other side, causing the anode to tilt towards the side with the via. This affects the flatness of the anode, resulting in increased color shift differences in the display panel and a deterioration in display performance.

[0099] As shown in Figures 1, 7, 10-13, and 16, this application provides a display panel, including: a substrate, a driving circuit layer on the substrate, and a plurality of light-emitting elements on the driving circuit layer away from the substrate.

[0100] The driving circuit layer includes at least a first conductive layer 101 and a second conductive layer 102; a first insulating layer 301 is disposed between the first conductive layer 101 and the second conductive layer 102; the first insulating layer 301 includes a first via K1; the first conductive layer 101 is electrically connected to the second conductive layer 102 through the first via K1.

[0101] The plurality of light-emitting elements includes at least a first light-emitting element 201; a second insulating layer 302 is disposed between the driving circuit layer and the first anode 2011 of the first light-emitting element 201;

[0102] The first insulating layer 301 and / or the second insulating layer 302 are provided with a first recessed area K2; at the first recessed area K2, the first conductive layer 101 and the second conductive layer 102 are isolated by the first insulating layer 301, and the driving circuit layer and the first anode 2011 are isolated by the second insulating layer 302.

[0103] The first orthographic projection of the first anode 2011 on the substrate has a first overlapping region J1 with the second orthographic projection of the first via K1 on the substrate; the first orthographic projection and the third orthographic projection of the first recessed region K2 on the substrate have a second overlapping region J2; the second orthographic projection and the third orthographic projection have no overlapping region.

[0104] In some embodiments, the driving circuit layer includes a sub-pixel driving circuit, which includes a driving transistor. Each sub-pixel corresponds to a light-emitting element, which includes an anode, an organic light-emitting layer, and a cathode sequentially stacked in a direction away from the substrate. The anode of the light-emitting element is electrically connected to the driving transistor in the sub-pixel driving circuit corresponding to the light-emitting element.

[0105] In some embodiments, the transistors in the sub-pixel driving circuit can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs). For example, active-matrix organic light-emitting diode (AMOLED) display panels often use LTPS TFTs.

[0106] Figure 1 illustrates a schematic diagram of a display panel structure provided in an embodiment of this application. As shown in Figure 1, the conductive layer of the driving circuit layer has a multi-layer structure, and the driving circuit layer includes at least a first conductive layer 101 and a second conductive layer 102. The first conductive layer 101 and the second conductive layer 102 are stacked sequentially in a direction away from the substrate. The first conductive layer 101 can serve as the input electrode and output electrode of each transistor in the sub-pixel driving circuit, and signal lines such as data lines and power lines can be disposed in the second conductive layer 102.

[0107] In some embodiments, the conductive layer of the driving circuit layer can be a source-drain metal layer (SD), which can be a multilayer structure, such as a 2SD or 3SD structure. A 2SD structure includes an SD1 layer and an SD2 layer, which are stacked sequentially in a direction away from the substrate. The SD1 layer can serve as the source and drain of each transistor in the sub-pixel driving circuit, and signal lines such as data lines and power lines can be disposed on the SD2 layer. This is merely an example, and the embodiments of this application do not impose limitations.

[0108] In some embodiments, insulating layers can be stacked between different conductive layers to provide insulation and planarization. Vias can be provided on the insulating layers, through which the conductive layers can be electrically connected. Specifically, a first insulating layer 301 can be provided between the first conductive layer 101 and the second conductive layer 102, and the first insulating layer 301 includes a first via K1. As shown in FIG1, the first conductive layer 101 is electrically connected to the second conductive layer 102 through the first via K1. For example, a first planarization layer 3011 (PLN1) can be provided between the SD1 layer and the SD2 layer, and the PLN1 has a first via K1 (PLN1 via).

[0109] In related technologies, some display panels include 2SD / 3SD structures. Using a 2SD structure results in denser backplane circuitry for the display panel, with more vias placed between the SD1 and SD2 layers. For example, some display panels employing Flexible Integrated Passive (FIP) technology use 2SD FIP or 3SD FIP processes. FIP technology integrates the edge wiring area of ​​the display panel into the display area, significantly reducing the area of ​​non-display regions and achieving extremely narrow bezels, such as 1 millimeter (mm).

[0110] Figure 2 exemplarily illustrates a wiring diagram of a display panel in the related art. As shown in Figure 2, FIP technology can integrate signal lines introduced into the display area from the bonding area via the fanout area into the display area, thereby reducing the bezel width near the bonding area. Specifically, as shown in Figure 2, the display area includes multiple signal lines, such as multiple data signal lines and multiple data connection lines (FIP traces). The data connection lines include a first connection line (FIP1) parallel to the pixel row direction and a second connection line (FIP2) parallel to the pixel column direction. The first connection line (FIP1) is electrically connected to the data signal line through a first connection hole (V1), and the first connection line (FIP1) is electrically connected to the second connection line (FIP2) through a second connection hole (V2). The bonding area is provided with a lead area. When the second connection line (FIP2) reaches the edge (B) of the display area, the second connection line (FIP2) connects to the lead line of the bonding area, thereby connecting the display area and the bonding area.

[0111] Figure 3 exemplarily illustrates a wiring diagram of another display panel in the related art. The display panel shown in Figure 3 adopts a 2SD FIP process, and the wiring in Figure 3 includes wiring on the SD1 layer and wiring on the SD2 layer. As shown in Figure 3, the FIP wiring extending along the row direction is the first connection line (FIP1), which is located on the SD1 layer, and the FIP wiring extending along the column direction is the second connection line (FIP2), which is located on the SD2 layer.

[0112] The data connection cable is installed in a portion of the display area. The display area can be divided into a first area with the first connection cable (FIP1), a second area with the second connection cable (FIP2), and a normal area excluding the adapter position of the data connection cable. The FIP area includes the first and second areas, and the normal area can also be referred to as the non-FIP area.

[0113] In related technologies, as shown in Figure 2, the bezel area of ​​a display panel typically has bezel power leads. These bezel power leads are configured to transmit low-voltage power signals. To reduce the voltage drop of the low-voltage power signals, the bezel power leads are relatively wide, resulting in a larger width for the left and right bezels of the display panel. In display panels using narrow bezel (FIP) technology, the first connecting line (FIP1) and the second connecting line (FIP2) in the non-FIP area can be separated from each other. Furthermore, by setting breaks in the first connecting line (FIP1) and / or the second connecting line (FIP2), the FIP traces can be disconnected, allowing other signals to be transmitted.

[0114] For example, Figure 3 shows the second connection line (FIP2) of the SD2 layer. The second connection line (FIP2) can transmit the power signal (VSS), which can be transmitted to the SD1 layer through the PLN1 via shown in Figure 3. Therefore, in non-FIP areas, FIP traces can be used as power traces, thereby placing the power traces within the display area. This can significantly reduce the width of the bezel power leads and shorten the width of the left and right bezels of the display panel.

[0115] Figure 4 exemplarily illustrates a wiring diagram of another display panel in the related art. Comparing Figure 3 and Figure 4, in Figure 3, the anode of the sub-pixel is located on the side closer to the substrate, with a number of PLN1 vias between the SD1 and SD2 layers. However, the PLN1 vias may be asymmetrically positioned, such as having one anode on one side but not the other, or the vias on the top / bottom or left / right sides being asymmetrical. This can cause one side of the anode to collapse, resulting in the entire anode tilting towards the collapsed side, affecting the anode flatness, and consequently affecting the color shift symmetry of the display panel.

[0116] Figure 5 exemplarily illustrates a schematic diagram of the wiring of another display panel in the related art. As shown in Figure 5, the display panel includes a 2SD structure. Figure 5 shows the wiring of SD1 layer and SD2 layer, the three sub-pixels of red (R), green (G), and blue (B), and the PLN1 via between SD1 layer and SD2 layer. The wiring of SD1 layer includes, for example, a first connection line (FIP1) extending along the row direction, and the wiring of SD2 layer includes, for example, a second connection line (FIP2) extending along the column direction, a voltage signal line (VDD), an initial signal line (Vinit), and a data signal line (Vdata). It should be noted that the data signal line (Vdata), the first connection line (FIP1), and the second connection line (FIP2) can all transmit data signals.

[0117] In Figure 5, the positional relationship between the anode and the PLN1 via of each sub-pixel is shown in Figure 6. There are cases where the vias on one side of the sub-pixel are present but not on the other (pixel G), or where the via projection on one side overlaps with the anode projection but not on the other (pixel R), or where the via projection on one side is completely inside the anode projection while the via projection on the other side only partially overlaps with the anode projection (pixel B). Similarly, there are also cases where the via positions are asymmetrical on the left and right sides of the sub-pixel, for example, where the via projection on one side only partially overlaps with the anode projection while the via projection on the other side is completely inside the anode projection (pixel G). Asymmetrical via positions can cause the anode to collapse to one side, making the entire anode tilt towards the collapsed side and affecting the flatness of the anode.

[0118] Figure 7 exemplarily illustrates a microscopic topography diagram of the anode edge of a display panel in the related art. As shown in Figure 7, a PLN1 via is provided on the D side of the anode. The anode collapses towards the substrate side on the D side, while the U side of the anode is flat and does not collapse towards the substrate side. This causes the anode to tilt overall towards the D side with the PLN1 via. The U side corresponds to the upper side of the anode of the sub-pixel shown in Figure 6, and the D side corresponds to the lower side of the anode of the sub-pixel shown in Figure 6.

[0119] Figure 8 shows the light emission diagram when the anode is relatively flat, while Figure 9 shows the light emission diagram when the anode is tilted to one side. In the case of a low D and high U anode, the light path is blocked. Referring to Figure 6, if any sub-pixel has an anode tilt, it will cause inconsistent brightness decay between that sub-pixel and other sub-pixels, resulting in asymmetrical color shift trajectories on both sides and an increased objective value of the vertical color shift difference (colorshift2), leading to a visual difference in color on both sides. For example, if the G pixel anode forms a low D and high U shape, while the R / B pixel anode is relatively flat, the brightness decay of the G pixel and the R / B pixel will be inconsistent. From the user's perspective, the slower decay on the D side of the G pixel will appear bluish, while the faster decay on the U side will appear pinkish, causing a visual difference between the U and D sides. This increases the objective value of the vertical color shift difference, resulting in a poor display effect on the display panel.

[0120] In some embodiments, as shown in FIG1, the plurality of light-emitting elements includes at least a first light-emitting element 201. The first light-emitting element 201 includes a first anode 2011, an organic light-emitting layer, and a first cathode, which are sequentially stacked in a direction away from the substrate. The first orthographic projection of the first anode 2011 on the substrate and the second orthographic projection of the first via K1 on the substrate have a first overlap region J1, that is, in the direction perpendicular to the substrate, the first orthographic projection corresponding to the first anode 2011 and the second orthographic projection corresponding to the first via K1 at least partially overlap.

[0121] When there is a first overlapping area J1 between the first orthographic projection and the second orthographic projection, if there is no via on the opposite side of the first via K1, or if the orthographic projection of the via on the opposite side of the first via K1 does not overlap with the first orthographic projection corresponding to the first anode 2011, or if the overlapping area of ​​the orthographic projection of the via on the opposite side of the first via K1 and the first orthographic projection is much smaller than the area of ​​the first overlapping area J1, the first anode 2011 will collapse on the side of the first via K1, causing the first anode 2011 to tilt towards the side of the first via K1, affecting the flatness of the first anode 2011.

[0122] The opposite side of the first via K1 can be the upper or lower side of the sub-pixel in the pixel column direction, or the left or right side of the sub-pixel in the pixel row direction, or different sides of the sub-pixel in the direction parallel to the substrate.

[0123] In some embodiments, a second insulating layer 302 is provided between the driving circuit layer and the first anode 2011. The second insulating layer 302 can serve as insulation and planarization. For example, for a driving circuit layer with a 2SD structure, a second planarization layer (PLN2) can be provided between the SD2 layer and the anode of the light-emitting element.

[0124] In some embodiments, as shown in FIG1, the first insulating layer 301 and / or the second insulating layer 302 may be provided with a first recessed region K2. It should be noted that insulation between the first conductive layer 101 and the second conductive layer 102, and between the first anode 2011 and the second conductive layer 102, still exists at the first recessed region K2. This prevents short circuits between the first conductive layer 101 and the second conductive layer 102 due to leakage from the first recessed region K2, and also prevents short circuits between the first anode 2011 and the second conductive layer 102 due to leakage from the first recessed region K2. That is, the first conductive layer 101 and the second conductive layer 102 are isolated by the first insulating layer 301, and the driving circuit layer and the first anode 2011 are isolated by the second insulating layer 302.

[0125] In some embodiments, when the first recessed region K2 is disposed in the first insulating layer 301, the conductive layer and the insulating layer stacked on the first insulating layer 301 in the direction away from the substrate will collapse to form a recessed region. Furthermore, the third orthographic projection of the first recessed region K2 on the substrate has a second overlap region J2 with the first orthographic projection corresponding to the first anode 2011; that is, in the direction perpendicular to the substrate, the first orthographic projection corresponding to the first anode 2011 and the third orthographic projection corresponding to the first recessed region K2 at least partially overlap. Thus, the first anode 2011 will collapse at the recessed region formed by the first recessed region K2, causing the first anode 2011 to tilt towards the first recessed region K2.

[0126] In some embodiments, when the first recessed area K2 is located in the second insulating layer 302, the first anode 2011 collapses at the first recessed area K2, causing the first anode 2011 to tilt towards the first recessed area K2. Alternatively, the first recessed area K2 can be located in the first insulating layer 301 and the second insulating layer 302, and the third orthographic projection corresponding to the first recessed area K2 partially overlaps with the first orthographic projection corresponding to the first anode 2011. This prevents the first anode 2011 from tilting only at the first via K1; by collapsing at the first recessed area K2, the first anode 2011 also tilts in the direction of the first recessed area K2. Since the second and third orthographic projections do not overlap, the direction of the first recessed area K2 does not coincide with the direction of the first via K1. Therefore, the problem of the entire anode of the display panel tilting towards the first via K1 in related technologies can be avoided, improving anode flatness, thereby reducing color shift differences in the display panel and improving the display effect.

[0127] In this embodiment, the display panel includes: a substrate, a driving circuit layer on the substrate, and a plurality of light-emitting elements on the driving circuit layer away from the substrate; the driving circuit layer includes at least a first conductive layer and a second conductive layer; a first insulating layer is disposed between the first conductive layer and the second conductive layer; the first insulating layer includes a first via; the first conductive layer is electrically connected to the second conductive layer through the first via; the plurality of light-emitting elements includes at least a first light-emitting element; a second insulating layer is disposed between the driving circuit layer and the first anode of the first light-emitting element; a first recessed region is provided in the first insulating layer and / or the second insulating layer; at the first recessed region, the first conductive layer and the second conductive layer are isolated by the first insulating layer, and the driving circuit layer and the first anode are isolated by the second insulating layer. This ensures that the first conductive layer and the second conductive layer are insulated and isolated at the first recessed region, preventing short circuits between the first conductive layer and the second conductive layer, and that the driving circuit layer and the first anode are insulated and isolated at the first recessed region, preventing short circuits between the conductive layer in the driving circuit layer and the first anode. Because the first orthographic projection of the first anode on the substrate has a first overlapping area with the second orthographic projection of the first via on the substrate; the first orthographic projection has a second overlapping area with the third orthographic projection of the first recessed area on the substrate; and the second orthographic projection and the third orthographic projection have no overlapping area. This causes the first anode to tilt not only towards the first via, but also to tilt towards the first recessed area due to its collapse there. Since the second and third orthographic projections have no overlapping area, the tilting direction of the first anode in the first recessed area does not coincide with its tilting direction at the first via. Therefore, the problem of the entire display panel anode tilting towards the first via in related technologies can be avoided, improving anode flatness, thereby reducing color shift differences in the display panel and improving the display effect.

[0128] Optionally, the first recessed area K2 is disposed on the first insulating layer 301;

[0129] At the first recessed region K2, the thickness of the first insulating layer 301 is greater than zero and less than the first target thickness;

[0130] The first target thickness is the thickness of the first insulating layer 301 corresponding to the surrounding area of ​​the first recessed region K2.

[0131] In some embodiments, the first recessed region K2 may be a recessed region formed on the first insulating layer 301. At the first recessed region K2, the thickness of the first insulating layer 301 is not zero, i.e., the thickness of the first insulating layer 301 is greater than zero, so that the first conductive layer 101 and the second conductive layer 102 are insulated and isolated at the first recessed region K2, thus preventing short circuits between the first conductive layer 101 and the second conductive layer 102. At the first recessed region K2, the thickness of the first insulating layer 301 is less than the first target thickness, making the thickness of the first insulating layer 301 thinner than the surrounding area. Thus, the conductive layers and insulating layers sequentially stacked on the first insulating layer 301 away from the substrate form a recessed region, causing the first anode 2011 above the driving circuit layer to collapse in the recessed region, and the first anode 2011 tilts towards the first recessed region K2.

[0132] The peripheral region of the first recessed region K2 includes the area formed by the first insulating layer 301 around the first recessed region K2 in a direction parallel to the substrate. For example, if the first recessed region K2 is a through hole, then the periphery of the first recessed region K2 is the area formed by the first insulating layer 301 surrounding the through hole.

[0133] In this embodiment, when the first recessed region K2 is disposed on the first insulating layer 301, the thickness of the first insulating layer 301 at the first recessed region K2 is greater than zero and less than the first target thickness, where the first target thickness is the thickness of the region of the first insulating layer 301 corresponding to the orthographic projection of the first anode 2011 onto the first insulating layer 301. This allows the first anode 2011 to collapse at the first recessed region K2, and the first conductive layer 101 and the second conductive layer 102 to be insulated and isolated.

[0134] Optionally, the first insulating layer 301 includes a first planarization layer 3011 and a passivation layer 3012 located on the side of the first planarization layer 3011 away from the substrate.

[0135] The first recessed region K2 is provided on the first planarization layer 3011 and / or passivation layer 3012;

[0136] At the first recessed region K2, the total thickness of the first planarization layer 3011 and the passivation layer 3012 is greater than zero and less than the first target thickness.

[0137] In some embodiments, the first insulating layer 301 includes a first planarization layer 3011 (PLN1) and a passivation layer 3012 (PVX) sequentially stacked on the first conductive layer 101 in the direction away from the substrate. A first recessed region K2 is disposed on the first planarization layer 3011 or the passivation layer 3012, and the first recessed region K2 may be formed by the first planarization layer 3011 and the passivation layer 3012 together; this application embodiment does not limit this.

[0138] At the first recessed region K2, the total thickness of the first planarization layer 3011 and the passivation layer 3012 is greater than zero, which insulates the first conductive layer 101 and the second conductive layer 102 from short circuit at the first recessed region K2. At the first recessed region K2, the total thickness of the first planarization layer 3011 and the passivation layer 3012 is less than the first target thickness, which makes the first insulating layer 301 thinner than the surrounding area, causing the first anode 2011 to collapse at the first recessed region K2 and tilt towards the first recessed region K2.

[0139] In this embodiment, since the first recessed region K2 is disposed on the first planarization layer 3011 and / or passivation layer 3012, the total thickness of the first planarization layer 3011 and passivation layer 3012 at the first recessed region K2 is greater than zero and less than the first target thickness. This allows the first anode 2011 to collapse at the first recessed region K2, and the first conductive layer 101 and the second conductive layer 102 to be insulated and isolated. The first planarization layer 3011 provides insulation and planarization, the passivation layer 3012 provides insulation, and protects the display panel from environmental influences.

[0140] Optionally, the first recessed region K2 is disposed on the first planarization layer 3011;

[0141] At the first recessed region K2, the first conductive layer 101 and the second conductive layer 102 are isolated by the passivation layer 3012.

[0142] In some embodiments, the first recessed region K2 may be a recessed region formed on the first planarization layer 3011. The passivation layer 3012, each conductive layer and each insulating layer are sequentially stacked on the first planarization layer 3011 away from the substrate and collapse in the first recessed region K2, thereby causing the first anode 2011 to collapse in the first recessed region K2.

[0143] At the first recessed region K2, the first conductive layer 101 and the second conductive layer 102 are isolated by a passivation layer 3012. The passivation layer 3012 can be a surface passivation protective film, which can effectively block the diffusion of water vapor and mobile ions, mainly used to protect the device from environmental influences and improve device performance. The passivation layer 3012 can be made of an insulating material, such as Si3N4. This is only an example, and the embodiments of this application are not limited thereto.

[0144] In this embodiment of the application, when the first recessed region K2 is disposed on the first planarization layer 3011, since the first conductive layer 101 and the second conductive layer 102 are isolated by the passivation layer 3012 at the first recessed region K2, the first conductive layer 101 and the second conductive layer 102 can be prevented from being short-circuited.

[0145] Optionally, the first recessed area K2 is a first through hole on the first planarization layer 3011.

[0146] In some embodiments, the thickness of the first planarization layer 3011 at the first recessed region K2 can be zero or greater than zero. When the thickness of the first planarization layer 3011 at the first recessed region K2 is zero, the passivation layer 3012 at the first recessed region K2 serves as an insulating barrier. For example, the first recessed region K2 is a first via on the first planarization layer 3011, that is, the residual amount (THK) of the first planarization layer 3011 at the first recessed region K2 is zero.

[0147] In some embodiments, when the thickness of the first planarization layer 3011 in the first recessed region K2 is greater than zero, the remaining portion of the first planarization layer 3011 is thinner than the surrounding area, and can be insulated by the remaining portion of the first planarization layer 3011 and the passivation layer 3012. For example, the first planarization layer 3011 can be fabricated using a halftone mask process. By setting different light transmittances for the grating, the THK at the first recessed region K2 can be thinned, thereby forming the first recessed region K2 on the first planarization layer 3011 (HPLN1), where HPLN1 represents the first planarization layer 3011 fabricated using the Halftone process. This is merely an example, and the embodiments of this application do not limit the scope of the invention.

[0148] Figure 10 exemplarily illustrates one of the microscopic topographic diagrams of the anode edge of a display panel according to an embodiment of this application. As shown in Figure 10, the first insulating layer 301 between the first conductive layer 101 (SD1) and the second conductive layer 102 (SD2) includes a first planarization layer 3011 (PLN1) and a passivation layer 3012 (PVX). The SD1 layer and the SD2 layer are electrically connected through a first via K1 (PLN1 via), and the PVX layer at the PLN1 via is removed, causing the edge of the first anode 2011 to collapse at the PLN1 via.

[0149] As shown in Figure 10, a first recessed region K2 is provided on the first planarization layer 3011 (PLN1), and the first recessed region K2 is a first via on the first planarization layer 3011 (PLN1). At the first recessed region K2, the first conductive layer 101 (SD1) and the second conductive layer 102 (SD2) are isolated by the passivation layer 3012 (PVX). At the first recessed region K2, the passivation layer 3012 (PVX), the second conductive layer 102 (SD2), and the second planarization layer (PLN2), which are sequentially stacked on the first planarization layer 3011 (PLN1) away from the substrate, collapse, causing the edge of the first anode 2011 to collapse at the first recessed region K2. In this way, the first anode 2011 can be tilted in the direction of the first recessed region K2, as shown in Figure 10, which can improve the flatness of the first anode 2011 and thus prevent the light-emitting path of the sub-pixel corresponding to the first anode 2011 from being blocked. Therefore, it can reduce the problem of inconsistent brightness attenuation between sub-pixels, improve the symmetry of color shift trajectory, and reduce color shift differences in the display panel. This avoids visual color differences from the user's perspective, thereby improving the display panel's display effect.

[0150] In this embodiment, the first recessed region K2 can be a first through hole on the first planarization layer 3011, and the first conductive layer 101 and the second conductive layer 102 are only insulated and isolated by the passivation layer 3012, which makes it easy to manufacture the first recessed region K2.

[0151] Figure 11 exemplarily illustrates a second schematic diagram of the microstructure of the anode edge of a display panel according to an embodiment of this application. As shown in Figure 11, a first planarization layer 3011 (HPLN1) and a passivation layer 3012 (PVX) are included between the SD1 layer and the SD2 layer. The SD1 layer and the SD2 layer are electrically connected through a first via K1 (HPLN1 via), and the PVX layer at the HPLN1 via is removed, causing the edge of the first anode 2011 to collapse at the HPLN1 via.

[0152] As shown in Figure 11, a first recessed region K2 is formed on the first planarization layer 3011 (HPLN1), and the thickness of the first planarization layer 3011 (HPLN1) in the first recessed region K2 is less than the thickness of the first planarization layer 3011 (HPLN1) on the side of the first anode 2011 closest to the substrate. This results in the total thickness of the first planarization layer 3011 (HPLN1) and the passivation layer 3012 (PVX) at the first recessed region K2 being less than the first target thickness, allowing the first insulating layer 301 to be thinner than the surrounding area. At the first recessed region K2, the SD1 layer and the SD2 layer are isolated by the PVX layer and the first planarization layer 3011 (HPLN1). At the first recessed region K2, the PVX layer, the SD2 layer, and the PLN2 layer, which are sequentially stacked on the HPLN1 layer away from the substrate, collapse, causing the edge of the first anode 2011 to collapse at the first recessed region K2. This improves the flatness of the first anode 2011, reduces color shift differences in the display panel, and thus enhances the display effect of the display panel.

[0153] Optionally, the first recessed region K2 is disposed on the passivation layer 3012;

[0154] At the first recessed region K2, the first conductive layer 101 and the second conductive layer 102 are isolated by the first planarization layer 3011.

[0155] In some embodiments, the first recessed region K2 may be a recessed region formed on the passivation layer 3012. The conductive layers and insulating layers sequentially stacked on the passivation layer 3012 away from the substrate collapse in the first recessed region K2, thereby causing the first anode 2011 to collapse in the first recessed region K2. At the first recessed region K2, the first conductive layer 101 and the second conductive layer 102 are isolated by the first planarization layer 3011. The first planarization layer 3011 may be made of an insulating material.

[0156] In this embodiment of the application, when the first recessed region K2 is disposed on the passivation layer 3012, since the first conductive layer 101 and the second conductive layer 102 are isolated by the first planarization layer 3011 at the first recessed region K2, the first conductive layer 101 and the second conductive layer 102 can be prevented from being short-circuited.

[0157] Optionally, the first recessed region K2 is a second via on the passivation layer 3012.

[0158] In some embodiments, the thickness of the passivation layer 3012 at the first recessed region K2 can be zero or greater than zero. When the thickness of the passivation layer 3012 at the first recessed region K2 is zero, the first planarization layer 3011 at the first recessed region K2 can provide insulation. For example, the first recessed region K2 is a second via on the passivation layer 3012, meaning the thickness of the passivation layer 3012 at the first recessed region K2 is zero. When the thickness of the passivation layer 3012 at the first recessed region K2 is greater than zero, the remaining portion of the passivation layer 3012 only needs to be thinner than the surrounding area, and insulation can be provided by the remaining portion of the passivation layer 3012 and the first planarization layer 3011 together.

[0159] In this embodiment, the first recessed region K2 can be a second via on the passivation layer 3012. The first conductive layer 101 and the second conductive layer 102 are only insulated and isolated by the first planarization layer 3011, which makes it easy to fabricate the first recessed region K2.

[0160] Optionally, the first recessed region K2 includes a first recessed portion and a second recessed portion;

[0161] The first recessed portion is disposed on the first planarization layer 3011, and the second recessed portion is disposed on the passivation layer 3012;

[0162] The orthographic projection of the first recessed portion on the substrate and the orthographic projection of the second recessed portion on the substrate at least partially overlap.

[0163] In some embodiments, the first recessed region K2 can be formed by the first planarization layer 3011 and the passivation layer 3012, provided that the total thickness of the first planarization layer 3011 and the passivation layer 3012 at the first recessed region K2 is greater than zero and less than a first target thickness. Specifically, the first recessed region K2 may include a first recessed portion disposed on the first planarization layer 3011 and a second recessed portion disposed on the passivation layer 3012. The overlapping portion of the projections of the first recessed portion and the second recessed portion has a first overlapping region J1 with the first orthographic projection corresponding to the first anode 2011, causing the first anode 2011 to collapse in the first recessed region K2.

[0164] Figure 12 illustrates, exemplarily, a third microscopic topography diagram of the anode edge of a display panel provided in an embodiment of this application. As shown in Figure 12, the SD1 layer and the SD2 layer include an HPLN1 layer and a PVX layer. The SD1 layer and the SD2 layer are electrically connected through an HPLN1 via. The PVX layer at the HPLN1 via is removed, and the edge of the first anode 2011 collapses at the HPLN1 via.

[0165] As shown in Figure 12, a first recessed portion is formed on the HPLN1 layer, and the thickness of the HPLN1 layer in the first recessed portion is less than the thickness of the HPLN1 layer on the side of the first anode 2011 closest to the substrate. A second recessed portion is formed on the PVX layer, which is a via on the PVX layer, i.e., the PVX layer at the second recessed portion is removed. At the first recessed region K2, the SD1 layer and SD2 layer are isolated by the thinned HPLN1 layer. At the first recessed region K2, the SD2 layer and PLN2 layer, which are sequentially stacked on the first insulating layer 301 away from the substrate, collapse, causing the edge of the first anode 2011 to collapse at the first recessed region K2. This improves the flatness of the first anode 2011, reduces color shift differences in the display panel, and thus improves the display effect of the display panel.

[0166] In this embodiment, the first recessed region K2 may include a first recessed portion on the first planarization layer 3011 and a second recessed portion on the passivation layer 3012. Since the orthogonal projection of the first recessed portion on the substrate and the orthogonal projection of the second recessed portion on the substrate overlap at least partially, the first recessed region K2 can be formed by the first planarization layer 3011 and the passivation layer 3012 together, causing the first anode 2011 to collapse in the first recessed region K2, thereby improving the anode planarity.

[0167] Optionally, the first recessed area K2 is disposed on the second insulating layer 302;

[0168] At the first recessed region K2, the thickness of the second insulating layer 302 is greater than zero and less than the thickness of the second target.

[0169] The second target thickness is the thickness of the second insulating layer 302 corresponding to the surrounding area of ​​the first recessed region K2.

[0170] In some embodiments, the first recessed region K2 can be a recessed area formed on the second insulating layer 302. At the first recessed region K2, the thickness of the second insulating layer 302 is not zero, that is, the thickness of the first insulating layer 301 is greater than zero, so that the second conductive layer 102 and the first anode 2011 are insulated and isolated at the first recessed region K2, thus preventing short circuits between the second conductive layer 102 and the first anode 2011. At the first recessed region K2, the thickness of the second insulating layer 302 is less than the second target thickness, making the thickness of the second insulating layer 302 thinner than the surrounding area. This causes the first anode 2011 on the second insulating layer 302 to collapse in the first recessed region K2, causing the first anode 2011 to tilt towards one side of the first recessed region K2.

[0171] The peripheral region of the first recessed region K2 includes the area formed by the second insulating layer 302 around the first recessed region K2 in a direction parallel to the substrate. For example, if the first recessed region K2 is a through hole, then the periphery of the first recessed region K2 is the area formed by the first insulating layer 301 surrounding the through hole.

[0172] In this embodiment, when the first recessed region K2 is disposed on the second insulating layer 302, since the thickness of the second insulating layer 302 at the first recessed region K2 is greater than zero and less than the second target thickness, where the second target thickness is the thickness of the region of the second insulating layer 302 corresponding to the orthographic projection of the first anode 2011 onto the second insulating layer 302, the first anode 2011 can be collapsed at the first recessed region K2, and the driving circuit layer and the first anode 2011 are insulated and isolated.

[0173] Optionally, the second insulating layer 302 includes a second planarization layer; the first recessed region K2 is disposed on the second planarization layer;

[0174] At the first depression region K2, the thickness of the second flattening layer is greater than zero and less than the thickness of the second target layer.

[0175] In some embodiments, the second insulating layer 302 may be a second planarization layer (PLN2) disposed on the second conductive layer 102 in a direction away from the substrate, and the first recessed region K2 is disposed on the second planarization layer.

[0176] At the first recessed region K2, the thickness of the second planarization layer is greater than zero, which insulates the second conductive layer 102 and the first anode 2011 from short circuit at the first recessed region K2. At the first recessed region K2, the thickness of the second planarization layer is less than the second target thickness, which makes the second planarization layer thinner than the surrounding area, causing the first anode 2011 to collapse at the first recessed region K2 and tilt towards the first recessed region K2.

[0177] Figure 13 illustrates, exemplarily, a fourth microscopic topography diagram of the anode edge of a display panel provided in an embodiment of this application. As shown in Figure 13, the SD1 layer and the SD2 layer include a PLN1 layer and a PVX layer. The SD1 layer and the SD2 layer are electrically connected through a PLN1 via. The PVX layer at the PLN1 via is removed, and the edge of the first anode 2011 collapses at the PLN1 via.

[0178] As shown in Figure 13, a first recessed region is formed on the HPLN2 layer, and the thickness of the HPLN2 layer in the first recessed region K2 is less than the thickness of the HPLN2 layer on the side of the first anode 2011 closest to the substrate. The first insulating layer 301 includes a PLN1 layer and a PVX layer. At the first recessed region K2, the SD2 layer and the first anode 2011 are isolated by the thinned HPLN2 layer. At the first recessed region K2, the edge of the first anode 2011 collapses. In this way, the flatness of the first anode 2011 can be improved, the color shift difference of the display panel can be reduced, thereby improving the display effect of the display panel.

[0179] In this embodiment, since the first recessed region K2 is disposed on the second planarization layer, the thickness of the second planarization layer at the first recessed region K2 is greater than zero and less than the second target thickness. In this way, the first anode 2011 can be collapsed at the first recessed region K2, and the driving circuit layer and the first anode 2011 are insulated and isolated. The second planarization layer can play the role of insulation and planarization.

[0180] Optionally, the first recessed region K2 includes a third recessed portion and a fourth recessed portion;

[0181] The third recessed portion is provided on the first insulating layer 301, and the fourth recessed portion is provided on the second insulating layer 302;

[0182] The orthographic projection of the third recessed portion on the substrate and the orthographic projection of the fourth recessed portion on the substrate at least partially overlap;

[0183] At the third recessed portion, the thickness of the first insulating layer 301 is greater than zero; at the fourth recessed portion, the thickness of the second insulating layer 302 is greater than zero.

[0184] At the first recessed region K2, the total thickness of the driving circuit layer is less than the thickness of the driving circuit layer corresponding to the surrounding area of ​​the first recessed region K2.

[0185] In some embodiments, the first recessed region K2 can be formed jointly by the first insulating layer 301 and the second insulating layer 302. Specifically, the first recessed region K2 includes a third recessed portion disposed on the first insulating layer 301 and a fourth recessed portion disposed on the second insulating layer 302. At the third recessed portion, the thickness of the first insulating layer 301 is greater than zero, thus isolating the first conductive layer 101 and the second conductive layer 102 by the first insulating layer 301, preventing short circuits between the first conductive layer 101 and the second conductive layer 102. At the fourth recessed portion, the thickness of the second insulating layer 302 is greater than zero, thus isolating the driving circuit layer and the first anode 2011 by the second insulating layer 302, preventing short circuits between the driving circuit layer and the first anode 2011.

[0186] The surrounding area of ​​the first recessed region K2 includes the area formed by the driving circuit layer around the first recessed region K2 in a direction parallel to the substrate. At the first recessed region K2, the total thickness of the driving circuit layer is less than the thickness of the driving circuit layer in the surrounding area.

[0187] The orthographic projection of the third recessed portion on the substrate and the orthographic projection of the fourth recessed portion on the substrate at least partially overlap, causing the first anode 2011 to collapse in the first recessed region K2.

[0188] In some embodiments, the formation of the third recessed portion and / or the fourth recessed portion includes, but is not limited to, opening holes in the insulating layer or thinning the insulating layer. If the insulating layer includes a multilayer structure, such as an insulating layer including a planarization layer and a passivation layer 3012, a combination of through holes and insulating layer thinning can be used, but the insulating material at the first recessed area K2 needs to be retained to ensure that the insulation is not damaged.

[0189] In this embodiment, the first recessed region K2 includes a third recessed portion on the first insulating layer 301 and a fourth recessed portion on the second insulating layer 302. The orthographic projections of the third recessed portion and the fourth recessed portion on the substrate at least partially overlap. At the third recessed portion, the thickness of the first insulating layer 301 is greater than zero. At the fourth recessed portion, the thickness of the second insulating layer 302 is greater than zero. At the first recessed region K2, the total thickness of the driving circuit layer is less than the thickness of the driving circuit layer region corresponding to the first orthographic projection. Thus, the first recessed region K2 can be formed jointly by the first planarization layer 3011 and the passivation layer 3012. At the third recessed portion, the first conductive layer 101 and the second conductive layer 102 are isolated by the first insulating layer 301. At the fourth recessed portion, the driving circuit layer and the first anode 2011 are isolated by the second insulating layer 302, causing the first anode 2011 to collapse in the first recessed region K2, improving anode planarity.

[0190] In some embodiments, the second overlapping region J2 is located on the side of the first overlapping region J1 near the center of the first orthographic projection. Without the first recessed region K2, the first anode 2011 will collapse at the first via K1, causing the first anode 2011 to tilt towards one side of the first via K1, with the tilt direction being the side of the first overlapping region J1 away from the center of the first orthographic projection. In a display panel provided by this application embodiment, the first recessed region K2 can be located on the opposite side of the first via K1. For example, the second overlapping region J2 is located on the side of the first overlapping region J1 near the center of the first orthographic projection. This causes the first anode 2011 to collapse at the first recessed region K2, and the first anode 2011 to tilt towards one side of the first recessed region K2, thereby improving the flatness of the first anode 2011.

[0191] Optionally, multiple light-emitting elements are arranged along a first direction to form multiple rows of light-emitting elements; or multiple light-emitting elements are arranged along a second direction to form multiple columns of light-emitting elements.

[0192] The first overlapping region J1 and the second overlapping region J2 are located in the first direction or the second direction;

[0193] The area of ​​the first overlapping region J1 is approximately equal to the area of ​​the second overlapping region J2.

[0194] In some embodiments, multiple light-emitting elements are arranged along a first direction to form multiple rows of light-emitting elements, where the first direction represents the row direction of pixels; multiple light-emitting elements are arranged along a second direction to form multiple columns of light-emitting elements, where the second direction represents the column direction of pixels.

[0195] If, in the pixel column direction, one side of the first anode 2011 has a first via K1 while the other side does not, the first anode 2011 will tilt towards the side with the first via K1, resulting in an asymmetrical color shift trajectory of the first anode 2011 in the pixel column direction. This increases the objective value of the color shift difference, causing a visual color difference in the pixel column direction. An embodiment of this application provides a display panel that can add a first recessed area K2 in the pixel column direction. The third orthographic projection of the first recessed area K2 on the substrate and the first orthographic projection of the first anode 2011 on the substrate have a second overlapping area J2, and the area of ​​the first overlapping area J1 is approximately equal to the area of ​​the second overlapping area J2.

[0196] Since the area of ​​the first overlapping region J1 is approximately equal to the area of ​​the second overlapping region J2, the first overlapping region J1 and the second overlapping region J2 are approximately symmetrical in the first direction. This makes the degree of collapse of the first anode 2011 in the first recessed region K2 comparable to the degree of collapse at the first via K1. This avoids the problem of the first anode 2011 tilting only towards the first via K1 in the pixel column direction, improving the flatness of the first anode 2011, enhancing the color shift symmetry in the pixel column direction of the display panel, and reducing visual color differences. It should be noted that "approximately equal areas" includes the case where the area of ​​the first overlapping region J1 is exactly equal to the area of ​​the second overlapping region J2, and the case where the difference between the two is less than 10% of their average value.

[0197] Similarly, the via asymmetry problem in the pixel row direction can be improved by adding a first recessed area K2 in the pixel row direction. The first overlapping area J1 and the second overlapping area J2 are located in the pixel row direction, and the area of ​​the first overlapping area J1 is approximately equal to the area of ​​the second overlapping area J2. This can improve the flatness of the first anode 2011, improve the color shift symmetry in the pixel row direction of the display panel, and reduce visual color differences.

[0198] In this embodiment, if the first overlapping region J1 and the second overlapping region J2 are located in the first direction, since the area of ​​the first overlapping region J1 is approximately equal to the area of ​​the second overlapping region J2, the first overlapping region J1 and the second overlapping region J2 are approximately symmetrical in the first direction. This can improve the flatness of the first anode 2011, improve the color shift symmetry of the display panel in the first direction, and reduce the visual color difference in the first direction. Similarly, if the first overlapping region J1 and the second overlapping region J2 are located in the second direction, the first overlapping region J1 and the second overlapping region J2 can be made approximately symmetrical in the second direction, which can improve the flatness of the first anode 2011, improve the color shift symmetry of the display panel in the second direction, and reduce the visual color difference in the second direction.

[0199] Optionally, the first anode 2011 includes a first edge and a second edge disposed opposite to each other along a first direction or a second direction;

[0200] The first overlapping region J1 is close to the first edge, and the vertical distance between the center of the first overlapping region J1 and the first edge is the first distance;

[0201] The second overlapping region J2 is close to the second edge, and the vertical distance between the center of the second overlapping region J2 and the second edge is the second distance;

[0202] The first distance and the second distance are approximately equal.

[0203] In some embodiments, the first overlapping region J1 and the second overlapping region J2 located in the first direction or the second direction are approximately symmetrical, such that the degree of collapse of the first anode 2011 in the first recessed region K2 is comparable to the degree of collapse at the first via K1, which can improve the flatness of the first anode 2011 and thus improve the color shift symmetry.

[0204] Specifically, the first overlapping region J1 and the second overlapping region J2 are located in a first direction. The first anode 2011 includes a first edge and a second edge disposed opposite to each other along the first direction. The first overlapping region J1 is close to the first edge, and the vertical distance between the center of the first overlapping region J1 and the first edge is a first distance. The second overlapping region J2 is close to the second edge, and the vertical distance between the center of the second overlapping region J2 and the second edge is a second distance. Since the first distance and the second distance are approximately equal, and the areas of the first overlapping region J1 and the second overlapping region J2 are approximately equal, the first overlapping region J1 and the second overlapping region J2 are approximately symmetrical in the first direction. This can improve the color shift symmetry in the first direction and reduce the visual color difference in the first direction.

[0205] Similarly, the first overlapping region J1 and the second overlapping region J2 are located in the second direction. The first anode 2011 includes a first edge and a second edge disposed opposite to each other along the second direction. By setting the distance between the first overlapping region J1 and the first edge, and the distance between the second overlapping region J2 and the second edge, the first overlapping region J1 and the second overlapping region J2 can be made approximately symmetrical in the second direction. This can improve the color shift symmetry in the second direction and reduce the visual color difference in the second direction. It should be noted that the above-mentioned "approximately equal distances" includes the case where the first distance and the second distance are completely equal, and the case where the difference between the two is less than 1 micrometer.

[0206] Figure 14 exemplarily illustrates one of the schematic diagrams of the anode and via positions of a display panel provided in an embodiment of this application. The first anode 2011 can be the G pixel anode. Comparing Figure 14 and Figure 6, in the pixel column direction (UD direction), a first recessed area K2 is added to the U-side position symmetrical to the PLN1 via on the D side of the G pixel, as shown in Figure 14. The first edge is the D-side edge of the G pixel, and the second edge is the U-side edge of the G pixel. The first overlapping area J1 is close to the D-side edge of the G pixel, and the second overlapping area J2 is close to the U-side edge of the G pixel. The distances of the two from the edges are approximately equal, that is, the first distance and the second distance are approximately equal, making the first overlapping area J1 and the second overlapping area J2 in the UD direction approximately symmetrical. In this way, the anode flatness in the UD direction can be improved.

[0207] In this embodiment, the first anode 2011 includes a first edge and a second edge disposed opposite to each other along a first direction or a second direction. Since the first overlapping region J1 is close to the first edge, the vertical distance between the center of the first overlapping region J1 and the first edge is a first distance. Similarly, the second overlapping region J2 is close to the second edge, and the vertical distance between the center of the second overlapping region J2 and the second edge is a second distance. The first distance and the second distance are approximately equal. This makes the first overlapping region J1 and the second overlapping region J2 approximately symmetrical along the first or second direction, improving the flatness of the first anode 2011, thereby improving color shift symmetry and reducing visual color differences.

[0208] Optionally, the vertical distance between the center of the first overlapping region J1 and the first straight line is the third distance; the vertical distance between the center of the second overlapping region J2 and the second straight line is the fourth distance; the third distance and the fourth distance are approximately equal.

[0209] The first straight line is a straight line perpendicular to the first direction and passing through the center of the first orthographic projection, or the first straight line is a straight line perpendicular to the second direction and passing through the center of the first orthographic projection.

[0210] In some embodiments, the first overlapping region J1 and the second overlapping region J2 located in the first direction or the second direction are approximately symmetrical, such that the degree of collapse of the first anode 2011 in the first recessed region K2 is comparable to the degree of collapse at the first via K1, which can improve the flatness of the first anode 2011 and thus improve the color shift symmetry.

[0211] Specifically, the first overlapping region J1 and the second overlapping region J2 are located in the first direction. The first straight line is perpendicular to the first direction and passes through the center of the first orthographic projection. The perpendicular distance between the center of the first overlapping region J1 and the first straight line is the third distance; the perpendicular distance between the center of the second overlapping region J2 and the second straight line is the fourth distance. Since the third distance and the fourth distance are approximately equal, and the areas of the first overlapping region J1 and the second overlapping region J2 are approximately equal, the first overlapping region J1 and the second overlapping region J2 are approximately symmetrical in the first direction. This can improve the color shift symmetry in the first direction and reduce the visual color difference in the first direction.

[0212] Similarly, the first overlapping region J1 and the second overlapping region J2 are located in the second direction. The first straight line is perpendicular to the second direction and passes through the center of the first orthographic projection. By setting the distance between the first overlapping region J1 and the first straight line, and the distance between the second overlapping region J2 and the second straight line, the first overlapping region J1 and the second overlapping region J2 can be made approximately symmetrical in the second direction. This can improve the color shift symmetry in the second direction and reduce the visual color difference in the second direction. It should be noted that the above-mentioned "approximately equal distances" includes the case where the third distance and the fourth distance are completely equal, and the case where the difference between the two is less than 1 micrometer.

[0213] For example, as shown in Figure 14, the first anode 2011 can be the anode of the R pixel. In the UD direction, there are two PLN1 vias on the U side of the R pixel, and the second orthographic projection of the PLN1 vias on the substrate and the first orthographic projection of the R pixel anode on the substrate have a first overlapping region J1. A first recessed region K2 can be added at the symmetrical D-side position of each of the two PLN1 vias on the U side of the R pixel in the UD direction. The third orthographic projection of the first recessed region K2 on the substrate and the first orthographic projection have a second overlapping region J2, and the first overlapping region J1 and the second overlapping region J2 in the UD direction are approximately symmetrical. In this way, the anode flatness in the UD direction of the R pixel can be improved. For the PLN1 vias on the D side of the B pixel of the display panel shown in Figure 14, the anode flatness can be improved by adding the first recessed region K2 in the same way, which will not be elaborated here.

[0214] In this embodiment, the vertical distance between the center of the first overlapping region J1 and the first straight line is the third distance, and the vertical distance between the center of the second overlapping region J2 and the second straight line is the fourth distance. The first straight line is a straight line perpendicular to the first direction and passing through the center of the first orthographic projection, or the first straight line is a straight line perpendicular to the second direction and passing through the center of the first orthographic projection. Since the third distance and the fourth distance are approximately equal, the first overlapping region J1 and the second overlapping region J2 located in the first direction or the second direction can be made approximately symmetrical, which can improve the flatness of the first anode 2011, thereby improving the color shift symmetry.

[0215] Optionally, the plurality of light-emitting elements further includes a second light-emitting element 202; the first insulating layer 301 further includes a second via K3 and a third via K4;

[0216] The first conductive layer 101 is electrically connected to the second conductive layer 102 through the second via K3 and the third via K4, respectively.

[0217] The second anode of the second light-emitting element 202 has a third overlapping region J3 on the substrate and the fifth orthogonal projection of the second via K3 on the substrate. The fourth orthogonal projection of the second anode and the sixth orthogonal projection of the third via K4 on the substrate have a fourth overlapping region J4.

[0218] The area of ​​the third overlapping region J3 is approximately equal to the area of ​​the fourth overlapping region J4.

[0219] In some embodiments, multiple pixel units are arrayed on the substrate, and each pixel unit includes at least a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel is configured to emit light of a first color, the second sub-pixel is configured to emit light of a second color, and the third sub-pixel is configured to emit light of a third color. The first color can be red, the second color can be green, and the third color can be blue. This is merely an example, and the embodiments of this application do not impose limitations.

[0220] The present application provides a display panel in which the first light-emitting element 201 can be the light-emitting element of any sub-pixel in the pixel unit, and the second light-emitting element 202 can also be the light-emitting element of any sub-pixel in the pixel unit. That is, the first light-emitting element 201 and the second light-emitting element 202 can be the same or different, and the present application does not limit this.

[0221] In some embodiments, the second light-emitting element 202 includes a second anode, an organic light-emitting layer, and a second cathode sequentially stacked in a direction away from the substrate. A third overlapping region J3 and a fourth overlapping region J4 are located in the first direction. To improve the flatness of the second anode in the first direction, the areas of the third overlapping region J3 and the fourth overlapping region J4 are approximately equal, making them approximately symmetrical in the first direction. This ensures that the degree of collapse of the second anode at the second via K3 and the third via K4 is comparable, improving the symmetry of the second anode in the first direction and thus improving the color shift symmetry in the second direction.

[0222] The same applies to the second direction, and will not be elaborated further here. It should be noted that the above "approximately equal areas" includes the case where the areas of the third overlapping region J3 and the fourth overlapping region J4 are completely equal, as well as the case where the difference between the two is less than 10% of their average.

[0223] Figure 15 exemplarily illustrates a second schematic diagram of the anode and via positions of a display panel according to an embodiment of this application. As shown in Figure 15, the second anode of the second light-emitting element 202 can be a G-pixel anode. In the pixel row direction, there are two PLN1 vias on both sides of the G-pixel, a second via K3 and a third via K4. The fifth and sixth orthographic projections of the second via K3 and the third via K4 on the substrate have a third overlapping region J3 and a fourth overlapping region J4 with the orthographic projection of the G-pixel anode on the substrate, respectively. The areas of the third overlapping region J3 and the fourth overlapping region J4 are approximately equal. In this way, the degree of collapse of the G-pixel anode at the second via K3 and the third via K4 can be made comparable, which can improve the flatness of the G-pixel anode in the second direction, thereby improving the color shift symmetry of the display panel.

[0224] In this embodiment, regarding the positional relationship between the second light-emitting element 202 and the second via K3 and the third via K4, the fourth orthographic projection of the second anode of the second light-emitting element 202 on the substrate and the fifth orthographic projection of the second via K3 on the substrate have a third overlapping region J3, and the fourth orthographic projection of the fourth orthographic projection of the third via K4 on the substrate have a fourth overlapping region J4. Since the areas of the third overlapping region J3 and the fourth overlapping region J4 are approximately equal, the third overlapping region J3 and the fourth overlapping region J4 are approximately symmetrical in the first or second direction, which can improve the anode flatness and thus improve the color shift symmetry of the display panel.

[0225] Optionally, the third overlapping region J3 and the fourth overlapping region J4 are symmetrically distributed within the fourth orthographic projection.

[0226] In some embodiments, the fourth orthographic projection of the second anode onto the substrate is symmetrical, for example, the fourth orthographic projection is symmetrical about a first direction and / or a second direction, then the third overlapping region J3 and the fourth overlapping region J4 are symmetrically distributed within the fourth orthographic projection. Specifically, the third overlapping region J3 and the fourth overlapping region J4 may be symmetrical about the first direction and / or the second direction within the fourth orthographic projection.

[0227] For example, as shown in Figure 15, the second anode can be a B-pixel anode. The orthographic projection of the B-pixel anode onto the substrate is symmetrical. Six PLN1 vias are included on the side of the B-pixel anode closest to the substrate. The orthographic projection of each PLN1 via onto the substrate overlaps with the orthographic projection of the B-pixel anode onto the substrate, and the areas of each overlapping area are approximately equal. These overlapping areas are symmetrically distributed within the fourth orthographic projection corresponding to the B-pixel anode. This ensures that the degree of collapse of the B-pixel anode at each PLN1 via is comparable, improving the anode flatness of the B-pixel and thus enhancing the color shift symmetry of the display panel.

[0228] In this embodiment, since the third overlapping region J3 and the fourth overlapping region J4 are symmetrically distributed in the fourth orthographic projection, the degree of collapse of the second anode at the second via K3 and the third via K4 is comparable, which can improve the flatness of the anode and thus improve the color shift symmetry of the display panel.

[0229] In some embodiments, the first signal line may include traces of the source and drain terminals of each transistor in the sub-pixel driving circuit. The first signal line is disposed on the same layer as the first conductive layer 101, and the first signal line and the first conductive layer 101 are made of the same conductive material; that is, the traces of the source and drain terminals are disposed on the first conductive layer 101. The first signal line may include data lines, power lines, and other signal lines of the sub-pixel driving circuit. The second signal line is disposed on the same layer as the second conductive layer 102, and the second signal line and the second conductive layer 102 are made of the same conductive material; that is, data lines, power lines, and other signal lines are disposed on the second conductive layer 102.

[0230] In some embodiments, the conductive layer of the driving circuit layer can be a source / drain metal layer (SD), which can be a multilayer structure, such as a 2SD or 3SD structure. A 2SD structure includes an SD1 layer and an SD2 layer, which are stacked sequentially in a direction away from the substrate. The SD1 layer can serve as the source and drain of each transistor in the sub-pixel driving circuit, and signal lines such as data lines and power lines can be disposed on the SD2 layer. This is merely an example, and the embodiments of this application do not impose limitations.

[0231] Optionally, the display panel includes a display area and a bonding area located on one side of the display area; the display panel includes multiple data signal lines, multiple first connection lines (FIP1) and multiple second connection lines (FIP2);

[0232] A first connecting line (FIP1) is disposed on the first conductive layer; a data signal line and a second connecting line (FIP2) are disposed on the second conductive layer; the first connecting line (FIP1), the second connecting line (FIP2), and the data signal line are located in the display area;

[0233] The first connecting line (FIP1) is electrically connected to the data signal line through the first connecting hole (V1), and the first connecting line (FIP1) is electrically connected to the second connecting line (FIP2) through the second connecting hole (V2); the second connecting line (FIP2) is also electrically connected to the lead wire of the bonding area;

[0234] The first via K1 includes a first connecting hole (V1) and / or a second connecting hole (V2).

[0235] In some embodiments, the first via K1 can be a first connecting hole (V1) connecting the first connecting line (FIP1) and the data signal line. The first via K1 can also be a second connecting hole (V2) connecting the first connecting line (FIP1) and the second connecting line (FIP2). This application does not limit the specific via K1. When the orthographic projection of the first connecting hole (V1) or the second connecting hole (V2) on the substrate overlaps with the orthographic projection of the sub-pixel anode on the substrate, the sub-pixel anode may collapse in the first connecting hole (V1) or the second connecting hole (V2), causing the sub-pixel anode to tilt towards the side with the hole, affecting the anode flatness. This can lead to inconsistent brightness attenuation between the sub-pixel and other sub-pixels, resulting in asymmetrical color shift trajectories on the display panel, increased objective color shift difference (colorshift2), and perceived color differences by the user.

[0236] For example, in the FIP region, at the junction of the first connecting line (FIP1) and the second connecting line (FIP2), the second connecting hole (V2) is a first via K1. The second orthographic projection of the first via K1 on the substrate and the first orthographic projection of the first anode 2011 of the first light-emitting element 201 on the substrate have a first overlap area, which will cause the first anode 2011 to collapse at the first via K1. The display panel provided in this application embodiment can provide a first recessed area K2 in the first insulating layer 301 and / or the second insulating layer 302 to improve the flatness of the first anode 2011 and avoid color shift differences in the display panel caused by the second connecting hole (V2) at the junction of the first connecting line (FIP1) and the data signal line (FIP2). Similarly, the first connecting hole (V1) of the first connecting line (FIP1) and the data signal line can also improve the anode flatness by providing a first recessed area K2. The first recessed area K2 can refer to the implementation method in the foregoing embodiment, and will not be repeated here.

[0237] In some embodiments, at the junction of the first connecting line (FIP1) and the second connecting line (FIP2), the seventh and eighth orthographic projections of the first connecting line (FIP1) and the second connecting line (FIP2) respectively have a fifth overlapping region. The orthographic projection of the second connecting hole (V2) on the substrate also overlaps with the fifth overlapping region, so that the first connecting line (FIP1) and the second connecting line (FIP2) are electrically connected through the second connecting hole (V2).

[0238] As shown in Figure 2, the first connecting line (FIP1) includes a first end and a second end in the row direction. The first end of the first connecting line (FIP1) is electrically connected to the data signal line through a first connecting hole (V1). The second end of the first connecting line (FIP1) is electrically connected to the first end of the second connecting line (FIP2) through a second connecting hole (V2). The second end of the second connecting line (FIP2) is electrically connected to the lead wire of the bonding area. The second connecting line (FIP2) includes a first end and a second end in the column direction, wherein the end closer to the edge (B) of the display area is the second end of the second connecting line (FIP2).

[0239] In some embodiments, the data signal line may also be directly connected to the lead-out line of the bonding area without passing through the first connecting line (FIP1) and the second connecting line (FIP2). In addition, there is only one transition point for a first connecting line (FIP1) and a second connecting line (FIP2) in the row direction, and they are electrically connected only through the second connecting hole (V2) at the transition point.

[0240] In this embodiment, the display panel includes a display area and a bonding area. The display area and the bonding area are connected by a first connecting line (FIP1), a second connecting line (FIP2), and a data signal line (FIP2) in the display area, and a lead wire in the bonding area. The first via K1 can be either a first connecting hole (V1) or a second connecting hole (V2). In this embodiment, by providing a first recessed area K2 in the first insulating layer 301 and / or the second insulating layer 302, the flatness of the first anode 2011 can be improved, and color shift differences in the display panel caused by the first connecting hole (V1) and / or the second connecting hole (V2) can be avoided, thereby improving the display effect of the display panel.

[0241] As shown in Figure 17, this application provides a display device including a display panel as described in the foregoing embodiments.

[0242] The display device provided in this application embodiment can achieve the same technical effect as the display panel in the foregoing embodiment. To avoid repetition, it will not be described again here.

[0243] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0244] Although alternative embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make further changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the alternative embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0245] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes the element.

[0246] The above provides a detailed description of the display panel and display device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

[0247] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0248] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this application. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0249] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0250] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0251] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, wherein, The display panel comprises a substrate, a driving circuit layer on the substrate, and a plurality of light emitting elements on the driving circuit layer away from the substrate; The driving circuit layer comprises at least a first conductive layer and a second conductive layer; A first insulating layer is arranged between the first conductive layer and the second conductive layer; The first insulating layer comprises a first via hole; The first conductive layer is electrically connected with the second conductive layer through the first via hole; The plurality of light emitting elements comprises at least a first light emitting element; A second insulating layer is arranged between the driving circuit layer and a first anode of the first light emitting element; The first insulating layer and / or the second insulating layer is provided with a first recessed area; At the first recessed area, the first conductive layer and the second conductive layer are separated by the first insulating layer, and the driving circuit layer and the first anode are separated by the second insulating layer; A first projection of the first anode on the substrate and a second projection of the first via hole on the substrate have a first overlapping area; The first projection and a third projection of the first recessed area on the substrate have a second overlapping area; and The second projection and the third projection have no overlapping area.

2. The display panel of claim 1, wherein, The first recessed area is arranged on the first insulating layer; and At the first recessed area, the thickness of the first insulating layer is greater than zero and less than a first target thickness; The first target thickness is the thickness of the first insulating layer corresponding to a peripheral area of the first recessed area.

3. The display panel of claim 2, wherein, The first insulating layer comprises a first planar layer and a passivation layer on the first planar layer away from the substrate; and The first recessed area is arranged on the first planar layer and / or the passivation layer.

4. The display panel of claim 3, wherein, The first recessed area is arranged on the first planar layer; and At the first recessed area, the first conductive layer and the second conductive layer are separated by the passivation layer.

5. The display panel of claim 4, wherein, The first recessed area is a first through hole on the first planar layer.

6. The display panel of claim 3, wherein, The first recessed area is arranged on the passivation layer; and At the first recessed area, the first conductive layer and the second conductive layer are separated by the first planar layer.

7. The display panel of claim 6, wherein, The first recessed area is a second through hole on the passivation layer.

8. The display panel of claim 3, wherein, The first recessed area comprises a first recessed part and a second recessed part; The first recessed part is arranged on the first planar layer, and the second recessed part is arranged on the passivation layer; And A projection of the first recessed part on the substrate and a projection of the second recessed part on the substrate at least partially overlap.

9. The display panel of claim 1, wherein, The first recessed area is arranged on the second insulating layer; and At the first recessed area, the thickness of the second insulating layer is greater than zero and less than a second target thickness; The second target thickness is the thickness of the second insulating layer corresponding to a peripheral area of the first recessed area.

10. The display panel of claim 9, wherein, The second insulating layer comprises a second planar layer; The first recessed area is arranged on the second planar layer; and At the first recessed area, the thickness of the second planar layer is greater than zero and less than the second target thickness.

11. The display panel of claim 1, wherein, The first recessed region comprises a third recessed portion and a fourth recessed portion; The third recessed portion is disposed on the first insulating layer, and the fourth recessed portion is disposed on the second insulating layer; A vertical projection of the third recessed portion on the substrate substrate at least partially overlaps with a vertical projection of the fourth recessed portion on the substrate substrate; At the third recessed portion, the thickness of the first insulating layer is greater than zero; At the fourth recessed portion, the thickness of the second insulating layer is greater than zero; And At the first recessed region, the total thickness of the driving circuit layer is less than the thickness of the driving circuit layer corresponding to the peripheral region of the first recessed region.

12. The display panel of any one of claims 1-11, wherein, The plurality of light emitting elements are arranged along a first direction to form a plurality of light emitting element rows; The plurality of light emitting elements are arranged along a second direction to form a plurality of light emitting element columns; The first overlap region and the second overlap region are located in the first direction or the second direction; and The area of the first overlap region is substantially equal to the area of the second overlap region.

13. The display panel of claim 12, wherein, The first anode comprises a first edge and a second edge oppositely arranged along the first direction or the second direction; The first overlap region is close to the first edge, and the vertical distance between the center of the first overlap region and the first edge is a first distance; The second overlap region is close to the second edge, and the vertical distance between the center of the second overlap region and the second edge is a second distance; and The first distance is substantially equal to the second distance.

14. The display panel of claim 12, wherein, The vertical distance between the center of the first overlap region and a first straight line is a third distance; The vertical distance between the center of the second overlap region and a second straight line is a fourth distance; and The third distance is substantially equal to the fourth distance; The first straight line is a straight line perpendicular to the first direction and passing through the center of the first vertical projection, or the first straight line is a straight line perpendicular to the second direction and passing through the center of the first vertical projection.

15. The display panel of any one of claims 1-11, wherein, The plurality of light emitting elements further comprise a second light emitting element; The first insulating layer further comprises a second via hole and a third via hole; The first conductive layer is electrically connected to the second conductive layer through the second via hole and the third via hole, respectively; A fourth vertical projection of the second anode of the second light emitting element on the substrate substrate and a fifth vertical projection of the second via hole on the substrate substrate form a third overlap region, and the fourth vertical projection and a sixth vertical projection of the third via hole on the substrate substrate form a fourth overlap region; and The area of the third overlap region is substantially equal to the area of the fourth overlap region.

16. The display panel of claim 15, wherein, The third overlap region and the fourth overlap region are symmetrically distributed within the fourth vertical projection.

17. The display panel of any one of claims 1-11, wherein, The display panel comprises a display area and a binding area located on one side of the display area; The display panel comprises a plurality of data signal lines, a plurality of first connection lines, and a plurality of second connection lines; The plurality of first connection lines are disposed on the first conductive layer; The plurality of data signal lines and the plurality of second connection lines are disposed on the second conductive layer; The plurality of first connection lines, the plurality of second connection lines, and the plurality of data signal lines are located in the display area; The first connection line is electrically connected with the data signal line through a first connection hole, and is electrically connected with the second connection line through a second connection hole; The second connection line is also electrically connected with the lead-out line of the binding area; and The first via hole includes the first connection hole, and / or the second connection hole. 18.The display panel of claim 1, wherein the driving circuit layer comprises a sub-pixel driving circuit, and transistors of the sub-pixel driving circuit are thin film transistors using low temperature poly-silicon. 19.The display panel of claim 1, wherein the second overlap area is located on one side of the first overlap area close to the center of the first orthographic projection. 20.The display panel of claim 3, wherein in the first recessed area, a total thickness of the first planar layer and the passivation layer is greater than zero and less than the first target thickness.

21. A display device, wherein, The display device comprises the display panel as claimed in any one of claims 1-20.

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