Current detection circuit and integrated circuit chip

Abstract

A current detection circuit and an integrated circuit chip. The current detection circuit comprises: a reference voltage generation circuit (100), which is used for generating a reference voltage; an offset voltage generation circuit (200), which is used for generating an offset voltage on the basis of the reference voltage, respectively generating a first intermediate voltage and a second intermediate voltage at a first output end and a second output end of the offset voltage generation circuit (200) on the basis of a received first input voltage and a received second input voltage, and respectively outputting a first output voltage and a second output voltage at the first output end and the second output end of the offset voltage generation circuit (200) after superposing the offset voltage; and a comparison circuit (300), which is used for comparing the first output voltage with the second output voltage, so as to output a current detection result. The current detection circuit at least has the following advantages: 1, not only can a dynamic current be detected, but a quiescent current can also be detected; 2, the requirements of a change in a common-mode level for an amplifier and a comparator are avoided; and 3, a high voltage is prevented from entering a chip.

Description

Current detection circuit and integrated circuit chip

[0001] The present application claims priority to the Chinese patent application No. 202410670197.3, filed on May 28, 2024, and entitled "A current detection circuit and integrated circuit chip", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of electronic technology, in particular to a current detection circuit and integrated circuit chip. BACKGROUND

[0003] Referring to FIG. 1, it is a circuit diagram of a current detection circuit in the related art. As shown in FIG. 1, the current detection circuit comprises a current source I1', which is configured to output a constant current; a resistor R1', a first end of the resistor R1' being electrically connected to an output end of the current source I1', and a second end of the resistor R1' being grounded; an amplifier A1', a positive input end of the amplifier A1' being electrically connected to the first end of the resistor R1', and a negative input end of the amplifier A1' being electrically connected to the second end of the resistor R1'; a voltage source E1', which is configured to output a reference voltage Vref'; a comparator A2', a positive input end of the comparator A2' being electrically connected to an output end of the amplifier A1', and a negative input end of the comparator A2' being electrically connected to an output end of the voltage source E1'; a NOT gate NOT1', an input end of the NOT gate NOT1' being electrically connected to an output end of the comparator A2'; a NOT gate NOT2', an input end of the NOT gate NOT2' being electrically connected to an output end of the NOT gate NOT1', and an output end of the NOT gate NOT2' being configured to output a current detection result Vout'.

[0004] When the current output by the current source I1' flows through the resistor R1', a voltage drop I1'xR1' is generated, that is, there is a voltage difference I1'xR1' between the positive input end and the negative input end of the amplifier A1'. The amplifier A1' amplifies the voltage difference I1'xR1' between the positive input end and the negative input end, and outputs a voltage I1'xR1'x A. Wherein, A is the amplification factor of the amplifier A1'. Further, the comparator A2' compares I1'xR1'x A with the reference voltage Vref' output by the voltage source E1', if I1'xR1'x A>Vref', then output 1, which represents that the current is detected; if I1'xR1'x A≤Vref', then output 0, which represents that the current is not detected. It can be understood that by setting the corresponding reference voltage Vref', the detection of any current value can be realized.

[0005] However, this scheme can only detect static current and cannot detect dynamic current. In addition, if the current to be detected is large, it will cause the common-mode voltage input by the amplifier and the comparator to be too large, and thus the voltage withstand requirement of the amplifier and the comparator will be increased.

[0006] It should be noted that the information disclosed in the background section of the present application is only intended to deepen the understanding of the general background of the present application and should not be regarded as acknowledging or implying in any form that the information constitutes prior art known to those skilled in the art. SUMMARY

[0007] The present application provides a current detection circuit and an integrated circuit chip, so as to solve the problem that only static current can be detected and dynamic current cannot be detected in the prior art, and the problem that the voltage resistance of an amplifier and a comparator is high.

[0008] In a first aspect, an embodiment of the present application provides a current detection circuit, comprising:

[0009] a reference voltage generation circuit configured to generate a reference voltage;

[0010] an offset voltage generation circuit configured to generate an offset voltage between a first output end and a second output end of the offset voltage generation circuit according to the reference voltage, generate a first intermediate voltage and a second intermediate voltage at the first output end and the second output end of the offset voltage generation circuit respectively according to a first input voltage and a second input voltage received, and output a first output voltage and a second output voltage at the first output end and the second output end of the offset voltage generation circuit respectively after superimposing the offset voltage;

[0011] a comparison circuit configured to receive the first output voltage and the second output voltage, compare the first output voltage and the second output voltage, and output a current detection result.

[0012] In a possible implementation manner, the reference voltage generation circuit comprises:

[0013] a first current source configured to output a first constant current;

[0014] a first resistor, a first end of the first resistor being electrically connected to an output end of the first current source, and a second end of the first resistor being grounded;

[0015] wherein a node between the first current source and the first resistor is configured to output the reference voltage.

[0016] In a possible implementation manner, the offset voltage generation circuit comprises:

[0017] an offset voltage generation sub-circuit configured to generate an offset voltage between a first output end and a second output end of the offset voltage generation circuit according to the reference voltage;

[0018] a voltage conversion sub-circuit, configured to generate a first intermediate voltage and a second intermediate voltage at a first output terminal and a second output terminal of the offset voltage generation circuit respectively according to a first input voltage and a second input voltage, wherein a voltage difference between the first input voltage and the second input voltage is positively correlated to a voltage difference between the first intermediate voltage and the second intermediate voltage.

[0019] In a possible implementation, the offset voltage generation sub-circuit comprises:

[0020] a first switch, a first terminal of the first switch being electrically connected to an output terminal of the reference voltage generation circuit;

[0021] a first capacitor, a first terminal of the first capacitor being electrically connected to a second terminal of the first switch, and a second terminal of the first capacitor being electrically connected to a first output terminal of the offset voltage generation sub-circuit;

[0022] a second switch, a first terminal of the second switch being electrically connected to a node between the first switch and the first capacitor, and a second terminal of the second switch being grounded;

[0023] a third switch, a first terminal of the third switch being electrically connected to the output terminal of the reference voltage generation circuit;

[0024] a second capacitor, a first terminal of the second capacitor being electrically connected to a second terminal of the third switch, and a second terminal of the second capacitor being electrically connected to a second output terminal of the offset voltage generation sub-circuit;

[0025] a fourth switch, a first terminal of the fourth switch being electrically connected to a node between the third switch and the second capacitor, and a second terminal of the fourth switch being grounded.

[0026] In a possible implementation, the voltage conversion sub-circuit comprises:

[0027] a third capacitor, a first terminal of the third capacitor being electrically connected to the first output terminal of the offset voltage generation sub-circuit;

[0028] a second resistor, a first terminal of the second resistor being electrically connected to a second terminal of the third capacitor;

[0029] a fourth capacitor, a first terminal of the fourth capacitor being electrically connected to a second terminal of the second resistor, and a second terminal of the fourth capacitor being electrically connected to the second output terminal of the offset voltage generation sub-circuit;

[0030] a first interface, the first interface being electrically connected to a node between the third capacitor and the second resistor, and configured to receive the first input voltage;

[0031] A second interface is electrically connected with a node between the second resistor and the fourth capacitor, and is configured to receive the second input voltage.

[0032] In a possible implementation, the comparison circuit includes:

[0033] An amplification sub-circuit is configured to receive the first output voltage and the second output voltage, and perform amplification processing on the first output voltage and the second output voltage.

[0034] A comparison sub-circuit is configured to compare the amplified first output voltage and the amplified second output voltage, and output a comparison result.

[0035] An output sub-circuit is configured to receive the comparison result, and output the current detection result.

[0036] In a possible implementation, the amplification sub-circuit includes:

[0037] An amplifier has a positive input end electrically connected with a first output end of the offset voltage generation circuit, and a negative input end electrically connected with a second output end of the offset voltage generation circuit, wherein a negative output end of the amplifier is configured to output the amplified first output voltage, and a positive output end of the amplifier is configured to output the amplified second output voltage.

[0038] In a possible implementation, the number of the amplifiers is N, and N≥2.

[0039] The positive input end of the first amplifier is electrically connected with the first output end of the offset voltage generation circuit, and the negative input end of the first amplifier is electrically connected with the second output end of the offset voltage generation circuit.

[0040] The positive input end of the i-th amplifier is electrically connected with the negative output end of the (i-1)-th amplifier, and the negative input end of the i-th amplifier is electrically connected with the positive output end of the (i-1)-th amplifier, wherein 2≤i≤N.

[0041] The negative output end of the last amplifier is configured to output the amplified first output voltage, and the positive output end of the last amplifier is configured to output the amplified second output voltage.

[0042] In a possible implementation, the amplifier includes:

[0043] A second current source is configured to output a second constant current.

[0044] A first transistor, a gate of the first transistor is a positive input terminal of the amplifier, a source of the first transistor is electrically connected with an output terminal of the second current source, and a drain of the first transistor is a negative output terminal of the amplifier;

[0045] A third resistor, a first end of the third resistor is electrically connected with the drain of the first transistor, and a second end of the third resistor is grounded;

[0046] A fifth switch, a first end of the fifth switch is electrically connected with the gate of the first transistor, and a second end of the fifth switch is electrically connected with the drain of the first transistor;

[0047] A second transistor, a gate of the second transistor is a negative input terminal of the amplifier, a source of the second transistor is electrically connected with the output terminal of the second current source, and a drain of the second transistor is a positive output terminal of the amplifier;

[0048] A fourth resistor, a first end of the fourth resistor is electrically connected with the drain of the second transistor, and a second end of the fourth resistor is grounded;

[0049] A sixth switch, a first end of the sixth switch is electrically connected with the gate of the second transistor, and a second end of the sixth switch is electrically connected with the drain of the second transistor.

[0050] In a possible implementation, the comparison sub-circuit comprises:

[0051] A comparator, a positive input terminal of the comparator is configured to receive the amplified first output voltage, a negative input terminal of the comparator is configured to receive the amplified second output voltage, and the comparator is configured to output the comparison result.

[0052] In a possible implementation, the output sub-circuit comprises:

[0053] A first NOT gate, an input terminal of the first NOT gate is electrically connected with an output terminal of the comparison sub-circuit;

[0054] A second NOT gate, an input terminal of the second NOT gate is electrically connected with an output terminal of the first NOT gate, and an output terminal of the second NOT gate is configured to output the current detection result.

[0055] In a possible implementation, the circuit further comprises:

[0056] A current conversion circuit, the current conversion circuit is configured to convert a static current into a dynamic current;

[0057] The offset voltage generation circuit is further configured to generate a first intermediate voltage and a second intermediate voltage at a first output terminal and a second output terminal of the offset voltage generation circuit respectively according to the received dynamic current, and output a first output voltage and a second output voltage at the first output terminal and the second output terminal of the offset voltage generation circuit respectively after superimposing the offset voltage.

[0058] In a possible implementation, the current conversion circuit comprises:

[0059] a current mirror, the current mirror comprising an input current sub-circuit and an output current sub-circuit, the output current sub-circuit being configured to generate an output current according to an input current in the input current sub-circuit;

[0060] an RC filter circuit, the input current circuit being electrically connected to the output current circuit through the RC filter circuit;

[0061] a control circuit, the control circuit being configured to control the input current sub-circuit and the output current sub-circuit to be turned on or turned off.

[0062] In a possible implementation, the input current sub-circuit comprises: a third current source configured to output a third constant current; a third transistor, a drain of the third transistor being electrically connected to an output terminal of the third current source, an emitter of the third transistor being grounded, and a gate of the third transistor being electrically connected to the drain of the third transistor.

[0063] The output current sub-circuit comprises: a fourth transistor, a drain of the fourth transistor being electrically connected to a second interface of the offset voltage generation circuit, the second interface being configured to input the second input voltage, and a source of the fourth transistor being grounded.

[0064] The RC filter circuit comprises: a fifth resistor, a first end of the fifth resistor being electrically connected to the gate of the third transistor; and a fifth capacitor, a first end of the fifth capacitor being electrically connected to a second end of the fifth resistor, and a second end of the fifth capacitor being grounded.

[0065] The control circuit comprises: a seventh switch, a first end of the seventh switch being electrically connected to the second end of the fifth resistor, and a second end of the seventh switch being electrically connected to the gate of the fourth transistor; and an eighth switch, a first end of the eighth switch being electrically connected to the gate of the fourth transistor, and a second end of the eighth switch being grounded.

[0066] In a second aspect, an embodiment of the present application provides an integrated circuit chip comprising the current detection circuit of any one of the first aspect.

[0067] The current detection circuit provided by the embodiment of the present application at least has the following advantages:

[0068] 1. It can detect both dynamic current and static current;

[0069] 2. It avoids the requirement of common mode level change to the amplifier and the comparator;

[0070] 3. It avoids high voltage entering the chip. BRIEF DESCRIPTION OF DRAWINGS

[0071] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described in the following are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative labor.

[0072] Fig. 1 is a circuit diagram of a current detection circuit in the related art;

[0073] Fig. 2 is a structural block diagram of a current detection circuit provided by an embodiment of the present application;

[0074] Fig. 3 is a structural block diagram of another current detection circuit provided by an embodiment of the present application;

[0075] Fig. 4A is a circuit diagram of a current detection circuit provided by an embodiment of the present application;

[0076] Fig. 4B is a circuit diagram of another current detection circuit provided by an embodiment of the present application;

[0077] Fig. 5 is a circuit diagram of another current detection circuit provided by an embodiment of the present application;

[0078] Fig. 6 is a circuit diagram of an amplifier provided by an embodiment of the present application;

[0079] Fig. 7 is a structural block diagram of another current detection circuit provided by an embodiment of the present application;

[0080] Fig. 8 is a structural block diagram of another current detection circuit provided by an embodiment of the present application;

[0081] Fig. 9 is a circuit diagram of a current conversion circuit provided by an embodiment of the present application;

[0082] Fig. 10 is a circuit diagram of another current detection circuit provided by an embodiment of the present application;

[0083] Fig. 11 is a structural block diagram of an integrated circuit chip provided by an embodiment of the present application. DETAILED DESCRIPTION

[0084] In order to better understand the technical solutions of the present application, the following will describe the embodiments of the present application in detail with reference to the drawings.

[0085] It should be noted that the described embodiments are merely a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0086] The terms used in the embodiments of the present application are merely for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0087] It should be understood that the term "and / or" used herein is merely to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in the present application generally represents an "or" relationship between the front and rear associated objects.

[0088] Referring to FIG. 2, a structural block diagram of a current detection circuit provided by the embodiments of the present application is shown. As shown in FIG. 2, the current detection circuit includes a reference voltage generation circuit 100, an offset voltage generation circuit 200 and a comparison circuit 300.

[0089] The reference voltage generation circuit 100 is configured to generate a reference voltage Vref. Specifically, as shown in FIGS. 4A and 4B, in a possible implementation, the reference voltage generation circuit 100 includes a first current source I1 and a first resistor R1. The first current source I1 is configured to output a first constant current, and the first end of the first resistor R1 is electrically connected to the output end of the first current source I1, and the second end of the first resistor R1 is grounded. The node between the first current source I1 and the first resistor R1 is configured to output the reference voltage Vref. It can be understood that the reference voltage Vref output by the reference voltage generation circuit 100 is I1 x R1. In the formula, "I1" represents the current value output by the first current source, and "R1" represents the resistance value of the first resistor.

[0090] It should be noted that the reference voltage generation circuit 100 in FIGS. 4A and 4B is only an exemplary description of the embodiments of the present application, and those skilled in the art can also use other circuit structures to generate the reference voltage Vref according to actual needs, which is not specifically limited in the embodiments of the present application.

[0091] The offset voltage generation circuit 200 is used to generate an offset voltage between its first and second output terminals based on a reference voltage Vref; and to generate a first intermediate voltage and a second intermediate voltage at its first and second output terminals respectively based on the received first and second input voltages, and to output a first output voltage and a second output voltage at its first and second output terminals respectively after superimposing the offset voltage. In other words, the first and second output voltages of the offset voltage generation circuit 200 are the voltage values ​​obtained by superimposing the first intermediate voltage and the offset voltage.

[0092] Specifically, as shown in Figure 3, in one possible implementation, the offset voltage generation circuit 200 includes an offset voltage generation sub-circuit 210 and a voltage conversion sub-circuit 220. The offset voltage generation sub-circuit 210 generates an offset voltage between the first and second output terminals of the offset voltage generation circuit 200 based on a reference voltage Vref. The voltage conversion sub-circuit 220 generates a first intermediate voltage and a second intermediate voltage at the first and second output terminals of the offset voltage generation circuit 200, respectively, based on the received first and second input voltages. It should be noted that the voltage difference between the first and second input voltages is positively correlated with the voltage difference between the first and second intermediate voltages.

[0093] Referring to Figures 4A and 4B, in one possible implementation, the offset voltage generation sub-circuit 210 (the part of the offset voltage generation circuit 200 excluding the voltage conversion sub-circuit 220) includes: a first switch S1, the first terminal of which is electrically connected to the output terminal of the reference voltage generation circuit 100; a first capacitor C1, the first terminal of which is electrically connected to the second terminal of the first switch S1, and the second terminal of the first capacitor C1 is electrically connected to the first output terminal A of the offset voltage generation sub-circuit 210; and a second switch S2, the first terminal of which is electrically connected to the first output terminal A of the offset voltage generation sub-circuit 210. A first switch S1 and a first capacitor C1 are electrically connected at a node; the second terminal of a second switch S2 is grounded. A third switch S3 has its first terminal electrically connected to the output terminal of the reference voltage generation circuit 100. A second capacitor C2 has its first terminal electrically connected to the second terminal of the third switch S3, and its second terminal is electrically connected to the second output terminal B of the offset voltage generation sub-circuit 210. A fourth switch S4 has its first terminal electrically connected to the node between the third switch S3 and the second capacitor C2, and its second terminal is grounded. It should be noted that the first and second output terminals of the offset voltage generation sub-circuit 210 are respectively the first and second output terminals of the offset voltage generation circuit 200.

[0094] For the convenience of understanding, the working principle of the offset voltage generating sub-circuit 210 is described in detail as follows.

[0095] Firstly, as shown in FIG. 4A, the first switch S1 and the fourth switch S4 are controlled to be closed, and the second switch S2 and the third switch S3 are controlled to be opened. In this state, the reference voltage generating circuit 100 provides the reference voltage Vref for the upper branch of the offset voltage generating sub-circuit 210; the lower branch of the offset voltage generating sub-circuit 210 is grounded, i.e. the voltage provided by the reference voltage generating circuit 100 for the lower branch of the offset voltage generating sub-circuit 210 is 0. That is, at this time, the voltage on the left side of the first capacitor C1 is Vref, i.e. I1xR1; the voltage on the left side of the second capacitor C2 is 0. In addition, since the voltage generated by the comparison circuit 300 at its first input end and second input end is V (the working principle of the comparison circuit 300 is described in detail below), in this state, the voltage on the right side of the first capacitor C1 and the second capacitor C2 is V.

[0096] Secondly, as shown in FIG. 4B, the first switch S1 and the fourth switch S4 are controlled to be opened, and the second switch S2 and the third switch S3 are controlled to be closed. In this state, the upper branch of the offset voltage generating sub-circuit 210 is grounded, i.e. the voltage provided by the reference voltage generating circuit 100 for the upper branch of the offset voltage generating sub-circuit 210 is 0, so that the voltage on the left side of the first capacitor C1 changes from I1xR1 to 0. Since the potential difference of the capacitor will not change abruptly, at this time, the voltage on the right side of the first capacitor C1 changes to V-I1xR1, i.e. the voltage at the first output end A of the offset voltage generating circuit 200 changes to V-I1xR1. At the same time, the reference voltage generating circuit 100 provides the reference voltage Vref, i.e. I1xR1, for the lower branch of the offset voltage generating sub-circuit 210, so that the voltage on the left side of the second capacitor C2 changes from 0 to I1xR1. Since the potential difference of the capacitor will not change abruptly, at this time, the voltage on the right side of the second capacitor C2 changes to V+I1xR1, i.e. the voltage at the second output end B of the offset voltage generating circuit 200 changes to V+I1xR1.

[0097] That is, the voltage at the first output end A of the offset voltage generating circuit 200 is pulled down by I1xR1, and the voltage at the second output end B of the offset voltage generating circuit 200 is pulled up by I1xR1, forming a potential difference of 2xI1xR1 between the first output end A and the second output end B of the offset voltage generating circuit 200, i.e. there is an offset voltage of 2xI1xR1 between the first output end A and the second output end B of the offset voltage generating circuit 200.

[0098] Please continue to refer to FIG. 4A and FIG. 4B, in a possible implementation, the voltage conversion sub-circuit 220 includes: a third capacitor C3, a first end of the third capacitor C3 is electrically connected with the first output end A of the offset voltage generation sub-circuit 210; a second resistor R2, a first end of the second resistor R2 is electrically connected with a second end of the third capacitor C3; a fourth capacitor C4, a first end of the fourth capacitor C4 is electrically connected with a second end of the second resistor R2, and a second end of the fourth capacitor C4 is electrically connected with the second output end B of the offset voltage generation sub-circuit 210; a first interface DSI, the first interface DSI is electrically connected with a node between the third capacitor C3 and the second resistor R2, and is used to receive a first input voltage; and a second interface DSI_0, the second interface DSI_0 is electrically connected with a node between the second resistor R2 and the fourth capacitor C4, and is used to receive a second input voltage.

[0099] In the working process, after the first interface DSI receives the first input voltage VDSI, due to the voltage division effect of the third capacitor C3, a first intermediate voltage generated at the first output end of the offset voltage generation circuit 200 is 1 / 2VDSI; correspondingly, after the second interface DSI_0 receives the second input voltage VDSI_0, due to the voltage division effect of the third capacitor C3, a second intermediate voltage generated at the second output end of the offset voltage generation circuit 200 is 1 / 2VDSI_0. It can be understood that the voltage difference between the first intermediate voltage and the second intermediate voltage is 1 / 2(VDSI-VDSI_0). That is to say, the voltage difference generated between the first output end A and the second output end B of the offset voltage generation circuit 200 by the first input voltage and the second input voltage is 1 / 2(VDSI-VDSI_0).

[0100] It should be noted that when the first interface DSI and the second interface DSI_0 do not have signal input, the voltage of the first interface DSI and the second interface DSI_0 remains unchanged, and the current input through the first interface DSI and the second interface DSI_0 is static current. Because of the "DC blocking and AC passing" characteristic of the capacitor, the static current input through the first interface DSI and the second interface DSI_0 will not cause the voltage change of the first output end A and the second output end B of the offset voltage generation circuit 200, that is, the offset voltage generation circuit 200 provided in the embodiment of the present application cannot detect static current. When the first interface DSI and the second interface DSI_0 have signal input, the input signal will cause the voltage change of the first interface DSI and the second interface DSI_0, and the current input through the first interface DSI and the second interface DSI_0 is dynamic current. Similarly, because of the "DC blocking and AC passing" characteristic of the capacitor, the dynamic current input through the first interface DSI and the second interface DSI_0 will not cause the voltage change of the first output end A and the second output end B of the offset voltage generation circuit 200, that is, the offset voltage generation circuit 200 provided in the embodiment of the present application can detect dynamic current.

[0101] Further, because only the dynamically changed voltage can cause the voltage change of the first output end A and the second output end B of the offset voltage generation circuit 200, the "first input voltage VDSI" and the "second input voltage VDSI_0" related in the embodiment of the present application are differential voltages before and after the change. For example, when the voltage of the first interface DSI without signal input is Vstatic1, and the voltage of the first interface DSI with signal input changes to Vstatic+ΔV1, the first input voltage VDSI=ΔV1, that is, the first input voltage is the voltage difference of the change of the first interface DSI, and further the first intermediate voltage generated at the first output end of the offset voltage generation circuit 200 is 1 / 2ΔV1. Similarly, when the voltage of the second interface DSI_0 without signal input is Vstatic2, and the voltage of the second interface DSI_0 with signal input changes to Vstatic2+ΔV2, the second input voltage VDSI_0=ΔV2, that is, the second input voltage is the voltage difference of the change of the second interface DSI_0, and further the second intermediate voltage generated at the second output end of the offset voltage generation circuit 200 is 1 / 2ΔV2.

[0102] In the embodiment of the present application, because the "first input voltage VDSI" and the "second input voltage VDSI_0" are differential voltages before and after the change, high voltage can be avoided from entering the chip. At the same time, the voltage resistance requirement of the subsequent circuit amplifiers, comparators and other devices is also reduced.

[0103] It should be noted that the offset voltage generation sub-circuit 210 and voltage conversion sub-circuit 220 in Figures 4A and 4B are merely exemplary illustrations of the embodiments of this application. Those skilled in the art can also use other circuit structures to achieve their corresponding functions according to actual needs, and the embodiments of this application do not impose specific limitations on this.

[0104] Please refer to Figure 2. In this embodiment, the comparator circuit 300 receives the first output voltage and the second output voltage from the offset voltage generation circuit 200, compares the first output voltage and the second output voltage, and outputs a current detection result. Specifically, when the first output voltage is greater than the second output voltage, a first current detection result (e.g., a high level "1") is output, indicating that current has been detected; when the first output voltage is less than or equal to the second output voltage, a second current detection result (e.g., a low level "0") is output, indicating that no current has been detected.

[0105] It is understood that the "first output voltage and second output voltage" involved in this application embodiment are the voltage values ​​after the first intermediate voltage and the second intermediate voltage are superimposed with the offset voltage. As mentioned above, the voltage difference between the first intermediate voltage and the second intermediate voltage is 1 / 2(VDSI-VDSI_0), and the offset voltage between the first output terminal and the second output terminal is 2×I1×R1. It is understood that when 1 / 2(VDSI-VDSI_0)>2×I1×R1, the first output voltage of the offset voltage generation circuit 200 is greater than the second output voltage; when 1 / 2(VDSI-VDSI_0)≤2×I1×R1, the first output voltage of the offset voltage generation circuit 200 is less than or equal to the second output voltage. That is to say, the output signal of the comparator circuit 300 will flip, indicating that current is detected, when the voltage difference generated between the first input voltage and the second input voltage between the first output terminal and the second output terminal of the offset voltage generation circuit 200 is greater than the offset voltage.

[0106] Specifically, as shown in Figure 3, in one possible implementation, the comparator circuit 300 includes an amplification sub-circuit 310, a comparator sub-circuit 320, and an output sub-circuit 330. The amplification sub-circuit 310 receives a first output voltage and a second output voltage, and amplifies them; the comparator sub-circuit 320 compares the amplified first and second output voltages and outputs the comparison result; the output sub-circuit 330 receives the comparison result and outputs the current detection result.

[0107] In a possible implementation, the amplification sub-circuit 310 includes a plurality of amplifiers connected in series. Specifically, the positive input terminal of the first amplifier is electrically connected to the first output terminal of the offset voltage generation circuit, and the negative input terminal of the first amplifier is electrically connected to the second output terminal of the offset voltage generation circuit; the positive input terminal of the i th amplifier is electrically connected to the negative output terminal of the (i-1) th amplifier, and the negative input terminal of the i th amplifier is electrically connected to the positive output terminal of the (i-1) th amplifier, 2≤i≤N (N represents the number of amplifiers); and the negative output terminal of the last amplifier is configured to output the amplified first output voltage, and the positive output terminal of the last amplifier is configured to output the amplified second output voltage.

[0108] For example, in the implementation shown in FIGS. 4A and 4B, the amplification sub-circuit 310 includes three amplifiers, namely, the amplifier A1, the amplifier A2, and the amplifier A3. It can be understood that the amplifier A1 is the first amplifier, and the amplifier A3 is the last amplifier. Specifically, the positive input terminal of the amplifier A1 is electrically connected to the first output terminal of the offset voltage generation circuit 200, and the negative input terminal of the amplifier A1 is electrically connected to the second output terminal of the offset voltage generation circuit 200; the positive input terminal of the amplifier A2 is electrically connected to the negative output terminal of the amplifier A1, and the negative input terminal of the amplifier A2 is electrically connected to the positive output terminal of the amplifier A1; the positive input terminal of the amplifier A3 is electrically connected to the negative output terminal of the amplifier A2, and the negative input terminal of the amplifier A3 is electrically connected to the positive output terminal of the amplifier A2; the negative output terminal of the amplifier A3 is configured to output the amplified first output voltage, and the positive output terminal of the amplifier A3 is configured to output the amplified second output voltage.

[0109] In the embodiments of the present application, since the amplification sub-circuit 310 adopts multiple amplifiers for multi-stage amplification, each amplifier can adopt a smaller gain to achieve higher symmetry and avoid system offset as much as possible.

[0110] Referring to FIG. 5, FIG. 5 is a circuit diagram of another current detection circuit provided by the embodiments of the present application. As shown in FIG. 5, in the embodiments of the present application, the amplification sub-circuit 310 includes one amplifier, namely, the amplifier A1 shown in FIG. 5. Specifically, the positive input terminal of the amplifier A1 is electrically connected to the first output terminal of the offset voltage generation circuit 200, the negative input terminal of the amplifier A1 is electrically connected to the second output terminal of the offset voltage generation circuit 200, the negative output terminal of the amplifier A1 is configured to output the amplified first output voltage, and the positive output terminal of the amplifier A1 is configured to output the amplified second output voltage.

[0111] It should be noted that the person skilled in the art can also set other numbers of amplifiers in the amplification sub-circuit 310 according to actual needs, for example, 2, 4, 5, etc., and the embodiments of the present application do not make specific limitations thereto.

[0112] Referring to FIG. 6, a circuit diagram of an amplifier provided by an embodiment of the present application is shown. As shown in FIG. 6, the amplifier comprises: a second current source I2, configured to output a second constant current; a first transistor M1, a gate of the first transistor M1 being a positive input terminal Vin+ of the amplifier, a source of the first transistor M1 being electrically connected with an output terminal of the second current source I2, and a drain of the first transistor M1 being a negative output terminal Vout- of the amplifier; a third resistor R3, a first end of the third resistor R3 being electrically connected with the drain of the first transistor M1, and a second end of the third resistor R3 being grounded; a fifth switch S5, a first end of the fifth switch S5 being electrically connected with the gate of the first transistor M1, and a second end of the fifth switch S5 being electrically connected with the drain of the first transistor M1; a second transistor M2, a gate of the second transistor M2 being a negative input terminal Vin- of the amplifier, a source of the second transistor M2 being electrically connected with the output terminal of the second current source I2, and a drain of the second transistor M2 being a positive output terminal Vout+ of the amplifier; a fourth resistor R4, a first end of the fourth resistor R4 being electrically connected with the drain of the second transistor M2, and a second end of the fourth resistor R4 being grounded; and a sixth switch S6, a first end of the sixth switch S6 being electrically connected with the gate of the second transistor M2, and a second end of the sixth switch S6 being electrically connected with the drain of the second transistor M2. In a specific implementation, the first transistor M1 and the second transistor M2 can be PMOS transistors. Of course, the person skilled in the art can also set other types of transistors according to actual needs, and the embodiments of the present application do not make specific limitations thereto.

[0113] As shown in FIG. 4A and FIG. 6, when the fifth switch S5 and the sixth switch S6 are turned off, the gates of the first transistor M1 and the second transistor M2 are only connected to the capacitor, which is equivalent to being suspended. If the first transistor M1 and the second transistor M2 are to be started, they need to be in a saturated state. Specifically, when the fifth switch S5 and the sixth switch S6 are turned on, the first transistor M1 and the second transistor M2 are connected in a MOS_Diode structure, and a voltage V appears at the gates of the first transistor M1 and the second transistor M2. That is, the voltage generated at the positive input terminal Vin+ and the negative input terminal Vin- of the amplifier is V, and the potential difference between the two is 0. In the subsequent working process, when the fifth switch S5 and the sixth switch S6 are turned off, the voltage at the gates of the first transistor M1 and the second transistor M2 still exists, which is equivalent to providing a working power supply for the first transistor M1 and the second transistor M2. It should be noted that the voltage at the gate of the first transistor M1 is equivalent to the "voltage generated at the first input terminal of the comparison circuit 300" described above; and the voltage at the gate of the second transistor M2 is equivalent to the "voltage generated at the second input terminal of the comparison circuit 300" described above.

[0114] Please continue to refer to FIG. 4A and FIG. 4B. In the embodiment of the present application, the comparison sub-circuit 320 includes a comparator A4, the positive input terminal of the comparator A4 is used to receive the amplified first output voltage, the negative input terminal of the comparator A4 is used to receive the amplified second output voltage, and the comparator A4 is used to output a comparison result. Specifically, when the amplified first output voltage is greater than the amplified second output voltage, the comparator A4 outputs a first comparison result, which is used to represent that a current is detected; and when the amplified first output voltage is less than or equal to the amplified second output voltage, the comparator A4 outputs a second comparison result, which is used to represent that a current is not detected.

[0115] Please continue to refer to FIG. 4A and FIG. 4B. In the embodiment of the present application, the output sub-circuit 330 includes a first NOT gate NOT1 and a second NOT gate NOT2. The input terminal of the first NOT gate NOT1 is electrically connected to the output terminal of the comparison sub-circuit 320; the input terminal of the second NOT gate NOT2 is electrically connected to the output terminal of the first NOT gate NOT1, and the output terminal of the second NOT gate NOT2 is used to output a current detection result.

[0116] In the embodiment of the present application, the first NOT gate NOT1 and the second NOT gate NOT2 can avoid the output of an intermediate level. Of course, the output sub-circuit 330 can not be provided according to actual needs, and the comparison result output by the comparison sub-circuit 320 can be directly used as the current detection result, which is not limited in the embodiment of the present application.

[0117] It should be noted that the amplification sub-circuit 310, the comparison sub-circuit 320 and the output sub-circuit 330 in FIG. 4A, FIG. 4B and FIG. 5 are only an exemplary illustration of the embodiments of the present application, and those skilled in the art can also use other circuit structures to realize the corresponding functions according to actual needs, and the embodiments of the present application do not make specific limitations in this regard.

[0118] As described above, the offset voltage generation circuit 200 provided by the embodiments of the present application can only detect the dynamic current. However, in actual applications, in addition to the need to detect the dynamic current, it can also be necessary to detect the static current. Based on this, the embodiments of the present application also provide another current detection circuit which can detect both dynamic current and static current, which will be described in detail below in conjunction with specific implementation manners.

[0119] Referring to FIG. 7, it is a circuit diagram of another current detection circuit provided by the embodiments of the present application. As shown in FIG. 7, on the basis of the current detection circuit shown in FIG. 2, a current conversion circuit 400 is added, which is used to convert the static current into dynamic current and input into the offset voltage generation circuit 200. The offset voltage generation circuit 200 is also used to generate the first intermediate voltage and the second intermediate voltage at the first output end and the second output end of the offset voltage generation circuit 200 respectively according to the received dynamic current, and output the first output voltage and the second output voltage at the first output end and the second output end of the offset voltage generation circuit 200 respectively after superimposing the offset voltage. That is, when it is necessary to detect the static current, the static current is first converted into dynamic current, and then the dynamic current is input into the offset voltage generation circuit 200 to detect the dynamic current, thereby indirectly realizing the detection of the static current.

[0120] Specifically, as shown in FIG. 8, the current conversion circuit 400 includes a current mirror 410, the current mirror 410 includes an input current sub-circuit 411 and an output current sub-circuit 412, the output current sub-circuit 412 is used to generate an output current according to an input current in the input current sub-circuit 411; an RC filter circuit 420, the input current circuit is electrically connected with the output current circuit through the RC filter circuit 420; a control circuit 430, the control circuit 430 is used to control the input current sub-circuit 411 and the output current sub-circuit 412 to be turned on or turned off. In the working process, when it is necessary to detect the static current, first, the connection between the input current sub-circuit 411 and the output current sub-circuit 412 is turned off by the control circuit 430, so that the output current in the output current sub-circuit 412 is 0; then the connection between the input current sub-circuit 411 and the output current sub-circuit 412 is turned on by the control circuit 430. At this time, under the action of the RC filter circuit 420, the output current of the output current sub-circuit 412 will gradually change from nothing to something, thereby realizing the conversion of the static current into the dynamic current.

[0121] Referring to FIG. 9, a circuit diagram of a current conversion circuit provided in an embodiment of the present application is shown; referring to FIG. 10, a circuit diagram of another current detection circuit provided in an embodiment of the present application is shown. As shown in FIG. 9 and in combination with FIG. 10, in the embodiment of the present application, the input current sub-circuit 411 includes a third current source I3 and a third transistor M3, the third current source I3 is configured to output a third constant current, the drain of the third transistor M3 is electrically connected with the output terminal of the third current source I3, the emitter of the third transistor M3 is grounded, and the drain of the third transistor M3 is electrically connected with the gate of the third transistor M3. The output current sub-circuit 412 includes a fourth transistor M4, the drain of the fourth transistor M4 is electrically connected with the second interface DSI_0 of the offset voltage generation circuit 200, the second interface DSI_0 is configured to input a second input voltage, and the source of the fourth transistor M4 is grounded. It should be noted that the first interface DSI is configured to input a fixed voltage.

[0122] The RC filter circuit 420 includes a fifth resistor R5 and a fifth capacitor C5, the first terminal of the fifth resistor R5 is electrically connected with the gate of the third transistor M3, the first terminal of the fifth capacitor C5 is electrically connected with the second terminal of the fifth resistor R5, and the second terminal of the fifth capacitor C5 is grounded. The control circuit 430 includes a seventh switch S7 and an eighth switch S8, the first terminal of the seventh switch S7 is electrically connected with the second terminal of the fifth resistor R5, the second terminal of the seventh switch S7 is electrically connected with the gate of the fourth transistor M4, the first terminal of the eighth switch S8 is electrically connected with the gate of the fourth transistor M4, and the second terminal of the eighth switch S8 is grounded.

[0123] It can be understood that, in the embodiment of the present application, the third current source I3, the third transistor M3 and the fourth transistor M4 constitute a current source. When it is needed to control the third transistor M3 and the fourth transistor M4 to be disconnected, the seventh switch S7 can be controlled to be opened and the eighth switch S8 can be controlled to be closed; when it is needed to control the third transistor M3 and the fourth transistor M4 to be turned on, the seventh switch S7 can be controlled to be closed and the eighth switch S8 can be controlled to be opened. In the process of switching the above switches, the output current of the output current sub-circuit 412 will gradually change from zero to a certain value, thereby causing the voltage at the second interface DSI_0 to change, and the detection of the static current is realized.

[0124] In a specific implementation, the third transistor M3 and the fourth transistor M4 can be NMOS transistors. Of course, other types of transistors can also be set according to actual needs, and the embodiments of the present application do not make specific limitations in this regard.

[0125] It should be noted that other contents of the current detection circuit can be referred to the description above, and will not be described here again for the sake of brevity.

[0126] Corresponding to the above-mentioned embodiments, the embodiments of the present application further provide an integrated circuit chip.

[0127] Referring to FIG. 11, a structural block diagram of an integrated circuit chip provided by the embodiments of the present application is shown. As shown in FIG. 11, the integrated circuit chip comprises a current detection circuit.

[0128] It should be noted that the integrated circuit chip can be an MCU, a DSP, an MPU, a micro CPU, and the like, which can process digital signals and analog signals, or can perform functions of signal control, instruction processing and operation, and the like.

[0129] The specific content of the current detection circuit can be referred to the description of the above-mentioned embodiments, and will not be described here again for brevity.

[0130] In the embodiments of the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the cases of A alone, A and B together, and B alone. Wherein A and B can be singular or plural. The character " / " generally represents that the associated objects before and after it are in an "or" relationship. "At least one of the following" and the like means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b and c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, and c can be single or multiple.

[0131] Those skilled in the art can realize that the units and algorithm steps described in the embodiments disclosed herein can be realized by electronic hardware, computer software and combination of electronic hardware and computer software. Whether the functions are realized in hardware or software mode depends on the specific application and design constraints of the technical solutions. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0132] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-mentioned system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here again.

[0133] In several embodiments provided in the present application, any function if realized in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part of the prior art or the part of the technical solutions of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0134] The above description is merely a specific implementation of the present application. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. The protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A current detection circuit, characterized in that, include: A reference voltage generation circuit is used to generate a reference voltage. An offset voltage generation circuit is used to generate an offset voltage between the first output terminal and the second output terminal of the offset voltage generation circuit according to the reference voltage; and to generate a first intermediate voltage and a second intermediate voltage at the first output terminal and the second output terminal of the offset voltage generation circuit respectively according to the received first input voltage and second input voltage, and to output a first output voltage and a second output voltage at the first output terminal and the second output terminal of the offset voltage generation circuit respectively after superimposing the offset voltage. A comparator circuit is used to receive the first output voltage and the second output voltage, compare the first output voltage and the second output voltage, and output the current detection result.

2. The current detection circuit according to claim 1, characterized in that, The reference voltage generation circuit includes: The first current source is used to output the first constant current; The first resistor has its first end electrically connected to the output terminal of the first current source, and its second end grounded. The node between the first current source and the first resistor is used to output the reference voltage.

3. The current detection circuit according to claim 1, characterized in that, The offset voltage generation circuit includes: Offset voltage generation sub-circuit, used to generate an offset voltage between the first and second output terminals of the offset voltage generation circuit according to the reference voltage; A voltage conversion sub-circuit is used to generate a first intermediate voltage and a second intermediate voltage respectively at the first output terminal and the second output terminal of the offset voltage generation circuit based on the received first input voltage and second input voltage, wherein the voltage difference between the first input voltage and the second input voltage is positively correlated with the voltage difference between the first intermediate voltage and the second intermediate voltage.

4. The current detection circuit according to claim 3, characterized in that, The offset voltage generation sub-circuit includes: A first switch, the first terminal of which is electrically connected to the output terminal of the reference voltage generation circuit; A first capacitor, the first terminal of which is electrically connected to the second terminal of the first switch, and the second terminal of which is electrically connected to the first output terminal of the offset voltage generation sub-circuit. The second switch has a first terminal electrically connected to the node between the first switch and the first capacitor, and a second terminal grounded. The third switch, the first end of which is electrically connected to the output terminal of the reference voltage generation circuit; The second capacitor has its first terminal electrically connected to the second terminal of the third switch, and its second terminal electrically connected to the second output terminal of the offset voltage generation sub-circuit. The fourth switch has its first terminal electrically connected to the node between the third switch and the second capacitor, and its second terminal grounded.

5. The current detection circuit according to claim 4, characterized in that, The voltage conversion sub-circuit includes: The third capacitor, the first terminal of which is electrically connected to the first output terminal of the offset voltage generation sub-circuit; The second resistor, the first end of which is electrically connected to the second end of the third capacitor; The fourth capacitor has its first terminal electrically connected to the second terminal of the second resistor, and its second terminal electrically connected to the second output terminal of the offset voltage generation sub-circuit. A first interface is electrically connected to the node between the third capacitor and the second resistor, and is used to receive the first input voltage; The second interface, which is electrically connected to the node between the second resistor and the fourth capacitor, is used to receive the second input voltage.

6. The current detection circuit according to claim 1, characterized in that, The comparison circuit includes: An amplifier sub-circuit is used to receive the first output voltage and the second output voltage, and to amplify the first output voltage and the second output voltage; The comparator circuit is used to compare the amplified first output voltage with the second output voltage and output the comparison result. An output sub-circuit is used to receive the comparison result and output the current detection result.

7. The current detection circuit according to claim 6, characterized in that, The amplifier sub-circuit includes: An amplifier is provided, wherein the positive input terminal of the amplifier is electrically connected to the first output terminal of the offset voltage generation circuit, the negative input terminal of the amplifier is electrically connected to the second output terminal of the offset voltage generation circuit, the negative output terminal of the amplifier is used to output the amplified first output voltage, and the positive output terminal of the amplifier is used to output the amplified second output voltage.

8. The current detection circuit according to claim 7, characterized in that, The number of amplifiers is N, where N≥2; The positive input terminal of the first amplifier is electrically connected to the first output terminal of the offset voltage generation circuit, and the negative input terminal of the first amplifier is electrically connected to the second output terminal of the offset voltage generation circuit. The positive input terminal of the i-th amplifier is electrically connected to the negative output terminal of the (i-1)-th amplifier, and the negative input terminal of the i-th amplifier is electrically connected to the positive output terminal of the (i-1)-th amplifier, 2≤i≤N; The negative output terminal of the last amplifier is used to output the amplified first output voltage, and the positive output terminal of the last amplifier is used to output the amplified second output voltage.

9. The current detection circuit according to claim 7 or 8, characterized in that, The amplifier includes: The second current source is used to output a second constant current; The first transistor has its gate being the positive input terminal of the amplifier, its source being electrically connected to the output terminal of the second current source, and its drain being the negative output terminal of the amplifier. The third resistor has its first end electrically connected to the drain of the first transistor and its second end grounded. The fifth switch has its first terminal electrically connected to the gate of the first transistor and its second terminal electrically connected to the drain of the first transistor. The second transistor has its gate being the negative input terminal of the amplifier, its source being electrically connected to the output terminal of the second current source, and its drain being the positive output terminal of the amplifier. The fourth resistor has its first end electrically connected to the drain of the second transistor, and its second end grounded. A sixth switch, wherein the first terminal of the sixth switch is electrically connected to the gate of the second transistor, and the second terminal of the sixth switch is electrically connected to the drain of the second transistor.

10. The current detection circuit according to claim 6, characterized in that, The comparator circuit includes: The comparator has its positive input terminal used to receive the amplified first output voltage, its negative input terminal used to receive the amplified second output voltage, and its output terminal used to output the comparison result.

11. The current detection circuit according to claim 6, characterized in that, The output sub-circuit includes: The first NOT gate, the input terminal of which is electrically connected to the output terminal of the comparator circuit; The second NOT gate has its input terminal electrically connected to the output terminal of the first NOT gate, and its output terminal is used to output the current detection result.

12. The current detection circuit according to any one of claims 1-10, characterized in that, Also includes: A current conversion circuit, wherein the current conversion circuit is used to convert static current into dynamic current; The offset voltage generation circuit is further configured to generate a first intermediate voltage and a second intermediate voltage at the first output terminal and the second output terminal of the offset voltage generation circuit respectively based on the received dynamic current, and after superimposing the offset voltage, output a first output voltage and a second output voltage at the first output terminal and the second output terminal of the offset voltage generation circuit respectively.

13. The current detection circuit according to claim 12, characterized in that, The current conversion circuit includes: A current mirror, comprising an input current sub-circuit and an output current sub-circuit, wherein the output current sub-circuit is used to generate an output current based on the input current in the input current sub-circuit; An RC filter circuit is provided, wherein the input current circuit is electrically connected to the output current circuit through the RC filter circuit. A control circuit is provided for controlling the input current sub-circuit and the output current sub-circuit to be turned on or off.

14. The current detection circuit according to claim 13, characterized in that, The input current sub-circuit includes: a third current source for outputting a third constant current; a third transistor, wherein the drain of the third transistor is electrically connected to the output terminal of the third current source, the emitter of the third transistor is grounded, and the drain of the third transistor is electrically connected to the gate of the third transistor. The output current sub-circuit includes: a fourth transistor, the drain of which is electrically connected to the second interface of the offset voltage generation circuit, the second interface being used to input the second input voltage, and the source of which is grounded; The RC filter circuit includes: a fifth resistor, the first end of which is electrically connected to the gate of the third transistor; and a fifth capacitor, the first end of which is electrically connected to the second end of the fifth resistor, and the second end of the fifth capacitor is grounded. The control circuit includes: a seventh switch, the first end of which is electrically connected to the second end of the fifth resistor, and the second end of which is electrically connected to the gate of the fourth transistor; and an eighth switch, the first end of which is electrically connected to the gate of the fourth transistor, and the second end of which is grounded.

15. An integrated circuit chip, characterized in that, Includes the current detection circuit according to any one of claims 1-14.

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