Semiconductor chip package having low-melting-point solder-high-melting-point solder-low-melting-point solder bonding structure, and manufacturing method therefor

Abstract

One embodiment of the present invention provides a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder structure, and a manufacturing method therefor. In the manufacturing method for a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder bonding structure, according to one embodiment of the present invention, a low-melting-point solder is simultaneously diffused in two directions (upward and downward) instead of one direction, such that components of a low-temperature solder can be quickly and uniformly distributed in a solder bonding part at a temperature less than or equal to the melting point of a high-melting-point solder, and thus the reliability of the semiconductor package can be improved and, simultaneously, power consumption can be reduced.

Description

Semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure and a manufacturing method thereof

[0001] The present invention relates to a semiconductor chip package, and more particularly, to a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure and a method for manufacturing the same.

[0002] As global concerns about climate change and the environment grow, interest in reducing carbon emissions across various industries is growing to achieve carbon neutrality and net-zero emissions by 2050.

[0003] A representative example of a soldering process for semiconductor packages is the Hybrid ball grid array (BGA) soldering method, which is a technology that simultaneously bonds high-temperature lead-free solder (HTS, high tempearture solder) material, Sn-3.0%Ag-0.5%Cu (melting point: 217℃), and low-temperature solder (LTS, low tempearture solder) materials.

[0004] This has the advantage of reducing power consumption by lowering the soldering process temperature through the solid-liquid inter-diffusive reaction between high-temperature solder (hereinafter referred to as high-melting-point solder) and low-temperature solder (hereinafter referred to as low-melting-point solder), and at the same time reducing thermal warpage of the package and deterioration of components.

[0005] At this time, the low-melting-point solder used is usually a solder with a small amount of Ag or In elements added to the Sn-Bi eutectic composition.

[0006] There are two major problems that arise when forming joints of these dissimilar alloys. First, when forming a joint where two alloys with different coefficients of thermal expansion are not completely mixed, the reliability was found to be low in thermal shock tests (crack propagation: SAC-SnBi interface). Second, in the case of Sn-58Bi solder, if Bi, a low-temperature solder component, is concentrated in the solder joint, especially on the solder interface on the printed circuit board (PCB) side or the silicon (Si) component side, the high brittleness of Bi greatly deteriorates reliability, such as drop impact characteristics.

[0007] To solve this problem, the conventional bonding method used a method in which low-temperature solder diffuses through unidirectional diffusion in an upward or downward direction. In order to diffuse uniformly throughout this diffusion process, the soldering process temperature was raised above the melting point of high-melting-point solder (SAC 305) or the amount of low-melting-point solder paste (LTS) was increased.

[0008] However, performing the process at a temperature higher than the melting point of high-melting-point solder (SAC 305) does not meet the purpose of using low-melting-point solder, and does not effectively reduce power consumption, thermal warpage, and deterioration of components.

[0009] Additionally, increasing the amount of low-melting-point solder paste (LTS) is not suitable for solving the brittleness problem, and at the same time, it can cause problems such as shorts between bumps as the aspect ratio of the solder joint increases.

[0010] Therefore, a new semiconductor chip package bonding method that can provide high reliability at low temperatures is required.

[0011] [Prior art literature]

[0012] Republic of Korea Patent No. 10-2386542

[0013] The technical problem to be achieved by the present invention is to provide a method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure in which a low-melting-point solder component is simultaneously diffused in both directions (upward and downward) rather than unidirectionally to form a solder joint.

[0014] The technical problems to be solved by the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the present invention belongs from the description below.

[0015] In order to achieve the above technical task, one embodiment of the present invention provides a method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure.

[0016] According to an embodiment of the present invention, a method for manufacturing a semiconductor chip package having the low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure comprises the steps of: screen-printing a first low-melting-point solder paste on a first substrate; depositing a high-melting-point solder ball on top of the first low-melting-point solder paste on the first substrate; performing a first soldering process on the first substrate on which the first low-melting-point solder paste and the high-melting-point solder ball are formed so that the first solder paste melts and bonds with the high-melting-point solder ball to form a bump; mounting a second substrate on which a second low-melting-point solder paste is screen-printed on the first substrate on which the bump is formed, aligning the bump and the second low-melting-point solder paste so as to face each other; It may be characterized by including a step of performing a second soldering process on the aligned first substrate and second substrate, wherein the low-melting-point solder paste of the second substrate melts and bonds with the bump of the first substrate, thereby manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder structure.

[0017] In addition, according to one embodiment of the present invention, the method for manufacturing a semiconductor chip package having the low-melting-point solder-high-melting-point solder-low-melting-point solder structure can be used in a semiconductor packaging process of a land grid array (LGA) or an interposer package on package (interposer PoP).

[0018] In addition, according to one embodiment of the present invention, in the step of screen printing the first low-melting-point solder paste on the first substrate, the first substrate may include a printed circuit board (PCB), a semiconductor chip, a semiconductor substrate, or a ceramic substrate.

[0019] In addition, according to one embodiment of the present invention, in the step of screen printing the first low-melting-point solder paste on the first substrate, the first low-melting-point solder paste may include a solder material of the Sn-Bi system, the Sn-Bi-X system (X is Ag, In, Ge, Co, Zn or Sb) or the In-Sn-Y system (Y is Ag, Ge, Co, Zn or Sb).

[0020] In addition, according to one embodiment of the present invention, in the step of depositing the high-melting-point solder ball, the high-melting-point solder ball may include at least one alloy selected from the group consisting of tin-silver-copper (Sn-Ag-Cu) and tin-silver (Sn-Ag).

[0021] In addition, according to one embodiment of the present invention, in the step of depositing the high-melting-point solder ball, the volume ratio of the first low-melting-point solder ball and the high-melting-point solder ball formed on the first substrate may be 0.1:1 to 0.45:1, thereby forming a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure.

[0022] In addition, according to one embodiment of the present invention, in the step of forming the bump, the first soldering process may be an IPL soldering process, a reflow soldering process, a laser soldering process, or a plasma soldering process.

[0023] Additionally, according to one embodiment of the present invention, in the step of forming the bump, the first soldering process may be performed at a temperature range of 170°C or more and less than 217°C.

[0024] Additionally, according to one embodiment of the present invention, in the step of aligning the bump and the second low-melting-point solder paste to face each other, the second substrate may be a printed circuit board (PCB), a semiconductor chip, a semiconductor substrate, or a ceramic substrate.

[0025] In addition, according to one embodiment of the present invention, in the step of aligning the bump and the second low-melting-point solder paste to face each other, the second low-melting-point solder paste may include a solder material of the Sn-Bi system, the Sn-Bi-X system (X is Ag, In, Ge, Co, Zn or Sb) or the In-Sn-Y system (Y is Ag, Ge, Co, Zn or Sb).

[0026] In addition, according to one embodiment of the present invention, in the step of manufacturing a semiconductor chip package having the low-melting-point solder-high-melting-point solder-low-melting-point solder structure, the second soldering process may be an IPL soldering process or a reflow soldering process.

[0027] In addition, according to one embodiment of the present invention, in the step of manufacturing a semiconductor chip package having the low-melting-point solder-high-melting-point solder-low-melting-point solder structure, the second soldering process can be performed at a temperature range of 170°C or more and less than 217°C.

[0028] In order to achieve the above technical task, another embodiment of the present invention provides a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure.

[0029] In addition, a semiconductor chip package having the low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure according to one embodiment of the present invention can be manufactured by performing a method for manufacturing a semiconductor chip package having the low-melting-point solder-high-melting-point solder-low-melting-point solder structure.

[0030] In addition, a semiconductor chip package having the low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure according to an embodiment of the present invention may include: a first substrate; a first low-melting-point solder paste layer positioned on the first substrate and printed at a predetermined interval; a high-melting-point solder ball layer positioned on the first low-melting-point solder paste, the high-melting-point solder ball layer formed on the first low-melting-point solder paste and bonded by diffusion of the low-melting-point solder paste through a soldering process; and a second substrate having a second low-melting-point solder paste layer positioned on the high-melting-point solder ball layer and bonded to the high-melting-point solder ball layer by diffusion through a soldering process.

[0031] A method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure according to an embodiment of the present invention allows the diffusion of the low-melting-point solder to occur simultaneously in both directions (upward and downward) rather than unidirectionally, thereby uniformly distributing the components of the low-temperature solder within the solder joint at a temperature lower than the melting point of the high-melting-point solder, thereby improving the reliability of various semiconductor packages and reducing power consumption.

[0032] The effects of the present invention are not limited to the effects described above, and should be understood to include all effects that can be inferred from the detailed description of the present invention or the composition of the invention described in the claims.

[0033] Figure 1 is a flowchart illustrating a method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure.

[0034] Figure 2 is a schematic diagram showing the bidirectional diffusion behavior of a method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure.

[0035] Figure 3 is a schematic diagram showing a method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure.

[0036] FIG. 4 is an exemplary diagram comparing the thickness of an intermetallic compound layer (IMC) of a conventional semiconductor chip package and a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure of the present invention.

[0037] Figure 5 is an SEM image showing a cross-section of a joint of a conventional semiconductor chip package.

[0038] Figure 6 is a BMR graph of a joint of a conventional semiconductor chip package.

[0039] Figure 7 is a polarizing microscope and SEM image showing a cross-section of a joint utilizing the double-sided diffusion process of the present invention.

[0040] Hereinafter, the present invention will be described with reference to the attached drawings. However, the present invention can be implemented in various different forms and is therefore not limited to the embodiments described herein. In the drawings, irrelevant parts have been omitted for clarity of description, and similar parts have been designated with similar reference numerals throughout the specification.

[0041] Throughout the specification, when a part is said to be "connected (connected, contacted, or coupled)" to another part, this includes not only cases where it is "directly connected," but also cases where it is "indirectly connected" with another member in between. Furthermore, when a part is said to "include" a component, this does not mean that it excludes other components, but rather that it may include other components, unless otherwise specifically stated.

[0042] The terminology used herein is merely used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this specification, it should be understood that the terms "comprises" or "has" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0043]

[0044] Below, the present invention will be described with reference to the drawings presented in this specification. Note that the drawings may be exaggerated to illustrate the features of the present invention. In such cases, it is preferable to interpret them in light of the overall intent of this specification.

[0045]

[0046] A method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure according to one embodiment of the present invention is described.

[0047] Figure 1 is a flowchart illustrating a method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure.

[0048] Referring to FIG. 1, a method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure according to an embodiment of the present invention comprises: a step of screen printing or plating a first low-melting-point solder paste on a first substrate (S100); a step of depositing a high-melting-point solder ball on top of the first low-melting-point solder paste on the first substrate (S200); a step of performing a first soldering process on the first substrate on which the first low-melting-point solder paste and the high-melting-point solder ball are formed so that the first solder paste melts and bonds with the high-melting-point solder ball to form a bump (S300); a step of mounting a second substrate on which a second low-melting-point solder paste is screen-printed on the first substrate on which the bump is formed, aligning the bump and the second low-melting-point solder paste so as to face each other (S400); The method may include a step (S500) of performing a second soldering process on the aligned first and second substrates, wherein the low-melting-point solder paste of the second substrate melts and bonds with the bumps of the first substrate to manufacture a semiconductor chip package having a low-melting-point solder-high-melting-point solder structure.

[0049] Among the conventional soldering processes for semiconductor packages, the hybrid ball grid array (HBGA) soldering process is a process that simultaneously uses high-melting-point solder (Sn-Ag-Cu) and low-melting-point solder materials in the solder joint to join the solder joints. It has the advantage of being able to lower the soldering process temperature by utilizing the solid-liquid inter-diffusion reaction between the high-melting-point solder and the low-melting-point solder, thereby reducing power consumption and simultaneously reducing thermal warpage, and is characterized by the low-melting-point solder diffusing in the direction of the high-melting-point solder.

[0050] The conventional method of diffusion through unidirectional diffusion made it impossible for the solder containing bismuth (Bi) to spread evenly, but referring to FIGS. 5 to 7, the present invention utilizes the characteristic of lowering the soldering process temperature by forming a low-melting-point solder on both sides of a high-melting-point solder so that the solder containing bismuth (Bi) can diffuse simultaneously in both directions, thereby quickly and evenly distributing the low-temperature solder component within the solder joint.

[0051]

[0052] Hereinafter, with reference to FIGS. 2 to 4, a method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure will be described.

[0053] In the first step, a step of screen printing a first low-melting-point solder paste on a first substrate may be included. (S100)

[0054] The first substrate may include a printed circuit board (PCB), a semiconductor chip, a semiconductor substrate, or a ceramic substrate.

[0055] At this time, in the case of a device in which an electronic circuit is formed using the first substrate, it can be used without limitation and is not necessarily limited to a printed circuit board (PCB), a semiconductor chip, a semiconductor substrate, or a ceramic substrate.

[0056] Additionally, the first low-melting-point solder paste may include a solder material of the Sn-Bi system, the Sn-Bi-X system (X is Ag, In, Ge, Co, Zn or Sb) or the In-Sn-Y system (Y is Ag, Ge, Co, Zn or Sb).

[0057] At this time, a low-melting-point solder can be formed by bismuth (Bi) in the Sn-Bi, Sn-Bi-Ag, or Sn-Bi-In system of the low-melting-point solder paste.

[0058] At this time, the present invention can use not only a Sn-Bi, Sn-Bi-Ag or Sn-Bi-In alloy as the first low-melting-point solder paste, but also a low-melting-point solder material of the Sn-Bi-X system (X is Ag, In, Ge, Co, Zn or Sb) or In-Sn-Y system (Y is Ag, Ge, Co, Zn or Sb).

[0059] At this time, the common characteristic of the low-melting-point solder paste used in the present invention is that a solder having a melting point of 140°C or less and having 1% or less of Ag element added to the eutectic composition can be used, and for example, Sn-57.6Bi-0.4Ag, Sn-57.6Bi-1.0Ag or Sn-58Bi is used, and in the case of a low-melting-point solder paste used by a person skilled in the art, it can be used without limitation.

[0060] At this time, the volume ratio of the first low-melting-point solder paste and the high-melting-point solder ball formed on the first substrate is characterized by being 0.1:1 to 0.45:1.

[0061] At this time, the reason why the volume ratio of the solder paste and the high-melting-point solder ball is 0.15:1 to 0.45:1 is that when the volume ratio is less than 0.1, there may be a problem that the amount of low-temperature solder is insufficient, resulting in a non-wet phenomenon (a phenomenon in which water or other liquids do not adhere well to a specific surface but easily slide off), and the reason why it exceeds 0.45:1 is that when the low-temperature solder covers the solder ball, it may overflow and connect to the adjacent electrode, resulting in problems such as a short circuit.

[0062]

[0063] In the second step, a step of depositing high-melting-point solder balls on top of the first low-melting-point solder paste on the first substrate may be included. (S200)

[0064] At this time, the high melting point solder ball may include at least one alloy selected from the group consisting of tin-silver-copper (Sn-Ag-Cu) and tin-silver (Sn-Ag).

[0065] Specifically, the high-melting-point solder ball used in the present invention may include Sn-α%Ag-0.5%Cu (α: 1.0 to 4.0) or Sn-βAg (β: 1.0 to 3.5), and may be used without limitation if it is a solder material used by a person skilled in the art and has a melting point of 217°C or higher.

[0066] In addition, the volume ratio of the first low-melting-point solder paste and the high-melting-point solder ball formed on the first substrate is characterized by being 0.1:1 to 0.45:1.

[0067] At this time, the reason why the volume ratio of the first low-melting-point solder paste and the high-melting-point solder ball formed on the first substrate is 0.1:1 to 0.45:1 is that the present invention is characterized by having a uniform distribution of the components of the low-temperature solder without increasing the amount of solder while lowering the melting temperature, and therefore the volume of the first low-melting-point solder ball is kept relatively small. If the volume ratio is less than 0.1:1, there may be a problem that a non-wet phenomenon (a phenomenon in which water or other liquids do not adhere well to a specific surface but easily slide) may occur, and if it exceeds 0.45:1, an overlapped portion occurs when the low-temperature solder comes into contact with the high-melting-point solder ball, and this may cause a problem such as a short circuit when it comes into contact with the adjacent bump.

[0068] At this time, the high-melting-point solder ball used in the present invention may have a diameter of 450 um to 460 um, and the diameter of the solder ball may differ depending on the volume ratio with respect to the first low-melting-point solder ball.

[0069]

[0070] In the third step, a step may be included of performing a first soldering process on the first substrate on which the first low-melting-point solder paste and the high-melting-point solder balls are formed, so that the first solder paste melts and bonds with the high-melting-point solder balls to form bumps (S300).

[0071] At this time, the first soldering process is characterized by performing an IPL soldering process or a reflow soldering process.

[0072] The present invention utilizes IPL soldering instead of conventional convection reflow soldering, enabling a soldering process to be performed in a time that is 1 / 10 of that of convection reflow soldering, and can secure high drop reliability due to the creation of a thin intermetallic compound.

[0073] At this time, the first soldering process is characterized in that it is performed in a temperature range of 170°C or more and less than 217°C.

[0074] At this time, the soldering of the present invention is characterized in that it is performed at a temperature relatively lower than the melting point of the high-melting-point solder, and if the first soldering process is performed at a temperature lower than 170°C, there may be a problem that soldering may not be performed because mutual diffusion of the low-temperature solder and the high-melting-point solder does not occur, and if it exceeds 217°C, there may be a problem that the melting point of the high-melting-point solder is exceeded, so the first soldering process may be performed at a temperature range of 170°C or more and less than 217°C.

[0075] At this time, by the first soldering process, the low-melting-point solder can be diffused into the high-melting-point solder ball, and at this time, the present invention can improve the reliability of the electronic package and reduce power consumption by quickly and evenly distributing the components of the low-temperature solder below the melting point of the high-melting-point solder.

[0076] At this time, in the first soldering process, the first low-melting-point solder paste spreads and is bonded to the high-melting-point solder ball, but the thickness of the intermetallic compound (IMC) layer formed between the bonding surface of the first substrate and the first low-melting-point solder paste is 1.25 um, but when the SAC bump is formed using the conventional method, a thick imc (2.875 um) is formed.

[0077]

[0078] In the fourth step, a step may be included of mounting a second substrate on which a second low-melting-point solder paste is screen-printed on the first substrate on which the bump is formed, and aligning the bump and the second low-melting-point solder paste so that they face each other (S400).

[0079] The second substrate is characterized in that it is a printed circuit board (PCB), a semiconductor substrate, or a ceramic substrate.

[0080] At this time, in the case of a device in which an electronic circuit is formed using the second substrate, it can be used without limitation and is not necessarily limited to a printed circuit board (PCB), semiconductor chip, semiconductor substrate, or ceramic substrate.

[0081] For example, the first substrate may be a printed circuit board (PCB) and the second substrate may be a semiconductor chip, or conversely, the first substrate may be a semiconductor chip and the second substrate may be a printed circuit board (PCB).

[0082] At this time, the second low-melting-point solder paste may include a solder material containing bismuth of the Sn-Bi system, Sn-Bi-Ag system, or Sn-Bi-In system.

[0083] At this time, in addition to the Sn-Bi system, Sn-Bi-Ag system or Sn-Bi-In system, the second low-melting-point solder paste may be replaced with a low-melting-point solder material such as the Sn-Bi-X system (X is Ag, In, Ge, Co, Zn or Sb) or the In-Sn-Y system (Y is Ag, Ge, Co, Zn or Sb).

[0084] At this time, the second low-melting-point solder paste may be the same material as the first low-melting-point solder paste, or may be a different material.

[0085]

[0086] In the fifth step, a second soldering process may be performed on the aligned first substrate and second substrate, and a step may be included to manufacture a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder structure by melting the low-melting-point solder paste of the second substrate and bonding it to the bump of the first substrate (S500).

[0087] The second soldering process is performed in a structure in which the first substrate and the second substrate are aligned to face each other, so that the low-melting-point solder paste of the second substrate melts and is bonded to the bump of the first substrate, and is characterized by an IPL soldering process or a reflow soldering process.

[0088] At this time, the second soldering process is characterized in that it is performed in a temperature range of 170°C or more and less than 217°C.

[0089] At this time, the method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder structure of the present invention can be used in a land grid array (LGA) semiconductor packaging process, and can also be applied to a package-on package (PoP), an interposer package on package (interposer PoP), and a system in package (SiP) packaging process.

[0090] The conventional method of diffusion through unidirectional diffusion made it impossible for the solder containing bismuth (Bi) to spread evenly, but referring to FIGS. 5 to 7, the present invention utilizes the characteristic of lowering the soldering process temperature by forming a low-melting-point solder on both sides of a high-melting-point solder so that the solder containing bismuth (Bi) can diffuse simultaneously in both directions, thereby quickly and evenly distributing the low-temperature solder component within the solder joint.

[0091] That is, a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure manufactured by the method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure of the present invention can have a superior degree of diffusion in a structure in which low-melting-point solder is formed on both sides centered on high-melting-point solder, compared to a conventional structure in which the degree of diffusion of low-melting-point solder is diffusion in a single direction.

[0092] In addition, the method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure according to an embodiment of the present invention has the effect of improving the reliability of the semiconductor package and reducing power consumption by simultaneously allowing the diffusion of the low-melting-point solder in both directions (upward and downward) rather than unidirectional diffusion, thereby enabling the low-temperature solder component to be distributed quickly and evenly within the solder joint at a temperature below the melting point of the high-melting-point solder.

[0093] In addition, the method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure of the present invention has the effect of reducing drop shock, thermal shock, and bending shock even when heated at a temperature lower than the melting point of SAC 305, which is a high-melting-point solder.

[0094]

[0095] A semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure according to another embodiment of the present invention is described.

[0096] A semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure according to one embodiment of the present invention can be manufactured by performing the method for manufacturing a semiconductor chip package having the low-melting-point solder-high-melting-point solder-low-melting-point solder structure described above.

[0097] The semiconductor chip package having the low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure is characterized by including a first substrate; a first low-melting-point solder paste layer positioned on the first substrate and printed at a predetermined interval; a high-melting-point solder ball layer positioned on the first low-melting-point solder paste, the high-melting-point solder ball layer formed on the first low-melting-point solder paste and bonded by spreading the low-melting-point solder paste through a soldering process; and a second substrate having a second low-melting-point solder paste layer formed on a surface thereof, the second low-melting-point solder paste layer positioned on the high-melting-point solder ball layer and bonded to the high-melting-point solder ball layer by spreading through a soldering process.

[0098] The description of the first substrate, the first low-melting-point solder paste layer, the high-melting-point solder ball layer, the second low-melting-point solder paste layer, and the second substrate above is replaced with a description of a method for manufacturing a semiconductor chip package having the above-described low-melting-point solder-high-melting-point solder structure.

[0099]

[0100] Hereinafter, the present invention will be described in more detail through manufacturing examples and experimental examples. These manufacturing examples and experimental examples are intended solely to illustrate the present invention, and the scope of the present invention is not limited by these manufacturing examples and experimental examples.

[0101]

[0102] Manufacturing example: Manufacturing method of a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure

[0103] First, in the land grid array packaging process of LGA (land grid array), Sn-57.6Bi-0.4Ag as a low-melting-point solder was printed on the electrode of the semiconductor substrate, then Sn-3.0Ag-0.5Cu as a high-melting-point solder ball was deposited, and IPL soldering or reflow soldering was performed to perform the first soldering process to form a bump.

[0104] At this time, the volume ratio of Sn-57.6Bi-0.4Ag as a low-melting-point solder and Sn-3.0Ag-0.5Cu as a high-melting-point solder ball on the electrode of the semiconductor substrate was limited to 0.1 to 0.45:1.

[0105] At this time, the bump formation temperature of the first soldering process was limited to 185°C to 215°C.

[0106] Next, the same low-melting-point solder paste was printed on the PCB electrodes, and then the IPL soldering or reflow soldering process was performed at the package stage.

[0107] At this time, the soldering process temperature at the PCB electrode was also limited to 185℃ to 215℃.

[0108] Experimental example

[0109] FIG. 4 is an exemplary diagram comparing the thickness of an intermetallic compound layer (IMC) of a conventional semiconductor chip package and a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure of the present invention.

[0110] FIG. 4(a) is a SEM image showing the thickness of the intermetallic compound layer (IMC) of a semiconductor chip package having a bidirectionally diffused low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure of the present invention and a conventional unidirectionally diffused semiconductor chip package.

[0111] Referring to Figure 4, it can be confirmed that Bi is observed on both sides when double-sided diffusion is used, whereas Bi is not observed in the conventional unidirectional bonding method because Bi does not diffuse to the semiconductor chip side (black area).

[0112] In the case of the conventional one-way bonding method, since only tin-silver-copper (SAC, Sn-Ag-Cu)305 is used, the process is performed at 250°C, so the thickness of the intermetallic compound layer is thick. On the other hand, since the double-sided diffusion process of the present invention is performed at a lower temperature, it can be confirmed that the thickness of the intermetallic compound layer is thin.

[0113] The double-sided diffusion process of the present invention can improve warpage and device damage and control the growth of the intermetallic compound layer (imc).

[0114] Additionally, it can be confirmed that the intermetallic compound layer thickness (IMC) of the semiconductor chip is much thinner in the case of double-sided diffusion.

[0115]

[0116] Figure 5 is an SEM image showing a cross-section of a joint of a conventional semiconductor chip package.

[0117] Figure 5 shows cross-sections of joints formed at three low-melting-point solder (SBA) paste thicknesses (50 um, 100 um, 150 um) and three temperatures (185°C, 200°C, 215°C).

[0118] Referring to the above Figure 5, it can be confirmed that the BMR increases as the low melting point solder (SBA) paste thickness (50um, 100um, 150um) increases, and it can be confirmed that the BMR increases in the same manner as the temperature increases.

[0119]

[0120] Figure 6 is a BMR graph of a joint of a conventional semiconductor chip package.

[0121] Referring to Figure 6, Bi represents the BMR (bismuth mixing ratio) according to the thickness of low melting point solder (SBA) and the peak temperature of reflow.

[0122] At this time, although the Bi distribution in the solder portion did not achieve 100% BMR in all nine conditions used in the above experiment, it was possible to design the present invention to exhibit an excellent degree of diffusion by achieving a BMR of 50% or more in four conditions.

[0123] Based on the above results, we attempted to achieve bonding utilizing bidirectional diffusion of low-melting-point solder (SBA) without increasing the total solder paste volume. As mentioned above, to create a structure through diffusion from both sides using high-melting-point solder, first, a bump structure of high-melting-point solder-low-melting-point solder (SAC305-SBA) was required on the electrodes of the LGA component.

[0124] First, low-melting-point solder (SBA) is printed on a Land Grid Array (LGA) component without bumps, and then high-melting-point solder balls (SAC) are placed on the solder paste.

[0125] At this time, the printing thickness is 50um, and the volume ratio of low-melting-point solder paste and high-melting-point solder is approximately 0.15:1.

[0126] Afterwards, the component is subjected to a first soldering process using IPL soldering or reflow soldering to form a bump.

[0127] At this time, the soldering temperature is between 185℃ and 215℃.

[0128] The conditions for the above IPL process were set similarly to the temperature condition value corresponding to the peak temperature of the reflow process.

[0129] Afterwards, a 50um low-melting-point solder (SBA) paste is applied to the PCB as well, and the manufactured component is placed on top of it, and a second soldering process using the IPL or reflow process is performed again.

[0130] At this time, the temperature of the second soldering process is between 185°C and 215°C.

[0131] In the above experiment, bumps were formed using a reflow process (185℃, 200℃, 215℃).

[0132] Afterwards, two processes were used to bond the components and PCB: IPL process and reflow process.

[0133]

[0134] Figure 7 is a polarizing microscope and SEM image showing a cross-section of a joint utilizing the double-sided diffusion process of the present invention.

[0135] Figure 7(a) is a cross-section of a joint where the IPL process was performed under the condition of n=35 during PCB bonding.

[0136] In addition, Figure 7(b) is a cross-section of the joint where the component and the PCB are joined under the condition of 215℃, which is the temperature of the reflow soldering process during PCB joining.

[0137] At this time, it was confirmed that Bi was diffused and distributed throughout the solder in the components manufactured at 200℃ and 215℃ during both the IPL and reflow processes.

[0138] Through this, it was confirmed that the low melting point can be uniformly distributed below the melting point of the high melting point solder when joining using the low melting point-high melting point-low melting point soldering method of the present invention.

[0139]

[0140] The foregoing description of the present invention is for illustrative purposes only, and those skilled in the art will readily appreciate that the present invention can be readily modified into other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single entity may be implemented in a distributed manner, and similarly, components described as distributed may be implemented in a combined manner.

[0141] The scope of the present invention is indicated by the claims described below, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

Claims

1. A step of screen printing or plating a first low-melting-point solder paste on a first substrate; A step of depositing a high-melting-point solder ball on top of a first low-melting-point solder paste on the first substrate; A step of performing a first soldering process on a first substrate on which the first low-melting-point solder paste and high-melting-point solder balls are formed, so that the first solder paste melts and bonds with the high-melting-point solder balls to form bumps; A step of mounting a second substrate on which a second low-melting-point solder paste is screen-printed on a first substrate on which the above bumps are formed, aligning the bumps and the second low-melting-point solder paste so that they face each other; and A method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure, characterized by comprising the step of performing a second soldering process on the aligned first and second substrates, wherein the low-melting-point solder paste of the second substrate melts and bonds with the bumps of the first substrate to manufacture a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder structure.

2. In paragraph 1, A method for manufacturing a semiconductor chip package having the above low-melting-point solder-high-melting-point solder-low-melting-point solder structure is characterized in that the method is used in a semiconductor packaging process of a land grid array (LGA) or an interposer package on package (interposer PoP, Package on Package).

3. In paragraph 1, In the step of screen printing or plating the first low-melting-point solder paste on the first substrate, A method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure, wherein the first substrate includes a printed circuit board (PCB), a semiconductor chip, a semiconductor substrate, or a ceramic substrate.

4. In paragraph 1, In the step of screen printing the first low-melting-point solder paste on the first substrate, A method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure, characterized in that the first low-melting-point solder paste includes a solder material of the Sn-Bi system, the Sn-Bi-X system (X is Ag, In, Ge, Co, Zn or Sb) or the In-Sn-Y system (Y is Ag, Ge, Co, Zn or Sb).

5. In paragraph 1, In the step of depositing the high melting point solder ball, A method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure, characterized in that the high-melting-point solder ball includes at least one alloy selected from the group consisting of tin-silver-copper (Sn-Ag-Cu) and tin-silver (Sn-Ag).

6. In paragraph 1, In the step of depositing the high melting point solder ball, A method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure, characterized in that the volume ratio of the first low-melting-point solder ball and the high-melting-point solder ball formed on the first substrate is 0.1:1 to 0.45:

1.

7. In paragraph 1, In the step of forming the above bump, A method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure, characterized in that the first soldering process performs an IPL soldering process, a reflow soldering process, a laser soldering process, or a plasma soldering process.

8. In paragraph 1, In the step of forming the above bump, A method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure, characterized in that the first soldering process is performed in a temperature range of 170°C or more and less than 217°C.

9. In paragraph 1, In the step of aligning the above bump and the second low-melting-point solder paste so that they face each other, A method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure, wherein the second substrate is a printed circuit board (PCB), a semiconductor chip, a semiconductor substrate, or a ceramic substrate.

10. In paragraph 1, In the step of aligning the above bump and the second low-melting-point solder paste so that they face each other, A method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure, characterized in that the second low-melting-point solder paste includes a solder material of the Sn-Bi system, the Sn-Bi-X system (X is Ag, In, Ge, Co, Zn or Sb) or the In-Sn-Y system (Y is Ag, Ge, Co, Zn or Sb).

11. In paragraph 1, In the step of manufacturing a semiconductor chip package having the above low melting point solder-high melting point solder-low melting point solder structure, A method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure, characterized in that the second soldering process performs an IPL soldering process, a reflow soldering process, a laser soldering process, or a plasma soldering process.

12. In paragraph 1, In the step of manufacturing a semiconductor chip package having the above low melting point solder-high melting point solder-low melting point solder structure, A method for manufacturing a semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure, characterized in that the second soldering process is performed at a temperature range of 170°C to 217°C.

13. First substrate; A first low-melting-point solder paste layer positioned on the first substrate and printed at regular intervals; A high-melting-point solder ball layer positioned on the first low-melting-point solder paste, formed on the first low-melting-point solder paste layer, and joined by spreading the first low-melting-point solder paste through a soldering process; and A semiconductor chip package having a low-melting-point solder-high-melting-point solder-low-melting-point solder joint structure, characterized in that it includes a second substrate having a second low-melting-point solder paste layer formed on a surface thereof, the second low-melting-point solder paste layer being positioned on the high-melting-point solder ball layer and being joined to the high-melting-point solder ball layer by a soldering process.

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