Semiconductor chip and semiconductor wafer

Abstract

A semiconductor chip and a semiconductor wafer. The semiconductor chip comprises a chip body and an outer electrode, wherein a buffer electrode is further formed between the chip body and the outer electrode, and the buffer electrode comprises a tensile stress layer, which is formed by sequentially stacking, in a staggered manner, a plurality of metal layers having a large thermal expansion coefficient and a plurality of metal layers having a small thermal expansion coefficient, so as to offset the compressive stress in an epitaxial layer of at least part of the chip body. Compared with the prior art, in the present application, the buffer electrode is arranged between the chip body and the outer electrode, and the buffer electrode has a tensile stress system which has a regional tensile stress effect and is formed by stacking, in a staggered manner, the metal layers having a large thermal expansion coefficient and the metal layers having a small thermal expansion coefficient, so as to offset the compressive stress in the epitaxial layer in at least part of the chip body, thereby reducing the wafer warpage and thus improving the chip yield.

Description

Semiconductor chips and semiconductor wafers Technical Field

[0001] This application relates to the semiconductor field, and more particularly to semiconductor chips and semiconductor wafers. Background Technology

[0002] With the continuous advancement of mini-LED display technology, market demands for mini-LED chips are becoming increasingly diverse and miniaturized. Therefore, mini-LED chips are evolving towards smaller sizes and thinner thicknesses. However, during the epitaxial growth of GaN layers on the substrate, GaN molecules are stacked from bottom to top, as shown in Figure 1. This lattice mismatch with the Al2O3 substrate generates compressive stress within the GaN material. The thinner the mini-LED wafer is after grinding, the more easily this stress manifests, leading to wafer warping, as shown in Figure 2. This, in turn, increases the difficulty of laser scribing and reduces chip yield.

[0003] Therefore, there is an urgent need for a semiconductor chip and semiconductor wafer that can solve the above problems and effectively release wafer stress.

[0004] Application content

[0005] The purpose of this application is to provide a semiconductor chip and a semiconductor wafer, wherein a buffer electrode is provided between the chip body and the external electrode to effectively release wafer stress.

[0006] To achieve the above objectives, this application provides a semiconductor chip, including a chip body and an external electrode. A buffer electrode is also formed between the chip body and the external electrode. The buffer electrode includes a tensile stress layer, which is formed by alternating layers of metal layers with high thermal expansion coefficients and metal layers with low thermal expansion coefficients to offset the compressive stress in at least a portion of the epitaxial layer of the chip body.

[0007] Both the buffer electrode and the external electrode are formed by vapor deposition.

[0008] Preferably, the metal layer with a high coefficient of thermal expansion comprises tin, aluminum, gold, silver, copper, or nickel; and the metal layer with a low coefficient of thermal expansion comprises titanium, platinum, or chromium.

[0009] Preferably, the tensile stress layer comprises 2-5 layers of metal layers with high thermal expansion coefficients and 2-5 layers of metal layers with low thermal expansion coefficients, and the thickness of each of the metal layers with high thermal expansion coefficients and low thermal expansion coefficients is 0.05-0.15 μm.

[0010] Optionally, the metal layer with large thermal expansion coefficient is a gold layer with a thickness of 0.05 μm, and the metal layer with small thermal expansion coefficient is a titanium layer with a thickness of 0.05 μm. Preferably, the metal layer with large thermal expansion coefficient is formed by high-temperature evaporation, and the metal layer with large thermal expansion coefficient generates a tensile stress effect when it is cooled to room temperature after high-temperature evaporation. In the tensile stress layer, the gold and titanium are alternately stacked to form a regional tensile stress system, and the gold electrode has a large thermal expansion coefficient. After high-temperature evaporation and cooling to room temperature, the gold layer has a tensile stress. If the thickness of the gold layer is too large, the tensile stress will relax, the gold layer will peel off, and the effect will be reduced. Therefore, the titanium with a small thermal expansion coefficient is used as a buffer, and then the gold thin film is evaporated, and the tensile stress effect is increased in this way.

[0011] Optionally, the metal layer with large thermal expansion coefficient is an aluminum layer with a thickness of 0.05 μm, and the metal layer with small thermal expansion coefficient is a titanium layer with a thickness of 0.05 μm. In this scheme, the tensile stress system in the buffer electrode is set to aluminum / titanium. Aluminum has a large thermal expansion coefficient, thereby generating a strong tensile stress, effectively offsetting the compressive stress in the epitaxial layer of the chip body, and reducing the warping degree of the thinned wafer.

[0012] Preferably, the buffer electrode further comprises a metal adhesion layer, a tensile stress layer, and a conductive protective layer. The metal adhesion layer is formed on the chip body, the tensile stress layer is formed on the metal adhesion layer, and the conductive protective layer is formed on the tensile stress layer. The metal adhesion layer enables the tensile stress layer to be better formed on the chip body, and the conductive protective layer effectively protects the structure of the buffer electrode.

[0013] Specifically, the conductive protective layer is a combination of one or more of platinum, gold, and titanium, and the thickness of the conductive protective layer is 0.3-2 μm.

[0014] Specifically, the metal adhesion layer comprises a combination of one or more of nickel, titanium, and chromium, and the thickness of the metal adhesion layer is 0.02-0.08 μm.

[0015] More specifically, the metal adhesion layer comprises a chromium layer with a thickness of 0.04 μm.

[0016] More specifically, when the metal layer with large thermal expansion coefficient is a gold layer, the conductive protective layer comprises a platinum layer with a thickness of 0.5 μm formed on the tensile stress layer and a titanium layer with a thickness of 0.5 μm formed on the platinum layer with a thickness of 0.5 μm.

[0017] More specifically, when the metal layer with large thermal expansion coefficient is an aluminum layer, the conductive protective layer comprises a gold layer with a thickness of 0.5 μm formed on the tensile stress layer and a platinum layer with a thickness of 0.5 μm formed on the gold layer with a thickness of 0.5 μm.

[0018] Optionally, the outer electrode comprises a plurality of metal layers stacked in sequence, each of the metal layers has a thickness of 0.05-2 microns, and the metal layers comprise at least two of aluminum, titanium, nickel, gold, platinum and chromium.

[0019] In particular, the outer electrode comprises a 0.1-micron titanium layer, a 0.2-micron aluminum layer, a 0.15-micron titanium layer, a 0.2-micron aluminum layer, a 0.15-micron titanium layer, a 1.5-micron nickel layer and a 0.15-micron gold layer stacked in sequence.

[0020] Preferably, the chip body is formed on a substrate, and the chip body comprises a GaN epitaxial layer and an indium tin oxide layer stacked in sequence, and the chip body further comprises a distributed Bragg reflector.

[0021] In particular, the substrate is an Al2O3 substrate, the Al2O3 substrate has a thickness of 400-900 microns, the GaN epitaxial layer comprises an N-GaN layer, a light-emitting layer comprising an InGaN quantum well, and a P-GaN layer, and the GaN epitaxial layer has a thickness of 3-15 microns.

[0022] In the application, the semiconductor chip is a mini-LED.

[0023] In the application, the buffer electrode has two buffer electrodes, and the two buffer electrodes are distributed adjacent to two opposite sides of the semiconductor chip in a side surface of the semiconductor chip, so that the application can buffer the compressive stress of the epitaxial layer from two ends of the semiconductor chip.

[0024] The application further provides a semiconductor wafer comprising a substrate and a plurality of semiconductor chips arranged on the substrate, wherein the semiconductor chips are the semiconductor chips as described above, and the chip body of the semiconductor chip is formed on the substrate.

[0025] Compared with the prior art, the application provides a buffer electrode between the chip body and the outer electrode, the buffer electrode has a tensile stress system with regional tensile stress effect formed by the metal layers with large thermal expansion coefficient and the metal layers with small thermal expansion coefficient stacked alternately, so as to offset at least part of the compressive stress in the epitaxial layer of the chip body, reduce the wafer warping after thinning, and improve the chip yield. In particular, when the semiconductor chips are arranged on the substrate to form dies, each die has a buffer electrode, which can at least partially offset the compressive stress in the epitaxial layer of the die, reduce the stretching effect of the epitaxial surface in the epitaxial layer, reduce the wafer warping after thinning, and improve the chip yield. BRIEF DESCRIPTION OF DRAWINGS

[0026] Fig. 1 is a stress method of an epitaxial layer on a wafer.

[0027] Fig. 2 is a side view of wafer warping after the substrate is thinned.

[0028] Fig. 3 is a structural diagram of a semiconductor chip in Embodiment 1 of the present application.

[0029] Fig. 4 is a structural diagram of an external electrode in the present application.

[0030] Fig. 5 is a structural diagram of a buffer electrode in Embodiment 1 of the present application.

[0031] Fig. 6 is a structural diagram of a semiconductor chip in Embodiment 2 of the present application.

[0032] Fig. 7 is a structural diagram of a buffer electrode in Embodiment 2 of the present application. DETAILED DESCRIPTION

[0033] To make the technical contents, structural features, achieved purposes and effects of the present application clear, the following will be described in detail in combination with the embodiments and the accompanying drawings.

[0034] The present application discloses a semiconductor wafer 100, comprising a substrate 10 and a plurality of semiconductor chips 200 arranged on the substrate 10, wherein a chip body 2 of the semiconductor chip 200 is formed on the substrate 10.

[0035] The substrate 10 is an Al2O3 substrate, and the thickness of the Al2O3 substrate is 400-900 μm. The substrate 10 is not limited to the Al2O3 substrate.

[0036] Referring to Figs. 1 and 2, which are side views of a stress method of an epitaxial layer on the wafer 100 and wafer warping after the substrate 10 is thinned, in order to reduce the stretching effect of the epitaxial surface of the epitaxial layer, reduce the warping degree of the wafer after being thinned, and improve the chip yield, the present application provides a buffer electrode 50 between the chip body 2 of the semiconductor chip 200 and the external electrode 40, which can at least partially offset the compressive stress in the epitaxial layer in the die. The semiconductor chip 200 is a mini-LED, and the epitaxial layer is a GaN epitaxial layer.

[0037] Embodiment 1:

[0038] Referring to Fig. 3, the semiconductor chip 200 comprises a chip body 2 and an external electrode 40, and a buffer electrode 50 is further formed between the chip body 2 and the external electrode 40.

[0039] Referring to Fig. 5, the buffer electrode 50 comprises a metal adhesion layer 51 formed on the chip body 2, a tensile stress layer 52 formed on the metal adhesion layer 51, and a conductive protective layer 53 formed on the tensile stress layer 52, wherein the tensile stress layer 52 is formed by stacking a plurality of layers of metal with large thermal expansion coefficient 521 and metal with small thermal expansion coefficient 522 in sequence. Of course, the tensile stress layer 52 in the buffer electrode 50 can be directly formed on the chip body 2, without the metal adhesion layer 51, and the external electrode 40 can be directly formed on the outer side of the tensile stress layer 52, without the conductive protective layer 53.

[0040] Referring to Fig. 3, the chip body 2 is formed on the substrate 10, and includes a GaN epitaxial layer 20 and an indium tin oxide layer 30 stacked in sequence, and a distributed Bragg reflector 60 is further formed outside the chip body 2. The GaN epitaxial layer 20 includes an N-GaN layer, a light-emitting layer containing an InGaN quantum well, and a P-GaN layer, and has a thickness of 3-15 μm. Of course, the structure of the chip body 2 is not limited to this.

[0041] The buffer electrode 50 and the outer electrode 40 are both formed by evaporation.

[0042] The outer electrode 40 includes a plurality of metal layers stacked in sequence, and each of the metal layers has a thickness of 0.05-2 μm. Referring to Fig. 4, the outer electrode 40 includes a 0.1 μm titanium layer 41, a 0.2 μm aluminum layer 42, a 0.15 μm titanium layer 43, a 0.2 μm aluminum layer 44, a 0.15 μm titanium layer 45, a 1.5 μm nickel layer 46, and a 0.15 μm gold layer 47 stacked in sequence. The metal layers of the outer electrode 40 include at least two of aluminum, titanium, nickel, gold, platinum, and chromium.

[0043] Referring to Fig. 5, the metal adhesion layer 51 of the buffer electrode 50 contains one or more of nickel, titanium, and chromium, and has a thickness of 0.02-0.08 μm. In this embodiment, the metal adhesion layer 51 includes a 0.04 μm chromium layer, as shown in Fig. 5.

[0044] In this embodiment, the tensile stress layer 52 includes 2-5 layers of large thermal expansion coefficient metal layers 521 and 2-5 layers of small thermal expansion coefficient metal layers 522, and each of the large thermal expansion coefficient metal layers 521 and the small thermal expansion coefficient metal layers 522 has a thickness of 0.05-0.15 μm. The large thermal expansion coefficient metal layers 521 contain tin, aluminum, gold, silver, copper, or nickel, etc., and the small thermal expansion coefficient metal layers 522 contain titanium, platinum, or chromium, etc.

[0045] Referring to Fig. 5, the large thermal expansion coefficient metal layers 521 are 0.05 μm gold layers, and the small thermal expansion coefficient metal layers 522 are 0.05 μm titanium layers. In this embodiment, there are 3 layers of large thermal expansion coefficient metal layers 521 and 3 layers of small thermal expansion coefficient metal layers 522.

[0046] The large thermal expansion coefficient metal layer 521 is formed by high-temperature evaporation, and the large thermal expansion coefficient metal layer 521 generates a tensile stress effect after recovering to room temperature after high-temperature evaporation. In the tensile stress layer 52, the gold / titanium staggered stack is a regional tensile stress system, and the thermal expansion coefficient of gold in the system is larger. After high-temperature evaporation and recovery to room temperature, the gold layer has a tensile stress. If the film thickness of the gold layer is too thick, the tensile stress relaxation will occur, the gold layer will peel off, and the effect will be reduced. Therefore, the titanium with a smaller thermal expansion coefficient is buffered, and then the gold film is evaporated, and the tensile stress effect is increased in this way.

[0047] The conductive protective layer 53 is one or more combinations of platinum, gold, and titanium, and the thickness of the conductive protective layer 53 is 0.3-2 μm. Referring to FIG. 5, the conductive protective layer 53 includes a 0.5-μm-thick platinum layer 531 formed on the tensile stress layer 52 and a 0.5-μm-thick titanium layer 532 formed on the 0.5-μm-thick platinum layer 531.

[0048] The distributed Bragg reflector 60 is formed by the mutual staggered stack of silicon oxide layers and titanium oxide layers, the number of stacked layers is 12-68, and the thickness of each layer is 0.08-0.15 μm. In this embodiment, the sum of the silicon oxide layers and the titanium oxide layers in the Bragg reflector is 33 layers, and the total thickness is 4 μm.

[0049] Embodiment 2:

[0050] Referring to FIG. 6, the semiconductor chip 200 includes a chip body 2 and an external electrode 40, and a buffer electrode 50 is further formed between the chip body 2 and the external electrode 40.

[0051] Referring to FIG. 7, the buffer electrode 50 includes a metal adhesion layer 51 formed on the chip body 2, a tensile stress layer 52a formed on the metal adhesion layer 51, and a conductive protective layer 53a formed on the tensile stress layer 52a, and the tensile stress layer 52a is formed by the sequential stack of a plurality of large thermal expansion coefficient metal layers 521a and small thermal expansion coefficient metal layers 522a.

[0052] Referring to FIG. 6, the chip body 2 is formed on a substrate 10, and the chip body 2 includes a GaN epitaxial layer 20 and an indium tin oxide layer 30 stacked in sequence, and a distributed Bragg reflector 60 is further formed outside the chip body 2. The GaN epitaxial layer 20 includes an N-GaN layer, a light-emitting layer containing an InGaN quantum well, and a P-GaN layer, and the thickness of the GaN epitaxial layer 20 is 3-15 μm.

[0053] The buffer electrode 50 and the external electrode 40 are both formed by evaporation.

[0054] The outer electrode 40 comprises a plurality of metal layers stacked in sequence, each of the metal layers having a thickness of 0.05-2 μm. Referring to FIG. 4, the outer electrode 40 comprises a 0.1 μm titanium layer 41, a 0.2 μm aluminum layer 42, a 0.15 μm titanium layer 43, a 0.2 μm aluminum layer 44, a 0.15 μm titanium layer 45, a 1.5 μm nickel layer 46, and a 0.15 μm gold layer 47 stacked in sequence.

[0055] Referring to FIG. 7, in the buffer electrode 50, the metal adhesion layer 51 comprises one or more of nickel, titanium, and chromium, and has a thickness of 0.02-0.08 μm. In this embodiment, the metal adhesion layer 51 comprises a 0.04 μm chromium layer.

[0056] In this embodiment, the tensile stress layer 52a comprises 2-5 layers of large thermal expansion coefficient metal layers 521a and 2-5 layers of small thermal expansion coefficient metal layers 522a, each of the large thermal expansion coefficient metal layers 521a and the small thermal expansion coefficient metal layers 522a having a thickness of 0.05-0.15 μm. The large thermal expansion coefficient metal layers 521a comprise tin, aluminum, gold, silver, copper, or nickel, etc., and the small thermal expansion coefficient metal layers 522a comprise titanium, platinum, or chromium, etc.

[0057] Referring to FIG. 7, the large thermal expansion coefficient metal layers 521a are 0.05 μm aluminum layers, and the small thermal expansion coefficient metal layers 522a are 0.05 μm titanium layers. In this scheme, aluminum has a larger thermal expansion coefficient, and can generate stronger tensile stress, and more effectively offset the compressive stress in the GaN epitaxial layer 20 in the chip body 2, and reduce the warpage of the thinned wafer 100. In this embodiment, there are 3 layers of large thermal expansion coefficient metal layers 521a and 3 layers of small thermal expansion coefficient metal layers 522a.

[0058] The conductive protective layer 53a comprises one or more of platinum, gold, and titanium, and has a thickness of 0.3-2 μm. Referring to FIG. 7, the conductive protective layer 53a comprises a 0.5 μm gold layer 531a formed on the tensile stress layer 52a, and a 0.5 μm platinum layer 532a formed on the 0.5 μm gold layer 531a.

[0059] The above description is merely preferred embodiments of the present application, and is not intended to limit the scope of the present application. Therefore, equivalents, modifications, and variations of the present application are still within the scope of the present application.

Claims

1. A semiconductor chip comprising a chip body, an external electrode, characterized by: A buffer electrode is further formed between the chip body and the external electrode, and the buffer electrode comprises a tensile stress layer formed by alternately stacking a plurality of layers of high thermal expansion coefficient metal and low thermal expansion coefficient metal to offset at least part of the compressive stress in the epitaxial layer of the chip body.

2. The semiconductor chip of claim 1, wherein: The high thermal expansion coefficient metal layer comprises tin, aluminum, gold, silver, copper or nickel; and the low thermal expansion coefficient metal layer comprises titanium, platinum or chromium.

3. The semiconductor chip of claim 1, wherein: The tensile stress layer comprises 2-5 layers of high thermal expansion coefficient metal and 2-5 layers of low thermal expansion coefficient metal, and each layer of the high thermal expansion coefficient metal and low thermal expansion coefficient metal has a thickness of 0.05-0.15 μm.

4. The semiconductor chip of claim 3, wherein: The high thermal expansion coefficient metal layer is a 0.05 μm gold layer, and the low thermal expansion coefficient metal layer is a 0.05 μm titanium layer; or The high thermal expansion coefficient metal layer is a 0.05 μm aluminum layer, and the low thermal expansion coefficient metal layer is a 0.05 μm titanium layer.

5. The semiconductor chip of claim 4, wherein: The high thermal expansion coefficient metal layer is formed by high-temperature evaporation, and the high thermal expansion coefficient metal layer generates a tensile stress effect after being restored to room temperature after high-temperature evaporation.

6. The semiconductor chip of claim 1, wherein: The buffer electrode further comprises a metal adhesion layer and a conductive protective layer, the metal adhesion layer is formed on the chip body, the tensile stress layer is formed on the metal adhesion layer, and the conductive protective layer is formed on the tensile stress layer.

7. The semiconductor chip of claim 6, wherein: The conductive protective layer is a combination of one or more of platinum, gold and titanium, and the conductive protective layer has a thickness of 0.3-2 μm. The metal adhesion layer comprises a combination of one or more of nickel, titanium and chromium, and the metal adhesion layer has a thickness of 0.02-0.08 μm.

8. The semiconductor chip of claim 7, wherein: The metal adhesion layer comprises a 0.04 μm chromium layer. When the high thermal expansion coefficient metal layer is a gold layer, the conductive protective layer comprises a 0.5 μm platinum layer formed on the tensile stress layer and a 0.5 μm titanium layer formed on the 0.5 μm platinum layer. When the high thermal expansion coefficient metal layer is an aluminum layer, the conductive protective layer comprises a 0.5 μm gold layer formed on the tensile stress layer and a 0.5 μm platinum layer formed on the 0.5 μm gold layer.

9. The semiconductor chip of claim 1, wherein: The external electrode comprises a plurality of metal layers stacked in sequence, each of the metal layers has a thickness of 0.05-2 μm, and the metal layers comprise at least two of aluminum, titanium, nickel, gold, platinum and chromium.

10. The semiconductor chip of claim 9, wherein: The external electrode comprises a 0.1 μm titanium layer, a 0.2 μm aluminum layer, a 0.15 μm titanium layer, a 0.2 μm aluminum layer, a 0.15 μm titanium layer, a 1.5 μm nickel layer and a 0.15 μm gold layer stacked in sequence.

11. The semiconductor chip of claim 1, wherein: The buffer electrode has two and is distributed adjacent to two opposite sides of the semiconductor chip in a side surface of the semiconductor chip.

12. A semiconductor wafer, characterized by: A substrate and a plurality of semiconductor chips disposed on the substrate, the semiconductor chips are as claimed in any one of claims 1-11, and the chip body of the semiconductor chips is formed on the substrate.

Images