Cache replacement policy management method and apparatus and electronic device

Abstract

A cache replacement policy management method and apparatus and an electronic device, relating to the technical field of computers. The method comprises: when a first replacement policy is used, acquiring from a simulator cache access information of a target cache group, the simulator being used for simulating the operation process of a processor system; on the basis of cache block addresses, classifying the cache access information and, on the basis of a timestamp, sorting the classified cache access information; on the basis of a sorting result, drawing a first cache access observation graph corresponding to the first replacement policy; and, on the basis of the first cache access observation graph, evaluating the decision-making performance of the first replacement policy. The present application allows for transparent cache operation processes, enhances policy interpretability and helps to assist in debugging and design.

Description

Cache replacement policy management method and device and electronic equipment

[0001] The present application claims priority to the Chinese patent application No. 202410726081.7, filed on June 6, 2024, and entitled "Cache replacement policy management method and device and electronic equipment", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of computer, and in particular, to a cache replacement policy management method and device and electronic equipment. BACKGROUND

[0003] In modern processors, cache often occupies a large proportion (more than 80%) of the chip area. Cache can use the temporal and spatial locality of application storage access to keep frequently accessed blocks in high-speed storage media, thereby improving program performance. However, due to the filtering of upper (L1 and L2) cache and other factors, the data access locality of L3 cache is poor, the utilization rate is low, and there are many dead blocks. Dead blocks are not accessed again before being replaced, causing waste of chip area and power consumption. At the same time, some data blocks that have reuse opportunities are replaced out of the cache before reuse due to capacity reasons. Cache replacement policy is one of the important ways to manage cache, and by reasonably planning the retention time of each cache block, the equivalent capacity of cache can be increased.

[0004] In order to evaluate the performance and power consumption of the processor and the corresponding optimization method, a clock-accurate full-system simulator is usually used to simulate the processor core and each component of the cache. The simulator can output relatively accurate counter values for performance and power consumption evaluation. Processor performance is usually evaluated by instructions per cycle (IPC). In the cache hierarchy subsystem, common evaluation indicators include miss rate, miss latency, etc. However, these indicators only evaluate the results of the replacement policy and cannot reflect the decision-making process of the replacement policy and the memory access characteristics of the application, so they cannot provide sufficient feedback for the design of the replacement policy.

[0005] SUMMARY

[0006] The embodiments of the present application provide a cache replacement policy management method, device and electronic equipment, which can solve the problem that the decision-making process of the replacement policy and the memory access characteristics of the application cannot be reflected in the related art, and the cache replacement policy cannot be provided with sufficient feedback.

[0007] To solve the above problems, the embodiment of the application discloses a cache replacement strategy management method, the method comprises:

[0008] obtaining, from a simulator, access information of a target cache group in a case of using a first replacement strategy; the simulator is used to simulate a running process of a processor system;

[0009] classifying the access information according to cache block addresses, and sorting the classified access information according to timestamps;

[0010] drawing a first access observation graph corresponding to the first replacement strategy based on the sorting result; the first access observation graph is used to reflect cache miss information and replacement block information in the target cache group when the first replacement strategy is used;

[0011] evaluating decision performance of the first replacement strategy according to the first access observation graph.

[0012] Optionally, the access information comprises related information of cache block access events; the drawing of the first access observation graph corresponding to the first replacement strategy based on the sorting result comprises:

[0013] determining a vertical coordinate of an access point according to a cache block address corresponding to the cache block access event, and determining a horizontal coordinate of the access point according to a sorting result corresponding to the cache block access event;

[0014] determining an identifier of the access point according to an access type of the cache block access event;

[0015] determining a color of the identifier according to a hit condition of the cache block access event;

[0016] drawing the first access observation graph corresponding to the first replacement strategy according to the vertical coordinate, the horizontal coordinate, the identifier and the color of the identifier of each access point.

[0017] Optionally, the access information further comprises refill information of a cache block refill event; the method further comprises:

[0018] in a case where there is a cache refill event in the target cache group, determining a refill block address and a replacement block address according to the refill information;

[0019] adding a replacement mark in the first access observation graph according to the refill block address and the replacement block address;

[0020] wherein a horizontal coordinate of the replacement mark is the same as a horizontal coordinate of an access point corresponding to the refill block address, and a vertical coordinate of the replacement mark is a vertical coordinate value corresponding to the replacement block address.

[0021] Optionally, the evaluating the decision performance of the first replacement strategy according to the first access observation graph comprises:

[0022] determining first cache miss information corresponding to the first replacement strategy according to the first access observation graph;

[0023] determining a target replacement block corresponding to each backfill block in the target cache group in the case of adopting a target replacement strategy according to access trace information reflected in the first access observation graph;

[0024] drawing a target access observation graph corresponding to the target replacement strategy according to the access trace information and the target replacement block;

[0025] determining target cache group miss information corresponding to the target replacement strategy according to the target access observation graph;

[0026] evaluating the decision performance of the first replacement strategy based on the first cache miss information and the target cache group miss information.

[0027] Optionally, the obtaining, from the simulator, access information of the target cache group in the case of adopting the first replacement strategy comprises:

[0028] obtaining a cache group identifier to be observed, the first replacement strategy, and a number of simulation instructions;

[0029] configuring the simulator according to the cache group identifier, the first replacement strategy, and the number of simulation instructions, so that the simulator executes a test program according to the first replacement strategy and the number of simulation instructions, and outputs access information of a target cache group corresponding to the cache group identifier.

[0030] Optionally, the method further comprises:

[0031] drawing a second access observation graph corresponding to a second replacement strategy;

[0032] determining performance scores of the first replacement strategy and the second replacement strategy according to the first access observation graph and the second access observation graph respectively;

[0033] in the case where the performance score of the first replacement strategy is lower than the performance score of the second replacement strategy, updating a cache replacement strategy of the target cache group to the second replacement strategy.

[0034] In another aspect, the embodiments of the present application disclose a management device of a cache replacement strategy, and the device comprises:

[0035] an acquisition module, configured to acquire, from a simulator, memory access information of a target cache set in a case where a first replacement strategy is adopted, the simulator being configured to simulate a running process of a processor system;

[0036] a preprocessing module, configured to classify the memory access information according to cache block addresses, and sort the classified memory access information according to time stamps;

[0037] a first drawing module, configured to draw a first memory access observation graph corresponding to the first replacement strategy based on the sorting result, the first memory access observation graph being configured to reflect cache miss information and replacement block information in the target cache set when the first replacement strategy is adopted;

[0038] an evaluation module, configured to evaluate decision performance of the first replacement strategy according to the first memory access observation graph.

[0039] In another aspect, an electronic device is also disclosed, which includes a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is configured to store executable instructions, and the executable instructions make the processor execute the aforementioned memory access method.

[0040] The embodiment of the present application also discloses a readable storage medium, when the instructions in the readable storage medium are executed by the processor of the electronic device, the electronic device can execute the aforementioned memory access method.

[0041] The embodiment of the present application has the following advantages:

[0042] The embodiment of the present application provides a cache replacement strategy management method, can draw a memory access observation graph from the memory access information of a target cache set provided by a simulator, and display all accesses and cache block refill events of the target cache set in a period of time from the perspective of cache block addresses, so that the refill and replacement timing of each cache block is clearly displayed, and the decision and influence of the replacement strategy are more intuitively displayed, feedback is provided for the design of the replacement strategy. The embodiment of the present application can realize the perspective of the cache running process, increase the interpretability of the strategy, and is beneficial to debugging and design.

[0043] The above description is only a summary of the technical solutions of the present application, in order to more clearly understand the technical means of the present application, the specific embodiments of the present application can be implemented according to the content of the description, and in order to make the above and other purposes, characteristics and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 is a flowchart illustrating the steps of an embodiment of a cache replacement strategy management method according to this application;

[0046] Figure 2 is an example of a memory access observation diagram according to this application;

[0047] Figure 3 is an example of another memory access observation diagram in this application;

[0048] Figure 4 is an example of a memory access observation graph for the two replacement strategies in this application;

[0049] Figure 5 is an example of a memory access observation diagram according to this application;

[0050] Figure 6 is an example of another memory access observation diagram in this application;

[0051] Figure 7 is an example of another memory access observation diagram in this application;

[0052] Figure 8 is a structural block diagram of a cache replacement strategy management device according to this application;

[0053] Figure 9 is a structural block diagram of an electronic device provided in this application. Specific Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0055] Method Implementation Examples

[0056] Referring to Figure 1, a flowchart illustrating an embodiment of a cache replacement strategy management method according to this application is shown. The method may specifically include the following steps:

[0057] Step 101: Obtain memory access information of the target cache group from the simulator when the first replacement strategy is adopted; the simulator is used to simulate the operation of the processor system.

[0058] Step 102, classifying the memory access information according to cache block addresses, and sorting the classified memory access information according to timestamps;

[0059] Step 103, drawing a first memory access observation graph corresponding to the first replacement strategy based on the sorting result; the first memory access observation graph is used to reflect cache miss information and replacement block information in the target cache group when the first replacement strategy is adopted;

[0060] Step 104, evaluating the decision performance of the first replacement strategy according to the first memory access observation graph.

[0061] The cache replacement strategy management method provided by the embodiments of the present application can evaluate the performance of the cache replacement strategy.

[0062] Cache is one of the important components of a computer processor, and is a storage device with a storage speed between a register and a memory. In a computer system, various storage devices (including registers, caches, memories, hard disks, etc.) can be divided into different levels according to working speed and unit cost. The closer to the processor end, the faster the working speed, the smaller the capacity, and the higher the cost per unit capacity; the closer to the memory end, the larger the capacity, the slower the working speed, and the lower the cost per unit capacity. The running speed of the cache is usually slower than that of the processor but faster than that of the memory. According to the locality principle of program execution, the data that is most likely to be repeatedly accessed is copied to the cache with a faster working speed, so that the data can be submitted to the processor with a very small time delay when the processor needs the data, thereby effectively reducing the time consumption of memory access and to a certain extent, covering up the working speed difference between the processor and the memory and improving the performance of the processor.

[0063] Due to the small capacity of the cache, the cache needs to be effectively managed, and the data required by the processor is put into the cache as much as possible, so as to reduce the probability of system memory access failure, reduce the memory access cost, and improve the overall performance of the system.

[0064] Currently, the mainstream cache replacement strategies mainly include random replacement strategy (Random), first in first out replacement strategy (FIFO), last in first out replacement strategy (LIFO), least recently used replacement strategy (LRU), least frequently used replacement strategy (LFU), adaptive replacement strategy (ARC), bimodal re-reference interval prediction replacement strategy (BRRIP), etc.

[0065] In a cache using ideal LRU replacement strategy, each cache line maintains a timestamp counter, which is used to record the clock count when the cache line was last accessed. Each time an invalidation occurs, the data in the cache line with the smallest timestamp in the same cache set will be replaced out of the cache, and the cache line will be used to store the newly read data from the memory. At the same time, each access, including the access of newly added data after invalidation, will update the timestamp in the cache line of the corresponding data, so as to ensure that the data replaced each time is from the cache line with the least recent use, i.e. the cache line with the smallest timestamp in the same set.

[0066] FIFO strategy is to replace data according to the order in which the data enters the cache. The data that enters the cache earliest will be replaced earliest, and the data that enters the cache latest will be kept.

[0067] LFU strategy is to replace data according to the frequency of access of each data item. Less frequently accessed data will be replaced first to make room for more frequently accessed data.

[0068] Random replacement strategy is a simple and direct method, which randomly selects a data for replacement. Due to randomness, this strategy cannot guarantee that the cache is storing the most useful data.

[0069] In addition, for applications with poor locality, the cache can use a strategy that does not update the timestamp of the newly added data cache line, i.e. the newly added data is placed in the first replaced position, which is usually called LRU position insertion policy (LIP).

[0070] In practical applications, selecting an appropriate cache replacement policy has a significant impact on the system performance of a computer system. Different application scenarios can have different requirements for the cache replacement policy. Common evaluation indicators for the cache replacement policy include: hit ratio, replacement overhead, fairness, miss rate, miss latency, and the like. Among them, the hit ratio refers to the proportion of data already existing in the cache in cache access, and a high hit ratio means that the data in the cache can meet most access demands, and the system performance is good. The replacement overhead refers to the time and computing resources required for cache replacement operations, and a lower replacement overhead can improve the response speed of the system. The fairness refers to whether the cache replacement policy is fair when treating different data items. If some data is frequently replaced, while other data is rarely replaced, it can lead to unbalanced system performance. The miss rate refers to the ratio of the number of times that the required data is not found to the total number of requests in cache access, and a high miss rate means that the data in the cache cannot meet most access demands, and the system performance is poor. The miss latency refers to the access delay caused by cache miss, and the higher the miss latency, the poorer the system performance.

[0071] It can be understood that the above evaluation indicators are only evaluations of the cache replacement results, and cannot reflect the decision-making process of the replacement policy and the memory access characteristics of the application, and cannot provide sufficient feedback for the design of the replacement policy.

[0072] The management method of the cache replacement policy provided by the embodiments of the present application can provide memory access information of a target cache set through a simulator, draw a micro-observation graph of memory access sequence in a set from the perspective of a cache block address, that is, a first memory access observation graph in the present application, display all access and cache fill events of the target cache set within a period of time, and clearly display the cache fill and replacement timing of each cache block, and more intuitively display the decision (selected replacement block) and influence (whether it causes subsequent access miss of the replacement block) of the replacement policy, thereby providing feedback for the design of the replacement policy.

[0073] It should be noted that the simulator in the embodiments of the present application is used to simulate the running process of a processor system. The processor system includes a processor core, a cache, and a memory, and the cache usually includes multiple levels of caches. The simulator can simulate each component such as the processor core and the cache, and provide memory access information of a target cache set. The memory access information of the target cache set includes memory access information from an upper cache and prefetch information of the current cache.

[0074] Optionally, the memory access information comprises at least one of the following: a cache block address accessed, an access type, an access hit condition, an access timestamp, and a replacement block address.

[0075] As an example, before full system simulation of a processor system is performed by a simulator, a user can specify a target cache set number to be observed in a certain level cache, the simulator discovers accesses from a higher level cache and local prefetches in the target cache set, and records relevant information and outputs to a specified file during simulation. The accesses from the higher level cache include prefetches sent by the higher level cache and read / write requests from a CPU, and the local prefetches include prefetch requests sent by the local cache. After the requests are discovered, the information to be recorded includes a cache block address accessed, an access type, an access hit condition, an access timestamp, and a replacement block address. The access hit condition includes a hit or a miss. The replacement block address refers to an address of a cache block replaced when a cache block is refilled.

[0076] Optionally, the access type includes a read / write of a processor core, a prefetch of a higher level cache, and a prefetch of a local cache.

[0077] In the embodiment, after the memory access information of the target cache set is obtained from the simulator, the memory access information is classified according to cache block addresses and arranged in time sequence to form an access point graph of the target cache set in a time period. Different events are marked on the access point graph according to event types, such as a cache block refill event, a cache block miss event, and a cache block hit event, to obtain a first memory access observation graph corresponding to the target cache set.

[0078] According to the first memory access observation graph, cache miss information and replacement block information in the target cache set when the first replacement strategy is adopted can be intuitively reflected. For example, according to the first memory access observation graph, a replacement block in the target cache set can be found, and whether the replacement block causes a subsequent access miss after the replacement block is replaced out of the cache can also be found. The number of cache misses in the target cache set can also be counted based on the first memory access observation graph. Based on the first memory access observation graph, the first replacement strategy can be evaluated from micro memory access characteristics in the target cache set, such as whether memory access exists in reuse and characteristics of reuse, and feedback can be provided for replacement strategy design.

[0079] Optionally, the memory access information of the target cache set when the first replacement strategy is adopted is obtained from the simulator in step 101, and the method comprises the following steps.

[0080] Step S11, obtaining a cache set identifier to be observed, a first replacement policy, and a number of simulation instructions;

[0081] Step S12, configuring the simulator according to the cache set identifier, the first replacement policy, and the number of simulation instructions, so that the simulator executes a test program according to the first replacement policy and the number of simulation instructions, and outputs access information of a target cache set corresponding to the cache set identifier.

[0082] The simulator in the embodiments of the present application can include, but is not limited to, a full-system simulator, a cache simulator, and the like, and the simulation mode can be functional simulation or performance simulation. Before the simulator runs, the cache set identifier to be observed, the first replacement policy, and the number of simulation instructions need to be specified. The cache set identifier can include a cache level, a target cache set number, and the like. The simulator executes a test program according to the first replacement policy and the number of simulation instructions, and outputs access information of a target cache set, for example, an access address of each access, an access request type, whether an access hits, an access timestamp, and an address of a cache block replaced when a cache block backfill occurs, and the like.

[0083] In an optional embodiment of the present application, the access information includes related information of a cache block access event; and step 103 of drawing a first access observation graph corresponding to the first replacement policy based on the sorting result includes:

[0084] Step S21, determining a vertical coordinate of an access point according to a cache block address corresponding to the cache block access event, and determining a horizontal coordinate of the access point according to a sorting result corresponding to the cache block access event;

[0085] Step S22, determining an identifier of the access point according to an access type of the cache block access event;

[0086] Step S23, determining a color of the identifier according to a hit condition of the cache block access event;

[0087] Step S24, drawing a first access observation graph corresponding to the first replacement policy according to the vertical coordinate, the horizontal coordinate, the identifier, and the color of the identifier of each access point.

[0088] When drawing the first memory access observation chart, the vertical coordinate of the access point can be determined according to the cache block address corresponding to the cache access event, and the horizontal coordinate of the access point can be determined according to the sorting result corresponding to the cache block access event. Illustratively, the access address tag can be determined according to the accessed cache block address. The access address tag can be obtained by performing a hash operation on the cache block address, or the high bits (for example, the high 4 bits) of the cache block address can be used as the access address tag. Then, the vertical coordinate is determined according to the access address tag. If the tag appears for the first time, the vertical coordinate is the current maximum vertical coordinate value + 1, otherwise it is equal to the vertical coordinate value corresponding to the original tag. After sorting the memory access information according to the access timestamp, the horizontal coordinate of the access point can be equal to the horizontal coordinate value of the previous access point + 1.

[0089] Next, the identifier of the access point is determined according to the access type. The access type can include processor core read and write, upper level cache prefetch, and current level cache prefetch. Different identifiers are used to represent different access types. For example, the marks "□", "○" and "△" are used to represent CPU read and write, upper level prefetch and current level prefetch, respectively. For each cache block access, different colors are used to represent whether the access causes a miss.

[0090] According to the vertical coordinate, the horizontal coordinate, the identifier of each access point, and the color of the identifier, the first memory access observation chart corresponding to the first replacement strategy can be drawn.

[0091] Optionally, the memory access information further includes refill information of a cache block refill event; and the method further includes:

[0092] In the case where the target cache group has a cache refill event, the refill block address and the replacement block address are determined according to the refill information.

[0093] In the case where the target cache group has a cache refill event, the refill block address and the replacement block address are determined according to the refill information.

[0094] The horizontal coordinate of the replacement mark is the same as the horizontal coordinate of the access point corresponding to the refill block address, and the vertical coordinate of the replacement mark is the vertical coordinate value corresponding to the replacement block address.

[0095] In the embodiments of the present application, if a cache block refill event occurs in the target cache group, a replacement mark can be added to the first memory access observation chart to indicate the refill block and the replacement block. The refill block refers to a data block refilled from the next level cache or the memory to the current level cache, and the replacement block refers to a cache block replaced by the refill block in the cache. The cache block refill event can be triggered by a cache block access miss or a current level prefetch access.

[0096] Exemplarily, if a cache block is refilled due to a cache block access miss or a level-1 prefetch access, the old cache block is replaced, which is indicated by a vertical dashed line and a replacement mark "X" in the figure. The horizontal coordinate of the replacement mark "X" is the same as that of the access point, and the vertical coordinate is equal to the vertical coordinate value corresponding to the replacement block address tag, representing that the cache block corresponding to the left address tag is replaced out.

[0097] Referring to FIG. 2, a memory access observation diagram provided by an embodiment of the present application is shown. As shown in FIG. 2, a Set memory access observation diagram of a 2-way set associative cache is shown from the perspectives of a cache set and a cache block address tag, respectively. An example shows 10 accesses to three cache blocks with address tags A, B and C in the set, and the corresponding cache block access sequence is "A-B-C-C-A-A-D-E-A-A". The left memory access observation diagram from the perspective of the cache set is a common observation method at present, which shows the cache blocks stored in the cache set before and after each access. However, the access miss and replacement block information can only be associated with the access sequence, which is very scattered, and cannot reflect the cache block reuse. In the right memory access observation diagram from the perspective of the cache block address tag, the access miss information and the replacement block information can be associated with the cache block address, which clearly shows the access, refilling, replacement and reuse of each cache block. In addition, the memory access observation diagram from the perspective of the cache block address tag can also be used to conveniently observe the program working set size in this period. The rectangular space surrounded by all address tags and all accesses in the set can be regarded as the access space-time diagram of the cache set, and the number of "X" marks indicates the number of cache misses in this period, representing the performance of the corresponding replacement strategy.

[0098] In the memory access observation diagram from the perspective of the cache block address tag, the dashed line circle represents a memory access miss, and the solid line circle represents a memory access hit. As can be seen from the figure, cache block A is reused at the 5th and 6th accesses, and cache block C is reused at the 4th access. At the 3rd access, cache block C replaces cache block A when refilling, thereby causing a memory access miss of cache block A at the 5th reuse.

[0099] Referring to FIG. 3, another memory access observation diagram provided by an embodiment of the present application is shown. It should be noted that FIG. 3 shows an example of a memory access observation diagram with prefetching. Compared with the first 6 cache set accesses shown in FIG. 2, a level-1 prefetch access to cache block C is added before the 3rd access, and the cache block is taken out from the lower-level cache (or memory) before the arrival of the upper-level read-write access, thereby reducing a miss of the upper-level read-write access.

[0100] Optionally, the decision performance of the first replacement strategy is evaluated according to the first memory access observation diagram in step 104, including:

[0101] Step S41, determining first cache miss information corresponding to the first replacement strategy according to the first memory access observation graph;

[0102] Step S42, determining a target replacement block corresponding to each backfill block in the target cache set in the case of adopting a target replacement strategy according to the memory trace information reflected in the first memory access observation graph;

[0103] Step S43, drawing a target memory access observation graph corresponding to the target replacement strategy according to the memory trace information and the target replacement block;

[0104] Step S44, determining target cache set miss information corresponding to the target replacement strategy according to the target memory access observation graph;

[0105] Step S45, evaluating the decision performance of the first replacement strategy based on the first cache miss information and the target cache set miss information.

[0106] In the embodiments of the present application, the target replacement block corresponding to each backfill block in the target cache set in the case of adopting a target replacement strategy can be determined according to the memory trace information reflected in the first memory access observation graph corresponding to the first replacement strategy. The target replacement strategy refers to a theoretically optimal strategy. For example, the target replacement strategy can be to select a cache block used in the future for replacement when each cache block backfill causes replacement. That is, in the existing trace information, the cache block not accessed in the trace is replaced first, and then the cache block accessed in the trace is replaced.

[0107] The target memory access observation graph corresponding to the target replacement strategy is drawn according to the target replacement block and the memory trace information determined according to the target replacement strategy. The drawing process can refer to the drawing process of the first memory access observation graph, which will not be described further in the embodiments of the present application.

[0108] The target memory access observation graph can be used to determine the performance upper limit of the replacement strategy and evaluate the performance of different replacement strategies. For example, for the first replacement strategy to be evaluated, the first cache miss information corresponding to the first replacement strategy can be determined based on the first memory access observation graph, the target cache miss information corresponding to the target replacement strategy can be determined based on the target memory access observation graph, and then the two sets of cache miss information are compared. The closer the data in the first cache miss information is to the target cache miss information, the better the performance of the first replacement strategy. The cache miss information can include the number of upper read misses, the number of upper write back misses, and the like.

[0109] In addition, the number of misses of each type of access in the target cache group when the first replacement strategy is used, such as CPU read / write miss, upper-level prefetch miss, and the like, can be counted directly based on the first access observation graph corresponding to the first replacement strategy, and the performance of the first replacement strategy is evaluated based on the counting result.

[0110] Optionally, the method further includes:

[0111] Step S51, drawing a second access observation graph corresponding to a second replacement strategy;

[0112] Step S52, determining the performance scores of the first replacement strategy and the second replacement strategy respectively according to the first access observation graph and the second access observation graph;

[0113] Step S53, updating the cache replacement strategy of the target cache group to the second replacement strategy in a case where the performance score of the first replacement strategy is lower than the performance score of the second replacement strategy.

[0114] In the embodiments of the present application, the performance of different replacement strategies can be compared by drawing the access observation graphs corresponding to the different replacement strategies respectively, and a replacement strategy with better performance can be selected as the cache replacement strategy actually used in the target cache group, so as to improve the cache replacement performance of the target cache group and improve the memory access performance of the entire computer system.

[0115] The first replacement strategy and the second replacement strategy can be any replacement strategy as long as they are different.

[0116] Exemplarily, referring to FIG. 4, the access observation graphs of two replacement strategies provided by the embodiments of the present application are shown. The replacement decision of strategy X is the same as that of FIG. 2, and cache block A is replaced when cache block C is backfilled at the third access, so that an access miss is caused when block A is reused at the fifth access. In contrast, strategy Y replaces cache block B at the third access, and hits when block A is reused. As can be seen from FIG. 4, strategy Y has one less upper-level read / write access miss than strategy X, and is also the optimal replacement strategy in this memory access scenario.

[0117] Referring to FIGS. 5 to 7, a memory access observation diagram provided by an embodiment of the present application is shown. Specifically, FIGS. 5 to 7 show an instance of the LRU and BRRIP strategies in the libquantum application of the SPEC 2006 test set using the cache replacement strategy management method provided by an embodiment of the present application. FIG. 5 is a memory access observation diagram corresponding to the LRU replacement strategy, FIG. 6 is a memory access observation diagram corresponding to the BRRIP replacement strategy, and FIG. 7 is a memory access observation diagram corresponding to the optimal replacement strategy. In the instance configuration, the associativity of the L3 cache is 16, and 40 million (40M) instructions are run, and the memory access observation diagrams of the two replacement strategies in the L3 cache are plotted. As can be seen from the diagrams, 32 different cache blocks are cyclically accessed in this period. Due to the characteristics of the L3 set association, only 16 different cache blocks can be accommodated in a cache set (Set), and the BRRIP protects the 16 cache blocks accessed in the front to avoid cache misses caused by the re-access of these memory accesses. The LRU always replaces the cache block accessed earliest, but since the reuse distance (the number of different cache blocks between two accesses of the same cache block) of all cache blocks is 32, which is greater than the set capacity 16, the cache block is replaced out of the set when re-accessed, causing cache misses. In the optimal strategy generated, the method of retaining the first 16 cache blocks is also used.

[0118] In the instance, there are superior read requests and superior write-back requests, and since the write-back requests are not on the critical path, the misses thereof have little impact on performance. The read requests issued by the superior cache are closely related to the data supply of the CPU, and the misses thereof will greatly affect the performance. According to the cache miss statistics, the LRU strategy causes 68 superior read access misses, while the BRRIP strategy causes only 50 superior read access misses, close to the 48 misses caused by the optimal strategy, and the performance is better.

[0119] In summary, the cache replacement strategy management method provided by an embodiment of the present application can draw a memory access observation diagram from the perspective of the cache block address by using the memory access information of the target cache set provided by the simulator, display all accesses (Access) and cache block refill events of the target cache set in a period of time, clearly display the refill and replacement timing of each cache block, more intuitively display the decision and impact of the replacement strategy, and provide feedback for the design of the replacement strategy. The embodiment of the present application can realize the perspective of the cache running process, white-box the previous black-box process, increase the interpretability of the strategy, and is beneficial to debugging and design.

[0120] It should be noted that, for the method embodiments, the series of acts complement each other to achieve the purpose of this application. Accordingly, the sequence of the acts should not be construed as limiting the application. For example, the sequence of the acts could be changed; other steps being performed in between; or in parallel. Additionally, certain acts could be left out altogether. In an embodiment, one or more of the acts are performed automatically.

[0121] Apparatus embodiments

[0122] Referring to FIG. 8, a structural block diagram of a management apparatus of a cache replacement policy is shown, which can specifically include:

[0123] The obtaining module 801 is configured to obtain, from a simulator, access information of a target cache group in a case where a first replacement policy is adopted; the simulator is configured to simulate a running process of a processor system.

[0124] The preprocessing module 802 is configured to classify the access information according to cache block addresses, and sort the classified access information according to time stamps.

[0125] The first drawing module 803 is configured to draw a first access observation graph corresponding to the first replacement policy based on the sorting result; the first access observation graph is configured to reflect cache miss information and replacement block information in the target cache group when the first replacement policy is adopted.

[0126] The evaluation module 804 is configured to evaluate decision performance of the first replacement policy according to the first access observation graph.

[0127] Optionally, the access information includes related information of cache block access events; and the first drawing module includes:

[0128] The coordinate determining sub-module is configured to determine a vertical coordinate of an access point according to a cache block address corresponding to the cache block access event, and determine a horizontal coordinate of the access point according to a sorting result corresponding to the cache block access event.

[0129] The identifier determining sub-module is configured to determine an identifier of the access point according to an access type of the cache block access event.

[0130] The color determining sub-module is configured to determine a color of the identifier according to a hit condition of the cache block access event.

[0131] The first drawing sub-module is configured to draw the first access observation graph corresponding to the first replacement policy according to the vertical coordinate, the horizontal coordinate, the identifier and the color of the identifier of each access point.

[0132] Optionally, the memory access information further comprises backfill information of a cache block backfill event; and the apparatus further comprises:

[0133] a backfill determination module configured to, in a case where the target cache group has a cache backfill event, determine a backfill block address and a replacement block address according to the backfill information;

[0134] a mark adding module configured to add a replacement mark in the first memory access observation graph according to the backfill block address and the replacement block address;

[0135] wherein a horizontal coordinate of the replacement mark is the same as that of an access point corresponding to the backfill block address, and a vertical coordinate of the replacement mark is a vertical coordinate value corresponding to the replacement block address.

[0136] Optionally, the evaluation module comprises:

[0137] a first determination sub-module configured to determine first cache miss information corresponding to the first replacement strategy according to the first memory access observation graph;

[0138] a second determination sub-module configured to determine a target replacement block corresponding to each backfill block in the target cache group in a case where a target replacement strategy is adopted, according to memory trace information reflected in the first memory access observation graph;

[0139] a second drawing sub-module configured to draw a target memory access observation graph corresponding to the target replacement strategy according to the memory trace information and the target replacement block;

[0140] a third determination sub-module configured to determine target cache group miss information corresponding to the target replacement strategy according to the target memory access observation graph;

[0141] an evaluation sub-module configured to evaluate decision performance of the first replacement strategy based on the first cache miss information and the target cache group miss information.

[0142] Optionally, the obtaining module comprises:

[0143] an obtaining sub-module configured to obtain a cache group identifier to be observed, a first replacement strategy, and a number of simulation instructions;

[0144] a configuration sub-module configured to configure the simulator according to the cache group identifier, the first replacement strategy, and the number of simulation instructions, so that the simulator executes a test program according to the first replacement strategy and the number of simulation instructions, and outputs memory access information of a target cache group corresponding to the cache group identifier.

[0145] Optionally, the apparatus further comprises:

[0146] a second drawing module, configured to draw a second memory access observation graph corresponding to a second replacement strategy;

[0147] a score determination module, configured to determine performance scores of the first replacement strategy and the second replacement strategy respectively according to the first memory access observation graph and the second memory access observation graph;

[0148] a strategy updating module, configured to update the cache replacement strategy of the target cache group to the second replacement strategy in a case where the performance score of the first replacement strategy is lower than the performance score of the second replacement strategy.

[0149] In summary, the embodiment of the present application provides a cache replacement strategy management device, which can draw a memory access observation graph from the perspective of a cache block address by using the memory access information of a target cache group provided by a simulator, display all access and cache block refill events of the target cache group in a period of time, clearly display the refill and replacement timing of each cache block, more intuitively display the decision and influence of the replacement strategy, and provide feedback for the design of the replacement strategy. The embodiment of the present application can realize the perspective of the cache running process, white-box the previous black-box process, increase the explainability of the strategy, and be beneficial to debugging and design.

[0150] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the related parts refer to the part of the method embodiment.

[0151] Each embodiment in the specification is described in a progressive manner, and each embodiment mainly describes the difference from other embodiments. The same and similar parts between the embodiments can be referred to each other.

[0152] As for the processor in the above-described embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be described in detail here.

[0153] Referring to FIG. 9, it is a structural block diagram of an electronic device for cache replacement strategy management provided by an embodiment of the present application. As shown in FIG. 9, the electronic device includes a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete the communication between each other through the communication bus; the memory is used to store executable instructions, and the executable instructions make the processor execute the cache replacement strategy management method of the foregoing embodiments.

[0154] The processor can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable device, a transistor logic device, a hardware component or any combination thereof. The processor can also be a combination of computing functions, such as one or more microprocessor combinations, combinations of DSP and microprocessor, etc.

[0155] The communication bus can include a path for transmitting information between the memory and the communication interface. The communication bus can be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one line is shown in FIG. 9, but it does not mean that there is only one bus or only one type of bus.

[0156] The memory can be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0157] The embodiments of the present application also provide a non-transitory computer readable storage medium, when the instructions in the storage medium are executed by the processor of an electronic device (server or terminal), the processor can execute the management method of the cache replacement policy shown in FIG. 1.

[0158] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between each embodiment can be referred to each other.

[0159] Those skilled in the art will understand that embodiments of the present application can be provided as a method, apparatus or computer program product. Accordingly, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, etc.) embodying computer readable program code.

[0160] The embodiments of the present application are described with reference to the flowchart illustrations and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processing device or other programmable data processing terminal devices to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal devices, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams block or blocks.

[0161] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing terminal device to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions means which implement the function specified in the flowchart illustrations and / or block diagrams block or blocks.

[0162] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device to cause a series of operational steps to be performed on the computer or other programmable terminal device to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal device provide steps for implementing the functions specified in the flowchart illustrations and / or block diagrams block or blocks.

[0163] Although preferred embodiments of the present application have been described, those skilled in the art will appreciate that additional modifications and changes can be made to these embodiments without departing from the scope of the present application. Accordingly, the appended claims are intended to cover all such modifications and changes as fall within the scope of the present application.

[0164] Those skilled in the art can clearly understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present disclosure.

[0165] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0166] In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented by other manners. For example, the apparatus embodiments described above are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0167] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0168] In addition, each functional unit in each embodiment of the present disclosure can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0169] It can be understood that the embodiments described in the disclosure can be implemented in hardware, software, firmware, middleware, microcode or a combination thereof. For hardware implementation, the modules, units, sub-units can be implemented in one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), general purpose processors, controllers, micro-controllers, microprocessors, other electronic units for performing the functions described in the disclosure or a combination thereof.

[0170] For software implementation, the technologies described in the disclosure can be implemented by modules (such as processes, functions, etc.) that perform the functions described in the disclosure. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or outside the processor.

[0171] Those skilled in the art should understand that in the disclosure, the terms "first", "second", "third", "fourth", "fifth" and the like are only used to distinguish different structures, and do not limit the number, connection relationship and the like of the specific structures; in addition, the orientation or position relationship indicated by "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore the above terms cannot be understood as a limitation on the present application.

Claims

1. A method of managing a cache replacement policy, wherein, The method comprises: obtaining, from a simulator, access information of a target cache group in a case of adopting a first replacement strategy; the simulator is used for simulating a running process of a processor system; classifying the access information according to cache block addresses, and sorting the classified access information according to time stamps; drawing a first access observation graph corresponding to the first replacement strategy based on a sorting result; the first access observation graph is used for reflecting cache miss information and replacement block information in the target cache group in the case of adopting the first replacement strategy; evaluating decision performance of the first replacement strategy according to the first access observation graph.

2. The management method of cache replacement policy according to claim 1, wherein, The access information comprises related information of cache block access events; The drawing of the first access observation graph corresponding to the first replacement strategy based on the sorting result comprises: determining a vertical coordinate of an access point according to a cache block address corresponding to the cache block access event, and determining a horizontal coordinate of the access point according to a sorting result corresponding to the cache block access event; determining an identifier of the access point according to an access type of the cache block access event; determining a color of the identifier according to a hit condition of the cache block access event; drawing the first access observation graph corresponding to the first replacement strategy according to the vertical coordinate, the horizontal coordinate, the identifier and the color of the identifier of each access point.

3. The management method of cache replacement policy according to claim 2, wherein, The access information further comprises refill information of cache block refill events; the method further comprises: in a case that there is a cache refill event in the target cache group, determining a refill block address and a replacement block address according to the refill information; adding a replacement mark in the first access observation graph according to the refill block address and the replacement block address; wherein the horizontal coordinate of the replacement mark is the same as the horizontal coordinate of an access point corresponding to the refill block address, and the vertical coordinate of the replacement mark is a vertical coordinate value corresponding to the replacement block address.

4. The management method of cache replacement policy according to claim 1, wherein, The evaluation of the decision performance of the first replacement strategy according to the first access observation graph comprises: determining first cache miss information corresponding to the first replacement strategy according to the first access observation graph; determining a target replacement block corresponding to each refill block in the target cache group in the case of adopting a target replacement strategy according to access trace information reflected in the first access observation graph; drawing a target access observation graph corresponding to the target replacement strategy according to the access trace information and the target replacement block; determining target cache group miss information corresponding to the target replacement strategy according to the target access observation graph; evaluating the decision performance of the first replacement strategy based on the first cache miss information and the target cache group miss information.

5. The management method of cache replacement policy according to claim 1, wherein, The obtaining of the access information of the target cache group in the case of adopting the first replacement strategy from the simulator comprises: obtaining a cache group identifier to be observed, a first replacement strategy and a number of simulation instructions; configuring the simulator according to the cache group identifier, the first replacement strategy and the number of simulation instructions, so that the simulator executes a test program according to the first replacement strategy and the number of simulation instructions, and outputs access information of a target cache group corresponding to the cache group identifier.

6. The management method of cache replacement policy according to claim 1, wherein, The method further comprises: drawing a second access observation graph corresponding to a second replacement strategy; determine performance scores of the first replacement strategy and the second replacement strategy respectively according to the first access observation graph and the second access observation graph; in a case where the performance score of the first replacement strategy is lower than the performance score of the second replacement strategy, update the cache replacement strategy of the target cache group to the second replacement strategy.

7. The management method of cache replacement policy according to claim 1, wherein, The access information comprises at least one of the following: accessed cache block address, access type, access hit condition, access timestamp, replacement block address.

8. The management method of cache replacement policy according to claim 2 or 7, wherein, The access type comprises at least one of the following: processor core read-write, upper level cache prefetch, current level cache prefetch.

9. The management method of cache replacement policy according to claim 1, wherein, The method further comprises: based on the first access observation graph corresponding to the first replacement strategy, counting the number of misses of each type of access in the target cache group when the first replacement strategy is adopted.

10. The management method of cache replacement policy according to claim 1, wherein, The sorting result comprises an access point graph corresponding to the target cache group; and the first access observation graph corresponding to the first replacement strategy is drawn based on the sorting result, which comprises marking different events on the access point graph according to event types to obtain the first access observation graph corresponding to the target cache group. The decision performance of the first replacement strategy is evaluated according to the first access observation graph, which comprises counting the number of cache misses in the target cache group based on the first access observation graph, and evaluating the first replacement strategy.

11. An apparatus for managing a cache replacement policy, wherein, The device comprises: an acquisition module configured to acquire access information of a target cache group when a first replacement strategy is adopted from a simulator configured to simulate a running process of a processor system; a preprocessing module configured to classify the access information according to cache block addresses, and sort the classified access information according to timestamps; a first drawing module configured to draw a first access observation graph corresponding to the first replacement strategy based on a sorting result; the first access observation graph is used to reflect cache miss information and replacement block information in the target cache group when the first replacement strategy is adopted; an evaluation module configured to evaluate decision performance of the first replacement strategy according to the first access observation graph.

12. The apparatus of claim 11, wherein, The access information comprises relevant information of cache block access events; The first drawing module comprises: a coordinate determination submodule configured to determine a vertical coordinate of an access point according to a cache block address corresponding to a cache block access event, and determine a horizontal coordinate of the access point according to a sorting result corresponding to the cache block access event; an identifier determination submodule configured to determine an identifier of the access point according to an access type of the cache block access event; a color determination submodule configured to determine a color of the identifier according to a hit condition of the cache block access event; a drawing submodule configured to draw the first access observation graph corresponding to the first replacement strategy according to the vertical coordinate, the horizontal coordinate, the identifier and the color of the identifier of each access point.

13. The apparatus of claim 11, wherein, The access information further comprises refill information of a cache block refill event; and the device further comprises: a refill determination module configured to determine a refill block address and a replacement block address according to the refill information in a case where there is a cache refill event in the target cache group. a marking adding module, configured to add a replacement mark in the first memory access observation graph according to the backfill block address and the replacement block address; wherein the horizontal coordinate of the replacement mark is the same as that of the access point corresponding to the backfill block address, and the vertical coordinate of the replacement mark is the vertical coordinate value corresponding to the replacement block address.

14. The apparatus of claim 11, wherein, The evaluation module comprises: a first determining submodule, configured to determine first cache miss information corresponding to the first replacement strategy according to the first memory access observation graph; a second determining submodule, configured to determine a target replacement block corresponding to each backfill block in the target cache group in the case of adopting a target replacement strategy according to the memory access trace information reflected in the first memory access observation graph; a second drawing submodule, configured to draw a target memory access observation graph corresponding to the target replacement strategy according to the memory access trace information and the target replacement block; a third determining submodule, configured to determine target cache group miss information corresponding to the target replacement strategy according to the target memory access observation graph; an evaluation submodule, configured to evaluate the decision performance of the first replacement strategy based on the first cache miss information and the target cache group miss information.

15. The apparatus of claim 11, wherein, The obtaining module comprises: an obtaining submodule, configured to obtain a cache group identifier to be observed, a first replacement strategy and a number of simulation instructions; a configuration submodule, configured to configure the simulator according to the cache group identifier, the first replacement strategy and the number of simulation instructions, so that the simulator executes a test program according to the first replacement strategy and the number of simulation instructions, and outputs memory access information of a target cache group corresponding to the cache group identifier.

16. The apparatus of claim 11, wherein, The apparatus further comprises: a second drawing module, configured to draw a second memory access observation graph corresponding to a second replacement strategy; a score determining module, configured to determine performance scores of the first replacement strategy and the second replacement strategy according to the first memory access observation graph and the second memory access observation graph respectively; a strategy updating module, configured to update the cache replacement strategy of the target cache group to the second replacement strategy in the case that the performance score of the first replacement strategy is lower than the performance score of the second replacement strategy.

17. An electronic device, comprising: The electronic device comprises a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions make the processor execute the cache replacement strategy management method in any one of claims 1 to 10.

18. A readable storage medium, wherein, When the instructions in the readable storage medium are executed by the processor of the electronic device, the processor can execute the cache replacement strategy management method in any one of claims 1 to 10.

19. A chip, wherein, The chip comprises a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to realize the cache replacement strategy management method in any one of claims 1 to 10.

20. A synchronization control apparatus / device comprising the apparatus / device (configured to) perform the cache replacement strategy management method in any one of claims 1 to 10.

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