Substrate processing method and substrate processing apparatus

Abstract

[Problem] To suppress the occurrence of variation in the etching amount of silicon in the depth direction of a pattern. [Solution] When etching is performed by having silicon, which is exposed in the side surface of a recessed pattern that is formed on a substrate, react with a processing gas that contains a fluorine gas and an ammonia gas within a processing chamber, the temperature of the substrate is maintained at a first temperature at which the reaction between the processing gas and the silicon is not promoted before the processing gas is supplied to the inside of the processing chamber, and the temperature of the substrate is increased from the first temperature upon the supply of the processing gas to the inside of the processing chamber.

Description

Substrate processing method and substrate processing apparatus

[0001] The present disclosure relates to a substrate processing method and a substrate processing apparatus.

[0002] A layer made of silicon (Si), silicon germanium (SiGe) or boron-doped silicon (SiB) formed on a wafer as a substrate is ionized with fluorine (F ２ ) gas and ammonia (NH ３ A technique for etching using a fluorine-containing gas has been proposed (see, for example, Patent Document 1).

[0003] In this technique, F is introduced into the processing chamber containing the stage on which the wafer is placed. ２ Gas and NH ３ A processing gas containing F is supplied, and the F in the processing gas is removed without generating plasma from the processing gas. ２ The gas reacts with the Si layer to form silicon tetrafluoride (SiF ４ ), but the produced SiF ４ This allows the Si layer to be vaporized and removed.

[0004] Japanese Patent Application Laid-Open No. 2017-224673

[0005] The technique according to the present disclosure suppresses the occurrence of variations in the amount of silicon etched in the depth direction of the pattern.

[0006] One aspect of the technology disclosed herein is a substrate processing method in which silicon exposed on the side surfaces of a recessed pattern formed on a substrate is etched by reacting it with a processing gas inside a processing chamber, the processing gas including at least fluorine gas and ammonia gas, and before the processing gas is supplied into the processing chamber, the temperature of the substrate is maintained at a first temperature at which reaction between the processing gas and the silicon is not promoted, and the temperature of the substrate is raised from the first temperature in response to the supply of the processing gas into the processing chamber.

[0007] According to the technique of the present disclosure, it is possible to suppress the occurrence of variations in the amount of silicon etched in the depth direction of the pattern.

[0008] FIG. 6 is a partial cross-sectional plan view schematically illustrating an example of the configuration of a substrate processing apparatus according to an embodiment of the technology disclosed herein. FIG. 7 is a cross-sectional view schematically illustrating an example of the configuration of a process module that performs an etching process to remove silicon from a wafer. FIG. 8 is an enlarged cross-sectional view illustrating an example of the structure of a wafer that is to be etched. FIG. 9 is an enlarged cross-sectional view illustrating an example of the structure of a wafer that is to be etched. FIG. 10 is a process diagram illustrating an example of a conventional substrate processing method for etching a silicon layer. FIG. 11 is a process diagram illustrating an example of a conventional substrate processing method for etching a silicon layer. FIG. 12 is a process diagram illustrating an example of a substrate processing method according to the present embodiment for etching a silicon layer. FIG. 13 is a process diagram illustrating an example of a substrate processing method according to the present embodiment for etching a silicon layer. FIG. 14 is a graph showing an example of a temperature change of a mounting table when the substrate processing method of FIG. 5 is performed. FIG. 15 is an enlarged cross-sectional view illustrating a structure of a modified example of a wafer that is to be etched. FIG. 16 is an enlarged cross-sectional view illustrating a structure of a modified example of a wafer that is to be etched.

[0009] An embodiment of the technology according to the present disclosure will be described below with reference to the drawings. FIG. 1 is a partial cross-sectional plan view schematically illustrating an example of the configuration of a substrate processing apparatus according to an embodiment of the technology according to the present disclosure. In FIG. 1, the substrate processing apparatus 10 includes a load / unload unit 11, a transfer module (hereinafter referred to as "TM") 12, and multiple process modules (hereinafter referred to as "PMs") 13. The load / unload unit 11 stores and loads wafers W as substrates. The TM 12 transfers wafers W between the load / unload unit 11 and each PM 13. Each PM 13 performs various processes, such as etching and film formation, on wafers W loaded from the TM 12. In the substrate processing apparatus 10, the interior of the TM 12 is maintained in a vacuum atmosphere. The interior of each PM 13 (more precisely, the interior of a chamber 28, described below) is also maintained in a vacuum atmosphere when various processes are performed on wafers W.

[0010] In the substrate processing apparatus 10, wafers W stored in the loading / unloading section 11 are transferred by a transfer arm 14 built into the TM 12, and the wafers W are placed on two mounting tables 15 arranged inside the PM 13. In the substrate processing apparatus 10, after various processes are performed on each wafer W in the PM 13, the processed wafers W are transferred to the loading / unloading section 11 by the transfer arm 14.

[0011] The loading / unloading section 11 has a plurality of load ports 17, a loader module (hereinafter referred to as "LM") 18, two load lock modules (hereinafter referred to as "LLM") 19, and a cooling storage 20. Each load port 17 functions as a mounting stage for mounting a FOUP 16, which serves as a container for accommodating a plurality of wafers W. The LM 18 receives wafers W from the FOUP 16 mounted on each load port 17, and stores processed wafers W received from each PM 13 in the FOUP 16. The LLM 19 temporarily holds wafers W for transferring wafers W between the LM 18 and the TM 12. The cooling storage 20 cools wafers W that have been subjected to, for example, heat treatment.

[0012] The LM 18 is a rectangular housing whose interior is kept under atmospheric pressure, with multiple load ports 17 arranged side by side on one side of the long side of the rectangle. Furthermore, the LM 18 has a transfer arm (not shown) inside that is movable in the longitudinal direction of the rectangle. The transfer arm transfers wafers W from FOUPs 16 placed on each load port 17 to the LLM 19, or transfers wafers W from the LLM 19 to each FOUP 16.

[0013] Each LLM 19 temporarily holds the wafer W with a buffer plate 21 when transferring the wafer W between the LM 18 and the TM 12. Each LLM 19 also has a gate valve 22a for ensuring airtightness with respect to the LM 18 and a gate valve 22b for ensuring airtightness with respect to the TM 12. Furthermore, the LLM 19 has a gas introduction system and a gas exhaust system (neither of which are shown), and is configured so that the interior can be switched between an atmospheric pressure atmosphere and a vacuum atmosphere.

[0014] The TM 12 loads unprocessed wafers W from the load / unload section 11 into the PM 13 and loads processed wafers W from the PM 13 to the load / unload section 11. The TM 12 is a rectangular housing with a vacuum atmosphere inside, and includes two transfer arms 14 that hold and move two wafers W, and a rotary table 23 that rotatably supports each transfer arm 14. The TM 12 also includes a rotary stage 24 on which the rotary stage 23 is mounted, and guide rails 25 that guide the rotary stage 24 so that it can move in the longitudinal direction of the TM 12. The TM 12 is also connected to each LLM 19 and each PM 13 via a gate valve 22b and each gate valve 26 described below. In the TM 12 , the transfer arm 14 transfers two wafers W from the LLM 19 to each PM 13 , and transfers the two processed wafers W from each PM 13 to another PM 13 or the LLM 19 .

[0015] The substrate processing apparatus 10 further includes a control unit 27. The control unit 27 includes a processing unit having a CPU that controls the operation of each component of the substrate processing apparatus 10, an input device (keyboard, mouse, etc.), an output device (printer, etc.), a display device (display, etc.), and a storage device (memory). The processing unit of the control unit 27 causes each component of the substrate processing apparatus 10 to perform various operations based on, for example, a processing recipe stored in the storage device.

[0016] 2 is a cross-sectional view schematically illustrating an example of the configuration of a PM 13 that performs an etching process to remove Si from a wafer W. Although only one mounting table 15 is shown in FIG. 2, as described above, the PM 13 actually has two mounting tables 15. As shown in FIG. 2, the PM 13 includes a sealed chamber 28 (processing chamber) that accommodates the wafer W therein, a gas supply mechanism 29 that supplies a processing gas into the chamber 28, and an exhaust mechanism 30 that exhausts the interior of the chamber 28.

[0017] The chamber 28 is composed of a main body 31 and a lid 32. The main body 31 has a generally cylindrical shape with an open top, and this opening is closed by the lid 32. The joint between the main body 31 and the lid 32 is sealed with a seal member (not shown), ensuring airtightness inside the chamber 28. A gas introduction nozzle 33 is inserted into the ceiling wall of the lid 32 from above toward the inside of the chamber 28. A transfer port 34 is opened in the main body 31 to transfer the wafer W between the main body 31 and the TM 12, and the gate valve 26 opens and closes the transfer port 34.

[0018] The mounting table 15 has a generally circular shape in a plan view and is installed at the bottom of the chamber 28. A temperature regulator 35 is provided inside the mounting table 15. The temperature regulator 35 is composed of, for example, a heater or a pipe through which a temperature-controlled medium circulates, and adjusts the temperature of the mounting table 15, thereby adjusting the temperature of the wafer W placed on the mounting table 15. An electrostatic chuck (ESC) 36 made of a dielectric material is also provided inside the mounting table 15. A DC power supply 37 is connected to the electrostatic chuck 36. When the DC power supply 37 applies a DC voltage to the electrostatic chuck 36, the electrostatic chuck 36 electrostatically chucks the wafer W placed on the mounting table 15 by electrostatic force. A temperature sensor (not shown) for detecting the temperature of the wafer W is provided near the wafer W placed on the mounting table 15.

[0019] The gas supply mechanism 29 is ２ Gas supply F ２ Gas supply 38 and NH ３ NH gas supply ３ A gas supply source 39, an Ar gas supply source 40 for supplying argon (Ar) gas, and a nitrogen (N ２ ) N supply gas ２ and a gas supply source 41. ２ The gas supply 38 contains F ２ A gas supply pipe 42 is connected, and NH ３ The gas supply source 39 contains NH ３ A gas supply pipe 43 is connected to the Ar gas supply source 40, an Ar gas supply pipe 44 is connected to the Ar gas supply source 40, and an N ２ The gas supply source 41 contains N ２ The gas supply pipe 45 is connected to these F ２ Gas supply pipes 42 to N２ The gas supply pipe 45 is connected to a collecting pipe 46, which is connected to the gas introduction nozzle 33. The gas supply mechanism 29 is ２ Gas, NH ３ Gas, Ar gas and N ２ The process gas containing F ２ Gas supply pipes 42 to N ２ The gas is supplied from the gas introduction nozzle 33 to the inside of the chamber 28 via the gas supply pipe 45 and the collecting pipe 46. ２ Gas supply pipe 42, NH ３ Gas supply pipe 43, Ar gas supply pipe 44 and N ２ A flow rate controller 47 that opens and closes each pipe and controls the flow rate of each gas is provided in the gas supply pipe 45. The flow rate controller 47 is configured with, for example, an on-off valve and a mass flow controller (MFC). Note that a shower plate may be provided above the chamber 28, and the process gas may be supplied into the chamber 28 in a shower-like manner via the shower plate.

[0020] Among the gases contained in the processing gas, F ２ Gas and NH ３ As will be described later, the gas is used as an etchant in etching the silicon layer, and is Ar gas or N ２ The gas is used as a purge gas or a dilution gas. The process gas may contain hydrogen fluoride (HF) gas. HF gas is used to remove native oxide films covering the patterns and surfaces of each layer of the wafer W and for termination processing after etching of a silicon layer.

[0021] The exhaust mechanism 30 includes an exhaust pipe 49 connected to an exhaust port 48 that opens into the chamber 28, an automatic pressure control valve (APC) 50 provided on the exhaust pipe 49 for controlling the pressure inside the chamber 28, and a vacuum pump 51 for evacuating the inside of the chamber 28.

[0022] In the PM 13, various components such as the chamber 28 and the mounting table 15 are made of aluminum (Al). The Al material constituting the chamber 28 may be solid, or may be anodized on the wall surface facing the inside of the main body 31. Furthermore, it is preferable that a highly wear-resistant oxide coating (e.g., a thermally sprayed film made of alumina or yttria) be formed on the surface of the Al material constituting the mounting table 15 after the anodization.

[0023] 3A and 3B are enlarged cross-sectional views illustrating an example of the structure of a wafer W to be etched in PM13 of Fig. 2, with Fig. 3A being a view illustrating the configuration of a pattern formed on the wafer W, and Fig. 3B being an enlarged cross-sectional view of a portion of the pattern in Fig. 3A. While Fig. 3 exemplarily shows only one pattern, in reality, many patterns having similar configurations are formed on the wafer W.

[0024] As shown in FIG. 3A , the wafer W has a multilayer structure 53 in which a number of various layers are stacked on the surface of a base 52, and a concave pattern 54, e.g., a hole, is formed so as to penetrate the multilayer structure 53 in the stacking direction (thickness direction of the multilayer structure 53). The depth of the pattern 54 is at least 4 μm or more, and may be 8 μm or more. Note that this pattern 54 is formed by an etching process in another PM 13 or the like before the wafer W is loaded into the PM 13 ( FIG. 2 ), where an etching process for removing Si is performed. Furthermore, the pattern formed in the multilayer structure 53 is a hole, but it may also be a trench.

[0025] As shown in FIG. 3B, the stacked structure 53 includes a number of Si layers 55, silicon nitride (SiN) layers 56 (other layers), and silicon oxide (SiO ２ In the laminated structure 53, a SiN layer 56 and a SiO ２ The Si layer 55 is sandwiched between the SiN layers 56 on the top and bottom, and the SiO layer 57 and the SiN layer 56 are sandwiched between the SiN layers 56 on both sides. ２The silicon layer 55 may be made of either polysilicon (polycrystalline silicon) or epitaxial silicon (single-crystalline silicon).

[0026] As described above, the pattern 54 penetrates the laminated structure 53 in the lamination direction, and therefore, the Si layer 55, the SiN layer 56, and the SiO ２ In the following drawings, the Si layer 55 is shown by cross-hatching, the SiN layer 56 is shown by white, and the SiO ２ Layer 57 is shown in dark shade.

[0027] In the technique according to the present disclosure, only the Si layers 55 in the stacked structure 53 are selectively etched, and the pattern 54 is partially (at the locations where the Si layers 55 exist) expanded in the horizontal direction (left and right in the drawing). ２ The gas and the Si of the Si layer 55 undergo a chemical reaction shown in the following formula (1), resulting in SiF ４ Also, NH ３ The gas acts as a catalyst and promotes the chemical reaction shown in formula (1) below.

[0028] Si + 2F ２ + NH ３ → SiF ４ ↑ + NH ３ …(1)

[0029] Here, SiF ４ Since the boiling point of SiF under atmospheric pressure is -95.5°C, ４ is easily sublimed, and the sublimed SiF ４ is exhausted from the chamber 28 by the exhaust mechanism 30. As a result, the Si layer 55 is etched and removed.

[0030] At this time, some NH ３ Gas is F ２ The chemical reaction shown in the following formula (2) occurs with the gas, and hydrogen (H ２ ) to produce gas.

[0031] 3F ２ + 2NH ３ → 2NF ３ + 3H ２ …(2)

[0032] The generated H ２ The gas is sublimated SiF ４ and NH ３ The gas undergoes a chemical reaction represented by the following formula (3), producing ammonia fluoride silicon (AFS), a silicon-containing by-product.

[0033] SiF ４ + H ２ + F ２ + 2NH ３ → (NH ４ ) ２ SiF ４ …(3)

[0034] This AFS is also relatively easy to sublimate, and the sublimated SiF ４ Similarly, the sublimated AFS is also exhausted from the chamber 28 by the exhaust mechanism 30. Note that no plasma is used in any of the chemical reactions shown in the above formulas (1) to (3).

[0035] Among the chemical reactions represented by the above formulas (1) to (3), the chemical reaction represented by the above formula (1) is not promoted unless the wafer W reaches a relatively high temperature, for example, 80° C. If the wafer W is maintained at room temperature or a slightly higher temperature, for example, 40° C., the chemical reaction represented by the formula (1) is unlikely to occur. Therefore, in the past, in order to promote the chemical reaction represented by the above formula (1) and improve throughput, F ２ Gas and NH ３ When the process gas containing the gas is supplied into the chamber 28, the wafer W is preheated to raise the temperature of the wafer W to, for example, approximately 80° C. Hereinafter, the temperature at which the chemical reaction shown in the above formula (1) is promoted, for example, 80° C., will be referred to as the "reaction promotion temperature," and the temperature at which the chemical reaction shown in the above formula (1) is unlikely to occur, for example, 40° C., will be referred to as the "reaction stop temperature."

[0036] 4A to 4C are process diagrams illustrating an example of a conventional substrate processing method for etching the Si layer 55. In the conventional substrate processing method, the temperature of the wafer W is raised to a reaction promotion temperature, and then F ２ Gas and NH ３A process gas containing a gas is supplied. Meanwhile, in the wafer W, the depth of the pattern 54 formed in the stacked structure 53 is at least 4 μm or more, and not only is the absolute value of the depth of the pattern 54 large, but the aspect ratio is also high. Therefore, immediately after the supply of the process gas starts, the etchant (indicated by "○" in the figure) serving as the process gas has difficulty reaching the lower part of the pattern 54, and the etchant is unevenly distributed upward inside the pattern 54 ( FIG. 4A ).

[0037] At this time, the temperature of the wafer W has already risen to the reaction acceleration temperature, so the chemical reaction shown in the above formula (1) occurs, but due to the etchant unevenly distributed above, the chemical reaction shown in the above formula (1) actively progresses above the pattern 54. On the other hand, because there is almost no etchant below the pattern 54, the chemical reaction shown in the above formula (1) progresses only slightly ( FIG. 4B ).

[0038] As a result, the Si layers 55 are sufficiently etched in the upper portion of the pattern 54 but are not etched as much in the lower portion thereof, resulting in variations in the amount of etching of the Si layers 55 in the depth direction of the pattern 54 ( FIG. 4C ). Such variations in the amount of etching of the Si layers 55 can cause product defects in semiconductor devices including the stacked structure 53, and therefore it is necessary to suppress the variations in the amount of etching of the Si layers 55 in the depth direction of the pattern 54.

[0039] In contrast, in the technique according to the present disclosure, the temperature of the wafer W is raised from the reaction stop temperature to the reaction promotion temperature in response to the supply of the processing gas toward the wafer W.

[0040] 5A to 5D are process diagrams illustrating an example of the substrate processing method of the present embodiment for etching the Si layer 55. The following processes are performed by the control unit 27 of the substrate processing apparatus 10 controlling the operation of each component of the PM 13.

[0041] In the substrate processing method of this embodiment, first, a wafer W is loaded into the chamber 28 of the PM 13 and placed on the mounting table 15. Thereafter, the chamber 28 is evacuated by the exhaust mechanism 30 to maintain a vacuum atmosphere inside the chamber 28. Then, the temperature of the mounting table 15 is maintained at a reaction stop temperature (first temperature) by the temperature regulator 35 of the mounting table 15. At this time, the temperature of the wafer W is also maintained at the reaction stop temperature due to heat transfer from the mounting table 15 to the wafer W.

[0042] Next, the gas supply mechanism 29 ２ Gas, NH ３ Gas, Ar gas and N ２ A process gas containing the gas is supplied into the chamber 28. In response to the supply of the process gas into the chamber 28, the temperature of the mounting table 15 is raised from the reaction stop temperature by the temperature regulator 35 of the mounting table 15. At this time, the temperature of the wafer W is also raised from the reaction stop temperature due to heat transfer from the mounting table 15 to the wafer W.

[0043] When not much time has passed since the process gas began to be supplied into the chamber 28, the etchant (indicated by "○" in the figure) serving as the process gas has difficulty reaching the lower part of the pattern 54, as in the conventional etching of each Si layer 55. Therefore, the etchant is unevenly distributed upward inside the pattern 54 (FIG. 5A). However, at this time, heat is not sufficiently transferred from the mounting table 15 to the wafer W, so the temperature of the wafer W remains at the reaction stop temperature, and the chemical reaction represented by the above formula (1) is unlikely to occur.

[0044] Then, while the chemical reaction represented by the above formula (1) is unlikely to occur, the etchant diffuses within the pattern 54 over time, and the etchant becomes almost evenly distributed (evenly distributed) in the vertical direction of the pattern 54 (Figure 5B).

[0045] Thereafter, the temperature of the wafer W begins to rise from the reaction stop temperature due to heat transfer from the mounting table 15. At this time, the chemical reaction represented by the above formula (1) progresses not only above the pattern 54 but also below the pattern 54 due to the etchant that is present almost uniformly in the vertical direction of the pattern 54 ( FIG. 5C ).

[0046] As a result, each Si layer 55 is sufficiently etched not only above but also below in the depth direction of the pattern 54, thereby suppressing variations in the amount of etching of each Si layer 55 in the depth direction of the pattern 54 (Figure 5D).

[0047] 6 is a graph showing an example of the temperature change of the mounting table 15 when performing the substrate processing method of FIG. 5A to FIG. 5D. As shown in FIG. 6, after the wafer W is loaded into the chamber 28 of the PM 13 and placed on the mounting table 15, the temperature of the mounting table 15 is adjusted to a reaction stop temperature (e.g., 40° C.) by the temperature regulator 35.

[0048] After a predetermined time has elapsed, the gas supply mechanism 29 starts supplying the processing gas into the chamber 28, and simultaneously the temperature regulator 35 starts increasing the temperature of the mounting table 15. This predetermined time is a necessary and sufficient time for the temperature of the wafer W mounted on the mounting table 15 to reach the reaction stop temperature through heat transfer from the mounting table 15 and then to stabilize at the reaction stop temperature. This predetermined time is determined through prior confirmation experiments, etc.

[0049] While the supply of the processing gas continues, the temperature of the mounting table 15 also continues to rise, but it takes time for heat to be transferred from the mounting table 15 to the wafer W. Therefore, the temperature of the wafer W does not rise immediately after the temperature of the mounting table 15 starts to rise, but is maintained at the reaction stop temperature for a while, for example, 30 seconds after the temperature of the mounting table 15 starts to rise. As a result, the chemical reaction represented by the above formula (1) is unlikely to occur on the wafer W, and the etchant, which is the processing gas, diffuses inside the pattern 54. As a result, the etchant becomes substantially uniformly distributed in the vertical direction of the pattern 54 about 30 seconds after the temperature of the mounting table 15 starts to rise, as shown in FIG. 5B .

[0050] Then, about 30 seconds after the temperature of the mounting table 15 starts to rise, the temperature of the wafer W starts to rise due to heat transfer from the mounting table 15, and the chemical reaction represented by the above formula (1) starts to occur. At this time, since the etchant is present almost uniformly in the vertical direction of the pattern 54, each Si layer 55 starts to be etched almost uniformly.

[0051] However, if the supply of the processing gas continues even after the temperature of the wafer W starts to rise from the reaction stop temperature, the newly supplied etchant will undergo the chemical reaction represented by the above formula (1) when it reaches above the pattern 54, and will not reach below the pattern 54. Therefore, only the etching of the Si layers 55 above the pattern 54 is promoted, which may result in variations in the amount of etching of the Si layers 55 in the depth direction of the pattern 54.

[0052] Therefore, in this embodiment, the supply of the process gas is stopped when the temperature of the wafer W starts to rise. Specifically, the supply of the process gas is stopped 30 seconds after the temperature of the mounting table 15 starts to rise. As a result, when the temperature of the wafer W starts to rise from the reaction stop temperature, no new etchant is added to the interior of the pattern 54, and etching of each Si layer 55 is started only by the etchant that is approximately uniformly present in the vertical direction of the pattern 54. As a result, it is possible to suppress variations in the etching amount of each Si layer 55 in the depth direction of the pattern 54.

[0053] Even after 30 seconds have passed since the start of the temperature increase of the mounting table 15 and the supply of the processing gas has been stopped, the temperature regulator 35 continues to increase the temperature of the mounting table 15, and the temperature of the wafer W also increases toward the reaction promotion temperature (e.g., 80° C.). In other words, the supply of the processing gas is stopped while the temperature of the mounting table 15 is increasing from the reaction stop temperature.

[0054] Thereafter, 60 seconds after the start of the temperature increase of the mounting table 15, the temperature increase of the mounting table 15 by the temperature regulator 35 is stopped, but by this time the temperature of the mounting table 15 has almost reached the reaction promotion temperature, and later the temperature of the wafer W also reaches almost the reaction promotion temperature. This promotes the chemical reaction represented by the above formula (1), and etching of each Si layer 55 progresses.

[0055] Then, the temperature of the mounting table 15 is maintained at the reaction acceleration temperature for a predetermined time by the temperature regulator 35, and then the temperature regulator 35 starts to lower the temperature of the mounting table 15. The predetermined time here is a time necessary and sufficient for the etchant present inside the pattern 54 to complete etching of each Si layer 55 on the wafer W whose temperature reaches the reaction acceleration temperature following the mounting table 15. This predetermined time is also determined through a preliminary confirmation experiment or the like.

[0056] Next, when the temperature of the mounting table 15 has been sufficiently decreased, the wafer W mounted on the mounting table 15 is carried out of the chamber 28 .

[0057] In the example shown in FIG. 6, in order to improve throughput by causing the chemical reaction represented by the above formula (1) to occur as soon as possible after the supply of the processing gas is started, the temperature of the mounting table 15 is raised from the reaction stop temperature simultaneously with the start of the supply of the processing gas.

[0058] However, by raising the temperature of the mounting table 15 from the reaction stop temperature after the supply of the process gas is started, the start of the chemical reaction represented by the above formula (1) may be slightly delayed, thereby buying time for a sufficient amount of etchant to reach below the pattern 54. This ensures that the etchant is uniformly distributed in the vertical direction of the pattern 54, thereby reliably preventing variations in the amount of etching of each Si layer 55 in the depth direction of the pattern 54.

[0059] The applicant also performed a conventional substrate processing method and the substrate processing method of the present embodiment, and compared the variations in the etching amount of each Si layer 55 in the depth direction of the pattern 54. The etching amount here refers to the amount of each Si layer 55 etched horizontally from the side surface of the pattern 54.

[0060] First, as Comparative Example 1, the applicant etched each Si layer 55 of pattern 54 by a conventional substrate processing method (FIGS. 4A to 4C) and confirmed the etching amount of each Si layer 55. As a result, the etching amount of the upper Si layer 55 of pattern 54 in Comparative Example 1 was 81.7 nm, while the etching amount of the central Si layer 55 was 63.2 nm, and the etching amount of the lower Si layer 55 was 60.5 nm. That is, it was confirmed that in Comparative Example 1, the etching amount of each Si layer 55 varies in the depth direction of pattern 54.

[0061] Next, the present applicant etched each Si layer 55 of pattern 54 using the substrate processing method of this embodiment ( FIGS. 5A to 5D ) as an example, and confirmed the etching amount of each Si layer 55. As a result, the etching amount of the upper Si layer 55 of pattern 54 in the example was 49.0 nm, while the etching amount of the central Si layer 55 was 46.6 nm, and the etching amount of the lower Si layer 55 was 52.6 nm. That is, it was confirmed that the example had smaller variations in the etching amount of each Si layer 55 in the depth direction of pattern 54 than the conventional substrate processing method. Therefore, it was found that the substrate processing method of this embodiment can suppress variations in the etching amount of each Si layer 55 in the depth direction of pattern 54.

[0062] Furthermore, as Comparative Example 2, the applicant conducted the substrate processing method of this embodiment by continuing to supply processing gas until 40 seconds had elapsed since the temperature of the mounting table 15 began to rise, thereby etching each Si layer 55 of the pattern 54, and confirmed the amount of etching of each Si layer 55.

[0063] In Comparative Example 2, the supply of the process gas continues even after 30 seconds have passed since the start of heating the mounting table 15 and the temperature of the wafer W has begun to rise from the reaction stop temperature. Therefore, the etchant supplied after 30 seconds has passed reaches the pattern 54 of the wafer W whose temperature has risen from the reaction stop temperature, and when it reaches above the pattern 54, it reacts with each Si layer 55 above the pattern 54 and does not reach below. That is, in Comparative Example 2, the etching amount of the Si layer 55 above the pattern 54 becomes larger than the etching amount of the Si layer 55 below the pattern 54, and it is expected that the etching amount of each Si layer 55 in the depth direction of the pattern 54 will vary.

[0064] The results of Comparative Example 2 showed that the etching amount of the Si layer 55 above the pattern 54 was 88.6 nm, while the etching amount of the Si layer 55 at the center was 58.6 nm, and the etching amount of the Si layer 55 below the pattern 54 was 47.8 nm. That is, in Comparative Example 2, it was confirmed that, as expected, the etching amount of the Si layer 55 above the pattern 54 was greater than the etching amount of the Si layer 55 below the pattern 54. This shows that it is preferable to stop the supply of the process gas after the temperature of the wafer W starts to rise from the reaction stop temperature.

[0065] Although the preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments, and various modifications and changes are possible within the scope of the gist of the present disclosure.

[0066] For example, the laminated structure 53 of the wafer W to which the substrate processing method of this embodiment is applied includes a number of Si layers 55, SiN layers 56, and SiO ２ The layer 57 is made of SiO ２ The substrate processing method of this embodiment may not include layer 57. In this case, Si layers 55 and SiN layers 56 are alternately stacked (FIG. 7A). The substrate processing method of this embodiment may also be applied to etching a single Si layer 58 (FIG. 7B). In this case, when the substrate processing method of this embodiment is performed, a pattern 59 as a hole or trench penetrating the single Si layer 58 in the thickness direction is expanded horizontally (left and right in the figure).

[0067] Furthermore, although an electrostatic adsorption unit 36 ​​is provided inside the mounting table 15 of the PM 13 that performs the substrate processing method of this embodiment, the electrostatic adsorption unit 36 ​​does not need to be provided if heat transfer from the mounting table 15 to the wafer W is possible.

[0068] 6 , the temperature regulator 35 stops increasing the temperature of the mounting table 15 60 seconds after the start of increasing the temperature of the mounting table 15. That is, the temperature increase time of the mounting table 15 is 60 seconds. However, if the temperature regulator 35 has a high temperature control capability and can increase the temperature of the mounting table 15 from the reaction stop temperature to the reaction promotion temperature in an even shorter time, the temperature increase time of the mounting table 15 may be further shortened. However, in this case, it is necessary to stop the supply of the process gas while the temperature of the mounting table 15 is increasing from the reaction stop temperature.

[0069] This application claims priority based on Japanese Patent Application No. 2024-090002, filed on June 3, 2024, the entire contents of which are incorporated herein by reference.

[0070] W wafer 10 substrate processing apparatus 13 PM 15 mounting table 28 chamber 35 temperature regulator 53 laminated structure 54, 59 patterns 55, 58 Si layer 56 SiN layer

Claims

1. A substrate processing method in which silicon exposed on the side surfaces of a recessed pattern formed on a substrate is etched by reacting it with a processing gas inside a processing chamber, wherein the processing gas contains at least fluorine gas and ammonia gas, the temperature of the substrate is maintained at a first temperature at which reaction between the processing gas and the silicon is not promoted before the processing gas is supplied into the processing chamber, and the temperature of the substrate is raised from the first temperature in response to the supply of the processing gas into the processing chamber.

2. The substrate processing method according to claim 1, wherein the supply of the processing gas into the processing chamber is stopped during the temperature rise of the substrate from the first temperature.

3. The substrate processing method according to claim 1, wherein the substrate is placed on a mounting table provided inside the processing chamber, and the temperature of the mounting table is raised from the first temperature simultaneously with the start of supplying the processing gas into the processing chamber.

4. The substrate processing method according to claim 1, wherein the substrate is placed on a mounting table provided inside the processing chamber, and the temperature of the mounting table is increased from the first temperature after the supply of the processing gas into the processing chamber is started.

5. The substrate processing method according to claim 1, wherein the pattern has a depth of 4 μm or more.

6. The substrate processing method according to claim 5, wherein the depth of the pattern is 8 μm or more.

7. The substrate processing method according to claim 1, wherein the substrate has a layered structure in which a plurality of silicon layers are stacked, wherein other layers are interposed between each of the silicon layers in the layered structure, and the pattern is formed so as to penetrate the layered structure in the stacking direction.

8. The substrate processing method according to claim 7, wherein the other layer is made of silicon nitride.

9. The substrate processing method according to claim 1, wherein the substrate has a single silicon layer, and the pattern is formed so as to penetrate the single silicon layer in a thickness direction.

10. The substrate processing method according to claim 3 or 4, wherein the mounting table has a temperature regulator, and the temperature regulator increases the temperature of the substrate.

11. The substrate processing method according to claim 1, wherein the etching reaction between the processing gas and the silicon is carried out without generating plasma from the processing gas.

12. The substrate processing method according to claim 1, wherein the pattern is a trench or a hole.

13. A substrate processing apparatus comprising a processing chamber that accommodates a substrate therein and a temperature regulator that adjusts the temperature of the substrate, wherein a processing gas is supplied into the processing chamber, and silicon exposed on the side surfaces of a recessed pattern formed on the substrate is etched inside the processing chamber by reacting with the processing gas, wherein the processing gas contains at least fluorine gas and ammonia gas, and before the processing gas is supplied into the processing chamber, the temperature regulator maintains the temperature of the substrate at a first temperature that does not promote a reaction between the processing gas and the silicon, and the temperature regulator raises the temperature of the substrate from the first temperature in response to the supply of the processing gas into the processing chamber.

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