Silicon-nitride charge-trapping memristor and preparation method therefor

Abstract

Disclosed in the present application are a silicon-nitride charge-trapping memristor and a preparation method therefor. The memristor has three functional layers, wherein the upper functional layer and the lower functional layer are made of SiO2, and the intermediate functional layer is made of SiNX. The memristor is treated by a low-temperature annealing process, such that SiNX in the functional layers forms silicon dangling bonds, which are traps for capturing and releasing charges. The memristor realizes a change in resistance by using the mechanism of capturing and releasing charges in the SiNX traps. The memristor provided in the present application does not have the non-uniformity problem caused by the random growth of conductive filaments, and does not require a high-voltage forming process, thereby achieving a relatively high uniformity and a relatively wide application prospect. Moreover, the memristor can achieve reliable multi-level storage and pulsed synaptic characteristics. In addition, by using silicon nitride as a core resistive-switching material, the advantages of low cost, ease of availability, and enhanced compatibility with CMOS processes are achieved.

Description

A silicon nitride charge-trapping memristor and its fabrication method Technical Field

[0001] This application belongs to the field of microelectronic devices, and more specifically, relates to a silicon nitride charge-trapping memristor and its fabrication method. Background Technology

[0002] In current research, conductive wire type memristors account for the majority. Their resistive switching principle is to form or melt conductive wires in resistive switching materials. When the conductive wire forms a path, the device becomes a low-resistance state, and when the conductive wire breaks, the device becomes a high-resistance state. However, the main problems faced by this type of memristor are as follows: (1) The non-uniformity caused by the random growth of conductive wires in the device is the main obstacle to the large-scale manufacturing of memristors; (2) The device requires a high-voltage forming initialization process, which will cause the device to break down and fail, reducing the reliability of the memristor. This not only brings higher power consumption, but also increases the complexity of peripheral circuit design.

[0003] Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this application is to provide a silicon nitride charge-trapping memristor and its fabrication method, aiming to solve the problems of poor consistency caused by the randomness of conductive wire growth and the need for high-voltage forming in traditional conductive wire memristors.

[0005] To achieve the above objectives, in a first aspect, this application provides a silicon nitride charge-trapping memristor, comprising a substrate, a lower electrode, a functional layer, and an upper electrode, wherein the functional layer is configured as three layers, wherein the upper and lower layers are SiO2, and the middle layer is SiN. X ;

[0006] The memristor is processed using a low-temperature annealing process, which makes the SiN in the functional layer... X Silicon dangling bonds are formed, which act as traps for capturing and releasing charges; the memristor utilizes the charge in SiN X The trapping and releasing mechanism in the trap achieves the change in resistance. When a positive voltage is applied between the upper and lower electrodes, charge flows from the lower electrode to the upper electrode under the influence of the electric field. The charge flows through the SiN in the functional layer. X Gradually SiN X As the SiN traps are filled, the resistance of the memristor gradually decreases, reaching its minimum when the traps are full. When a negative voltage is applied between the upper and lower electrodes, the charge is gradually absorbed by the SiN. X As the charge in the trap is released, it flows to the lower electrode, and the resistance of the memristor gradually increases. When all the charge in the trap is released, the resistance of the memristor reaches its maximum.

[0007] The SiO2 is used to increase the potential barrier difference between the functional layer and the upper and lower electrodes, and the SiN X The process of trap capturing and releasing.

[0008] As further preferred, in the functional layer, the thickness of the SiN X is less than or equal to 20 nm, and the thickness of the SiO2 is less than or equal to 10 nm.

[0009] As further preferred, the material of the upper electrode and the lower electrode is Pt, Ti, W, Au, Ru, Al, Hf, Ta or TiN.

[0010] As further preferred, the memristor can obtain stable multi-value storage characteristics by applying different sizes of direct current or pulse voltage between the upper electrode and the lower electrode thereof, and can realize the pulse synapse characteristics of long-term potentiation and long-term depression by continuously applying pulse voltage between the upper electrode and the lower electrode thereof.

[0011] In a second aspect, the application provides a preparation method of the silicon nitride charge trapping type memristor as described above, comprising the following steps:

[0012] S10, preparing a substrate;

[0013] S20, depositing a lower electrode on the substrate;

[0014] S30, depositing a functional layer on the lower electrode, the functional layer being provided in three layers, the upper and lower layers being SiO2, and the middle layer being SiN X ;

[0015] S40, depositing and patterning an upper electrode on the functional layer;

[0016] S50, placing the device prepared in step S40 into an annealing furnace to perform a low-temperature annealing process, so that the SiN X in the functional layer forms silicon dangling bonds, which are traps for capturing and releasing charges.

[0017] As further preferred, in step S50, the annealing temperature in the low-temperature annealing process is controlled at 200-500°C, and the annealing time is 500-2500 seconds.

[0018] As further preferred, the functional layer is prepared by chemical vapor deposition or physical vapor deposition.

[0019] As further preferred, the upper electrode and the lower electrode are both prepared by physical vapor deposition or chemical vapor deposition.

[0020] As a further preferred option, the upper electrode is patterned on the functional layer using photolithography.

[0021] The silicon nitride charge-trapping memristor and its fabrication method provided in this application have the following advantages:

[0022] (1) The functional layer adopts SiO2 / SiN X / SiO2 three-layer structure, SiN through low temperature annealing process X The formed silicon dangling bonds trap and release charges to achieve the resistance change of the memristor. This resistance change process does not have the randomness problem of conductive filament growth, so there is no large voltage forming process, which is beneficial to reduce the power consumption of the memristor and the complexity of the peripheral circuit design, improve the reliability of the device, and has high consistency.

[0023] (2) By using silicon dangling bonds to trap and release charges to complete the resistive switching, the memristor provided in this application can have multiple conduction states by applying DC or pulse voltages of different magnitudes to the electrodes, thus achieving stable multi-resistance value retention. In addition, by continuously applying pulse voltages to the electrodes, pulse collision characteristics such as long-term enhancement and long-term suppression can be achieved, which has the potential for in-memory computing integration applications.

[0024] (3) Using SiN X As a core resistive switching material, it has the advantages of low cost, easy availability and greater compatibility with CMOS processes compared with traditional ion-migratory memristor resistive switching materials. Moreover, the preparation method provided in this application is applicable to mass production equipment and processes such as CVD and PVD, and has better prospects for large-scale mass production. Attached Figure Description

[0025] Figure 1 is a schematic diagram of the silicon nitride charge-trapping memristor provided in this application;

[0026] Figure 2 is a flowchart of the fabrication method of the silicon nitride charge-trapping memristor provided in this application;

[0027] Figure 3 is a schematic diagram of the energy band structure of a silicon nitride charge-trapping memristor provided in a specific embodiment of this application;

[0028] Figure 4 is an IV curve of the silicon nitride charge-trapping memristor provided in a specific embodiment of this application after the first to 100 consecutive DC voltage scans.

[0029] Figure 5 is a multi-resistance retention performance diagram of the silicon nitride charge-trapping memristor provided in a specific embodiment of this application;

[0030] Figure 6 shows a silicon nitride charge-trapping memristor provided in a specific embodiment of this application, under which a 10... 4 A graph showing the change in conductance of a pulse voltage. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0032] It should be understood that, in the description of this application, the term "several" means at least one, such as one, two, etc., unless otherwise expressly and specifically defined; the term "multiple" means two or more, unless otherwise expressly and specifically defined; the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order of objects; the term "and / or" includes any and all combinations of one or more of the related listed items.

[0033] Furthermore, throughout this specification, references to "an embodiment"; "an embodiment," "an example," or similar language indicate that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of this application. Therefore, the appearance of the phrase "in one embodiment;" throughout this specification, and similar language, may, but not necessarily, refer to the same embodiment.

[0034] To address the issues of poor consistency due to the randomness of conductive wire growth and the need for high-voltage forming in traditional conductive wire memristors, this application provides a silicon nitride charge-trapping memristor. Figure 1 is a schematic diagram of the structure of the silicon nitride charge-trapping memristor provided in this application. As shown in Figure 1, the memristor sequentially includes a substrate 100, a lower electrode 101, a functional layer, and an upper electrode 105.

[0035] The substrate 100 can be made of materials commonly used in the art, such as Si or SiO2, and this application does not impose any restrictions. The upper electrode 101 and the lower electrode 105 can be made of conductive materials such as Pt, Ti, W, Au, Ru, Al, Hf, Ta or TiN, and this application does not impose any restrictions.

[0036] The functional layer has a three-layer structure: the upper layer 104 and the lower layer 102 are both SiO2, and the middle layer 103 is SiN. X SiN X It is the core resistive switching material of the functional layer.

[0037] Before use, the aforementioned memristor structure needs to be treated with a low-temperature annealing process to ensure that the SiN in the functional layer is properly bonded. X Silicon dangling bonds are formed, which are traps for capturing and releasing charges.

[0038] The memristor provided in this application utilizes charge on SiN XThe trapping and releasing mechanism in the trap realizes the change of resistance, that is, when a forward voltage is applied between the upper electrode and the lower electrode (that is, a negative bias is applied to the lower electrode and the upper electrode is grounded), the charges flow from the lower electrode to the upper electrode under the action of the electric field, and the charges gradually flow through the SiN X in the functional layer are gradually trapped in the SiN X , so that the resistance of the memristor gradually decreases, and when the traps in the SiN X are filled, the resistance of the memristor decreases to the minimum; when a negative voltage is applied between the upper electrode and the lower electrode (that is, a positive bias is applied to the lower electrode and the upper electrode is grounded), the charges are gradually released from the traps in the SiN X , flow to the upper electrode, and the resistance of the memristor gradually increases, and when all the charges in the traps are released, the resistance of the memristor increases to the maximum.

[0039] In the functional layer, the addition of two layers of SiO2 is used to increase the potential barrier difference between the functional layer and the upper and lower electrodes, and to buffer the process of charge being trapped and released by the SiN X traps, and this buffering effect can make the memristor perform analog resistance change and thus realize the pulse synapse function.

[0040] Specifically, the memristor provided in the present application can change the number of charges trapped by the functional layer by adjusting the voltage applied to the electrodes, and different numbers result in different resistances of the device. Applying different sizes or different numbers of direct current or pulse voltages to the electrodes can realize stable multi-resistance value retention; by continuously applying pulse voltages to the electrodes, the long-term potentiation and long-term depression and other pulse synapse characteristics can be realized, which is an important biological learning mechanism.

[0041] Preferably, the thickness of the SiN X layer in the functional layer provided in the present application is less than or equal to 20 nm, and the thickness of the SiO2 layer is less than or equal to 10 nm. Within this thickness range, the functional layer can achieve the effect of subsequent stable charge trapping, and beyond this range, it exhibits insulating properties and cannot be resistance changed.

[0042] In addition, the present application also provides a preparation method for the above-mentioned silicon nitride charge trapping type memristor, as shown in FIG. 2, which comprises steps S10-S50, and the details are as follows:

[0043] S10, preparing a substrate.

[0044] In step S10, the substrate can adopt Si / SiO2 material.

[0045] S20, depositing a lower electrode on the substrate.

[0046] In step S20, the lower electrode can be prepared by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0047] S30, depositing a functional layer on the lower electrode, the functional layer being provided as three layers, wherein the upper and lower layers are SiO2, and the middle layer is SiN X .

[0048] In step S30, the functional layer can be prepared by chemical vapor deposition or physical vapor deposition.

[0049] S40, depositing and patterning an upper electrode on the functional layer.

[0050] In step S40, the upper electrode can be prepared by physical vapor deposition or chemical vapor deposition. The upper electrode can be patterned on the functional layer by photolithography.

[0051] S50, placing the device prepared in step S40 into an annealing furnace to perform a low-temperature annealing process, so that the SiN X in the functional layer forms silicon dangling bonds, which are traps for capturing and releasing charges.

[0052] Specifically, the device prepared in step S40 can be annealed in an N2 atmosphere or a vacuum environment in the annealing furnace, which is not limited in the present application. To better enable the SiN X in the functional layer to form silicon dangling bonds, the annealing temperature in the low-temperature annealing process can be controlled at 200-500°C, and the annealing time is 500-2500 seconds.

[0053] The silicon nitride charge trapping type memristor and the preparation method thereof provided by the present application have the following effects:

[0054] (1) The functional layer adopts a SiO2 / SiN X / SiO2 three-layer structure, and the SiN X formed by the low-temperature annealing process captures and releases charges to realize the resistance change of the memristor. The resistance change process has no randomness problem of conductive wire growth, so there is no large voltage forming process, which is beneficial to reduce the power consumption of the memristor and the complexity of the peripheral circuit design, improve the reliability of the device, and has high consistency.

[0055] (2) The resistance change is completed by the silicon dangling bonds capturing and releasing charges, which can make the memristor provided by the present application have multiple conductance states by applying direct current or pulse voltage of different sizes to the electrode, realize stable multi-resistance value retention, and realize long-term potentiation and long-term depression and other pulse synapse characteristics by continuously applying pulse voltage to the electrode, which has potential for storage-computing fusion application.

[0056] (3) The SiN XCompared with traditional ion migration type resistive random access memory resistive change materials, the core resistive change material has the advantages of low cost, easy acquisition and more compatibility with CMOS process; and the preparation method provided in the application is suitable for CVD, PVD and other mass production equipment and processes, and has better large-scale mass production prospect.

[0057] The silicon nitride charge trapping type memristor and the preparation method thereof provided in the application will be described in detail below in combination with specific embodiments.

[0058] The silicon nitride charge trapping type memristor and the preparation method thereof provided in the embodiment have a device structure of Ti / SiO2 / SiN X / SiO2 / Pt, wherein the lower electrode is Pt, the functional layer is a three-layer superimposed structure of SiO2 / SiN X / SiO2, and the upper electrode is Ti, and the specific preparation process flow is as follows (without describing the substrate cleaning process):

[0059] (1) The Si / SiO2 substrate is prepared in advance;

[0060] (2) Direct current magnetron sputtering is performed on the substrate, the power is 100 W, the argon flow rate is 60 sccm, the gas pressure is maintained at 0.5 Pa, the target material is metal Ti, and a 5-10 nm thick Ti electrode is deposited as an adhesion layer; then the power is set to 40-60 W, the gas pressure is 0.5 Pa, the argon flow rate is 60 sccm, the target material is Pt, and a 50-120 nm thick Pt electrode is deposited;

[0061] (3) A 2 nm SiO2 film is deposited on the Pt electrode using a plasma enhanced chemical vapor deposition method (PECVD), the deposition temperature is 300 DEG C, the reaction pressure is 850 mTorr, and the reaction gas source is 5% SiH4 / N2, N2 and N2O; then a 6 nm SiN X film is deposited on the SiO2 film using the PECVD method, the deposition temperature is 300 DEG C, the reaction pressure is 1000 mTorr, and the reaction gas source is 5% SiH4 / N2, NH3 and N2; then a 3 nm SiO2 film is deposited on the SiN X film using the PECVD method, the deposition temperature is 300 DEG C, the reaction pressure is 850 mTorr, and the reaction gas source is 5% SiH4 / N2, N2 and N2O.

[0062] (4) The upper electrode pattern is photoetched on the functional layer using ultraviolet photoetching technology, and is prepared through six processes of uniform coating, pre-baking, pre-exposure, post-baking, post-exposure and development;

[0063] (5) DC magnetron sputtering, power 100 W, argon flow rate 60 sccm, pressure maintained at 0.5 Pa, target material metal Ti, depositing a Ti electrode with a thickness of 50-120 nm, the upper electrode is a square block with a size of 50 μm x 50 μm, 100 μm x 100 μm, 200 μm x 200 μm, 300 μm x 300 μm;

[0064] (6) soaking the sample prepared in step (5) in acetone for 15-30 minutes, then cleaning with anhydrous ethanol and deionized water, and blowing dry with nitrogen;

[0065] (7) placing the device prepared in step (6) into an annealing furnace, annealing under a nitrogen atmosphere, setting the temperature to 350°C, and maintaining for 1200 seconds.

[0066] After the above steps are completed, a Ti / 3 nm SiO2 / 6 nm SiN X / 2 nm SiO2 / Pt memristor is prepared. When a negative bias voltage is applied to the Pt lower electrode and the upper electrode is grounded, charges pass through the SiO2 layer from the Pt electrode into the SiN X under the action of an electric field, and are then captured by traps in the SiN X , at which time the memristor gradually converts to a low resistance state; when a positive bias voltage is applied to the Pt lower electrode and the upper electrode is grounded, charges are released from the traps under the action of an electric field, and flow from the SiN X to the Pt electrode through the SiO2 layer, at which time the memristor gradually converts to a high resistance state.

[0067] Fig. 3 is a band diagram of a Ti / SiO2 / SiN X / SiO2 / Pt memristor provided by the embodiment, the potential barrier difference between the Ti and Pt electrodes and the SiN X is 2.5 eV and 3.8 eV, respectively, and the potential barrier difference between the Ti and Pt electrodes and the SiO2 is 3.35 eV and 4.65 eV, respectively, and the addition of the two layers of SiO2 increases the potential barrier difference between the functional layer and the upper and lower electrodes, hindering the process of charge capture and release by the SiNx traps, and this buffering effect causes the resistance of the device to gradually change.

[0068] Fig. 4 is a I-V curve diagram of a Ti / SiO2 / SiN X / SiO2 / Pt memristor provided by the embodiment under the first to 100th continuous direct current voltage scan, and the voltage scan range is controlled to be between -2 and 3 V, it can be seen that the memristor has no Forming process, and the operating voltage is low, and according to statistics, the coefficient of variation of the SET voltage is 4.8%, and the coefficient of variation of the RESET voltage is 2.1%, and the low coefficient of variation proves that the consistency of the memristor is high.

[0069] Fig. 5 is a plot of the multi-value retention performance of a Ti / SiO2 / SiN X / SiO2 / Pt memristor at a high temperature of 85°C, which can stably retain 12 resistance states, which is of great significance to improve the storage capacity of the memristor.

[0070] Fig. 6 is a plot of the conductance value change of a Ti / SiO2 / SiN X / SiO2 / Pt memristor subjected to 10 4 pulse voltages, and the continuous long-term potentiation and depression characteristics have little change compared with the initial, which exhibits a very stable and reliable synaptic function, indicating that the memristor has the potential for storage-computing integrated application.

[0071] Those skilled in the art will readily understand that the above description is only preferred embodiments of the present application, and is not intended to limit the present application, and any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A silicon nitride charge-trapped memristor, characterized in that, The functional layer is arranged in three layers, wherein the upper and lower layers are SiO2, and the middle layer is SiN X ; The memristor is processed using a low-temperature annealing process, which makes the SiN in the functional layer... X Silicon dangling bonds are formed, which act as traps for capturing and releasing charges; the memristor utilizes the charge in SiN X The trapping and releasing mechanism in the trap achieves the change in resistance. When a positive voltage is applied between the upper and lower electrodes, charge flows from the lower electrode to the upper electrode under the influence of the electric field. The charge flows through the SiN in the functional layer. X Gradually SiN X As the SiN is trapped in the traps, the resistance of the memristor gradually decreases, reaching its minimum value when the traps are filled. When a negative voltage is applied between the upper and lower electrodes, the charge is gradually absorbed by the SiN. X As the charge in the trap is released, it flows to the lower electrode, and the resistance of the memristor gradually increases. When all the charge in the trap is released, the resistance of the memristor reaches its maximum. The SiO2 is used to increase the potential barrier difference between the functional layer and the upper and lower electrodes, and the buffer charge is captured by SiN X The process of trap capture and release.

2. The silicon nitride charge-trapped memristor of claim 1, wherein, In the functional layer, the thickness of the SiN X is less than or equal to 20 nm and the thickness of the SiO2is less than or equal to 10 nm.

3. The silicon nitride charge-trapped memristor of claim 1 or 2, wherein, The upper electrode and the material of the upper electrode are made of Pt, Ti, W, Au, Ru, Al, Hf, Ta or TiN.

4. The silicon nitride charge-trapped memristor of claim 1 or 2, wherein, The memristor can obtain stable multi-value storage characteristics by applying different sizes of direct current or pulse voltage between the upper electrode and the lower electrode thereof, and can realize long-term potentiation and long-term depression pulse synapse characteristics by continuously applying pulse voltage between the upper electrode and the lower electrode thereof.

5. A method of fabricating a silicon nitride charge-trapped memristor as claimed in claim 1, wherein, The method comprises the following steps: S10, preparing a substrate; S20, depositing a lower electrode on the substrate; S30, depositing a functional layer on the lower electrode, the functional layer being arranged in three layers, wherein the upper and lower layers are SiO2and the middle layer is SiN X ; S40, depositing and patterning an upper electrode on the functional layer; S50, the device prepared in step S40 is put into an annealing furnace for low-temperature annealing process, so that the SiN in the functional layer is converted into SiOx X silicon dangling bonds, which are traps for capturing and releasing charges.

6. The method for fabricating a silicon nitride charge-trapping memristor as described in claim 5, characterized in that, In step S50, the annealing temperature in the low-temperature annealing process is controlled at 200-500 DEG C, and the annealing time is 500-2500 seconds.

7. The method for fabricating a silicon nitride charge-trapping memristor as described in claim 5, characterized in that, The functional layer is prepared by chemical vapor deposition or physical vapor deposition.

8. The method for fabricating a silicon nitride charge-trapping memristor as described in claim 5, characterized in that, The upper electrode and the lower electrode are both prepared by physical vapor deposition or chemical vapor deposition.

9. The method for fabricating a silicon nitride charge-trapping memristor as described in claim 5, characterized in that, The upper electrode is patterned on the functional layer by using a photolithography technology.

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