Memory device

Abstract

The present disclosure provides a memory device, comprising: a sensing unit, a memory cell electrically connected to a first input terminal of the sensing unit, and a reference cell electrically connected to a second input terminal of the sensing unit, wherein the reference cell comprises a reference resistor, and a temperature coefficient of a resistive material of the reference resistor is less than -1000 ppm / °C. According to the present disclosure, a resistance value of the reference cell decreases as a resistance value of the memory cell decreases, which serves the function of adjusting a voltage and current of a read operation, so as to maintain a read window of the memory device within an appropriate range, thereby preventing the problem of a limited read window due to the resistance value of the memory cell decreasing as the temperature increases, achieving an optimal read window, solving the problem in the prior art where the reference resistance of the memory device affects the read window, and further improving the read accuracy of stored information.

Description

A memory device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The present disclosure claims priority to the Chinese patent application No. 202410755680.1, filed on June 12, 2024, with the title of “A memory device”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of memory, in particular, to a memory device. BACKGROUND

[0004] Magnetic random access memory has the advantages of fast read and write and low power consumption, and is a new type of memory with great potential. By flipping the magnetic free layer of the storage unit of the magnetic random access memory through a magnetic field or a spin-polarized current, the storage unit can present a high resistance state or a low resistance state, thereby recording the storage information (1 or 0).

[0005] In order to read the storage information of the above-mentioned storage unit, it is necessary to detect the magnetization direction of the free layer in the storage unit or the resistance value of the storage unit, and by adjusting the reference resistance, the state of the circuit can be controlled, so that the corresponding storage information is transmitted to the output end, thereby realizing the read operation of the storage information. Therefore, selecting a suitable reference resistance has a great influence on reading the storage information of the storage unit. However, the reference resistance in the prior art has at least one of the following problems:

[0006] 1) greatly affected by process, voltage and temperature, affecting the read window;

[0007] 2) has a certain bit error rate (BER) by itself, and when reading data, there will be a certain error rate, and this bit error rate is usually affected by read disturbance and data loss, thereby causing read errors to occur;

[0008] 3) large area, not suitable for large capacity storage.

[0009] DISCLOSURE

[0010] The main purpose of the present disclosure is to provide a memory device to at least solve the problem of the reference resistance of the memory device in the prior art affecting the read window.

[0011] In order to achieve the above-mentioned purpose, according to one aspect of the present disclosure, a memory device is provided, comprising: a sensing unit, a storage unit electrically connected to a first input end of the sensing unit, and a reference unit electrically connected to a second input end of the sensing unit; wherein the reference unit comprises a reference resistance, and the temperature coefficient of the resistance material of the reference resistance is less than -1000 ppm / ℃.

[0012] In some embodiments, the memory cell comprises a first electrode layer, a reference layer, a barrier layer and a free layer arranged in sequence, the reference resistance is arranged apart from the first electrode layer on a side of the reference layer away from the free layer, and the electrode material of the first electrode layer is the same as the resistance material, and the first input end is electrically connected with the first electrode layer.

[0013] In some embodiments, the memory device further comprises: a first metal wiring layer on a side of the first electrode layer away from the free layer; a first conductive channel between the first electrode layer and the first metal wiring layer, the first input end being electrically connected with the memory cell through the first metal wiring layer and the first conductive channel; and a second conductive channel between the first metal wiring layer and the reference resistance, the first input end being electrically connected with the reference resistance through the first metal wiring layer and the second conductive channel.

[0014] In some embodiments, the memory cell comprises a reference layer, a barrier layer, a free layer and a second electrode layer arranged in sequence, the reference resistance is arranged apart from the second electrode layer on a side of the free layer away from the reference layer, and the electrode material of the second electrode layer is the same as the resistance material, and the first input end is electrically connected with the reference layer.

[0015] In some embodiments, the memory cell comprises a reference layer, a barrier layer and a free layer arranged in sequence, and the memory device further comprises: a second metal wiring layer on a side of the reference layer away from the free layer and electrically connected with the reference layer; or a second metal wiring layer on a side of the free layer away from the reference layer and electrically connected with the free layer; and the reference resistance is arranged in contact with the second metal wiring layer.

[0016] In some embodiments, the reference resistance comprises a first resistance and at least one second resistance, and the reference cell further comprises: a decoder having a plurality of output ends; and a plurality of switching devices corresponding to the plurality of output ends one by one, each of the switching devices having a control end, a first end and a second end, each of the control ends being electrically connected with one of the output ends, the first end being electrically connected with the first input end, and the second end being electrically connected with the first resistance through the at least one second resistance.

[0017] In some embodiments, the second resistance has a resistance value of 50-300 ohm.

[0018] In some embodiments, the reference resistance is a metal film resistance, and the metal film resistance comprises a plurality of different metal films.

[0019] In some embodiments, the material of the reference resistance comprises any one or more of the following: tantalum nitride, chromium-nickel alloy, nickel-chromium-silicon alloy, zinc-manganese alloy, cobalt-manganese alloy, semiconductor material having metal-insulator transition property, and topological insulator material.

[0020] In some embodiments, the square resistance of the reference resistance is 10-200 ohm / SQ.

[0021] The technical solution of the present disclosure provides a memory device, which comprises a sensing unit, a storage unit electrically connected to a first input end of the sensing unit, and a reference unit electrically connected to a second input end of the sensing unit. The reference unit comprises a reference resistance, and the material of the reference resistance has a negative temperature coefficient of resistance less than -1000 ppm / ℃. When reading the storage information of the storage unit, the resistance value of the reference unit decreases with the increase of temperature, which narrows the read window of the memory device and can only be read within a specific voltage or current range, thereby causing the storage state of the memory device to be unable to be accurately read or increasing the error rate of reading. On this basis, the present disclosure provides a reference unit, which comprises a reference resistance with a negative temperature coefficient of resistance, and the negative temperature coefficient is less than -1000 ppm / ℃. That is, the resistance value of the reference unit also decreases with the increase of temperature. Therefore, during the reading of the storage information of the memory device, the resistance value of the reference unit decreases with the decrease of the resistance value of the storage unit, which can adjust the voltage and current of the read operation, so that the read window of the memory device can be kept within a suitable range, thereby avoiding the problem that the resistance value of the storage unit decreases with the increase of temperature and the read window is limited, optimizing the read window, solving the problem that the reference resistance of the memory device affects the read window in the prior art, and further improving the reading accuracy of the storage information. BRIEF DESCRIPTION OF DRAWINGS

[0022] The accompanying drawings, which form a part of the present disclosure, are used to provide a further understanding of the present disclosure, and the illustrative embodiments of the present disclosure and their description serve the purpose of explaining the present disclosure. In the drawings:

[0023] FIG. 1 shows a structural schematic diagram of a memory device according to an embodiment of the present disclosure;

[0024] FIG. 2 shows a structural schematic diagram of a reference resistance prepared in the same layer as the second electrode layer in a memory device according to an embodiment of the present disclosure;

[0025] FIG. 3 shows a structural schematic diagram of an additional reference resistance in a memory device according to an embodiment of the present disclosure;

[0026] FIG. 4 shows a partial structural schematic diagram of a read circuit with a memory device according to an embodiment of the present disclosure;

[0027] FIG. 5 shows a structural schematic diagram of a reference resistance comprising a plurality of metal thin films in the memory device shown in FIG. 1.

[0028] The above figures include the following reference signs: 100, sensing unit; 200, storage unit; 300, reference unit; 10, reference resistor; 20, first metal wiring layer; 30, second conductive channel; 40, third metal wiring layer; 50, fourth conductive channel; 60, second metal wiring layer; 70, first resistor; 80, second resistor; 90, switching device; 101, first metal thin film; 102, second metal thin film. DETAILED DESCRIPTION

[0029] It should be noted that the embodiments and features of the embodiments in the present disclosure can be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0030] In order to enable those skilled in the art to better understand the present disclosure scheme, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below in combination with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present disclosure.

[0031] It should be noted that the terms "first", "second" and the like in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] As mentioned in the background, in order to read the storage information of the storage unit of the storage device, it is necessary to realize it by detecting the magnetization direction of the free layer in the storage unit or the resistance value of the storage unit, and by adjusting the reference resistance, the state of the circuit can be controlled, so that the corresponding storage information is transmitted to the output end, thereby realizing the read operation of the storage information, therefore, selecting a suitable reference resistance has a great influence on reading the storage information of the storage unit. However, the reference resistance in the prior art has at least one of the following problems: 1) greatly affected by process, voltage, temperature (PVT), affecting the read window; 2) due to itself having a certain bit error rate (BER), there will be a certain error rate when reading data, and this bit error rate is usually affected by read disturbance and data loss, thereby causing read errors to occur; 3) large area, not suitable for large capacity storage. In order to at least solve the problem of the reference resistance of the storage device in the prior art affecting the read window, the present disclosure proposes a new storage device.

[0033] In some optional embodiments, the storage device proposed by the present disclosure, as shown in FIG. 1, includes a sensing unit 100, a storage unit 200 electrically connected to the first input end of the above-mentioned sensing unit 100, and a reference unit 300 electrically connected to the second input end of the above-mentioned sensing unit 100; wherein the above-mentioned reference unit 300 includes a reference resistance 10, and the temperature coefficient of the resistance material of the above-mentioned reference resistance 10 is less than -1000ppm / ℃.

[0034] Optionally, the above-mentioned sensing unit 100 of the present disclosure can be a current sensitive amplifier, which has a first input end and a second input end, wherein the first input end can be electrically connected to the storage unit 200 of the above-mentioned storage device, and the second input end can be electrically connected to the reference unit 300 of the above-mentioned storage device. And in the case that the above-mentioned reference unit of the present disclosure includes a reference resistance, the above-mentioned second input end can be electrically connected to one end of the above-mentioned reference resistance 10.

[0035] In the above embodiment, when the memory device reads the storage information of the storage unit 200, the resistance value of the storage unit 200 decreases with the increase of the temperature, so that the read window of the memory device is narrowed and can only be performed within a specific voltage or current range, and thus the storage state of the memory device cannot be accurately read or the error rate of reading is increased. On this basis, the memory device in the present disclosure provides a reference unit 300, which includes a reference resistance 10 of a resistance material with a negative temperature coefficient, and the negative temperature coefficient is less than -1000 ppm / ℃, that is, the resistance value of the reference unit 300 also decreases with the increase of the temperature. Therefore, in the process of reading the storage information of the memory device, the resistance value of the reference unit 300 decreases with the decrease of the resistance value of the storage unit 200, which can adjust the voltage and current of the read operation, so that the read window of the memory device can be kept within a suitable range, thereby avoiding the problem that the resistance value of the storage unit 200 decreases with the increase of the temperature and the read window is limited, optimizing the read window, solving the problem that the reference resistance 10 of the memory device in the prior art affects the read window, and further improving the reading accuracy of the storage information.

[0036] In some optional embodiments, the storage unit 200 can be a magnetic tunnel junction, which can include a free layer, a barrier layer and a reference layer arranged in sequence. Moreover, the reference layer of the magnetic tunnel junction away from the free layer can be electrically connected to the first input end of the sensing unit 100 (current sensitive amplifier). In other optional embodiments, the storage unit 200 can include the magnetic tunnel junction and a control transistor (not shown in the figure) connected in series with the magnetic tunnel junction. Moreover, in the case that the storage unit 200 includes the control transistor, the control transistor can be connected in series with the side of the free layer of the magnetic tunnel junction away from the reference layer. In addition, it should be noted that the temperature coefficient of the magnetic tunnel junction is negative, that is, the resistance value of the magnetic tunnel junction decreases with the increase of the temperature, so that the resistance value of the storage unit 200 decreases with the increase of the temperature.

[0037] In some optional embodiments, the storage unit 200 includes a first electrode layer, a reference layer, a barrier layer and a free layer arranged in sequence, the reference resistance 10 is arranged on the side of the reference layer away from the free layer and spaced apart from the first electrode layer, and the electrode material of the first electrode layer is the same as the resistance material, and the first input end is electrically connected to the first electrode layer.

[0038] That is, in this embodiment, the storage unit 200 includes, in addition to the magnetic tunnel junction composed of the free layer, the barrier layer and the reference layer stacked in sequence, a first electrode layer located on the side of the reference layer of the magnetic tunnel junction away from the free layer, which can be considered as a top electrode of the magnetic tunnel junction. Thus, the case that the storage unit 200 in the memory device is electrically connected with the first input end of the sensing unit 100 can be that the magnetic tunnel junction of the memory device is electrically connected with the first input end of the sensing unit 100 through the first electrode layer.

[0039] It should be noted that the first electrode layer of the memory device and the reference resistance 10 in the present disclosure can be different conductive parts of the same conductive layer, and thus the electrode material of the first electrode layer of the magnetic tunnel junction and the resistance material of the reference resistance 10 can be the same. Corresponding to the preparation process of the memory device, the conductive layer can be first formed on the side of the reference layer of the magnetic tunnel junction away from the free layer, and then the conductive layer can be divided into a plurality of different conductive parts, and the plurality of different conductive parts can include the first electrode layer and the reference resistance 10. Thus, it can be known that the reference resistance 10 in the memory device provided by the present embodiment does not need to be formed by adding an additional preparation process step, but is compatible with the preparation process of the storage unit 200 in the memory device, and thus the memory device in the present embodiment has a simpler structure compared with the memory device in the prior art.

[0040] Further, as shown in FIG. 1, in order to electrically connect the storage unit 200 with the first input end of the sensing unit 100 and to electrically connect the reference unit 300 with the second input end of the sensing unit 100, in some optional embodiments, the memory device further includes: a first metal wiring layer 20 located on the side of the first electrode layer away from the free layer (or the first metal wiring layer 20 can be located on the side of the reference resistance 10); a first conductive channel located between the first electrode layer and the first metal wiring layer 20, the first input end being electrically connected with the storage unit through the first metal wiring layer 20 and the first conductive channel; and a second conductive channel 30 located between the first metal wiring layer 20 and the reference resistance 10, the second input end being electrically connected with the reference resistance 10 through the first metal wiring layer 20 and the second conductive channel 30. It should be noted that the sheet resistance of the first electrode layer is much larger than the resistance of the wiring of the first conductive channel, the second conductive channel 30 and the first metal wiring layer 20. It should be noted that the reference resistance 10 in the structure shown in FIG. 1 is prepared in the same layer as the first electrode layer of the storage unit 200.

[0041] In some alternative embodiments, the storage unit includes a reference layer, a barrier layer, a free layer and a second electrode layer which are sequentially stacked, the reference resistance is disposed apart from the second electrode layer on a side of the free layer away from the reference layer, and the electrode material of the second electrode layer is the same as the resistance material, and the first input end is electrically connected with the reference layer.

[0042] That is, in this embodiment, the storage unit includes a second electrode layer on a side of the free layer of the magnetic tunnel junction away from the reference layer in addition to the magnetic tunnel junction composed of the free layer, the barrier layer and the reference layer which are sequentially stacked, and the second electrode layer can be considered as a bottom electrode of the magnetic tunnel junction. Thus, the case that the storage unit in the memory device is electrically connected with the first input end of the sensing unit can be that the first input end of the sensing unit is electrically connected with the reference layer of the magnetic tunnel junction.

[0043] Similarly, the reference resistance in the memory device provided by the above embodiment does not need to increase additional manufacturing process steps and is also compatible with the manufacturing process of the storage unit. That is, the second electrode layer and the reference resistance can be different conductive parts of the same conductive layer, and thus the electrode material of the second electrode layer of the magnetic tunnel junction can be the same as the resistance material of the reference resistance. Corresponding to the manufacturing process of the memory device, the conductive layer can be formed first, and then the conductive layer can be divided into a plurality of different conductive parts, and the plurality of different conductive parts can include the second electrode layer and the reference resistance. Further, the magnetic tunnel junction can be sequentially formed on a side of the second electrode layer, wherein the magnetic tunnel junction includes the sequentially stacked free layer, barrier layer and reference layer, and the second electrode layer is in contact with the free layer of the magnetic tunnel junction. As above, the memory device in this embodiment has a simpler structure compared with the memory device in the prior art.

[0044] Similarly, in order to electrically connect the storage unit with the first input end of the sensing unit and to electrically connect the reference unit with the second input end of the sensing unit, in some alternative embodiments, as shown in FIG. 2, the memory device further includes a third metal wiring layer 40 on a side of the second electrode layer away from the free layer, a third conductive channel between the second electrode layer and the third metal wiring layer 40, the first input end is electrically connected with the magnetic tunnel junction through the third metal wiring layer 40 and the third conductive channel, and a fourth conductive channel 50 between the third metal wiring layer 40 and the reference resistance 10, the second input end is electrically connected with the reference resistance 10 through the third metal wiring layer 40 and the fourth conductive channel 50.

[0045] It is also easily conceivable that, in some alternative embodiments, the storage unit can include both the first electrode layer and the second electrode layer. On this basis, the reference resistance can be formed synchronously in the process of forming the first electrode layer or in the process of forming the second electrode layer, so as to achieve the effects of "realizing that the voltage and current of the read operation can be adjusted so that the read window of the memory device can be kept within a proper range, and avoiding the problem that the resistance value of the storage unit decreases with the increase of temperature, resulting in the limitation of the read window", and the effect of "also making the preparation process of the reference resistance compatible with the preparation process of the storage unit, and simplifying the structure of the memory device".

[0046] In some alternative embodiments, the storage unit includes a reference layer, a barrier layer and a free layer which are sequentially stacked, and the memory device further includes: a second metal wiring layer located on the side of the reference layer away from the free layer and electrically connected with the reference layer; or as shown in FIG. 3, the second metal wiring layer 60 is located on the side of the free layer away from the reference layer and electrically connected with the free layer; and the reference resistance 10 is in contact with the second metal wiring layer 60.

[0047] Optionally, in the case where the reference resistance 10 is in direct contact with the second metal wiring layer 60 located on the side of the reference layer away from the free layer, the reference layer of the storage unit of the memory device can be electrically connected with the second metal wiring layer 60 through a fifth conductive channel. Further, the first input end of the sensing unit can be electrically connected with the storage unit through the second metal wiring layer 60 and the fifth conductive channel, and the second input end of the sensing unit can be electrically connected with the reference resistance 10 of the reference unit through the second metal wiring layer 60.

[0048] Optionally, as shown in FIG. 3, in the case where the reference resistance 10 is in direct contact with the second metal wiring layer 60 located on the side of the free layer away from the reference layer, the free layer of the storage unit of the memory device can be electrically connected with the second metal wiring layer 60 through a sixth conductive channel. Further, the first input end of the sensing unit can be electrically connected with the storage unit through the second metal wiring layer 60 and the sixth conductive channel, and the second input end of the sensing unit can be electrically connected with the reference resistance 10 of the reference unit through the second metal wiring layer 60.

[0049] In summary, in the embodiment, the preparation process of the reference resistance can be independent of the preparation process of the memory cell. Further, in the case that the memory device comprises a second metal wiring layer, by setting the reference resistance in the embodiment in direct contact with the second metal wiring layer, the reference resistance can be electrically connected with the second input end of the sensing cell. It can be further understood that, since the preparation process of the reference resistance is independent of the preparation process of the memory cell, the reference resistance in contact with the second metal wiring layer can be a conductive component in any semiconductor layer, which can include but is not limited to a conductive layer in which the first electrode layer of the memory cell is located and a conductive layer in which the second electrode layer of the memory cell is located, so that the setting position of the reference resistance in the embodiment is relatively flexible.

[0050] In the read circuit of the memory device, in order to more accurately adjust the resistance value of the reference cell of the memory device, as shown in FIG. 4, in some optional embodiments, the reference resistance comprises a first resistance 70 and at least one second resistance 80, and the reference cell further comprises: a decoder having a plurality of output ends; a plurality of switching devices 90 corresponding to the plurality of output ends one by one, and each of the switching devices 90 has a control end, a first end and a second end, each of the control ends is electrically connected to one of the output ends, the first end is electrically connected to the first input end, and the second end is electrically connected to the first resistance 70 through at least one second resistance 80.

[0051] In the above embodiment, the decoder is used to control the opening or closing of the switching device 90. Wherein, when the decoder controls one of the switching devices 90 to be opened, and the second end of the switching device 90 is electrically connected to one first resistance 70 through one second resistance 80, the resistance value of the reference resistance in the reference cell of the memory device is the sum of the resistance of the one second resistance 80 and the one first resistance 70; when the decoder controls one of the switching devices 90 to be opened, and the second end of the switching device 90 is electrically connected to one first resistance 70 through N second resistances 80 (2≤N), the resistance value of the reference resistance in the reference cell of the memory device is the sum of the resistance of the N second resistances 80 and the one first resistance 70. It is again stated that the first resistance 70 and the second resistance 80 can be formed in the same process step, so that the first resistance 70 and the second resistance 80 are of the same resistance material. Alternatively, the second resistance 80 with a resistance value of 50-300 ohm can be formed by layout design, so that when the resistance value of the reference resistance in the reference cell is accurately adjusted, a resistance range of 50-300 ohm can be formed.

[0052] In some optional embodiments, in order to make the resistivity of the reference resistance controllable and stable, the reference resistance can be a metal film resistance, and in order to regulate the sheet resistance of the metal film resistance and the temperature coefficient of the resistance material, the metal film resistance can include multiple layers of different metal films. It is explained that the difference of the multiple layers of metal films can be embodied as the difference of materials, or the difference of doping elements. For example, as shown in FIG. 5, FIG. 5 shows the corresponding structure when the reference resistance 10 is set as multiple layers of metal films based on the structure shown in FIG. 1. The multiple layers of metal films can include a first metal film 101 and a second metal film 102 arranged in layers.

[0053] Optionally, the sheet resistance of the reference resistance can be 10-200 ohm / SQ. By changing the resistance value of the reference resistance, the read window of the stored data can be adjusted to be in the best state, the data read error rate can be reduced, and the read operation is facilitated.

[0054] For example, the material of the first metal film 101 can be a negative temperature coefficient material, and the material of the second metal film 102 can be a conductive material; or the material of the first metal film 101 can be a conductive material, and the material of the second metal film 102 can be a negative temperature coefficient material, so that the resistance material of the reference resistance is a composite material including a negative temperature coefficient and a conductive material, to accurately regulate the resistance coefficient of the reference resistance and match the read operation of the bit of the memory cell array in the memory device. The negative temperature coefficient material can include but is not limited to any one or more of tantalum nitride, chromium-nickel alloy, nickel-chromium-silicon alloy, zinc-manganese alloy, cobalt-manganese alloy, semiconductor material with metal-insulator transition property, topological insulator material, and conductive material doped with other elements. Further, the semiconductor material with metal-insulator transition property can include but is not limited to any one or more of ruthenium dioxide, vanadium-tungsten oxide, and titanium-vanadium oxide; the topological insulator material can include but is not limited to bismuth antimony (BiSb), bismuth selenide (Bi2Se3), bismuth telluride (Bi2Te3), and antimony telluride (Sb2Te3), etc. For example, the doping element can include but is not limited to silicon element, and the conductive material can include but is not limited to tantalum, tantalum nitride, chromium-nickel alloy, nickel-chromium-silicon alloy, titanium nitride, rubidium, tungsten, etc.

[0055] Optionally, the reference resistance mentioned in the present disclosure can be composed of a bending line with a certain total length L, and L / W=(R p +R ap ) / 2R s , where R p is the resistance value when the free layer and the reference layer of the magnetic tunnel junction are in the parallel state, and R apR is a resistance value of the magnetic tunnel junction when the free layer and the reference layer are in an anti-parallel state s R is a sheet resistance of the reference resistance. In addition, it can be understood that the resistance value of the reference resistance is equal to half of the sum of the high resistance state resistance and the low resistance state resistance of the magnetic tunnel junction in the storage unit.

[0056] From the above description, it can be seen that the above-mentioned embodiments of the present disclosure achieve the following technical effects:

[0057] A memory device in the present disclosure includes a sensing unit, a storage unit electrically connected to a first input end of the sensing unit, and a reference unit electrically connected to a second input end of the sensing unit. The reference unit includes a reference resistance, and the material of the reference resistance has a negative temperature coefficient less than -1000 ppm / ℃. When reading the storage information of the storage unit, the resistance value of the storage unit decreases with the increase of temperature, which narrows the read window of the memory device and can only be performed within a specific voltage or current range, thereby causing the storage state of the memory device to be unable to be accurately read or increasing the error rate of reading. On this basis, the present disclosure provides a reference unit including a reference resistance with a negative temperature coefficient, and the negative temperature coefficient is less than -1000 ppm / ℃. That is, the resistance value of the reference unit also decreases with the increase of temperature. Therefore, during the process of reading the storage information of the memory device, the resistance value of the reference unit decreases with the decrease of the resistance value of the storage unit, which can adjust the voltage and current of the read operation, so that the read window of the memory device can be kept within a suitable range, thereby avoiding the problem that the resistance value of the storage unit decreases with the increase of temperature, which limits the read window, optimizing the read window, solving the problem that the reference resistance of the memory device in the prior art affects the read window, and further improving the reading accuracy of the storage information.

[0058] The above only describes the preferred embodiments of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A memory device, comprising: The sensing unit, a storage unit electrically connected to a first input end of the sensing unit, and a reference unit electrically connected to a second input end of the sensing unit; wherein The reference unit comprises a reference resistance, and a temperature coefficient of a resistance material of the reference resistance is less than -1000 ppm / ℃.

2. The memory device of claim 1, wherein, The storage unit comprises a first electrode layer, a reference layer, a barrier layer, and a free layer arranged in sequence, the reference resistance is arranged on a side of the reference layer away from the free layer and spaced from the first electrode layer, and an electrode material of the first electrode layer is the same as the resistance material, and the first input end is electrically connected to the first electrode layer.

3. The memory device of claim 2, wherein, The storage device further comprises: A first metal wiring layer located on a side of the first electrode layer away from the free layer; A first conductive channel located between the first electrode layer and the first metal wiring layer, and the first input end is electrically connected to the storage unit through the first metal wiring layer and the first conductive channel; A second conductive channel located between the first metal wiring layer and the reference resistance, and the first input end is electrically connected to the reference resistance through the first metal wiring layer and the second conductive channel.

4. The memory device of claim 1, wherein, The storage unit comprises a reference layer, a barrier layer, a free layer, and a second electrode layer arranged in sequence, the reference resistance is arranged on a side of the free layer away from the reference layer and spaced from the second electrode layer, and an electrode material of the second electrode layer is the same as the resistance material, and the first input end is electrically connected to the reference layer.

5. The memory device of claim 1, wherein, The storage unit comprises a reference layer, a barrier layer, and a free layer arranged in sequence, and the storage device further comprises: A second metal wiring layer located on a side of the reference layer away from the free layer and electrically connected to the reference layer, or located on a side of the free layer away from the reference layer and electrically connected to the free layer; The reference resistance is arranged in contact with the second metal wiring layer.

6. The memory device of any one of claims 1-5, wherein, The reference resistance comprises a first resistance and at least one second resistance, and the reference unit further comprises: A decoder having a plurality of output ends; A plurality of switching devices corresponding to the plurality of output ends one by one, and each of the switching devices has a control end, a first end, and a second end, each of the control ends is electrically connected to one of the output ends, the first end is electrically connected to the first input end, and the second end is electrically connected to the first resistance through at least one of the second resistances.

7. The memory device of claim 6, wherein, The second resistance has a resistance value of 50-300 ohm.

8. The memory device of any one of claims 1-5, wherein, The reference resistance is a metal film resistance, and the metal film resistance comprises a plurality of different metal films.

9. The memory device of any one of claims 1-5, wherein, The material of the reference resistance comprises any one or more of a tantalum nitride, a chromium-nickel alloy, a nickel-chromium-silicon alloy, a zinc-manganese alloy, a cobalt-manganese alloy, a semiconductor material having a metal-insulator transition property, and a topological insulator material.

10. The memory device of any one of claims 1-5, wherein, The sheet resistance of the reference resistance is 10-200 ohm / SQ.

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