Graphene field effect transistors and methods for their production

Abstract

The present invention broadly relates to the fabrication and processing of graphene electronic devices and in particular graphene field effect transistors (gFETs).

Description

Graphene Field Effect Transistors and Methods for their Production FIELD

[0001] The present invention broadly relates to the fabrication and processing of graphene electronic devices and in particular graphene field effect transistors (gFETs). BACKGROUND

[0002] Field effect transistors (FET) are the basis of modern electronics. Since the discovery and isolation of graphene, its electronic properties have made it a desired material to integrate into silicon FET architecture. So-called gFETs (or graphene field effect transistors) have been fabricated and researched since graphene was isolated in 2004.

[0003] Graphene is a highly promising material for use in electronic devices, specifically graphene field effect transistors (gFETs). Since graphene is essentially a 1 atom thick surface layer, its electronic properties are incredibly sensitive to the surrounding media above and below it. As such, graphene, when integrated into an electronic device, can detect changes in that media through changes in the electronic state of the graphene. Due to this, it is promising for analogue applications, such as gas and biological molecule sensors, and digital applications at certain low dimensional sizes. Graphene and related devices, including transistors, electronically integrating graphene, are yet to go beyond lab-scale applications, which is in-part due to a lack of process integration into traditional silicon (Si) wafer production lines. The main issues with graphene processing and integration with Si are: transferring graphene from growth substrates, protecting the graphene during fabrication, and degradation of electrical performance of graphene caused by the processing of polymer resists used in lithography.

[0004] Graphene is not typically grown on SiO2substrates. This is an issue in the fabrication of graphene-based semiconductor devices as many electronic devices integrated into silicon technology (i.e. integrated circuits and sensors) require a thin layer of SiO2 to act as an insulating layer. This layer is imperative in activating the field-effect which is responsible for allowing materials to function as transistors. Since direct growth of graphene on silicon substrates is not easily realisable, graphene is usually synthesised and then transferred to theSiO2surface. This includes graphene layers removed from graphite, graphene synthesised via chemical vapour deposition (CVD) and chemically synthesised and separated graphene dispersed in solution. Of these, exfoliated graphene from graphite typically produces the best quality of graphene, however, the methods are not industrially scalable and are mostly confined to research applications. Both CVD and chemically synthesised graphene are more suitable to fabrication scale-up. CVD generally involves growth on a metallic catalyst (either copper or nickel) and transfer to the Si wafer. Many transfer processes are in use, which either leave chemical residues or defects (sometimes both) negatively effecting the electronic properties. Despite this, CVD is widely regarded as a process advantageous in graphene fabrication as it results in the repeatability and reproducibility of homogenous mono-to-few layer graphene batch-to-batch.

[0005] To effectively integrate CVD grown graphene into gFETs, a method needs to be developed to prevent undesirable defects and delamination of graphene while retaining electronic properties. These two properties are inextricably linked, as broken sp2bonds in graphene (either through vacancy or sp3bond defects) will result in decreased electronic transport through the graphene surface. Therefore, a decrease in defects can be directly measured electronically as an improvement in carrier mobility (i.e., lower sheet resistance).

[0006] There exist some strategies to reduce defects and delamination, including patterning with metals (specifically Ti and Au) and cleaning graphene (using vacuum heating and laser and electron beams). While metallic protection is effective in protection during processing, post process packaging including plasma and laser dicing require further photoresist-based lithography, which cannot be protected against using these processes post fabrication. Simultaneously, the energy intensive based cleaning methods tend to induce more undesirable defects while removing residue.

[0007] For full integration of gFETs into silicon technology, fabrication of gFETs must be compatible with cleanroom environments. This means developing lithography methods compatible with photo or electron polymer resists, and using pristine graphene with in-plane crystallinity on Si (i.e. CVD). Further developing gFETs into sensing platforms (particularly biosensors utilising liquid gating) requires electrode passivation and isolation to reducecrosstalk. This introduces another layer of complexity (and lithography) beyond just fabricating graphene electrodes. Therefore, even if sacrificial metal layers are used to protect graphene during fabrication, the issue of reliably removing polymer resist and residue will also need to be solved.

[0008] Graphene is a semimetal whose conduction and valence bands meet at the Dirac points, which are six locations in momentum space, the vertices of its hexagonal Brillouin zone, divided into two non-equivalent sets of three points. Electrons traversing through a graphene lattice effectively lose their mass, producing quasi-particles that are described by a 2D analogue of the Dirac equation.

[0009] Accordingly, even if one were to develop processes for minimising delamination and undesirable defects, the continued and extended use of a gFET invariably leads to changes in the electronic properties (probed via a liquid gate) including a shift of the Dirac point to higher voltages. One reason is likely due to surface contaminants p-doping the graphene.

[0010] Based on the totality of the aforementioned hurdles, gFET fabrication on a large scale remains difficult. There is a need for a process which increases the yield, and improved extended-lifetime efficiency of graphene devices.

[0011] The present invention seeks to overcome the above current shortcomings in the art. SUMMARY OF THE INVENTION

[0012] The present invention is a process for the fabrication of a gFET which has been developed to function with a liquid ionic top-gate gold electrode and a back gate at room temperature.

[0013] The present invention is directed to the fabrication of a liquid gated gFET with a backgate as, for instance, depicted in Diagram 1 below. Source and drain electrodes ("S-D electrode") are usually encapsulated to prevent liquid shorting. Gate electrode and graphene are unencapsulated so that they can be in contact with a liquid droplet. The liquid droplet typically then acts as the dielectric. The backgate is usually isolated with a solid high-kdielectric material (such as AlOx or HfOx) which is a thin layer, for instance AlOx is ~50 nm to ~90 nm and HfOx is more typically ~20 nm to ~40 nm. As used herein, k or κ refers to the dielectric constant of a material.Diagram 1 – an embodiment of a liquid gated gFET in accordance with the present invention.

[0014] This is to be contrasted to the gFET assemblies disclosed in Figure 1 of Szunerts et al (reproduced below, see Analytical and Bioanalytical Chemistry, 2023, June 3: pages 1- 14): (a) Schematic illustration of back-gated, top-gated, liquid gated, and co-planar configurations.

[0015] While performing liquid gated measurements of analytes on graphene field effect transistors (gFETs), the present inventors identified that the Dirac point shifted to larger positive values. Without wishing to be bound by any particular theory, the inventors postulate that this is likely because of greater p-doing of the graphene due to accumulated contaminants on the graphene surface. Furthermore, this is thought to be compounded by inherent changes to graphene structure; doping from functionalisation molecules (linkers, blockers, etc.); and charge accumulation between the graphene and SiO2substrate.

[0016] This is an issue when the Dirac point shifts to voltages higher than ~1.6 V, it will not be resolvable during liquid gating. This is due to electrolysis of the gold electrodes beginning at voltages higher than this, damaging the device beyond repair. Therefore, the present invention provides, in certain aspects, methods to prevent or reduce this shift, by keeping the Dirac point shift between -1 V and 1 V.

[0017] In certain embodiments of the present inventions, the inventors have successfully overcome this problem with the introduction of a second gate (i.e. a backgate) positioned (or isolated) between two solid dielectric layers (see Diagram 1) which can modify the electronic properties of the FET independent of the liquid analyte and can compensate for these changes by “shifting” the transfer curve.

[0018] In relation to the gate electrode exposed to the ionic fluid or liquid droplet (as shown in Diagram 1), gold is found to be useful in this application because it is: 1) conductive, 2) chemically inert and 3) has a relatively higher potential for electrolysis, providing more range to scan for the Dirac point.

[0019] Because the gold electrode in the present system is in contact with an ionic fluid, it can electrolyse if too much voltage is applied in normal function. The contaminants discussed herein are materials which dope (mostly P but some can N-dope) the graphene causing shifts in the Dirac point. If there is excessive doping, the point can move beyond ±1.6 V and thus cannot be ascertained from measurement.

[0020] It would be appreciated that “excessive doping” would best be quantified by how much of the trans conductance arms around the Dirac point can be kept in the -1 V to 1 V range. The Dirac point is the minimum in a curve, with each side of the curve having information regarding the carrier concentration of holes and electrons. The slope of this curve can therefore be useful, so it may be thought of as how much of the slope can be seen until the current vs gate voltage returns to a “constant” value.

[0021] The inventors have identified contaminating residues which can form on graphene, and in particular residues from resist lithography processes, for instance, PMMA (polymethyl methacrylate), AZ (e.g. AZTM1500, 6600 or 1512HS); MA-N resists (e.g. MA- N 2400 series), or other resists etc. Additional contaminants may also include adventitious carbon from the atmosphere, and small aromatic molecules forming small islands on the multi-layer graphene.

[0022] Furthermore, phosphates and acetate buffers which are used in analytes could leave these kinds of residues on the electrode surface. This may also be expected during surface contact with other ionic salts. In essence potentially any molecule which is not the analyte can also effect the electronic property of graphene, via doping or fields.

[0023] The inventors herein teach that one can shift the Dirac point by over ±50 mV with an up to ± 15 V applied to the backgate (as shown in Figures 1 to 5). That is, the invention resides, in part, in being able to use the back gate to compensate for an, until now, often unavoidable result of liquid gating, i.e., fouling. The inventors postulate gFET biosensor devices which include both a backgate and the electrodes required to liquid gate, which in addition to biosensing, is also seen in ion-sensitive field-effect transistor (ISFET) gating.

[0024] Traditionally the gates are deposited on the SiO2 layer, these gates then being covered with a thin high-K dielectric layer (AlOx or HfOx in most occurrences, for instance, AlOx is ~50 nm to ~90 nm and HfOx is more typically ~20 nm to ~40 nm), then the layers seen in the above figure on the SiO2 would be deposited on top of this dielectric layer. In the present invention, the top gate is different, as it is based on using a liquid in the place of the top gate oxide (see Diagram 1 for instance). A gFET made on Si with a SiO2oxide isolation layer, can be backgated by electronically contacting the Si under the SiO2 layer. Based on the experience of the present inventors, with a device which was fabricated primarily to function with a liquid gate, this has been quite difficult but found to be possible using gold to improve the contact to the Si.

[0025] The solid dielectric layer (as shown in Diagram 1) is typically SiO2. As used herein, the term "high-K dielectric" refers to materials which are more insulative compared SiO2. They are typically used as a thinner gate oxide as one needs less material to create the capacitance required for gating. The material used could be HfO2or AlOx, but it is typically simpler to fabricate a solid dielectric SiO2layer by thermal oxidation of the Si wafer. In theory, there is no reason the "solid dielectric" as shown in Diagram 1 could not also be a high-K dielectric, but standard Si fabrication focuses on using SiO2 when integrating complementary metal-oxide-semiconductor (CMOS) based circuits.

[0026] In the present invention, and as depicted in Diagram 1, the backgate is Au and is sandwiched / isolated between a solid dielectric layer (typically SiO2) and a thinner high-K dielectric layer (e.g. AlOx and HfO2).

[0027] Another issue is that backgating is usually done directly on enclosed graphene or graphene in a vacuum, as backgating on graphene in atmosphere leads to a Dirac point around 25- 50 V due to doping. Of course, submerging the graphene in liquid can also help in reducing this voltage, hence the much lower value Dirac point (i.e. below 1 V) with liquid gating.

[0028] Currently, most gFETs utilise either a backgate, a top gate (in which a dielectric layer is deposited on the graphene, followed by a gold or metallic contact) or a liquid gate (in which a liquid contacts the graphene to a separate gold or other metallic contact). Top and backgates are typically used in gas sensing, while top gating is used in condensed matter applications. Liquid gates are typically used in biological or liquid sensors as a way of providing closer contact between the analyte and sensor, while using the lower conductivity of a liquid to decrease the complexity of devices. However, liquid gates tend to foul the surface and not all changes in electronic properties are due to the analyte specifically. In this case, a combination of back and liquid gating is used to track changes in the liquid gate transport properties, opening a new possible vector of control on a biosensor built using a gFET. BRIEF DESCRIPTION OF THE FIGURES

[0029] Figure 1 shows the source drain current while the liquid gate is swept across voltages from 0 V to 1 V. Each curve is taken while a different voltage is applied to the backgate, showing how much the liquid gated Dirac point shifts with a backgating voltage. The voltage does not just change the Dirac voltage but also the concentration of carriers as seen by the "arms" of the curve on each side of the Dirac point.

[0030] Figure 2 shows the same measurements for a gFET on a different chip, showing that this is not just seen on one device. a) In this case the device was run from 0 V to 14 V. b) It was then run from -15 V to 15 V. c) shows the shift of the 0 V applied to the backgate, inthis case which indicates that there may be more shift not observed and that the backgate could be struggling with leakage.

[0031] Figure 3. The a) Dirac point / voltage, b) the gate current at the Dirac point, c) the hole transconductance and d) the electron transconductance of the liquid gate at each backgate voltage applied. This is summarised data from the chip seen in Figure 1.

[0032] Figure 4. The a) Dirac point / voltage, b) the gate current at the Dirac point, c) the hole transconductance and d) the electron transconductance of the liquid gate at each backgate voltage applied. This is summarised data from the chip seen in Figure 2. This data is from the data set in Figure 2a.

[0033] Figure 5. The a) Dirac point / voltage, b) the gate current at the Dirac point, c) the hole transconductance and d) the electron transconductance of the liquid gate at each backgate voltage applied. This is summarised data from the chip seen in Figure 2. This data is from the data set in Figure 2b.

[0034] Figure 6 shows the layout of an Archer designed gFET which incorporates ionic or liquid gates and gold backgates separated by a high-k dielectric. The red layer is the first layer, being the gold electrode for backgate biasing. A high-K dielectric is deposited on top, followed by graphene. The graphene pattern in this case is the purple layer keeping graphene only where the devices are. The blue layer on top is the electrode and ionic gate / liquid gate layer. An encapsulating layer is deposited on top of this, and the final via layer (the dark blue layer that can be seen by the smaller squares on the bond pads, graphene and liquid gates) is outlined which will remove the high-K dielectric from regions which need electrically or liquid contact.

[0035] In one aspect, the invention provides a gFET device or component thereof which minimises or prevents the Dirac point shift over time, said gFET device or component characterised by at least one drain, source, liquid ionic gate electrode and backgate electrode, wherein said backgate electrode is isolated between two layers of independently selected solid dielectric materials wherein when in use an effective voltage is applied to said backgatein order to ensure that the Dirac point shift of the device or component remains between - 1.6 V and 1.6 V, and preferably between -1 V and 1 V.

[0036] In an embodiment and with reference to the above aspect the backgate electrode is an Au layer.

[0037] In an embodiment and with reference to the above aspect the backgate electrode is an Au layer, and is isolated between two layers of independently selected solid dielectric materials selected from SiO2 and AlOx or HfOx.

[0038] In an embodiment and with reference to the above aspect the backgate electrode is an Au layer, and is isolated between of a layer of a solid dielectric material and a layer of a solid high K-dielectric material.

[0039] In an embodiment and with reference to the above aspect the backgate electrode is an Au layer, and is isolated between of a layer of a solid dielectric material which is SiO2, and a layer of a solid high K-dielectric material selected from AlOx or HfOx.

[0040] In another aspect, the invention provides a method of fabricating a gFET device or component thereof which minimises or prevents the Dirac point shift overtime, said gFET device or component characterised by at least one drain, source, liquid ionic gate electrode and backgate electrode, said method comprising the step of at least one graphene deposition step, at least one lithography step, and at least one O2 plasma etching step, and further applying an effective voltage to said backgate when in use in order to ensure that the Dirac point shift of the device or component remains between -1.6V and 1.6V, and preferably between -1 V and 1 V.

[0041] In some embodiments, the effective voltage is applied for the duration of the measurement. In certain other embodiments the effective applied voltage is in the range of - 15 V to 15 V, for instance in the -14 V to 14 V range, the -13 V to 13 V range, the -12 V to 12 V range, or the -11 V to 11 V range. The person would understand that the voltage neededwill depend on how much voltage is required to shift the Dirac point measurement in the liquid gate.

[0042] It will be appreciated by those skilled in the art that the present invention aims to prevent the Dirac point from shifting more than 1 V and more specifically more than 1.6 V (in both positive and negative directions), i.e. the invention serves to keep the Dirac point between -1.6 V and 1.6 V, and ideally between -1 V and 1 V.

[0043] In a further aspect, the invention provides a method of fabricating a gFET device or component thereof which maintains the Dirac point of the liquid gate between the range of about -1 V to 1 V, said gFET device or component characterised by at least one drain, source, top gate and backgate electrodes, said method comprising the step of at least one graphene deposition step, at least one lithography step, and at least one O2 plasma etching step, and wherein after each one of the aforementioned steps the graphene layer is cleaned with a methylbenzene, followed by a ketone, and then followed by an alcohol, and further applying an effective voltage to said backgate when in use in order to maintain the Dirac point of the liquid gate between about -1 V to 1 V.

[0044] The present invention also provides a method of fabricating a gFET device or component thereof which minimises or prevents the Dirac point of the liquid gate from shifting out of the -1 V and 1 V range, said gFET device or component characterised by at least one drain, source, top gate and backgate electrodes, said method comprising the steps of at least one deposition step, at least one lithography step, and at least one O2 plasma etching step, and wherein after each one of the aforementioned steps the graphene layer is cleaned with a methylbenzene, followed by a ketone, and then followed by an alcohol, and wherein the method further comprises at least one polymer resist coating layer which is developed using a methyl isobutyl ketone (MiBK): isopropanol (IPA) mixture in a ratio of about 3:1, and further applying an effective voltage to said backgate when in use in order to minimise or prevent the Dirac point of the liquid gate device or component from shifting outside the range of -1 V and 1 V.

[0045] In one aspect, the invention provides a method of fabricating a graphene field effect transistor (gFET) comprising a graphene layer deposited on SiO2 / Si substrate and wherein said gFET is characterised with at least one drain, at least one source, at least one top-gate electrode and at least one backgate electrode, said method comprising the steps of: i) providing a Si wafer substrate; ii) depositing a solid dielectric layer on the wafer substrate; iii) depositing at least one backgate electrode on said solid dielectric layer; iv) depositing another solid dielectric layer on the at least one backgate electrode; v) depositing a CVD (chemical vapour deposition) grown graphene layer to the surface of said solid dielectric layer by polymer deposition transfer; vi) cleaning the graphene deposited later with a methylbenzene; vii) cleaning the layer after step vi) with a ketone; viii) cleaning the layer after step vii) with an alcohol; ix) depositing a polymer resist on the layer after step viii); x) defining areas where graphene will remain on wafer substrate using e-beam lithography; xi) removing unneeded graphene using O2plasma etching; xii) cleaning off any remaining polymer resist using a methylbenzene; xiii) cleaning the remaining graphene layer with a ketone; xiv) cleaning the graphene layer after step xiii) with an alcohol; xv) depositing an adhesive layer comprising Ti or Cr unto the graphene surface layer after step xiv); xvi) depositing a metal electrode material layer unto the adhesive layer after step xv); and xvii) stripping the metal layer of step xvi) to form the gFET, which comprises at least one each of a drain, source, top-gate and backgate electrodes, and further applying an effective voltage to said at least one backgate when in use in order to minimise or prevent the Dirac point of the liquid gate device or component from shifting outside the range of -1 V and 1 V.

[0046] The backgate will come into the process as outlined above in step (iii). In certain embodiments, a layer outlining the back positions and bond pads are lithographically definedand then metabolised. Following the lift-off, a high-K dielectric is deposited. This may be then patterned in a way to open vias to the metal bond pads underneath via reactive ion etching or wet etching. From then, graphene is transferred and the process continues as described in the process.

[0047] Thus another step is contemplated to isolate the backgate from the graphene and electrodes (see Diagram 1) which is the deposition of a solid dielectric layer, usually a high- k dielectric material (from instance, HfO2, Al2O3) or other ceramic materials, such as zirconium dioxide, hafnium silicate, zirconium silicate, tantalum pentoxide and lanthanum oxide, but preferably HfO2. The reason for using a high-k dielectric in this solid dielectric layer is that high-k dielectrics offer greater capacitance for gating (i.e. can apply less power for a similar effect) and are better at preventing leakage current to backgates than SiO2 alone. SiO2 has the main advantage that it can be grown directly off a silicon wafer, but with the present invention case, the inventors have proposed to deposit a dielectric on top. In this case the inventors postulate the use of a high-k dielectric due to relative ease of deposition, that it can offer better dielectric properties, is thin, and that not as much material (cost) is needed in fabrication (i.e. minimises extra CapEx costs).

[0048] Another distinguishing feature of the gFET device is that one may fabricate a structure with multiple parallel graphene strips (parallelised circuit, taken in combination with a biocompatible encapsulation layer). Most current gFETs use a continuous graphene sheet between the source and drain. In current transfer and fabrication processes, large areas of the graphene are prone to becoming damaged. The aforementioned process aims to reduce the effect of damage on the device by reducing the total graphene footprint necessary. Simultaneously, by using multiple graphene strips in parallel, it aims to produce a device which has multiple layers of redundancy if some strips are damaged or become inoperable.

[0049] The present invention relates to processes for the fabrication of a gFET which is developed to function with a liquid ionic gate electrode at room temperature. The inventors have focused, for the gFET, in measuring the drain-source current as a function of sweeping the liquid gate voltage (see Figures 1 and 2). This means that the inventors have measured the source drain voltage as a function of the voltage applied to the liquid gate (usuallybetween -1.6 V and 1.6 V but ideally between -1 V and 1 V). The backgate comes into this by performing this sweep with a different constant voltage applied to the backgate. So performing a sweep of the liquid gate between –1.6 V and 1.6V while the backgate has a constant voltage of 5 V applied is one example. While the current experimentation discussed below in the experimental section involved the use of the mock analyte, sodium acetate, the skilled person would understand that the present device would be appropriate for sensing and quantifying other analytes or mixtures thereof. The methods and devices may be used to sense biological molecules in a pH buffered sample, for instance, measuring salts present in a composition, or measuring pH of the composition, but one of the main concepts for the present technology would be to build a biosensor.

[0050] The gFET developed by a process of the present invention may be a foundational underlying technology of a new biosensor. The liquid-gated transistor design of the gFET disclosed herein would allow the biosensor to detect biomolecules in liquid samples without biofouling. The biosensor in certain embodiments of the present invention could function as part of a larger biochip. The design allows the gFET to function in liquid environments, requiring certain components being isolated from the liquid, while others need to be exposed. The technology also enables the building of the gFET device into a chip that can be packaged into a more compact readout device. As disclosed herein, and in certain embodiments the inventors have fabricated a gFET with unique in-house processing methodology and parameters, verifying its electronic operation using liquid gating. The gFET is specially fabricated to prevent the liquid shorting the circuit, while, simultaneously attaining electronic signals using the liquid as a part of the device.

[0051] In certain embodiments, the present invention provides methods of gFET fabrication suitable in an ISO 5 cleanroom environment and includes three cleaning processing steps. A layer of solid dielectric (SiO2) on an Si backgate (as shown in Diagram 1 – and where the backgate is isolated from the silicon wafer by another layer of solid dielectric) is covered with a complete mono-to-few layer graphene film (produced from CVD) was used for fabrication. First, the graphene on the dielectric layer is rinsed with a methylbenzene (in one case xylene), second rinsed with a ketone (in one case acetone), and finally rinsed in an alcohol (in one case isopropyl alcohol (IPA)). Additionally, the methylbenzene is used inthe removal of the polymer resist (e.g. PMMA) following deposition of gold or etch of graphene (e.g. lithography), followed by the cleaning with ketone and alcohol. The present inventors have found that first cleaning with a methylbenzene such as xylene, is beneficial in preventing graphene delamination during resist removal post lithography. This is primarily attributed to the removal of defects related to amorphous carbon deposit during CVD.

[0052] The commercial process uses photoresist to pattern. In this case each layer of lithography is patterned through the creation of a new mask. It also uses masks to pattern the photoresist. The layering is the same, first involving patterning and then removal of graphene, then patterning once more and deposition of a metal layer for electrodes. Finally, there is the deposit of an encapsulation layer of high-k dielectric Al2O3, which is then patterned and removed from the graphene, gates and bond pads.

[0053] In certain embodiments, the invention contemplates the use of the methods to construct multiple graphene pieces to create 16 or more parallel source drains. Most gFETs feature a single graphene sheet between the source and drain. The reason for the smaller strips is to reduce any effect of graphene damage from the processing and transfer. Tears in a large single sheet of graphene in series with a source-drain will ruin the gFET. In the case of the parallel graphene, there is less graphene on the surface and more redundancy (that is, if some of the graphene strips are damaged, the current can still move through the remaining undamaged sheets). The current methods allow for very small (on the nanoscale) graphene channels of arbitrary aspect ratio or shape.

[0054] According to another aspect, the invention provides a method of fabricating a gFET component which minimises or prevents graphene delamination, damage, and / or reducing defects on the graphene layer while at the same time minimising or preventing the Dirac point of the liquid gate of the component from shifting outside the range of -1 V and 1 V, said method comprising the steps of: a) providing a Si / SiO2wafer substrate characterised with a backgate electrode deposited thereon and wherein a solid high-dielectric layer is placed on saidbackgate and wherein a graphene layer is deposited on said solid high-dielectric layer; b) cleaning the graphene deposited layer with a methylbenzene; c) cleaning the layer after step b) with a ketone; and d) cleaning the layer after step c) with an alcohol; e) depositing a polymer resist on the graphene layer after step d); f) defining areas where graphene will remain on wafer substrate using lithography; g) removing any unneeded graphene using O2 plasma etching; h) cleaning off any remaining polymer resist using a methylbenzene; i) cleaning the remaining graphene layer with a ketone; j) cleaning the graphene layer after step i) with an alcohol; k) depositing an adhesive layer comprising Ti or Cr on to the graphene surface layer after step j); l) depositing a gold electrode material layer unto the adhesive layer after step k); m) stripping the gold layer of step l) to form the gFET component which comprises at least one drain, source and gate electrodes, n) applying an effective voltage to the backgate electrode when in use in order to minimise or prevent the Dirac point of the liquid gate component from shifting outside the range of -1 V and 1 V.

[0055] With reference to the above aspect, cleaning steps b)-d) are repeated again after step g), that is, see h)-j).

[0056] According to another aspect the invention provides a method of fabricating a gFET device which minimises or prevents graphene delamination, damage, and / or reducing defects on the graphene layer while at the same time minimising or preventing the Dirac point of the liquid gate of the device from shifting outside the range of -1 V and 1 V, said method comprising the steps of: a) providing a SiO2 / Si wafer substrate characterised with a backgate electrode deposited thereon and wherein a solid high-dielectric layer is placed on saidbackgate and wherein a graphene layer is deposited on said solid high-dielectric layer; b) cleaning the graphene deposited layer with a methylbenzene; c) cleaning the layer after step b) with a ketone; d) cleaning the layer after step c) with an alcohol; e) depositing a polymer resist on the graphene layer after step d); f) defining areas where graphene will remain on wafer substrate using lithography; g) removing any unneeded graphene using O2 plasma etching; h) cleaning off any remaining polymer resist using a methylbenzene; i) cleaning the remaining graphene layer with a ketone; j) cleaning the graphene layer after step i) with an alcohol; k) depositing an adhesive layer comprising Ti or Cr unto the graphene surface layer after step j); l) depositing a gold electrode material layer unto the adhesive layer after step k); m) stripping the gold layer of step l); n) depositing an encapsulation layer to form the gFET device which comprises at least one drain, source and gate electrodes, and wherein only the source and drain gold electrode is encapsulated to prevent shorting, while the graphene and at least part of the gate electrode is unencapsulated and therefore exposed; and o) applying an effective voltage to the backgate electrode when in use in order to minimise or prevent the Dirac point of the liquid gate of the device from shifting outside the range of -1 V and 1 V.

[0057] In still a further aspect, the invention provides a method of fabricating a graphene field effect transistor (gFET) component comprising a graphene layer deposited on SiO2 / Si substrate and wherein said gFET is characterised with at least one drain, source and gate electrodes, said method comprising the steps of: i) providing a SiO2 / Si wafer substrate with a backgate electrode deposited thereon and wherein a solid high-dielectric layer is placed on said backgate; ii) depositing a CVD (chemical vapour disposition) grown graphene layer to the surface of said solid high-dielectric layer by polymer deposition transfer;iii) cleaning the graphene deposited later with a methylbenzene; iv) cleaning the layer after step iii) with a ketone; v) cleaning the layer after step iv) with an alcohol; vi) depositing a polymer resist on the layer after step v) wherein the layer is developed using a methyl isobutyl ketone (MiBK): isopropanol (IPA) mixture in a ratio of about 3:1; vii) defining areas where graphene will remain on wafer substrate using e-beam lithography; viii) removing unneeded graphene using O2 plasma etching; ix) cleaning off any remaining PMMA resist using a methylbenzene; x) cleaning the remaining graphene layer with a ketone; xi) cleaning the graphene layer after step x) with an alcohol; xii) depositing an adhesive layer comprising Ti or Cr unto the graphene surface layer after step xi); xiii) depositing a gold electrode material layer unto the adhesive layer after step xii); xiv) stripping the metal layer of step xiii) to form the gFET component which comprises at least one drain, source and gate electrodes; and xv) applying an effective voltage to the backgate electrode when in use in order to minimise or prevent the Dirac point of the liquid gate of the component from shifting outside the range of -1 V and 1 V.

[0058] In still a further aspect the invention provides a method of fabricating a graphene field effect transistor (gFET) device comprising a graphene layer deposited on SiO2 / Si substrate and wherein said gFET is characterised with at least one drain, source and gate electrodes, said method comprising the steps of: i) providing a SiO2 / Si wafer substrate with a backgate electrode deposited thereon and wherein a solid high-dielectric layer is placed on said backgate electrode; ii) depositing a CVD (chemical vapour disposition) grown graphene layer to the surface of said solid high-dielectric layer by polymer deposition transfer; iii) cleaning the graphene deposited later with a methylbenzene;iv) cleaning the layer after step iii) with a ketone; v) cleaning the layer after step iv) with an alcohol; vi) depositing a polymer resist on the layer after step v) wherein the layer is developed using a methyl isobutyl ketone (MiBK): isopropanol (IPA) mixture in a ratio of about 3:1; vii) defining areas where graphene will remain on wafer substrate using lithography; viii) removing unneeded graphene using O2plasma etching; ix) cleaning off any remaining PMMA resist using a methylbenzene; x) cleaning the remaining graphene layer with a ketone; xi) cleaning the graphene layer after step x) with an alcohol; xii) depositing an adhesive layer comprising Ti or Cr unto the graphene surface layer after step xi); xiii) depositing a metal electrode material layer unto the adhesive layer after step xii); xiv) stripping the metal layer of step xiii); xv) depositing an encapsulation layer to form the gFET device which comprises at least one drain, source and gate electrodes, and wherein only the source and drain metallic electrode is encapsulated to prevent shorting, while the graphene and at least part of the gate electrode is unencapsulated and therefore exposed; and xvi) applying an effective voltage to the backgate electrode when in use in order to minimise or prevent the Dirac point of the liquid gate of the device from shifting outside the range of -1 V and 1 V.

[0059] In certain embodiments and with reference to all aspects, the method further involves a step of depositing an encapsulation layer.

[0060] In respect to all of above aspects, in certain embodiments the methylbenzene is selected from the group consisting of xylene (ortho-xylene, meta-xylene, or para-xylene), toluene, hemellitene (1,2,3-trimethylbenzene), mesitylene (1,3,5-trimethylbenzene), pseudocumene (1,2,4-trimethylbenzene), prehnitene (1,2,3,4-tetramethylbenzene),isodurene (1,2,3,5-tetramethylbenzene), durene (1,2,4,5-tetramethylbenzene), and hexamethylbenzene.

[0061] In respect to all aspects, in certain embodiments the ketone is selected from the group consisting of acetone, ethyl acetate, cyclohexanone, methyl ethyl ketone, or diacetone.

[0062] In respect to all aspects, in certain embodiments the alcohol is selected from the group consisting of isopropanol (IPA), n-propanol, n-butanol, isobutanol, tert-butanol, or n- pentanol, DESCRIPTION

[0063] The term "about" or "approximately" as used herein means within an acceptable error range for the particular value as determined by one of ordinary skill in the art, which will depend in part on how the value is measured or determined, i.e., the limitations of the measurement system.

[0064] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the invention belongs. For the purposes of the present invention, the following terms are defined below.

[0065] Presently in the art one of the most basic cleaning methods used in cleanrooms is the use of ketones and alcohols. The present inventors have also found that the additional cleaning with a methylbenzene (e.g. xylene) is able to improve the graphene layer in terms of minimising delamination and / or defects. So in certain embodiments while also providing methods for improving or minimizing the delamination of the graphene surface, the gFET device or components of the present invention minimise or prevents the Dirac point of the liquid gate from shifting outside the range of -1 V and 1 V.

[0066] In an embodiment, the SiO2 / Si wafer substrate comprises a SiO2 insulation layer of about 100 nm to 400 nm, for instance, about 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, or about 400 nm (or any range between any two of the recited thicknesses). In the present invention the SiO2 layer functions as the solid dielectric layer.

[0067] The backgate layer is deposited on the SiO2side of the wafer.

[0068] A further solid dielectric layer (preferably a solid high K-dielectric layer) is deposited on the Au backgate layer, essentially isolating the backgate layer between two dielectric layers.

[0069] In certain embodiments, chemical vapour disposition (CVD) grown graphene may be deposited on said the upper dielectric layer (preferably a solid high K-dielectric layer) in a cleanroom environment (such as ISO5 / Class 100 type).

[0070] As used herein, "CVD grown graphene" refers to the technique of depositing graphene as a thin film onto a substrate (e.g. Cu or Ni foil) from vapour species through chemical reactions. The process and types of the various possible chemical reactions that occur in a CVD reactor are governed by many complex factors, including the system setup, reactor configuration, gas feedstock, gas ratios, both reactor pressure and gas partial pressures, reaction temperature, growth time, temperature, etc. CVD is an extensively used bottom-up approach for the synthesis of few-layer and single-layer graphene films. A variety of different CVD methods are available that can be employed to synthesise graphene-based materials. According to the characteristics of the processing parameters (pressure, temperature, precursor nature, gas flow state, wall / substrate temperature, depositing time, and activation manner), these methods can be categorised into seven main types based on temperature, pressure, wall / substrate, nature of precursor, depositing time, gas flow state and activation / power source.

[0071] While the CVD grown graphene is often regarded as high-quality graphene, which implies a single crystalline material without contamination, wrinkle, cracks, or other defects. There is a required transfer step to deposit the graphene from the CVD grown graphene substrate onto the desired technological substrate, in the present case the SiO2 / Si wafer substrate.

[0072] It will be appreciated however that the present method is amenable to a commercially available graphene on a Si / SiO2 wafer substrate.

[0073] The transfer may be facilitated by polymer deposition transfer, with the aid of a polymer transfer agent, such as polymethyl methacrylate (PMMA) or poly(bisphenol A carbonate).

[0074] After graphene transfer, delamination and / or defects are commonly observed on the deposited graphene layer which degrade the quality of the graphene available for the application.

[0075] The sources of the above defects most often come from sacrificial CVD grown graphene substrate (e.g. Cu foil); etchant used to dissolve the sacrificial substrate (e.g. ammonium persulfate (APS)); and the support layer (usually organic polymers such as polymethyl methacrylate (PMMA)) that also favours defect formations and produces the most undesirable type of residue owing to the interaction of the polymers with graphene. These defects have a detrimental effect on graphene, mainly related to undesired doping that degrades the electrical and catalytic properties of graphene by creating charge-scattering centres and charge gradients.

[0076] Graphene layers are usually one atom or two atoms thick and as such cracking and delamination can easily occur as a result of mechanical strain applied during cleaning and repeated transfer, and damage from sharp tools. Such damage degrades the electrical properties and mechanical stability of the graphene, resulting in subsequent operational inefficiency or even failure. In addition, analysis of impure and damaged graphene makes it challenging to develop correct structure–property relationships.

[0077] The present inventors have found that the amount of defects and / or delamination can be minimised or avoided by cleaning the graphene-deposited layer with a three-step method comprising a methylbenzene; a ketone; and finally an alcohol. With specific reference to the use of xylene the inventors have recognized that it has been only typically used as a developer in cleanrooms, as most polymers used are not as soluble in xylene as compared to other cleaners (e.g. acetone) and strippers (e.g. N-methyl-2-pyrrolidone). As such, using xylene as a cleaner and solvent has been overlooked. The inventors have identified xyleneas being excellent for removing amorphous carbon deposits and being effective in the dissolution of polymer resists (particularly at thicknesses around and below a micron).

[0078] The present inventors have identified the following advantages of the defined methods:^^ a reduction in the degradation (i.e. delamination and / or defects) to graphene whenpatterned with polymer resists;^^ less complex (with less process steps and solvents) then methods using metalsacrificial layers;^^ current methods of residue removal take more time and energy than this method;^^ easier to integrate into post fabrication processing (i.e. dicing);^^ xylene is not as strong a solvent as traditional removers / cleaners, so less risk ofdamage of graphene;^^ reduces the importance of perfecting the graphene synthesis and transfer methods, asdefective additives can be removed.

[0079] The invention thus in certain embodiments also provides: a) cleaning the graphene deposited layer with a methylbenzene; This may involve washing the layer in the methylbenzene (e.g. xylene) by dispersion and gentle agitation for 1 to 5 minutes. The cleaning may also be achieved by mechanical means such as wiping or aspirating the surface with the methylbenzene through pressure with an inert gas. b) then cleaning the layer with a ketone; and This may involve washing the layer in ketone (e.g. acetone) by dispersion and gentle agitation for 1 to 7 minutes. c) and then subsequently cleaning the layer after with an alcohol This may involve washing the layer in alcohol (e.g. IPA) by dispersion and gentle agitation for 1 to 5 minutes.

[0080] After each of these cleaning steps, or after all three cleaning steps, the graphene deposited layer is optionally dried with an inert gas such as nitrogen.

[0081] As stated above Raman spectroscopy may be used to quantify the number of defects on the deposited graphene layer. In this respect, the intensity of the graphitic peak at approx. 1600 cm-1(such as between 1605-1590 cm-1) is increased by at least 5% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g. acetone and IPA).

[0082] In another embodiment, the intensity of the graphitic peak at approx. 1600 cm-1is increased by at least 10% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g. acetone and IPA).

[0083] In another embodiment, the intensity of the graphitic peak at approx. 1600 cm-1is increased by at least 15% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g. acetone and IPA).

[0084] In another embodiment, the intensity of the graphitic peak at approx. 1600 cm-1is increased by at least 20% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g. acetone and IPA).

[0085] In another embodiment, the intensity of the graphitic peak at approx. 1600 cm-1is increased by at least 25% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g. acetone and IPA).

[0086] In another embodiment, the intensity of the graphitic peak at approx. 1600 cm-1is increased by at least 30% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g. acetone and IPA).

[0087] In this respect, the intensity of the graphitic peak at approx. 2650 cm-1(such as between 2655-2645 cm-1) is increased by at least 5% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g. acetone and IPA).

[0088] In another embodiment, the intensity of the graphitic peak at approx. 2650 cm-1is increased by at least 7% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g. acetone and IPA).

[0089] In another embodiment, the intensity of the graphitic peak at approx. 2650 cm-1is increased by at least 10% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g. acetone and IPA).

[0090] In another embodiment, the intensity of the graphitic peak at approx. 2650cm-1is increased by at least 12% after the three cleaning steps compared to an graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g. acetone and IPA).

[0091] In another embodiment, the intensity of the graphitic peak at approx. 2650 cm-1is increased by at least 15% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g. acetone and IPA).

[0092] In another embodiment, the intensity of the graphitic peak at approx. 2650cm-1is increased by at least 17% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g. acetone and IPA).

[0093] In certain embodiments, the intensity of the graphitic peaks at approx.1600 cm-1and approx. 2650 cm-1are both increased by at least 5% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g. acetone and IPA).

[0094] In certain embodiments, the intensity of the graphitic peaks at approx.1600 cm-1and approx. 2650 cm-1are both increased by at least 7% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g. acetone and IPA).

[0095] In certain embodiments, the intensity of the graphitic peaks at approx.1600 cm-1and approx.2650 cm-1are both increased by at least 10% after the three cleaning steps comparedto an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g. acetone and IPA).

[0096] In certain embodiments, the electrical resistance measurements taken of the graphene deposited layer cleaned with methylbenzene (after PMMA removal), shows electrical resistance in a range close to graphene while when xylene is not included in the processing steps the resistance is over 100 M^.

[0097] The method also contemplates the depositing of an encapsulation layer which may preferably be alumina. The purpose of the layer is to ensure that the gate(s) and the graphene layer are in contact with the gating liquid, but the other parts of the device are not in contact with the liquid. This will prevent shorting between the source and the drain and ensure that the field runs through the liquid only. In certain preferred embodiments, the encapsulation layer is Al2O3. In other certain embodiments, the encapsulation layer is a SU-8 photoresist which is a commonly used epoxy-based negative photoresist, characterised by 8-epoxy groups of the following formula:

[0098] Many of the reported gFETs (devices and componentry) use alumina as an encapsulation layer. Some previous designs also used polymers such as SU-8. SU-8 is useful as an encapsulation layer because it can be directly patterned by lithographic means. Therefore, there is no etching or lift-off required to remove another dielectric encapsulation layer (i.e. alumina). SU-8 is active in both photo and electron beam lithography. Due to this,it may be possible that on a chip, a single layer of SU-8 can be exposed to both forms of lithography. Large areas which need to be encapsulated can be dealt with by photolithography, while smaller more delicate features can be addressed with electron beam.

[0099] In certain embodiments, the encapsulation layer is developed by a glycol ether or acetate, such as propylene glycol methyl ether acetate (PGMEA).

[0100] Reference will now be made to experiments that embody the above general principles of the present invention. However, it is to be understood that the following description is not to limit the generality of the above description. EXPERIMENTAL METHODS

[0101] A Si wafer (with a 300nm SiO2 insulation layer) may be washed with acetone for about 5 minutes with gentle agitation to remove any organic residues. Isopropanol (IPA) may be used for a 3-minute rinse (again with gentle agitation) to remove any further residues. A photoresist layer (AZ1512HS) may then be spin coated before being patterned using a maskless aligner. The photoresist may then be developed using AZ726 for about 1 minute and placed in an e-beam evaporator. A thin layer of a titanium adhesion layer may be deposited before depositing a gold contact layer immediately after without breaking vacuum. Photoresist may then be removed leaving only gold gates and markers.

[0102] HfO2 or Al2O3 may then be deposited on this using an atomic layer deposition (ALD) process. This layer can be approximately 20-30 nm thick. Another layer of photo resist may be patterned exactly as that outlined above with the same cleaning, resist and patterning, and developing. The layer which is patterned in this case is access vias to the bond pads to the gold gates. In this case, HfO2 or Al2O3 may be etched using a wet method (with either a basic or acidic material). Alternative process 1

[0103] CVD graphene may be grown and transferred to a Si / SiO2-backgate-solid high K dielectric-layer surface using an appropriate method.

[0104] The graphene deposited wafer may be introduced or reintroduced to the cleanroom (ISO 5 / Class 100). This wafer may be cleaned by first washing in xylene for 3 minutes with gentle agitation. Following this, the wafer may be placed in acetone for another 5 minutes with gentle agitation to remove any organic residues. Finally, isopropanol (IPA) may be used for a 3-minute rinse (again with gentle agitation) to remove any further residues. This wafer may then be dried with a N2 flow.

[0105] Another lithography step may be performed using the same method as above, this time outlining where the graphene will remain. In this case all the graphene which needs to be removed is exposed.

[0106] Once this is achieved, graphene may be etched using O2 plasma with a reactive ion etcher (Southbay Technologies). Plasma may generated in 30 mT of O2 with an RF power of 50 W, for a time of 1 min. This process may be performed before Au marker deposition (ensuring Au deposition directly on SiO2layer), and to separate graphene sheet into multiple devices (following lithography for the graphene pattern). This process may be performed before Au marker deposition (ensuring Au deposition directly on SiO2layer), and to separate graphene sheet into multiple devices (following lithography for the graphene pattern).

[0107] Following this, a final layer of Al2O3may be deposited using ALD. Once again, a lithography may be performed which creates, via on the liquid gates electrodes, graphene squares and the bond pads to all gates and electrodes. Alternative process 2

[0108] Deposition of Au layer for markers and electrodes may be achieved using an electron beam evaporator (AJA international). Au layers of 30 nm thickness (deposition rate of 2 A / s) may be deposited on the marker (post plasma etching) and electrode lithography patterns. A Ti adhesion layer of 10nm (deposition rate of 1 A / s) may first be deposited prior to Au deposition.

[0109] CVD grown graphene on a Si / SiO2-backgate layer-solid dielectric layer (with a 300nm SiO2 insulation layer) was introduced to the cleanroom (ISO 5 / Class 100). The graphene deposited wafer is cleaned by first washing in xylene for 3 minutes with gentle agitation. Following this, the wafer is placed in acetone for another 5 minutes with gentle agitation to remove any organic residues. Finally, isopropanol (IPA) was used for a 3-minute rinse (again with gentle agitation) to remove any further residues. The wafer was then dried with a N2flow.

[0110] To demonstrate the effect of the xylene in cleaning, a separate process was also conducted involving only washing with acetone and IPA (for the same time and same conditions), before spin coating with a similar layer of PMMA.

[0111] Lithography was carried out with an Elionix F-125 electron beam lithography system. Electron beam voltage was set to 125 keV, while the dose for patterns varied from 1250 µC.cm-2for electrodes and markers (1nA beam size), and 1250 µC.cm-2for the graphene patterns (10 nA beam size). Development of the PMMA was conducted using methyl isobutyl ketone (MiBK) in IPA in a ratio of 1:3 (MiBK:IPA). PMMA was developed first in MiBK:IPA (for 40 s) before being rinsed in IPA (20 s). The die is then dried in an N2stream.

[0112] The design of the markers, graphene and electrode layout was completed with Klayout and converted into a .con file using the Beamer software.

[0113] Graphene rectangles were formed via lithographically defining the areas, then etching the exposed graphene from the surface. Once this was achieved, graphene was etched using O2 plasma with a reactive ion etcher (Southbay Technologies). Plasma was generated in 30 mT of O2with an RF power of 50 W, for a time of 1 min. This process was performed before Au marker deposition (ensuring Au deposition directly on solid dielectric layer), and to separate graphene sheet into multiple devices (following lithography for the graphene pattern).

[0114] Deposition of Au layer for markers and electrodes was achieved using an electron beam evaporator (AJA international). Au layers of 30nm thickness (deposition rate of 2 A / s) were deposited on the marker (post plasma etching) and electrode lithography patterns. A Ti adhesion layer of 10 nm (deposition rate of 1 A / s) was first deposited prior to Au deposition. Also in certain embodiments it is not required to have the markers in this layer if the markers are in the bottom layer. Alternative process 3

[0115] Chips may be fabricated based on a commercial process using photo resist to pattern. In this case each layer of lithography is patterned through the creation of a new mask. It also uses masks to pattern the photoresist. The layering is the same, first there is patterning and removal graphene, then they pattern and deposit a metal layer for electrodes. Finally, there is a depositing of a layer of high-k dielectric (in this case Al2O3), which is then patterned and removed from the graphene, gates and bond pads via etching. Graphene may be grown via a CVD process and use a semi-dry transfer process.

[0116] Backgating experiments were performed with multiple types of gFETs. These gFETs commercially available were then modified to have a gold layer for better electrical access to the Si underneath the SiO2 for backgating. This was achieved by spin coating a the gFET chip with photoresist to protect the device in post processing. The underside of the device was then treated with hydrofluoric acid to remove the native silicon oxide. Following this, a titanium adhesion layer, followed by a gold contact layer was deposited using evaporation. This produced a device that could be through the SiO2 layer under the gFET and through a liquid on top of the gFET. Further Examples Material and Methods

[0117] A global backgate was fabricated on prefabricated S22 gFETs (Graphenea). This was achieved by cleaning the backside of the S22 Si wafer with hydrofluoric acid (HF) to remove the native SiO2layer. To achieve this, the topside of the S22 was spin coated with photo resist to protect the gFET. P-type photoresist, AZ1512 was used, spun in an three step process (first a 5 s ramp to 500 rpm, accelerating at 100 rpm / s, main step at 4000 rpm for 30s with a 1000 rpm / s ramp, and an final ramp down to 0 rpm at 500 rpm / s for 10 s) and then baked at 110 ^C for 5 min. SiO2 was etched by applying a thin film of HF to the backside of the S22 die. When the process was completed, the HF formed a single drop on the back due to the increased hydrophobic nature of the clean Si. The S22 was then loaded in an Evaporator, which was used to deposit 10 nm of Ti, followed by 100 nm of Au. Following this, the photoresist was removed with acetone and rinsed in IPA as mentioned further below. The Design

[0118] The design is 5 layers of lithography Figure 6. First is the (red) is the backgate layer (Ti-Au) which will be deposited on an SiO2 on Si (90nm to 300nm). A high k dielectric (likely AlOx of HfOx) is then deposited on that, with vias being made on top of the backgate bond pads (brown). This is done either by depositing the dielectric on a resist and then lifting off or depositing a continuous layer of dielectric and then etching to the pad. The graphene is then transferred to the dielectric and patterned using a resist and O2 plasma etching the extraneous graphene (purple layer). Metal contacts (Ti-Au) are patterned (light blue) on top of this. Finally, an encapsulating layer is added on top, either polymer based or ceramic based (i.e. AlOx of HfOx) are formed on the contact pads, graphene, and liquid gate electrodes either through lift off patterning or etching (dark blue).

[0119] In certain process embodiments, before each step graphene was cleaned with the method using xylene, acetone and then isopropanol (IPA). The fabrication of electronic components of the gFET occurred across three lithographic layers. First layer is defining and depositing alignment markers (optical lithography). The second layer is defining and etching the appropriate shape of the graphene (Using an oxygen plasma generated in a reactive ion etcher). The graphene is etched into multiple strips of different sizes. The size differences at this stage are mostly demonstrational. The strips are thought to act together as one single conductor in parallel (i.e. there is no way to differentiate which strip the signal is coming from). The strips may be situated between the interdigitated source and drain electrodes. If one strip is damaged during the processing, then the other strips can still make an effective connection, providing redundancy. The other positive is that less graphene is required to make the gFET, meaning that there is a higher tolerance for damages which occur to the larger graphene sheet during processing and transfer. The third step is the definition anddeposition of electrodes (markers and electrodes are gold due to conductivity and chemically inert nature. In the case of the markers, gold is also highly important as it provides a significant contrast when imaged via optics or electrons for the alignment process required in the following layers).

[0120] Finally, a layer of lithography is required to encapsulate and thus insulate most of the device, except electric contacts, the “gate” electrodes (which are used to generate an electric field around the graphene) and the graphene itself. This encapsulation layer prevents the liquid from electrically shorting the chip, while ensuring that sensitive graphene areas are exposed to the liquid solvent, which would be carrying biomarkers in a biological sample. The encapsulating layer was Al2O3, which is a suitable encapsulant for electronics which interface with liquids.

[0121] Measurement of gFET was conducted as follows:^^ Conducted using a Keithley 236 SMU for source drain measurement and an EG&G5209 lock-in Amplifier as a voltage source for the liquid gate and backgate. A PDMS well (~ 5 mm) was placed around the gate and graphene area of the gFET, and 20 µL of 100 mM sodium acetate was pipetted into the well.^^ Measurements were taken at room temperature, measuring the current between thesource-drain as a function of the voltage applied to the liquid gate. A constant source bias was applied to the source-drain electrode, while the liquid gate voltage was varied from 0 V to 1 V with an increment of 0.02 V (first measurement was between 0 V and 1 V, while others were 0.4 V and 0.8 V).^^ This measurement was performed while different voltages were applied to the gFETsbackgate to observe whether the liquid gate Dirac point would be shifted ( see Figures 1 and 2).

[0122] An Isd-Vgate (current vs voltage) curve of the gFET (the current measurement at a particular liquid gate voltage) at room temperature while the liquid gate was immersing the gFET was taken for an series of backgate voltages. This embodiment can be seen in Figure 1 and 2.

[0123] The reference in this specification to any prior publication (or information derived from it), or to any matter which is known, is not, and should not be taken as an acknowledgment or admission or any form of suggestion that that prior publication (or information derived from it) or known matter forms part of the common general knowledge in the field of endeavour to which this specification relates.

[0124] Throughout this specification and the claims which follow, unless the context requires otherwise, the word "comprise", and variations such as "comprises" and "comprising", will be understood to imply the inclusion of a stated integer or step or group of integers or steps but not the exclusion of any other integer or step or group of integers or steps.

[0125] Throughout this specification and the claims which follow, unless the context requires otherwise, the phrase "consisting essentially of", and variations such as "consists essentially of" will be understood to indicate that the recited element(s) is / are essential i.e. necessary elements of the invention. The phrase allows for the presence of other non-recited elements which do not materially affect the characteristics of the invention but excludes additional unspecified elements which would affect the basic and novel characteristics of the method defined.

Claims

THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS:

1. A gFET device or component thereof which minimises or prevents the Dirac point shift overtime, said gFET device or component characterised by at least one drain, source, liquid ionic gate electrode and backgate electrode, wherein said backgate electrode is isolated between two layers of independently selected solid di electric materials wherein when in use an effective voltage is applied to said backgate in order to ensure that the Dirac point shift of the device or component remains between -1.6 V and 1.6 V, and preferably between -1 V and 1 V.

2. A gFET device or component thereof according to claim 1, wherein the backgate electrode is an Au layer.

3. A gFET device or component thereof according to claim 1 or 2, wherein the backgate electrode is a Au layer, and is isolated between two layers of independently selected solid di electric materials selected from SiO2and AlOxor HfOx.

4. A gFET device or component thereof according to claim 1 or claim 2 wherein the backgate electrode is a Au layer, and is isolated between of a layer of a solid di electric material and a layer of a solid high K-dielectric material.

5. A method of fabricating a gFET device or component thereof which minimises or prevents the Dirac point shift overtime, said gFET device or component characterised by at least one drain, source, liquid ionic gate electrode and backgate electrode, said method comprising the step of at least one graphene deposition step, at least one lithography step, and at least one O2 plasma etching step, and further applying an effective voltage to said backgate when in use in order to ensure that the Dirac point shift of the device or component remains between -1.6 V and 1.6 V, and preferably between -1 V and 1 V.

6. A method of fabricating a gFET device or component thereof which minimises or prevents the Dirac point of the liquid gate from shifting out of the -1 V and 1 V range, said gFET device or component characterised by at least one drain, source, top gateand backgate electrodes, said method comprising the steps of at least one graphene deposition step, at least one lithography step, and at least one O2 plasma etching step, and wherein after each one of the aforementioned steps the graphene layer is cleaned with a methylbenzene, followed by a ketone, and then followed by an alcohol, and wherein the method further comprises at least one polymer resist coating layer which is developed using a methyl isobutyl ketone (MiBK): isopropanol (IPA) mixture in a ratio of about 3:1, and further applying an effective voltage to said backgate when in use in order to minimise or prevent the Dirac point of the liquid gate device or component from shifting outside the range of -1 V and 1 V.

7. A gFET or component thereof or a method according to anyone of claims 1 to 6, wherein the effective voltage is applied for the duration of the measurement.

8. A gFET or component thereof or a method according to any one of claims 1 to 6, wherein the effective applied voltage is in the range of -15 V to 15 V, for instance in the -14 V to 14 V range, the -13 V to 13 V range, the -12 V to 12 V range, or the -11 V to 11 V range.

9. A gFET or component thereof or a method according to any one of claims 1 to 8, wherein the Dirac point is prevented from shifting above 1 V and more specifically above 1.6 V (in both positive and negative directions), and preferably between -1 V and 1 V.

10. A method of fabricating a graphene field effect transistor (gFET) comprising a graphene layer deposited on SiO2 / Si substrate and wherein said gFET is characterised with at least one drain, at least one source, at least one top-gate electrode and at least one backgate electrode, said method comprising the steps of: i) providing a Si wafer substrate; ii) depositing a solid dielectric layer on the wafer substrate; iii) depositing at least one backgate electrode on said solid dielectric layer; iv) depositing another solid dielectric layer on the at least one backgate electrode;v) depositing a CVD (chemical vapour disposition) grown graphene layer to the surface of said solid dielectric layer by polymer deposition transfer; vi) cleaning the graphene deposited later with a methylbenzene; vii) cleaning the layer after step vi) with a ketone; viii) cleaning the layer after step vii) with an alcohol; ix) depositing a polymer resist on the layer after step viii); x) defining areas where graphene will remain on wafer substrate using e-beam lithography; xi) removing unneeded graphene using O2 plasma etching; xii) cleaning off any remaining polymer resist using a methylbenzene; xiii) cleaning the remaining graphene layer with a ketone; xiv) cleaning the graphene layer after step xiii) with an alcohol; xv) depositing an adhesive layer comprising Ti or Cr unto the graphene surface layer after step xv); xvi) depositing a metal electrode material layer unto the adhesive layer after step xv); and xvii) stripping the metal layer of step xvi) to form the gFET, which comprises at least one each of a drain, source, top-gate and backgate electrodes, and further applying an effective voltage to said at least one backgate when in use in order to minimise or prevent the Dirac point of the liquid gate device or component from shifting outside the range of -1 V and 1 V.

11. A method of fabricating a gFET component which minimises or prevents graphene delamination, damage, and / or reducing defects on the graphene layer while at the same time minimising or preventing the Dirac point of the liquid gate of the component from shifting outside the range of -1 V and 1 V, said method comprising the steps of: a) providing a Si / SiO2wafer substrate characterised with a backgate electrode deposited thereon and wherein a solid high-dielectric layer is placed on said backgate and wherein a graphene layer is deposited on said solid high-dielectric layer; b) cleaning the graphene deposited layer with a methylbenzene; c) cleaning the layer after step b) with a ketone; andd) cleaning the layer after step c) with an alcohol; e) depositing a polymer resist on the graphene layer after step d); f) defining areas where graphene will remain on wafer substrate using lithography; g) removing any unneeded graphene using O2 plasma etching; h) cleaning off any remaining polymer resist using a methylbenzene; i) cleaning the remaining graphene layer with a ketone; j) cleaning the graphene layer after step i) with an alcohol; k) depositing an adhesive layer comprising Ti or Cr unto the graphene surface layer after step j); l) depositing a gold electrode material layer unto the adhesive layer after step k); m) stripping the gold layer of step l) to form the gFET component which comprises at least one drain, source and gate electrodes; and n) applying an effective voltage to the backgate electrode when in use in order to minimise or prevent the Dirac point of the liquid gate component from shifting outside the range of -1 V and 1 V.

12. A method of fabricating a gFET device which minimises or prevents graphene delamination, damage, and / or reducing defects on the graphene layer while at the same time minimising or preventing the Dirac point of the liquid gate of the device from shifting outside the range of -1 V and 1 V, said method comprising the steps of: a) providing a SiO2 / Si wafer substrate characterised with a backgate electrode deposited thereon and wherein a solid high-dielectric layer is placed on said backgate and wherein a graphene layer is deposited on said solid high-dielectric layer; b) cleaning the graphene deposited layer with a methylbenzene; c) cleaning the layer after step b) with a ketone; and d) cleaning the layer after step c) with an alcohol; e) depositing a polymer resist on the graphene layer after step d); f) defining areas where graphene will remain on wafer substrate using lithography;g) removing any unneeded graphene using O2plasma etching; h) cleaning off any remaining polymer resist using a methylbenzene; i) cleaning the remaining graphene layer with a ketone; j) cleaning the graphene layer after step i) with an alcohol; k) depositing an adhesive layer comprising Ti or Cr unto the graphene surface layer after step j); l) depositing a gold electrode material layer unto the adhesive layer after step k); m) stripping the gold layer of step l); n) depositing an encapsulation layer to form the gFET device which comprises at least one drain, source and gate electrodes, and wherein only the source and drain gold electrode is encapsulated to prevent shorting, while the graphene and at least part of the gate electrode is unencapsulated and therefore exposed; and o) applying an effective voltage to the backgate electrode when in use in order to minimise or prevent the Dirac point of the liquid gate of the device from shifting outside the range of -1 V and 1 V.

13. A method of fabricating a graphene field effect transistor (gFET) device comprising a graphene layer deposited on SiO2 / Si substrate and wherein said gFET is characterised with at least one drain, source and gate electrodes, said method comprising the steps of: i) providing a SiO2 / Si wafer substrate with a backgate electrode deposited thereon and wherein a solid high-dielectric layer is placed on said backgate electrode; ii) depositing a CVD (chemical vapour disposition) grown graphene layer to the surface of said solid high-dielectric layer by polymer deposition transfer; iii) cleaning the graphene deposited later with a methylbenzene; iv) cleaning the layer after step iii) with a ketone; v) cleaning the layer after step iv) with an alcohol; vi) depositing a polymer resist on the layer after step v) wherein the layer is developed using a methyl isobutyl ketone (MiBK): isopropanol (IPA) mixture in a ratio of about 3:1; vii) defining areas where graphene will remain on wafer substrate using lithography; viii) removing unneeded graphene using O2 plasma etching;ix) cleaning off any remaining PMMA resist using a methylbenzene; x) cleaning the remaining graphene layer with a ketone; xi) cleaning the graphene layer after step x) with an alcohol; xii) depositing an adhesive layer comprising Ti or Cr unto the graphene surface layer after step xi); xiii) depositing a metal electrode material layer unto the adhesive layer after step xii); xiv) stripping the metal layer of step xiii); and xv) depositing an encapsulation layer to form the gFET device which comprises at least one drain, source and gate electrodes, and wherein only the source and drain metallic electrode is encapsulated to prevent shorting, while the graphene and at least part of the gate electrode is unencapsulated and therefore exposed, and xvi) applying an effective voltage to the backgate electrode when in use in order to minimise or prevent the Dirac point of the liquid gate of the device from shifting outside the range of -1 V and 1 V.

14. A method according to anyone of claims 5 to 13, further involves a step of depositing an encapsulation layer.

15. A method according to claim 14, wherein the encapsulation layer is Al2O3.

16. A method according to claim 14, wherein the encapsulation layer is developed by a glycol ether or acetate, such as propylene glycol methyl ether acetate (PGMEA).

17. A method according to claims 5 to 14, wherein the methylbenzene is selected from the group consisting of xylene (ortho-xylene, meta-xylene, or para-xylene), toluene, hemellitene (1,2,3-trimethylbenzene), mesitylene (1,3,5-trimethylbenzene), pseudocumene (1,2,4-trimethylbenzene), prehnitene (1,2,3,4-tetramethylbenzene), isodurene (1,2,3,5-tetramethylbenzene), durene (1,2,4,5-tetramethylbenzene), and hexamethylbenzene, preferably xylene.

18. A method according to claims 5 to 15, wherein the ketone is selected from the group consisting of acetone, ethyl acetate, cyclohexanone, methyl ethyl ketone and diacetone, preferably acetone.

19. A method according to claims 5 to 15, wherein the alcohol is isopropyl alcohol (IPA).

20. A method according to claims 5 to 15, wherein: ^^ cleaning the graphene deposited layer with a methylbenzene;which involves washing the layer in the methylbenzene (e.g. xylene) by dispersion and gentle agitation for 1 to 5 minutes or cleaning by mechanical means such as wiping or aspirating the surface with the methylbenzene through pressure with an inert gas; ^^ cleaning the layer with a ketone;which involves washing the layer in ketone (e.g. acetone) by dispersion and gentle agitation for 1 to 7 minutes; and ^^ cleaning the layer after with an alcohol;which involves washing the layer in alcohol (e.g. IPA) by dispersion and gentle agitation for 1 to 5 minutes.

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