Chip and manufacturing method therefor, and electronic device

Abstract

The present application relates to the technical field of chips, and provides a chip and a manufacturing method therefor, and an electronic device, which can improve the quality of source-drain structures. The chip comprises a gate-all-around field effect transistor provided on a substrate. The gate-all-around field effect transistor comprises a fin structure, a first semiconductor layer, and a source-drain structure. A channel layer and a gate layer are provided in the fin structure. The first semiconductor layer is disposed on a side surface of the fin structure, and continuously covers the end surfaces of the channel layer and the gate layer. The source-drain structure is grown on the surface of the side of the first semiconductor layer distant from the fin structure. The side surface of the first semiconductor layer is a continuous crystal plane, so that the source-drain structure grown on the side surface of the first semiconductor layer is a continuous structure, avoiding the epi merge problem, improving the quality of the source-drain structure, and facilitating the improvement of device performance.

Description

Chip, manufacturing method thereof, and electronic device TECHNICAL FIELD

[0001] The present application relates to the technical field of chips, and in particular to a chip, a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] A gate-all-around field effect transistor (GAA) is an innovative next-generation transistor device that has been widely adopted by the industry. The gate of the GAA surrounds the channel in four directions, which can achieve stronger control over the channel and further reduce the influence of short channel effect (SCE).

[0003] FIG. 1 is a structural schematic diagram of a GAA device in a manufacturing process according to the prior art. Referring to FIG. 1, in the manufacturing process of the GAA device, the source-drain structure S / D is epitaxially grown on the end surface of the inner spacer and the channel layer. Since the current epitaxy is based on the selection growth of the semiconductor crystal surface, and the inner spacer is made of insulator material rather than crystal material, the source-drain structure S / D can only be epitaxially grown on the end surface of the channel layer, and cannot be normally epitaxially grown on the end surface of the inner spacer, thereby causing epi merge problem and generating defects such as dislocation and stacking fault.

[0004] In the GAA device, the quality of the source-drain structure S / D will affect the stress on the channel and further affect the channel mobility, and thus is crucial to the performance of the device.

[0005] SUMMARY

[0006] The present application provides a chip, a manufacturing method thereof, and an electronic device, which can improve the quality of the source-drain structure.

[0007] The application provides a chip, which comprises a ring gate field effect transistor arranged on a substrate, and the ring gate field effect transistor comprises a fin structure, a first semiconductor layer and a source-drain structure. The fin structure is provided with a channel layer and a gate layer. The first semiconductor layer is arranged on the side surface of the fin structure and continuously covers the end surface of the channel layer and the gate layer. The source-drain structure is grown on the surface of the first semiconductor layer away from the fin structure. Since the side surface of the first semiconductor layer is a continuous crystal surface, the source-drain structure epitaxially grown thereon is a continuous structure, the epitaxial fusion problem in the prior art is avoided, the quality of the source-drain structure is improved, and the device performance is more favorable to be improved.

[0008] In some possible implementation manners, the first semiconductor layer has the same crystal orientation as the end surface of the channel layer in the region covering the end surface of the channel layer. Since the first semiconductor layer is directly grown on the end surface of the channel layer, the surface of the first semiconductor layer and the surface of the channel layer have the same crystal orientation, for example, both are (110) crystal surfaces, in the contact region.

[0009] In some possible implementation manners, the surface of the first semiconductor layer close to the fin structure has the same or approximately the same crystal orientation. In the manufacturing process, since the first semiconductor layer is grown on the continuous crystal surface of the second semiconductor layer, the first semiconductor layer can be ensured to have a continuous and flat film structure, so that the surface of the first semiconductor layer close to the fin structure has the same or approximately the same crystal orientation, for example, a (110) crystal surface.

[0010] In some possible implementation manners, the surface of the first semiconductor layer close to the fin structure is a (110) crystal surface, and the end surface of the channel layer is a (110) crystal surface.

[0011] In some possible implementation manners, the fin structure further comprises an inner side wall between the two adjacent channel layers, and the end surface of the inner side wall is flush or approximately flush with the end surface of the channel layer on the side close to the first semiconductor layer. On the one hand, the arrangement of the inner side wall can reduce the gate capacitance of the device, and is more favorable to improve the device performance. On the other hand, before the inner side wall is manufactured in the gap between the two channel layers, the second semiconductor layer needs to be removed, and the exposed first semiconductor layer is used as the growth surface of the inner side wall. In the process of removing the second semiconductor layer, the first semiconductor layer is not obviously damaged, and the end surface of the inner side wall can be flush or approximately flush with the end surface of the channel layer.

[0012] In some possible implementation manners, the fin structure further comprises an inner side wall located between two adjacent channel layers; and an end surface of the inner side wall protrudes from an end surface of the channel layer on a side close to the first semiconductor layer. In one aspect, the inner side wall can reduce the gate capacitance of the device, and is more conducive to improving the performance of the device. In another aspect, before the inner side wall is manufactured in the gap between the two channel layers, the second semiconductor layer needs to be removed, and the exposed first semiconductor layer is used as a growth surface of the inner side wall. When the second semiconductor layer is removed, the first semiconductor layer can be damaged to form a recess, so that the end surface of the inner side wall protrudes from the end surface of the channel layer.

[0013] In some possible implementation manners, the ring gate field effect transistor further comprises: a top gate structure and a side wall; the side wall and the top gate structure are located on the top of the fin structure, and the side wall is located on both sides of the top gate structure; and the side wall and the inner side wall are made of the same material. The side wall and the inner side wall are made by one processing technology, so that they have the same material. In this way of manufacturing the inner side wall, the material selection can be diversified.

[0014] In some possible implementation manners, the fin structure further comprises an interface layer and a high-k dielectric layer; the high-k dielectric layer surrounds the gate layer; and the interface layer is located on the surface of the channel layer and extends from a region between the high-k dielectric layer and the channel layer to a region between the inner side wall and the channel layer.

[0015] In some possible implementation manners, the fin structure further comprises an interface layer and a high-k dielectric layer; the interface layer and the high-k dielectric layer are located in a region between the gate layer and the channel layer, the interface layer is located on the surface of the channel layer, and the high-k dielectric layer is located on a side of the interface layer away from the channel layer; and the region between the inner side wall and the channel layer is not provided with the interface layer and the high-k dielectric layer.

[0016] In some possible implementation manners, the fin structure further comprises an interface layer and a high-k dielectric layer; the high-k dielectric layer surrounds the gate layer; and the interface layer is located on the surface of the channel layer, and the region between the inner side wall and the channel layer is not provided with the interface layer.

[0017] In some possible implementation manners, the material of the first semiconductor layer is different from the material of the channel layer, so as to meet the etching selection ratio of the two.

[0018] In some possible implementation manners, the thickness of the first semiconductor layer is in a range of 1 nm to 4 nm.

[0019] In some possible implementation manners, the first semiconductor layer and the channel layer are provided with a second semiconductor layer; the material of the second semiconductor layer is the same as the material of the channel layer, and the material of the second semiconductor layer is different from the material of the first semiconductor layer.

[0020] The application further provides a chip manufacturing method, which can include: manufacturing a fin structure on a substrate, the fin structure including a channel layer and a sacrificial layer; sequentially forming a second semiconductor layer and a first semiconductor layer on the side surface of the fin structure; wherein the first semiconductor layer and the second semiconductor layer both continuously cover the end surface region of the channel layer and the sacrificial layer; forming a source-drain structure on the side surface of the first semiconductor layer by epitaxial growth; removing the sacrificial layer in the fin structure to form a gap and expose the second semiconductor layer; removing the second semiconductor layer at both ends of the gap and expose the first semiconductor layer; and manufacturing a gate layer in the gap.

[0021] By sequentially forming the second semiconductor layer and the first semiconductor layer on the side surface of the fin structure, the first semiconductor layer is grown outside the second semiconductor layer, so that the first semiconductor layer has a continuous crystal surface, and the source-drain structure grown thereon has a continuous structure, thereby improving the quality of the source-drain structure and facilitating the improvement of the device performance.

[0022] In some possible implementation manners, before manufacturing the gate layer in the gap, the chip manufacturing method further includes: forming an inner side wall on the surface of the first semiconductor layer exposed in the gap, and forming an interface layer on the surface of the channel layer. The inner side wall can reduce the gate capacitance of the device, thereby facilitating the improvement of the device performance.

[0023] In some possible implementation manners, the forming of the inner side wall on the surface of the first semiconductor layer exposed in the gap and the forming of the interface layer on the surface of the channel layer include: first performing surface pre-cleaning treatment on the gap, so that the surface of the first semiconductor layer is hydrophilic and the surface of the channel layer is hydrophobic; then forming a self-assembled monolayer on the surface of the first semiconductor layer, so that the surface of the first semiconductor layer is hydrophobic; then forming the interface layer with hydrophilicity on the surface of the channel layer; and then forming the inner side wall with hydrophilicity on the surface of the first semiconductor layer. The manufacturing of the gate layer in the gap includes: first forming a high-k dielectric layer (i.e., a high-dielectric-constant dielectric layer) on the surface of the interface layer and the inner side wall; and then forming the gate layer in the inner side region of the high-k dielectric layer.

[0024] In some possible implementation manners, the forming of the inner side wall on the surface of the first semiconductor layer exposed in the gap and the forming of the interface layer on the surface of the channel layer include: first performing surface pre-cleaning treatment on the gap, so that the surface of the first semiconductor layer is hydrophilic and the surface of the channel layer is hydrophobic; then forming the inner side wall with hydrophilicity on the surface of the first semiconductor layer; then forming a self-assembled monolayer on the surface of the inner side wall, so that the surface of the inner side wall is hydrophobic; and then forming the interface layer with hydrophilicity on the surface of the channel layer. The manufacturing of the gate layer in the gap includes: first forming a high-k dielectric layer on the surface of the interface layer; and then forming the gate layer in the inner side region of the high-k dielectric layer and the inner side wall.

[0025] In some possible implementation manners, the surface of the first semiconductor layer exposed in the gap forms the inner sidewall, and the surface of the channel layer forms the interface layer, including: performing surface pre-cleaning treatment on the gap, so that the surface of the first semiconductor layer is hydrophilic, and the surface of the channel layer is hydrophobic. Then, the inner sidewall with hydrophilic property is formed on the surface of the first semiconductor layer. Then, the interface layer with hydrophilic property is formed on the surface of the channel layer. The gate layer is manufactured in the gap, including: forming the high-k dielectric layer on the surface of the interface layer and the inner sidewall. Then, the gate layer is formed in the inner region of the high-k dielectric layer.

[0026] In some possible implementation manners, the manufacturing method further includes: forming a sacrificial gate structure on the top of the fin structure and a sacrificial sidewall on both sides of the sacrificial gate structure. The surface of the first semiconductor layer exposed in the gap forms the inner sidewall, including: removing the sacrificial sidewall, and forming the inner sidewall on the surface of the first semiconductor layer exposed in the hole, and forming the sidewall on both sides of the sacrificial gate structure.

[0027] The sidewall and the inner sidewall are manufactured by one processing technology, so that the sidewall and the inner sidewall have the same material, and the manufacturing process can be simplified, the manufacturing cost is reduced, and the material selection of the inner sidewall can be diversified by etching.

[0028] The application further provides an electronic device, including a circuit board and a chip provided in any one of the possible implementation manners, and the circuit board is electrically connected with the chip. BRIEF DESCRIPTION OF DRAWINGS

[0029] FIG. 1 is a structure schematic diagram of a GAA device in a manufacturing process provided in the prior art;

[0030] FIG. 2 is a process schematic diagram of manufacturing a GAA device in the prior art;

[0031] FIG. 3 is a structure schematic diagram of a GAA in a chip provided in an embodiment of the application;

[0032] FIG. 4 is a flowchart of a manufacturing method of a chip provided in an embodiment of the application;

[0033] FIG. 5 is a structure schematic diagram of a chip in a manufacturing process provided in an embodiment of the application;

[0034] FIG. 6 is a structure schematic diagram of a chip in a manufacturing process provided in an embodiment of the application;

[0035] FIG. 7 is a structure schematic diagram of a chip in a manufacturing process provided in an embodiment of the application;

[0036] FIG. 8 is a structure schematic diagram of a chip in a manufacturing process provided in an embodiment of the application;

[0037] FIG. 9 is a structural schematic diagram of a chip in a manufacturing process according to an embodiment of the present application;

[0038] FIG. 10 is a structural schematic diagram of a chip in a manufacturing process according to an embodiment of the present application;

[0039] FIG. 11 is a structural schematic diagram of a chip in a manufacturing process according to an embodiment of the present application;

[0040] FIG. 12 is a structural schematic diagram of a chip in a manufacturing process according to an embodiment of the present application;

[0041] FIG. 13 is a structural schematic diagram of a chip in a manufacturing process according to an embodiment of the present application;

[0042] FIG. 14 is a structural schematic diagram of a chip in a manufacturing process according to an embodiment of the present application;

[0043] FIG. 15 is a structural schematic diagram of a chip in a manufacturing process according to an embodiment of the present application;

[0044] FIG. 16 is a structural schematic diagram of a chip in a manufacturing process according to an embodiment of the present application;

[0045] FIG. 17 is a structural schematic diagram of a chip in a manufacturing process according to an embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme of the present application will be described clearly and completely below in combination with the drawings in the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those of ordinary skill in the art without any creative work, fall within the scope of protection of the present application.

[0047] The terms "first", "second", etc. in the description embodiments of the present application and claims and drawings are only used for distinguishing description purposes and cannot be understood as indicating or implying relative importance, nor can be understood as indicating or implying sequence. "And / or" is used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, wherein A and B can be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connection" and the like should be broadly understood, for example, it can be an electrical connection, or a mechanical connection; it can be a fixed connection, or a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or a connection between two elements. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a series of steps or units. The method, system, product or device is not necessarily limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right" and the like are only used for the orientation of the components in the drawings, and these directional terms are relative concepts, which are used for relative description and clarification, which can change accordingly according to the change of the orientation of the components in the drawings.

[0048] The embodiment of the present application provides a chip, a new GAA structure is used in the chip, and a continuous semiconductor layer (which can also be a first semiconductor layer) is formed on the side of a fin structure (including a channel layer and a sacrifice layer arranged in a stack) in the process of manufacturing the GAA, and a source-drain structure is epitaxially grown on the side of the semiconductor layer. Since the side of the semiconductor layer is a continuous growth surface, the problem of epi merge is avoided, and the quality of the source-drain epitaxial structure is improved.

[0049] The embodiment of the present application also provides an electronic device using the chip, which can be a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, and the like, and the present application does not limit this.

[0050] The consumer electronic product can be a mobile phone, a tablet computer, a notebook computer, a personal computer (PC), a personal digital assistant (PDA), a smart wearable product (for example, a smart watch, a smart bracelet, etc.), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone, etc. The home electronic product can be a smart door lock, a television, a smart speaker, a refrigerator, a sweeping robot, etc. The vehicle-mounted electronic product can be a vehicle-mounted navigator, a vehicle-mounted display, etc. The financial terminal product can be an automated teller machine (ATM), a self-service electronic device, etc. The communication electronic product can be a server, a memory, a radar, a base station, etc.

[0051] Of course, according to actual needs, other devices such as a printed circuit board (PCB) and an input / output device can be electrically connected to the chip, and the present application does not limit this.

[0052] The following describes a new GAA structure provided by the embodiments of the present application in combination with the prior art.

[0053] FIG. 2 is a schematic diagram of a process of manufacturing a GAA device in the prior art.

[0054] The process of manufacturing a GAA device in the prior art can include:

[0055] First, as shown in (a) of FIG. 2, a fin structure F (also referred to as a semiconductor fin structure) is manufactured on a substrate, and the fin structure F includes channel layers 1 and sacrificial layers 2 which are alternately stacked. The channel layers 1 and the sacrificial layers 2 are made of different semiconductor materials, for example, the channel layers 1 can be made of silicon (Si), and the sacrificial layers 2 can be made of silicon germanium (SiGe).

[0056] Then, as shown in (b) of FIG. 2, the sacrificial layers 2 are etched from the side of the fin structure F, so as to form cavities a on the side of the sacrificial layers 2.

[0057] Then, as shown in (c) and (d) of FIG. 2, a dielectric layer 3 is deposited on the side of the fin structure F, and the dielectric layer 3 is etched, so as to retain the dielectric layer 3 in the cavities a, thereby forming inner sidewalls 31 on the side of the sacrificial layers 2.

[0058] It should be understood that, when etching the medium layer 3, due to process reasons, the side surface of the inner side wall 31 and the side surface of the channel layer 1 are inevitably not flush, that is, the side surface of the fin structure F is not a flat surface.

[0059] Then, as shown in (e) of FIG. 2, an epitaxial growth process is adopted to grow an epitaxial structure EPI on both sides of the fin structure F, respectively as a GAA device source-drain structure, that is, a source S and a drain D.

[0060] When growing the epitaxial structure EPI on the side surface of the fin structure F, since the crystal structure of the inner side wall 31 is different from that of the fin structure F, selective epitaxial growth cannot form an epitaxial structure on the surface thereof, and can only be epitaxial growth on the crystal material on the side surface of the channel layer 1. When the crystal of each layer epitaxial growth on the side surface of the channel layer 1 reaches a sufficient size, epi merge occurs, thereby generating defects such as dislocations and stacking faults, which further affects the channel mobility and causes the device performance to be affected.

[0061] Based on this, as shown in FIG. 3, an embodiment of the present application provides a chip, which adopts a new GAA structure. The GAA structure includes a fin structure F disposed on a substrate 100, and the fin structure F includes a channel layer 101 and a gate layer G stacked and disposed. First semiconductor layers A1 are disposed on both sides of the fin structure F, and the first semiconductor layers A1 continuously cover the end surfaces of the channel layer 101 and the gate layer G, that is, the first semiconductor layers A1 continuously cover the side surface of the fin structure F. A source-drain structure S / D (which can also be referred to as a source-drain epitaxial structure) is grown on the side surface of the first semiconductor layer A1 (the surface away from the fin structure F).

[0062] Similar to the complete crystal surface of the side surface of the fin structure of a conventional finfet (fin field effect transistor), the side surface of the first semiconductor layer A1 is a continuous complete crystal surface, so that the source-drain structure S / D grown on the side surface is a continuous structure, thereby avoiding the epi merge problem in the prior art, improving the quality of the source-drain structure S / D, and being more conducive to improving the device performance (such as channel mobility).

[0063] It should be understood that the GAA device provided by the embodiment of the present application can be a nano sheet GAA device or a nano wire GAA device. Of course, the GAA device can also be applicable to a complementary field effect transistor (CFET). The following embodiments are described by taking the nano sheet GAA device as an example.

[0064] The GAA device provided by the embodiment of the present application is further described below in combination with the manufacturing process of the chip.

[0065] It is illustrated that the manufacturing method of the chip provided by the embodiment of the present application can include the following steps:

[0066] FIGS. 5 to 10 are schematic structural diagrams of different stages in the manufacturing of the GAA according to some embodiments of the present application. It should be understood that additional operations can be provided before, during and after the processes shown in FIGS. 5 to 10, and for other embodiments of the manufacturing method, some of the operations / process steps described below can be replaced or removed, and the order of some of the operations / process steps can be interchanged.

[0067] Step 10, as shown in FIG. 5, a fin structure F is formed on the substrate 100; wherein the fin structure F includes channel layers 101 and sacrificial layers 102 which are alternately stacked.

[0068] The substrate 100 described above can be silicon (Si), i.e., a silicon substrate; the channel layer 101 can be silicon (Si); and the sacrificial layer 102 can be silicon germanium (SiGe). Of course, in other possible implementations, the substrate 100 described above can be silicon germanium (SiGe); the channel layer 101 can be silicon germanium (SiGe), such as SiGe 0.2x ; and the sacrificial layer 102 can be silicon (Si). The selection of the channel layer 101 and the sacrificial layer 102 should satisfy the etching selectivity ratio to ensure normal process requirements. In practice, the materials of the substrate 100, the channel layer 101 and the sacrificial layer 102 can be selected as needed, which is not limited in the present application.

[0069] It is illustrated that in some possible implementations, as shown in FIG. 5, the step 10 described above can include: providing a silicon substrate 100 and doping the silicon substrate 100 to form a well region. Then, a semiconductor stack layer is formed on the surface of the silicon substrate 100, which includes SiGe layers (102) and Si layers (101) which are alternately stacked. Then, a film layer (not shown in FIG. 5) such as a dummy gate layer and a mask layer is manufactured on the semiconductor stack layer, and the semiconductor stack layer is patterned under the mask effect of the mask layer to form a fin structure F.

[0070] It should be noted that FIG. 5 is only illustrative to take the fin structure F provided with three channel layers 101 and two sacrificial layers 102 as an example for illustration, but the present application is not limited thereto, and in practice, the number of channel layers 101 and sacrificial layers 102 in the fin structure F can be set as needed.

[0071] Step 20, as shown in FIG. 6, sequentially forming a second semiconductor layer A2 and a first semiconductor layer A1 on the side of the fin structure F; wherein the second semiconductor layer A2 and the first semiconductor layer A1 both continuously cover the end surface region of the channel layer 101 and the sacrificial layer 102.

[0072] It should be noted that the above-mentioned "covering" can be direct contact covering or indirect covering, which is determined according to the position of the film layer.

[0073] The above-mentioned "the second semiconductor layer A2 and the first semiconductor layer A1 both continuously cover the end surface of the channel layer 101 and the sacrificial layer 102" means that the second semiconductor layer A2 and the first semiconductor layer A1 continuously cover the end surface region of the channel layer 101 and the sacrificial layer 102, the second semiconductor layer A2 can directly cover the end surface of the channel layer 101 and the sacrificial layer 102 and contact the end surface of the channel layer 101 and the sacrificial layer 102; the first semiconductor layer A1 can cover the side of the second semiconductor layer A2 and does not contact the end surface of the channel layer 101 and the sacrificial layer 102.

[0074] The above-mentioned second semiconductor layer A2 can adopt the same semiconductor material as the channel layer 101, that is, adopt different semiconductor material from the sacrificial layer 102, so as to meet the etching selectivity ratio between the second semiconductor layer A2 and the sacrificial layer 102, which can be referred to the subsequent manufacturing process. For example, in some possible implementation modes, the second semiconductor layer A2 and the channel layer 101 both adopt Si, and the sacrificial layer 102 adopts SiGe. For another example, in some possible implementation modes, the second semiconductor layer A2 and the channel layer 101 both adopt SiGe, and the sacrificial layer 102 adopts Si. It is illustrated that the thickness of the second semiconductor layer A2 can be in the range of 1 nm to 4 nm.

[0075] The above-mentioned first semiconductor layer A1 can adopt different semiconductor material from the second semiconductor layer A2, so as to ensure the etching selectivity ratio between the first semiconductor layer A1 and the second semiconductor layer A2, which can be referred to the subsequent manufacturing process. For example, in some possible implementation modes, the second semiconductor layer A2 adopts Si, and the first semiconductor layer A1 adopts SiGe. For another example, in some possible implementation modes, the second semiconductor layer A2 adopts SiGe, and the first semiconductor layer A1 adopts Si. It is illustrated that the thickness of the first semiconductor layer A1 can be in the range of 1 nm to 4 nm.

[0076] In some possible implementation manners, the step 10 can include, as shown in (a) of FIG. 6, epitaxially growing a second semiconductor layer A2 of Si with a thickness of 1-2 nm on both sides of the fin structure F; in this case, the second semiconductor layer A2 continuously covers the end surfaces of the channel layer 101 and the sacrificial layer 102 on both sides of the fin structure F and directly contacts the end surfaces of the channel layer 101 and the sacrificial layer 102. Then, as shown in (b) of FIG. 6, a first semiconductor layer A1 of SiGe with a thickness of 1-2 nm is epitaxially grown on the outside of the second semiconductor layer A2 (Si), and the first semiconductor layer A1 continuously covers the end surface regions of the channel layer 101 and the sacrificial layer 102 but does not contact the end surfaces of the channel layer 101 and the sacrificial layer 102.

[0077] It should be noted that the part of the second semiconductor layer A2 covering the end surface of the channel layer 101 is used as a channel of the GAA device and can be regarded as a channel layer.

[0078] Since the first semiconductor layer A1 is grown on the outside of the second semiconductor layer A2, the first semiconductor layer A1 can be ensured to be a continuous and flat film layer structure, in which case, the surface of the first semiconductor layer A1 close to the side of the fin structure F has the same or substantially the same crystal orientation, and the contact surface of the first semiconductor layer A1 and the second semiconductor layer A2 has the same or substantially the same crystal orientation, for example, the contact surface of the first semiconductor layer A1 and the second semiconductor layer A2 can both be (110) crystal surfaces.

[0079] In addition, as described above, the part of the second semiconductor layer A2 covering the end surface of the channel layer 101 can be regarded as a channel layer and used as a channel of the GAA device. In this case, it can be considered that the region of the first semiconductor layer A1 covering the cross section of the channel layer 101 has the same crystal orientation as the end surface of the channel layer 101, for example, the region of the first semiconductor layer A1 covering the cross section of the channel layer 101 and the end surface of the channel layer 101 can both be (110) crystal surfaces; in this case, the substrate can be a Si<100> substrate.

[0080] The step 30 can include, as shown in FIG. 7, forming a source / drain structure S / D on the side surface of the first semiconductor layer A1 by epitaxial growth.

[0081] In some possible implementation manners, the step 30 can include, as shown in FIG. 7, using an epitaxial growth process to epitaxially grow a source / drain structure S / D on the surface of the first semiconductor layer A1 on both sides of the fin structure F, that is, the source structure (source) and the drain structure (drain) of the GAA device on both sides. In the present application, the source structure (source) and the drain structure (drain) can be used interchangeably, and their structures are basically the same.

[0082] The material of the source-drain structure S / D is determined according to the NMOS and PMOS. For example, for the NMOS device, in some possible implementation manners, Si:P can be grown on the surface of the first semiconductor layer A1 located on both sides of the fin structure F as the source-drain structure S / D. For the PMOS device, in some possible implementation manners, SiGe:B can be grown on the surface of the first semiconductor layer A1 located on both sides of the fin structure F as the source-drain structure S / D.

[0083] Since the growth surface of the source-drain structure S / D (i.e., the side surface of the first semiconductor layer A1) is a continuous crystal surface, the source-drain structure S / D can be grown in a complete crystal surface epitaxy similar to the fin structure of the conventional finfet, instead of being grown in an epitaxy from the intermittent channel side surface of the GAA stack in the prior art, thereby avoiding the epi merge problem in the prior art and improving the quality of the source-drain structure.

[0084] In addition, due to the epi merge problem, the GAA device in the prior art causes defects such as gaps, stacking faults, and dislocations in the epitaxial part (S / D), and the crystal lattice of the epitaxial part (S / D) is in a disordered state in the region on both sides of the inner spacer. In contrast, in the GAA device of the present application, there are almost no defects such as dislocations, stacking faults, and gaps caused by epi merge in the source-drain structure S / D, and only a small amount of defects will occur in the case of poor process control; and the crystal in the source-drain structure S / D is in an ordered state in the region on both sides of the inner spacer. In other words, the crystal in the source-drain structure S / D is generally in a continuous and ordered state on the entire side surface of the fin structure F. The inner spacer in the GAA device of the present application can be referred to the related content below.

[0085] Step 40, referring to FIG. 8, the gap b is formed by removing the sacrificial layer 102 in the fin structure F, and the second semiconductor layer A2 is exposed.

[0086] In some possible implementation manners, referring to FIG. 8, the step 40 can include: removing the sacrificial layer 102 by selective etching to form the gap b, and exposing the second semiconductor layer A2 at both ends of the gap b close to the source-drain structure S / D, while releasing the channel layer 101.

[0087] Step 50, referring to FIG. 9, the second semiconductor layer A2 at both ends of the gap b is removed, and the first semiconductor layer A1 is exposed.

[0088] In some possible implementation manners, as shown in FIG. 9, step 50 can include: removing the second semiconductor layer A2 on both sides of the gap b by etching, and exposing the first semiconductor layer A1 on both sides of the gap b, taking the first semiconductor layer A1 as an etch stop layer. For example, in the case where the second semiconductor layer A2 and the channel layer 101 are both made of Si, silicon thinning (Si trim) is performed by step 50 to expose SiGe (A1) on both sides of the gap b.

[0089] It should be understood that, when removing the second semiconductor layer A2 on both sides of the gap b, the first semiconductor layer A1 is taken as an etch stop layer, which has small etching difficulty and is easy to control.

[0090] Step 60, as shown in FIG. 10, a gate layer G is made in the gap b.

[0091] Of course, before making the gate layer G, other film layers also need to be made in the gap b, which can be referred to the relevant description below.

[0092] In some possible implementation manners, step 60 can include: using an HKMG (high-k metal gate) technology to make a high-k dielectric layer and a metal gate (the gate layer G) and other related film layers in the gap b.

[0093] It is considered that directly making the gate layer G and other related film layers in the gap b will make the capacitance (gate capacitance) of the device larger, which is not conducive to the performance improvement of the device. Therefore, in order to reduce the capacitance of the device, as shown in FIG. 11, in some possible implementation manners, an inner spacer 103 can be formed on the surface of the first semiconductor layer A1 exposed at both ends of the gap b before making the gate layer G in the gap b. Then, the gate layer G is made inside the inner spacer 103.

[0094] In some possible implementation manners, as shown in (a) of FIG. 11, a low-k material (low dielectric constant material) can be deposited on the surface of the first semiconductor layer A1 exposed at both ends of the gap b by selective deposition to form a low-k dielectric layer as the inner spacer 103, so as to reduce the gate capacitance of the device.

[0095] In addition, as shown in FIG. 1, in the prior art, due to the process, the end surface of the inner spacer on the side close to the source-drain structure S / D is not flush with the end surface of the channel layer, and generally the end surface of the inner spacer is recessed inward relative to the end surface of the channel layer.

[0096] In contrast, the end surface of the inner sidewall 103 near the source / drain structure S / D is different from that in the prior art based on the manufacturing method of the present application.

[0097] For example, in some possible implementations, the second semiconductor layer A2 is removed in step 50 without causing significant damage to the first semiconductor layer A1 (see FIG. 9). In this case, as shown in (a) of FIG. 11, the end surface of the inner sidewall 103 near the source / drain structure S / D is flush or substantially flush with the end surface of the channel layer 101.

[0098] For another example, in some possible implementations, as shown in FIG. 12, the second semiconductor layer A2 is removed in step 50, which can cause damage to the first semiconductor layer A1, thereby forming recesses on the surface of the first semiconductor layer A1 at both ends of the gap b. In this case, as shown in FIG. 12, the end surface of the inner sidewall 103 near the source / drain structure S / D protrudes from the end surface of the channel layer 101.

[0099] In addition, the present application does not limit the manufacturing method of the inner sidewall 103 and the gate layer G described above, and in practice, a suitable process can be used for manufacturing according to the needs. Taking the channel layer 101 using Si and the first semiconductor layer A1 using SiGe as an example, three different manufacturing methods are provided below.

[0100] Manufacturing Method One

[0101] First, as shown in (a) of FIG. 13, the gap b is subjected to surface pre-cleaning treatment to make the surface of the first semiconductor layer A1 hydrophilic and the surface of the channel layer 101 hydrophobic.

[0102] For example, by subjecting the gap b to surface pre-cleaning treatment, the silicon oxide SiO2 on the surface of the channel layer 101 and the GeO2 on the surface of the first semiconductor layer A1 can be removed, but other germanium oxides GeOx cannot be removed. In this case, the surface (GeOx) of the first semiconductor layer A1 is hydrophilic, and the surface (Si) of the channel layer 101 is hydrophobic.

[0103] Then, a self-assemble monolayers (SAM) is formed on the hydrophilic surface of the first semiconductor layer A1 to convert the hydrophilic surface of the first semiconductor layer A1 into a hydrophobic surface. At this time, the surface of the first semiconductor layer A1 and the surface of the channel layer 101 are both hydrophobic. The SAM is not shown in FIG. 13.

[0104] The self-assembled monolayer (SAM) can be formed by a wet process or a dry process. In the wet process, the substrate to be processed is immersed in a SAM solution in which the SAM compound is diluted with water, alcohol (e.g., isopropyl alcohol (IPA), ethanol, methanol), or an organic solvent. In the dry process, a vaporized SAM material is supplied to the substrate to be processed in a vacuum chamber.

[0105] Then, as shown in (b) of FIG. 13, an interface layer IL having hydrophilicity is formed on the hydrophobic surface of the channel layer 101.

[0106] The interface layer IL can be formed by using thermal oxidation or wet chemical oxidation. In some embodiments in which the interface layer IL is formed using wet chemical oxidation, an aqueous solution containing sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM), ozone water, an aqueous solution containing NH4OH and H2O2 (SC1), or an aqueous solution containing HCl and H2O2 (SC2) can be used to form the interface layer IL.

[0107] Then, as shown in (c) of FIG. 13, an inner sidewall 103 having hydrophilicity is formed on the hydrophobic surface of the first semiconductor layer Al.

[0108] The inner sidewall 103 can be formed by a selective deposition process in which a low-k material (low dielectric constant material) is deposited on the hydrophobic surface of the first semiconductor layer Al to form a low-k dielectric layer as the inner sidewall 103.

[0109] Then, as shown in (d) of FIG. 13, a high-k material (high dielectric constant material) can be deposited in the space formed by the interface layer IL and the inner sidewall 103 to form a high-k dielectric layer 104. In this case, since both the interface layer IL and the inner sidewall 103 have hydrophobic surfaces, the high-k dielectric layer 104 covers the surfaces of the interface layer IL and the inner sidewall 103. Then, a metal material is deposited inside the high-k dielectric layer 104 to form a gate layer G (i.e., a metal gate).

[0110] In the GAA device formed by the first fabrication method, as shown in (d) of FIG. 13, the high-k dielectric layer 104 is arranged around the gate layer G in the region between the two channel layers 101; the interface layer IL covers the entire surface of the channel layer 101, and the interface layer IL extends from the region between the high-k dielectric layer 104 and the channel layer 101 to the region between the inner sidewall 103 and the channel layer 101.

[0111] Second fabrication method

[0112] First, as shown in (a) of FIG. 14, the gap b is subjected to a surface pre-cleaning process to make the surface of the first semiconductor layer Al hydrophilic and the surface of the channel layer 101 hydrophobic.

[0113] As shown, by performing the surface pre-cleaning process on the gap b, the silicon oxide SiO2 on the surface of the channel layer 101 and the GeO2 on the surface of the first semiconductor layer A1 can be removed, but other germanium oxides GeOx cannot be removed. In this case, the surface of the first semiconductor layer A1 (GeOx) is hydrophilic, and the surface of the channel layer 101 (Si) is hydrophobic.

[0114] Then, as shown in (b) of FIG. 14, an inner sidewall 103 with hydrophilic property is formed on the surface of the first semiconductor layer A1.

[0115] As shown, by using a selective deposition process, a low-k material (low dielectric constant material) can be deposited on the hydrophilic surface of the first semiconductor layer A1 to form a low-k dielectric layer as the inner sidewall 103.

[0116] Then, a self-assembled monolayer (SAM) is formed on the surface of the inner sidewall 103 to make the surface of the inner sidewall 103 hydrophobic. The SAM is not shown in FIG. 14.

[0117] As shown, a self-assembled monolayer (SAM) is formed on the hydrophilic surface of the inner sidewall 103 to convert the hydrophobic surface of the inner sidewall 103 into a hydrophilic surface. The SAM can refer to the first fabrication method and related technologies, which will not be described here.

[0118] Then, as shown in (c) of FIG. 14, an interface layer IL with hydrophilic property is formed on the surface of the channel layer 101.

[0119] The interface layer IL can refer to the first fabrication method, which will not be described here. Since the inner sidewall 103 has been formed, only the surface of the channel layer 101 inside the inner sidewall 103 is processed to form the interface layer IL.

[0120] Then, as shown in (d) of FIG. 14, since the surface of the interface layer IL is hydrophilic and the surface of the inner sidewall 103 is hydrophobic, a high-k dielectric layer 104 can be selectively formed on the surface of the interface layer IL, but not on the surface of the inner sidewall 103. Then, a metal material is deposited inside the high-k dielectric layer 104 to form a gate layer G (i.e., a metal gate).

[0121] In the GAA device using the second fabrication method, as shown in (d) of FIG. 14, in the region between the two channel layers 101, the interface layer IL and the high-k dielectric layer 104 are both located in the region between the gate layer G and the channel layer 101, and the high-k dielectric layer 104 is located inside the interface layer IL. In the region between the inner sidewall 103 and the channel layer 101, no high-k dielectric layer 104 is located in the interface layer IL.

[0122] Fabrication Method Three

[0123] First, as shown in (a) of FIG. 15, a surface pre-cleaning process is performed on the gap b, so that the surface of the first semiconductor layer A1 is hydrophilic and the surface of the channel layer 101 is hydrophobic.

[0124] By the surface pre-cleaning process on the gap b, the silicon oxide SiO2 on the surface of the channel layer 101 and the GeO2 on the surface of the first semiconductor layer A1 can be removed, but other germanium oxides GeOx cannot be removed. In this case, the surface of the first semiconductor layer A1 (GeOx) is hydrophilic and the surface of the channel layer (Si) is hydrophobic.

[0125] Then, as shown in (b) of FIG. 15, an inner spacer 103 with hydrophilic property is formed on the surface of the first semiconductor layer A1.

[0126] The inner spacer 103 can be formed by a selective deposition process, in which a low-k material (low dielectric constant material) is deposited on the hydrophilic surface of the first semiconductor layer A1 to form a low-k dielectric layer as the inner spacer 103.

[0127] Then, as shown in (c) of FIG. 15, an interface layer IL with hydrophilic property is formed on the surface of the channel layer 101.

[0128] The interface layer IL can be formed by the method one, which will not be described here.

[0129] Then, as shown in (d) of FIG. 15, a high-k material (high dielectric constant material) can be deposited in the space formed by the interface layer IL and the inner spacer 103 to form a high-k dielectric layer 104. In this case, since the interface layer IL and the inner spacer 103 both have hydrophilic surfaces, the high-k dielectric layer 104 will cover the surfaces of the interface layer IL and the inner spacer 103. Then, a metal material is deposited inside the high-k dielectric layer 104 to form a gate layer G (i.e. metal gate).

[0130] In the GAA device formed by the method three, as shown in (d) of FIG. 15, in the region between two channel layers 101, the high-k dielectric layer 104 surrounds the gate layer G; the interface layer IL is on the surface of the channel layer 101, and the region between the inner spacer 103 and the channel layer 101 is not provided with the interface layer IL.

[0131] In addition, as shown in FIG. 16, in the process of forming the fin structure F by patterning in step 10, a dummy gate structure G' and a spacer SP' are formed on the top of the fin structure F, and the spacer SP' is on both sides of the dummy gate structure G'. The dummy gate structure G' can be a poly Si material, and the spacer SP' can be SiO2, etc.

[0132] Of course, a mask layer or the like (not shown in FIG. 16) is also arranged on top of the dummy gate structure G'. In the accompanying drawings of FIGS. 5-15, the film layer structure on top of the fin structure F is omitted and is not shown.

[0133] In some possible implementations, by the above-mentioned manufacturing method one, manufacturing method two and manufacturing method three, the side wall SP' is removed at the same time as the surface pre-cleaning treatment of the gap b removes the silicon oxide on the surface of the channel layer 101. And the side wall SP is reformed on the side of the dummy gate structure G' at the same time as the subsequent manufacturing of the inner side wall 103 (see FIG. 17), that is, the side wall SP and the inner side wall 103 have the same material. In the subsequent process of manufacturing the gate layer G, the dummy gate structure G' is replaced by the top gate structure G1.

[0134] That is, as shown in FIG. 17, in some embodiments of the GAA device, the top gate structure G1 and the side wall SP are formed on top of the fin structure F, the side wall SP is located on both sides of the top gate structure G1 (or the source and drain sides), and the side wall SP and the inner side wall 103 have the same material.

[0135] It should be understood that, compared with the prior art, the inner side wall is manufactured from the outside of the fin structure F, and the etching selectivity of the material of the inner side wall and the top side wall (oxide) needs to be considered. In the manufacturing method of the present application, the material of the inner side wall 103 can be diversified, for example, a low-k material can be selected.

[0136] It should be noted that the GAA device provided by the present application can be manufactured by the above-mentioned manufacturing method, or the related process can be adjusted on the basis of the above-mentioned manufacturing method, which will not be described here.

[0137] The above describes only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip, characterized by The ring gate field effect transistor comprises a fin structure, a first semiconductor layer and a source-drain structure. The ring gate field effect transistor comprises a fin structure, a first semiconductor layer and a source-drain structure. The fin structure is provided with a channel layer and a gate layer. The first semiconductor layer is arranged on the side surface of the fin structure, and the first semiconductor layer continuously covers the end surface of the channel layer and the gate layer. The source-drain structure is grown on the surface of the first semiconductor layer away from the fin structure.

2. The chip according to claim 1, wherein The first semiconductor layer has the same crystal orientation as the end surface of the channel layer in the region covering the end surface of the channel layer.

3. The chip according to claim 1 or 2, wherein The first semiconductor layer has the same or substantially the same crystal orientation on the surface close to the side of the fin structure.

4. The chip according to any one of claims 1-3, wherein The surface close to the side of the fin structure of the first semiconductor layer is a (110) crystal surface. The end surface of the channel layer is a (110) crystal surface.

5. The chip according to any one of claims 1-4, wherein The fin structure further comprises an inner side wall located at both ends of the gate layer. On the side close to the first semiconductor layer, the end surface of the inner side wall is flush or close to flush with the end surface of the channel layer. Or, on the side close to the first semiconductor layer, the end surface of the inner side wall protrudes from the end surface of the channel layer.

6. The chip according to claim 5, wherein The ring gate field effect transistor further comprises a top gate structure and a side wall; the side wall and the top gate structure are both located on the top of the fin structure, and the side wall is located on both sides of the top gate structure. The side wall and the inner side wall are made of the same material.

7. The chip according to claim 5 or 6, wherein The fin structure further comprises an interface layer and a high-k dielectric layer. The high-k dielectric layer surrounds the gate layer. The interface layer is located on the surface of the channel layer, and the interface layer extends from the region between the high-k dielectric layer and the channel layer to the region between the inner side wall and the channel layer.

8. The chip according to claim 5 or 6, wherein The fin structure further comprises an interface layer and a high-k dielectric layer. The interface layer and the high-k dielectric layer are both located in the region between the gate layer and the channel layer, and the interface layer is located on the surface of the channel layer, and the high-k dielectric layer is located on the side of the interface layer away from the channel layer. The region between the inner side wall and the channel layer is not provided with the interface layer and the high-k dielectric layer.

9. The chip according to claim 5 or 6, wherein The fin structure further comprises an interface layer and a high-k dielectric layer. The high-k dielectric layer surrounds the gate layer. The interface layer is located on the surface of the channel layer, and the region between the inner side wall and the channel layer is not provided with the interface layer.

10. The chip according to any one of claims 1-9, wherein The material of the first semiconductor layer is different from the material of the channel layer.

11. The chip of any one of claims 1-10, wherein: a thickness of the first semiconductor layer is in a range from 1 nm to 4 nm.

12. The chip of any one of claims 1-8, wherein: the first semiconductor layer has a second semiconductor layer between the first semiconductor layer and the channel layer; a material of the second semiconductor layer is the same as a material of the channel layer, and a material of the second semiconductor layer is different from a material of the first semiconductor layer.

13. A method of fabricating a chip, characterized by: comprising: forming a fin structure on a substrate, the fin structure including a channel layer and a sacrificial layer; forming a second semiconductor layer and a first semiconductor layer on a side of the fin structure in sequence, wherein the first semiconductor layer and the second semiconductor layer both continuously cover an end surface region of the channel layer and the sacrificial layer; forming a source / drain structure on a side of the first semiconductor layer by epitaxial growth; removing the sacrificial layer in the fin structure to form a gap and expose the second semiconductor layer; removing the second semiconductor layer at both ends of the gap and exposing the first semiconductor layer; forming a gate layer in the gap.

14. The method of claim 13, wherein: before the forming a gate layer in the gap, the method further comprises: forming an inner sidewall on a surface of the first semiconductor layer exposed in the gap, and forming an interface layer on a surface of the channel layer.

15. The method of claim 14, wherein: the forming an inner sidewall on a surface of the first semiconductor layer exposed in the gap, and forming an interface layer on a surface of the channel layer, comprises: first performing a surface pre-cleaning treatment on the gap to make the surface of the first semiconductor layer hydrophilic and the surface of the channel layer hydrophobic; then forming a self-assembled monolayer on the surface of the first semiconductor layer to make the surface of the first semiconductor layer hydrophobic; then forming the interface layer with hydrophilic property on the surface of the channel layer; then forming the inner sidewall with hydrophilic property on the surface of the first semiconductor layer; the forming a gate layer in the gap, comprises: first forming a high-k dielectric layer on a surface of the interface layer and the inner sidewall; then forming a gate layer in an inner region of the high-k dielectric layer.

16. The method of claim 14, wherein: the forming an inner sidewall on a surface of the first semiconductor layer exposed in the gap, and forming an interface layer on a surface of the channel layer, comprises: first performing a surface pre-cleaning treatment on the gap to make the surface of the first semiconductor layer hydrophilic and the surface of the channel layer hydrophobic; then forming the inner sidewall with hydrophilic property on the surface of the first semiconductor layer; then forming a self-assembled monolayer on a surface of the inner sidewall to make the surface of the inner sidewall hydrophobic; then forming the interface layer with hydrophilic property on the surface of the channel layer; the forming a gate layer in the gap, comprises: first forming a high-k dielectric layer on a surface of the interface layer; then forming a gate layer in an inner region of the high-k dielectric layer and the inner sidewall.

17. The method of claim 14, wherein the surface of the first semiconductor layer exposed in the gap forms an inner sidewall and an interface layer on the surface of the channel layer, comprising: pre-cleaning the surface of the gap to make the surface of the first semiconductor layer hydrophilic and the surface of the channel layer hydrophobic; forming the inner sidewall on the surface of the first semiconductor layer with hydrophilic property; forming the interface layer on the surface of the channel layer with hydrophilic property; forming the gate layer in the gap, comprising: forming a high-k dielectric layer on the surface of the interface layer and the inner sidewall; forming the gate layer in the inner region of the high-k dielectric layer.

18. The method of any one of claims 14-17, wherein the method further comprises forming a sacrificial gate structure on the top of the fin structure and sacrificial sidewalls on both sides of the sacrificial gate structure; and wherein the forming the inner sidewall on the surface of the first semiconductor layer exposed in the gap comprises: removing the sacrificial sidewalls to form the inner sidewall on the surface of the first semiconductor layer exposed in the hole and form the sidewalls on both sides of the sacrificial gate structure. A circuit board electrically connected to the chip of any one of claims 1-12. ​ ​ 19. An electronic device, comprising: ​

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