3D inspection of buried regions of interest with reduced milling artefacts

Abstract

A wafer inspection system configured for 3D volume image generation of deeply buried critical layers and a method for 3D volume image generation of deeply buried critical layers are provided. With a system and the method, a 3D volume-inspection of deeply buried critical layers of logic devices is enabled.

Description

[0001] 3D Inspection of buried regions of interest with reduced milling artefacts

[0002] Field

[0003] The present invention relates to a pattern measurement method of semiconductor objects within buried regions of interest within a semiconductor wafer, more particularly, to a method, computer program product and a corresponding semiconductor inspection device for performing a slice- and image method of a buried region of interest within a semiconductor wafer. The method, computer program product and semiconductor inspection device can be utilized for different inspection tasks, such as quantitative metrology, defect detection, process monitoring, or defect review of buried integrated circuits within semiconductor wafers.

[0004] Background

[0005] Semiconductor structures are amongst the finest man-made structures. Semiconductor manufacturing involves precise manipulation, e.g., lithography or etching, of materials such as silicon or oxide at very fine scales in the range of nm. A wafer made of a thin slice of silicon serves as the substrate for microelectronic devices containing semiconductor structures built in and upon the wafer. The semiconductor structures are constructed layer by layer using repeated processing steps that involve repeated chemical, mechanical, thermal and optical processes. Dimensions, shapes and placements of the semiconductor structures and patters are subject to several influences. For example, during the manufacturing of 3D- memory devices, the critical processes are currently etching and deposition. Other involved process steps such as the lithography exposure or implantation also can have an impact on the properties of the elements of the integrated circuits. Therefore, fabricated semiconductor structures suffer from rare and different imperfections. Devices for quantitative metrology, defect-detection or defect review are looking for these imperfections. The semiconductor structures are manufactured from a sequence of layers being parallel to a substrate. During fabrication, semiconductor wafers run through about 1000 process steps or more. Within the semiconductor wafer, about 100 and more parallel layers are formed, comprising transistor layers, the layers of the middle of the line, and the interconnect layers and, in areas of memory, a plurality of 3D arrays of memory cells. For example, in a logic type wafer sample, the critical structures within the critical layers are buried below dozens to hundreds of further layers, for example interconnection or metal layers or isolating layers. Within these layers, metal lines are running parallel and metal vias run perpendicular to the layers. The critical structures in the lower, critical layers comprise features of the critical dimension, which are crucial for a performance of a logic chip. For example, the minimum feature size or critical dimension is below 10nm, for example 7nm or 5nm, and is approaching feature sizes below 3 nm or even less in near future. With FinFets and variations thereof, the complexity and dimensions of the critical layers is growing into the 3rddimension and of complex 3D-structures are built within. For example, within FinFets according to gate-all-around technology, tiny stacks of wires or sheets are stacked on top of each other. For example, stacked FinFets comprise several gate layers. It is therefore a need for measuring the shape, dimensions and orientation of the three-dimensional (3D) features and patterns within the deeply buried critical layers.

[0006] A common way to generate 3D tomographic data from semiconductor samples on nm scale is the so-called slice- and image-method obtained for example by a dual beam device. A slice- and image-method is described in WO 2020 / 244795 A1 . According to the method of the WO 2020 / 244795 A1 , a 3D volume inspection is obtained at an inspection sample extracted from a semiconductor wafer. In another example, the slice and image method is applied under a slanted angle into the surface of a semiconductor wafer, as described in WO 2021 / 180600 A1 . According to this method, a 3D volume image of an inspection volume is obtained by slicing and imaging a plurality of cross-section surfaces within the inspection volume. For a precise measurement, a large number N of cross-section surfaces in the inspection volume is generated, with the number N exceeding 100 or even more image slices. For example, in a volume with a lateral dimension of 5pm and a slicing distance of 5nm, 1000 slices are milled and imaged. With the slice-and image method and corresponding apparatus, shape, dimension and orientation of the three-dimensional (3D) features and patterns can be measured. However, the slice-and image method according to the prior art is not well suited for the deeply buried critical layers within a logic device. For example, the many metal layers above the deeply buried critical layers may deteriorate the milling of cross-sections with the FIB. It is therefore a need for an improved slice-and image method for deeply buried critical layers within logic devices.

[0007] US 2017 / 0 138 725 A1 discloses a pattern measurement method and a device for achieving highly accurate measurement in the depth direction of a pattern. The method involves a focused ion beam irradiated to form an inclined surface in a sample area; a field of view of a SEM set to include the boundary between the inclined surface and a sample surface; and an image of the field of view obtained on the basis of a detection signal. Such an acquired image is used to specify a first position, the boundary between inclined surface and noninclined surface, and a second position, the position of a desired deep hole or deep groove positioned within the inclined surface. The pattern dimension in a height direction is determined on the basis of the distance in the sample surface direction between the first position and second position and the angle of the inclined surface.

[0008] US 2022 / 0 392 793 A1 relates to dual beam devices and three-dimensional circuit pattern inspection techniques by cross sectioning of inspection volumes with large depth extension exceeding 1 pm below the surface of a semiconductor wafer, as well as to methods, computer program products and apparatuses for generating 3D volume image data of a deep inspection volume inside a wafer without removal of a sample from the wafer. The disclosure further relates to 3D volume image generation and cross section image alignment methods utilizing a dual beam device for three-dimensional circuit pattern inspection.

[0009] The objects are solved by the invention. The invention is described by the claims, details are provided by the embodiments and examples.

[0010] The present patent application claims the priority of German patent application No 10 2024 205 636.7 filed on 19 June 2024, the disclosure of which in the full scope thereof is incorporated in the present patent application by reference.

[0011] According to a first embodiment, a method of volume inspection of deeply buried critical layers within a semiconductor wafer is given. The method is comprising a step of milling a first, coarse cross-section at a first milling angle GF1 with respect to a surface of a wafer through a stack of interconnection layers. The method is comprising a step of milling at least a first fine cross-section through the deeply buried inspection volume at a second milling angle GF2 with respect to a surface of a wafer, wherein the second milling angle GF2 is different to the first milling angle GF1 . During the step of milling at least a first fine crosssection, a first edge at the intersection of the first coarse cross-section and the first fine cross-section is formed. The method is further comprising a step of acquiring at least a first image of the first fine cross-section, and a step of reconstructing a three-dimensional (3D) volume-image within the inspection volume. In an example, the step of reconstructing the three-dimensional (3D) volume-image comprises a method selected from the group of methods including image processing, image alignment, depth extrapolation and pixel interpolation.

[0012] The first milling angle GF1 is for example between 20° and 40°, but other, for example shallower angles are possible as well. The second milling angle GF2 is larger than the first milling angle GF1 , for example with a difference dGF = GF2 - GF1 of dGF = 2° or more. For example, the difference dGF is selected between 2° and 20°, for example between 2° and 10°. For example, a difference angle dGF = 5° is selected. The stack of interconnection layers typically has a thickness of several 100nm and more, for example 1 pm or even more. The critical layers within the inspection volume are thus buried under a thick stack of interconnection layers. With the sequence of milling steps with different milling angles GF1 and GF2, and with forming the first edge between the coarse and the fine cross-section, a milling depth for the milling of the fine cross-sections is reduced and a surface quality of the fine cross-section through the buried intersection volume is improved.

[0013] In an example, the method is further comprising milling at least a second fine cross-section through the buried inspection volume at the second milling angle GF2 and acquiring at least a second image of the second fine cross-section. By repeating of milling and imaging of further fine cross-sections, a three-dimensional (3D) volume image of the deeply buried inspection volume is obtained with high precision and high accuracy.

[0014] In an example, the method is further comprising a step of determining a surface quality of a fine cross-section and comparing the quality of a fine cross-section with a predetermined threshold. If a surface quality exceeds the threshold, the method is further comprising milling at least a second coarse cross-section at a first milling angle GF1 through the stack of interconnection layers, thereby forming a third edge with a previously formed fine crosssection through the buried inspection volume. The position of the second coarse crosssection can be adjusted such that the third edge is at the upper position of the deeply buried inspection volume, such that a cross-section of the interconnection layers within the fine cross-section is minimized. The step of milling further coarse cross-section at angle GF1 can be repeated as often as required for obtaining the desired surface quality of a fine crosssection as a result of milling under angle GF2. In an example, the step of reconstructing the three-dimensional (3D) volume-image is comprising reconstructing a 3D volume-image of a 3D-feature within the inspection volume. The step of reconstructing the 3D volume-image of a 3D-feature can be assisted by CAD- data of the volume of interest, for example of CAD data comprising a representative model of the 3D-feature of interest. For example, the 3D-feature is a repetitive 3D-feature within the inspection volume, and a virtual 3D-feature is computed from a plurality of intersections through the plurality of repetitive 3D-features at different depth according to the slanted milling angle GF2. Examples of 3D-feature can be FinFets, Complementary Field-Effect Transistors, a Gate-AII-Around Field-Effect Transistors, or a Field-Effect Transistors comprising Nanosheets or Nanowires.

[0015] In a second embodiment, a wafer inspection system for volume inspection of deeply buried critical layers is provided. The wafer inspection system comprises a dual beam system with a first charged particle or FIB column for milling of cross-sections and a second, charged particle beam imaging system for high-resolution imaging of cross-sections. The second charged particle beam imaging system can be a scanning electron microscope of a focused ion beam system utilizing for example Helium or Neon ions. The wafer inspection system comprises a wafer support table connected to a stage and an operation control unit. The operation control unit is comprising at least one processing engine and a memory or storage for storing software instructions, which, when executed by the processing engine, are causing the wafer inspection system to perform any of the methods according to the first embodiment. In an example, the wafer support table connected to a stage comprises a tilt axis for adjusting a tilt angle of the wafer support table with respect to the axis of the FIB column for adjusting the milling angle GF between GF1 and GF2.

[0016] With the method and the wafer inspection system, a high precision volume inspection of deeply buried inspection volumes within semiconductor wafers is enabled. For example, buried features of GAA-FinFets (Gate all around FinFets) can be inspected with high resolution in a semiconductor wafer even after at least some interconnection layers are formed thereon. Deeply buried inspections volumes can be inspected with the slice-and image method without any negative impact of milling through at least some interconnection layers. With the first milling of a coarse cross section at a first, slanted angle GF1 , a milling depth through the buried inspection volume is reduced and milling artefacts are reduced or eliminated.

[0017] The method and the wafer inspection system is described at the example of logic structures, for example wafers comprising processors, comprising a stack of interconnection layers covering the critical layers with the features of interest of a wafer inspection task. The method and the wafer inspection system is however not limited to logic structures, but can be applied to other structures as well, for example DRAM structures.

[0018] The invention described by examples and embodiments is not limited to the embodiments and examples but can be implemented by those skilled in the art by various combinations or modifications thereof. The present invention will be even more fully understood with reference to the following drawings:

[0019] Figure 1 shows an illustration of a wafer inspection or metrology system for 3D volume inspection with a dual beam device.

[0020] Figure 2 is an illustration of the slice-and image method of a volume inspection in a wafer.

[0021] Figure 3 is an illustration of a cross section through a logic structure

[0022] Figures 4a-h illustrate an improved method according to an embodiment

[0023] Figure 5 illustrates improved method steps according to an embodiment

[0024] Figure 6 shows an inspection system according to an embodiment

[0025] Figures 7a-d illustrate an improved wafer inspection system according to an embodiment and a method of operation thereof Throughout the figures and the description, same reference numbers are used to describe same features or components.

[0026] Recently, for the investigation of 3D inspection volumes in semiconductor wafers, a slice and imaging method has been proposed, which is applicable to inspection volumes inside a wafer. Thereby, a 3D volume image is generated at an inspection volume inside a wafer in the so called “wedge-cut” approach or wedge-cut geometry, without the need of a removal of a sample from the wafer. The slice and image method is applied to an inspection volume with dimensions of few pm, for example with a lateral extension of 5pm to 10pm in wafers with diameters of 200mm or 300mm. The lateral extension can also be larger and reach up to few 10ths of micrometers. A V-shaped groove or edge is milled in the top surface of an integrated semiconductor wafer to make accessible a cross-section surface at an angle to the top surface. 3D volume images of inspection volumes are acquired at a limited number of inspection sites, for example representative sites of dies, for example at process control monitors (PCM), or at sites identified by other inspection tools. The slice and image method will destroy the wafer only locally, and other dies may still be used, or the wafer may still be used for further processing. The methods and inspection systems according to the 3D Volume image generation are described in WO 2021 / 180600 A1 , which is fully incorporated herein by reference. An example of a wafer inspection system 1000 for 3D volume inspection is illustrated in Figure 1. The wafer inspection system 1000 is configured for a slice and imaging method under a wedge cut geometry with a dual beam device 1 . For a wafer 8, several inspection sites, comprising inspection sites 6.1 and 6.2, are defined in a location map or inspection list generated from an inspection tool or from design information. The wafer 8 is placed on a wafer support table 15. The wafer support table 15 is mounted on a stage 155 with actuators and position control. Actuators and means for precision control for a wafer stage such as Laser interferometers are known in the art. A control unit 16 is configured to control the wafer stage 155 and to adjust an inspection site 6.1 of the wafer 8 at the intersection point 43 of the dual-beam device 1 . The dual beam device 1 is comprising a FIB column 50 with a FIB optical axis 48 and a charged particle beam (CPB) imaging system 40 with optical axis 42. At the intersection point 43 of both optical axes of FIB and CPB imaging system, the wafer surface 55 is arranged at a slant angle GF to the FIB axis 48. FIB axis 48 and CPB imaging system axis 42 include an angle GFE, and the CPB imaging system axis forms an angle GE with the normal to the wafer surface 55. In the coordinate system of figure 1 , the normal to the wafer surface 55 is given by the z-axis. The focused ion beam (FIB) 51 is generated by the FIB-column 50 and is impinging under angle GF on the surface 55 of the wafer 8. Slanted cross-section surfaces are milled into the wafer by ion beam milling at the inspection site 6.1 under approximately the slant angle GF. In the example of figure 1 , the slant angle GF is approximately 30°, but other angles GF, for example between GF = 20° and GF = 60° are possible as well. The actual slant angle of the slanted cross-section surface can deviate from the slant angle GF by up to 1° to 4° due to the beam divergency of the focused ion beam, for example a Gallium-lon beam. With the charged particle beam imaging system 40, inclined under angle GE to the wafer normal, images of the milled surfaces are acquired. In the example of Figure 1 , the angle GE is about 15°. However, other arrangements are possible as well, for example with GE = GF, such that the CPB imaging system axis 42 is perpendicular to the FIB axis 48, or GE = 0°, such that the CPB imaging system axis 42 is perpendicular to the wafer surface 55.

[0027] During imaging, a beam of charged particles 44 is scanned by a scanning unit of the charged particle beam imaging system 40 along a scan path over a cross-section surface of the wafer at inspection site 6.1 , and secondary particles as well as scattered particles are generated. Particle detector 17 collects at least some of the secondary particles and scattered particles and communicates the particle count with a control unit 19. Other detectors for other of interaction products may be present as well. Control unit 19 is in control of the charged particle beam imaging column 40 and of FIB column 50 and connected to a control unit 16 to control the position of the wafer 8 mounted on the wafer support table 15 via the wafer stage 155. Control unit 19 communicates with operation control unit 2, which triggers placement and alignment for example of inspection site 6.1 of the wafer 8 at the intersection point 43 via wafer stage movement and triggers repeatedly operations of FIB milling, image acquisition and stage movements.

[0028] Each new intersection surface is milled by the FIB beam 51 , and imaged by the charged particle imaging beam 44, which is for example scanning electron beam or a Helium-lon- beam of a Helium ion microscope (HIM).

[0029] Figure 2 illustrates the wedge cut geometry at the example of a 3D-memory stack. Figure 2 illustrates the situation, when the surface 52 is the actual cross-section surface after milling by FIB 51 . The actual cross-section surface 52 is scanned for example by SEM beam 44, which is in the example of Figure 2 arranged at normal incidence to the wafer surface 55, and a high-resolution cross-section image slice is generated. The subsequent cross-section surfaces 53.1 ...53.N are subsequently milled with a FIB beam 51 at the angle GF. Each cross-section image slice comprises first cross-section image features, formed by intersections with high aspect ratio (HAR) structures or vias (for example first cross-section image features of HAR-structures 4.1 , 4.2, and 4.3) and second cross-section image features formed by intersections with layers L.1 ... L.M, which comprise for example SiO2, SiN- or Tungsten lines. Some of the lines are also called “word-lines”. The maximum number M of layers is typically more than 50, for example more than 100 or even more than 200. The HAR-structures and layers extend throughout most of the volume in the wafer but may comprise gaps. The HAR structures typically have diameters below 100nm, for example about 80nm, or for example 40nm. The cross-section image slices contain therefore first cross-section image features as intersections or cross-sections of the HAR structures at different depths (Z) at the respective XY-location. In case of vertical memory HAR structures of a cylindrical shape, the obtained first cross-sections image features are circular or elliptical structures at various depths determined by the locations of the structures on the sloped cross-section surface 52. The memory stack extends in the Z-direction perpendicular to the wafer surface 55. The thickness d or minimum distances d between two adjacent crosssection image slices is adjusted to values typically in the order of few nm, for example 30nm, 20nm, 10nm, 5nm, 4nm or even less. Once a layer of material of predetermined thickness d is removed with FIB, a next cross-section surface 53. i... 53. J is exposed and accessible for imaging with the charged particle imaging beam 44. During repeated milling an imaging, a plurality of cross sections is formed, and a plurality of cross section images are obtained, such that an inspection volume 160 of size LX x LY x LZ is properly sampled and a 3D volume image can be generated. Thereby, the damage to the wafer is limited to the inspection volume 160 plus a damaged volume in y-direction of length LYO. With an inspection depth LZ about 10pm, the additional damage volume in y-direction is typically limited to below 20pm.

[0030] A memory stack shows a homogeneous material distribution with similar features sizes throughout the inspection volume 160. Therefore, during the milling operation, smooth cross section surfaces are generated, which do not show a so-called curtaining effect. Figure 3 illustrates an example of a logic chip. In a logic chip, the critical layers 73 are buried below a stack of layers 75 comprising metal and isolating structures. The critical layers 73 comprise for example doped areas within the bulk silicon 71 or structures of FinFets. The stack of layers 75 comprises metal interconnections of increasing dimension from lower layer 75.1 to lop layer 75.2, including top contact layer 77 for external bonding contact. During manufacturing, the wafer may further be covered by a protection layer 79. The dimensions of the upper interconnection layers 75 or the contact layer 77 are at least two orders of magnitude larger compared to the critical dimensions within the buried critical layers 73. During milling through interconnection layers 75, the large metal structures may generate inhomogeneities within the cross-section surfaces and milling artefacts from the interconnection layers 75 may superpose the tiny features of the buried critical layers 73. Figure 4 illustrates a method of slice- and imaging for 3D volume image generation of deeply buried critical layers 73 according to a first embodiment. In a first step (Figure 4a), a first, coarse cross-section surface 81 .1 through the surface 55 of the wafer 8 is milled by FIB beam 51 under first milling angle GF1 . The milling of the first or coarse cross-section surface 81 .1 is continued until the buried region of interest ROI is reached. The buried region of interest ROI is also described as the inspection volume 160, which is comprising the critical layers 73. The depth of the inspection volume 160 with respect to the surface can be up to several 100nm. For example, in a logic device, the inspection volume 160 comprising the critical layers 73 can be buried under about 50 to 100 interconnection layers, each with a thickness of several 10nm up to 500nm. In an example, with the first coarse cross-section surface 81.1 , the buried region of interest ROI or inspection volume 160 comprising the critical layers 73 is intersected. Whether the milling depth is large enough and the ROI comprising the critical layers 73 is intersected can be verified by obtaining an electron beam image during the coarse milling step.

[0031] In a second step (Figure 4b), the first fine cross-section surface 53.1 is milled through the region of interest (ROI) by FIB 51 at a second milling angle GF2. The second milling angle GF2 is larger than the first milling angle GF1 and a first edge 83.1 is generated between the coarse cross-section surface 81 .1 and the first fine cross-section surface 53.1 . Thereby, the fine cross-section surfaces 53 are milled though a smaller volume, which is not comprising the stack of interconnection layers 75. Thereby, milling artefacts are reduced. The difference dGF between second angle GF2 and first angle GF1 , dGF = GF2 - GF1 , is typically selected between 2° and 10°, but larger angles up to 20° are possible as well. In a third step (Figure 4c), an image of the first fine cross-section surface 53.1 is acquired by scanning electron beam 44.

[0032] In an example, second and third step are repeated (Figure 4d and Figure 4e), and a plurality of subsequent fine cross section surfaces 53.2 are formed by ion beam milling under the second angle GF2, and a plurality of cross-section images are acquired by scanning electron beam 44. During the sequence of milling by FIB 51 , focused ion beam 51 is moved relative to the wafer 8 in y-direction (see figure 4d). Thereby, the edge 83.2 is moving in y- direction and - in the coordinate system of figure 4d - in negative z-direction.

[0033] During milling under angle GF2, the cross section surfaces 53.2 increase in size and requires milling through an increasing distance though the stack of interconnection layers 75. In an example, the first step of milling under angle GF1 is repeated and a second coarse crosssection surface 81.2 is milled under angle GF1 . Thereby, a further edge 83.3 is generated at a depth level of the region of interest (ROI, 160). Thereby, the increased distance though the stack of interconnection layers 75 is reduced (Figure 4f). Second and third step are then repeated (Figure 4g and Figure 4h) with reduced milling artefacts.

[0034] Figure 5 illustrates the method steps according to an example of the first embodiment. In Step SO, a measurement site 6 on a wafer 8 is selected and adjusted at the intersection point 43 by stage 155.

[0035] In step S1 , a first coarse cross-section 81 is generated at angle GF1 . Focus ion beam 51 and wafer surface 55 are adjusted to form angle GF1 between focused ion beam 51 and wafer surface 55. For example, wafer stage 155 is tilted such that angle GF1 is adjusted. Angle GF1 can be between 20° and 40°, for example 30° or 36°. The first coarse crosssection 81 is generated by FIB milling until the buried critical layers 73 within the region of interest (ROI) are reached (see Figure 4a).

[0036] In step S2, the slice-and image method is performed for generating a 3D volume image of the region of interest (ROI) comprising a segment of the buried critical layer 73.

[0037] In a first sub-step S2.1 , a fine cross section surface 53 is formed by ion beam milling under angle GF2 with respect to the wafer surface 55. The angle FG2 between wafer surface 55 and focus ion beam is selected to be larger than the first angle GF1 .For example, angle GF2 exceeds angle GF1 by three degree or more, for example five degree, for example eight degree.

[0038] In a second sub-step S2.2, an image is acquired of the cross-section surface 53 by scanning electron beam 44. In an example, the image is acquired by scanning electron beam 44 utilizing a first detector 17.1 for collecting secondary electrons. In an example, the image is acquired by scanning electron beam 44 utilizing a second detector 17.2 for collecting backscattered electrons. In an example, two images are acquired by scanning electron beam 44 utilizing the first and the second detector 17.1 and 17.2 for collecting secondary and backscattered electrons in parallel.

[0039] Steps S2.1 and S2.2 are repeated until a predetermined number of cross-section image slices of the inspection volume is obtained. A predetermined number can be any number between two and several hundreds. With increasing number of fine cross-sections and crosssection image slices acquired therefrom, a 3D-volume image of an inspection volume 160 can be obtained with high resolution.

[0040] In step Q1 , it is determined whether the predetermined number of cross-section image slices is reached. In an example, step Q1 comprises determining whether a fine cross-section 53.2 is deteriorated by milling artefacts from the interconnection layers. With each milling of a fine cross sections, a new milling edge, for example milling edge 83.2 is formed. The milling edge 83.2 is formed between the coarse cross section 81 .1 and the fine cross section 53.2 (see figure 4d and 4e). With increasing number of milling steps at angle GF2, the milling edge 83.2 moves in direction of the wafer surface 55 and the fine cross-sections comprise increasing amount of cross-sections with the interconnection layers 75. These of crosssections with the interconnection layers 75 can form milling artefacts such as an uneven topography. Such an effect is known as curtaining. For example, interconnection layers 75 may comprise metal lines with different milling etch rate compared to silicon compounds of the critical layers 73, and therefore, shadow grooves are formed through the critical layers 73. For example, during milling with FIB 51 , a surface quality typically deteriorates with increasing milling depth, and milled surfaces might slope away from an ideal planar crosssection. For example, during step Q1 , a surface quality of a fine cross-section 53 is evaluated and compared to a predetermined threshold. A surface quality can for example be a noise level or a topography contrast due to curtaining, or a surface curvature. If the surface quality exceeds the predetermined threshold, the iteration of step S2 is interrupted. The predetermined threshold can for example be determined by a user input according to a resolution requirement.

[0041] In Step Q2, it is determined whether the inspection volume is sufficiently covered by cross section image slices and a 3D volume image of a feature of interest can be derived from the acquired image data. If not, step S1 is repeated to mill a second coarse cross section at milling angel GF1 (see Figure 4f), followed by another sequence of step S2 (see figure 4g and 4h).

[0042] After the inspection volume is sufficiently covered by cross section image slices, the three- dimensional (3D) volume-image is generated and analyzed in step S3. During the generation of the three-dimensional (3D) volume-image from the plurality of cross section image slices, for example image processing, image alignment, depth extrapolation and pixel interpolation are applied. For example, step S3 comprises reconstructing a 3D volume-image of a 3D- feature within the inspection volume 160. For example, the reconstruction of a 3D-feature is assisted by CAD-data of the volume of interest 160. A three-dimensional (3D) features can be a FinFet or variations of FinFets such as Complementary Field-Effect Transistors, Gate- All-Around Field-Effect Transistors, Nanosheets or Nanowires. In an example, a 3D-feature comprised within the inspection volume (160) is reconstructed from a single first fine crosssection surface 53.1 . For example, if the 3D-feature is a repetitive feature within the inspection volume (160), and a single, virtual 3D-feature can be computed from a plurality of intersections through the plurality of repetitive 3D-features at different depth, given by the slanted milling angle GF2. Generally, similar techniques as known from exploration can be applied.

[0043] In Step S4, the 3D volume image data is analyzed for example by methods of pattern recognition and feature extraction, comparison to CAD data or comparison to a reference 3D volume image data. Such methods may comprise analytical or numerical methods, image processing and filtering operations, and generally machine learning techniques. As a result, a length, an area or a volume of a 3D-feature can be determined.

[0044] Figure 6 illustrates an example of a wafer inspection system 1000 according to the second embodiment. The wafer inspection system is configured for executing the method according to the first embodiment. The wafer inspection system 1000 is comprising a dual beam system 1 . A dual beam system is illustrated in figure 1 with more detail and reference is made to the description of figure 1 . Essential features of a dual beam system 1 are a first charged particle or FIB column 50 for milling and a second, charged particle beam imaging system 40 for high-resolution imaging of cross section surfaces. A dual beam system 1 comprises at least one detector 17 for detecting secondary particles, which can be electrons or photons. A dual beam system 1 further comprises a wafer support table 15 configured for holding during use a wafer 8. The wafer support table 15 is connected to a stage 155 and is position controlled by a stage control unit 16, which is connected to the control unit 19 of the dual beam system 1 . The stage is at least a five-axis stage capable of lateral movement and rotation in x-y-plane of the coordinate system of figure 6, and of at least one tilt or rotation around the x- or y-axis. The control unit 19 is configured with memory and logic to control operation of the dual beam system 1 . The wafer inspection system 1000 is further comprising an operation control unit 2. The operation control unit 2 comprises at least one processing engine 201 , which can be formed by multiple parallel processors including GPU processors and a common, unified memory. The operation control unit 2 further comprises an SSD memory and disk memory or storage 203 for storing a plurality of cross section images. The operation control unit 2 further comprises a user interface 205, comprising the user interface display 400 and user command devices 401 , configured for receiving input from a user. The operation control unit 2 further comprises a memory or storage 219 for storing process information of the image generation process of the dual beam device 1 and for storing software instructions, which can be executed by the processing engine 201 . The software instructions comprise software for performing, when executed, a method according to the first embodiment.

[0045] The operation control unit 2 is further connected to an interface unit 231 , which is configured to receive further commands or data, for example CAD data, from external devices or a network. The interface unit 231 is further configured to exchange information, for example receive instructions from external devices or provide measurement results to external devices or store a set of training data or a trained machine learning algorithm.

[0046] The processing engine 201 is configured to consider process information of the image generation process with for example a dual beam device 1 , including for example selected imaging parameters of the dual beam system. The imaging parameters can for example be selected by a user according to a required speed or accuracy of the measurement task.

[0047] The inspection system 1000 is configured to receive user information, for example comprising CAD information of the semiconductor object of interest and the selection of an inspection site. The inspection system 1000 can be configured to combine the user information with process information of the image generation process. The processing engine 201 is further configured to execute the method steps SO to S4 of the method described above. The processing engine 201 is thereby configured to display information via the user display 400 and to receive user input via user interface 401 . According to the second embodiment, a wafer inspection system 1000 is configured for 3D volume image generation of deeply buried critical layers 73.

[0048] Figure 7 illustrates an example of the wafer inspection system 1000 configured for 3D volume image generation of deeply buried critical layers 73. In this example, the imaging charged particle beam column is arranged vertically with the imaging electron beam (not shown) parallel to the z-direction of the coordinate system of Figure 7. Stage 155 comprises a tilt axis for adjusting a tilt angle of wafer support table 15 with respect to the focuses ion beam axis for adjusting the milling angle GF between GF1 and GF2. During step S1 , the wafer support table 15 is tilted via stage 155 by tilt angle 157.1 corresponding to dGF of for example five degree. Thereby, a first milling angle GF1 is adjusted and the first, coarse cross section surface 81 is milled at angle GF1 between wafer surface and first, coarse cross section surface 81 (Figure 7a, b). After the coarse milling step S1 , the wafer table 15 is tilted via stage 155 by tilt angle 157.2 of for example minus five degree, such that for example the wafer surface 55 is perpendicular to z-axis or perpendicular to the scanning electron beam 44. In this configuration, the steps S2 are performed, including a sequence of milling fine cross-sections at the second angle GF2 > GF1 .

[0049] With the wafer inspection system 1000 configured for 3D volume image generation of deeply buried critical layers 73 and the method for 3D volume image generation of deeply buried critical layers 73, logic devices are made accessible for 3D volume image generation.

[0050] The invention is not limited to the examples and embodiments and can be implemented by those skilled in the art by various combinations or modifications.

[0051] A list of reference numbers is provided: 1 Dual Beam system

[0052] 2 Operation Control Unit

[0053] 4 first cross section image features

[0054] 6 measurement sites

[0055] 8 wafer

[0056] 15 wafer support table

[0057] 16 stage control unit

[0058] 17 Secondary or backscattered electron detector

[0059] 19 Control Unit

[0060] 40 charged particle beam (CPB) imaging system

[0061] 42 Optical Axis of imaging system

[0062] 43 Intersection point

[0063] 44 Imaging charged particle beam

[0064] 48 Fib Optical Axis

[0065] 50 FIB column

[0066] 51 focused ion beam

[0067] 52 actual cross section surface

[0068] 53 cross section surface

[0069] 55 wafer top surface

[0070] 71 bulk silicon

[0071] 73 critical layers

[0072] 75 stack of interconnection layers

[0073] 77 contact layer

[0074] 79 cover layer

[0075] 81 coarse cross section

[0076] 83 milling edge

[0077] 155 wafer stage

[0078] 157 tilt angle 160 inspection volume

[0079] 201 processing engine

[0080] 203 memory

[0081] 205 User interface 219 memory

[0082] 231 Interface unit

[0083] 400 user interface display

[0084] 401 user command devices

[0085] 1000 Wafer inspection system

Claims

CLAIMS1 . A method of volume inspection of deeply buried critical layers (73) within a semiconductor wafer (8), comprising:- milling a first, coarse cross-section (81 .1 ) at a first milling angle GF1 with respect to a surface (55) of a wafer (8) through a stack of interconnection layers (75),- milling at least a first fine cross-section (53.1) through the buried inspection volume (160) at a second milling angle GF2 with respect to a surface (55) of a wafer (8), wherein the second milling angle GF2 is larger than the first milling angle GF1 , thereby forming a first edge (83.1) at the intersection of the first coarse cross-section(81.1) and the first fine cross-section (53.1 ),- acquiring at least a first image of the first fine cross-section (53.1 ),- reconstructing a three-dimensional (3D) volume-image within the inspection volume (160).

2. The method according to claim 1 , further comprising milling at least a second fine cross-section (53.2) through the buried inspection volume (160) at the second milling angle GF2 and acquiring at least a second image of the second fine cross-section(53.2).

3. The method according to claim 3, further comprising a step of determining a surface quality of a fine cross-section (53, 53.1 , 53.2, 53.3) and comparing the quality of a fine cross-section (53, 53.1 , 53.2, 53.3) with a predetermined threshold.

4. The method according to any of the claims 1 to 3, further comprising milling at least a second coarse cross-section (81 .2) at a first milling angle GF1 through the stack of interconnection layers (75), thereby forming a third edge (83.3) with a fine cross-section (53.2) through the buried inspection volume (160).

5. The method according to any of the claims 1 to 4, wherein the step of reconstructing the three-dimensional (3D) volume-image comprises a method selected from the group of methods including image processing, image alignment, depth extrapolation and pixel interpolation.

6. The method according to any of the claims 1 to 5, wherein the step of reconstructing the three-dimensional (3D) volume-image is comprising reconstructing a three- dimensional (3D) volume-image of a 3D-feature within the inspection volume (160).

7. The method according to claim 6, wherein the step of reconstructing the three- dimensional (3D) volume-image of a 3D-feature is assisted by CAD-data of the volume of interest (160).

8. The method according to any of the claims 6 to 7, wherein the 3D-feature is a repetitive 3D-feature within the inspection volume (160), and a virtual 3D-feature is computed from a plurality of intersections through the plurality of repetitive 3D- features at different depth according to the slanted milling angle GF2.

9. The method according to any of the claims 6 to 8, wherein the 3D-feature is comprising at least one of a FinFet, a Complementary Field-Effect Transistors, a Gate-AII-Around Field-Effect Transistors, or a Field-Effect Transistors comprisingNanosheets or Nanowires.

10. The method according to any of the claims 1 to 9, wherein the difference dGF between second angle GF2 and first angle GF1 , dGF = GF2 - GF1 , is selectedbetween 2° and 20°, for example between 2° and 10°.11 . A wafer inspection system (1000) for volume inspection of deeply buried critical layers (73), comprising- a dual beam system (1 ) comprising a first charged particle or FIB column (50) for milling of cross-sections (53) and a second, charged particle beam imaging system (40 for high-resolution imaging of cross-sections (53),- a wafer support table (15) connected to a stage (155),- an operation control unit (2), comprising at least one processing engine (201 ) and a memory or storage (219) for storing software instructions, which, when executed by the processing engine (201 ), are causing the wafer inspection system (1000) to perform any of the methods according to any of the claims 1 to 10.

12. The wafer inspection system (1000) according to claim 11 , wherein the wafer support table (15) connected to stage (155) comprises a tilt axis for adjusting a tilt angle(157.1 , 157.2) of wafer support table (15) with respect to the axis (48) of the FIB column (50) for adjusting the milling angle GF between GF1 and GF2.

Images