Semiconductor component with shielding

Abstract

The invention relates to a semiconductor component, in particular a V-trench MISFET (100), comprising a substrate (102), a drift region (104), a p-body region (105) arranged thereabove, and a source region (106), wherein the source region (106) comprises a trench structure (107) extending from said source region through the p-body region (105) into the underlying drift region (104) and having a plurality of V-shaped trenches (107a), preferably arranged parallel, and wherein a first p-doped implantation region (110) is formed in the bottom region of an associated trench (107a).

Description

[0001] Description

[0002] Semiconductor component with shielding

[0003] Technical field

[0004] The invention relates to a semiconductor device, in particular a trench-gate power MISFET based on silicon carbide (SiC).

[0005] State of the art

[0006] Silicon carbide (SiC) trench-gate power MISFETs (metal insulator-semiconductor field-effect transistors) have, compared to planar MISFETs, in addition to a reduced cell pitch, the advantage that their trench sidewalls can be aligned along non-polar crystal faces using special etching processes, thereby reducing the channel resistance and thus the area-specific resistance RDS. on *A can be achieved in the conducting state of a MISFET.

[0007] A challenge with SiC trench MISFETs is combining good conduction characteristics with good short-circuit withstand capability. Typically, the current flowing from source to drain through the device during a short circuit is significantly higher than during normal conduction. One approach to achieving good short-circuit withstand capability is to limit the current density during a short circuit to the lowest possible values. This limits the power dissipation density and the heating rate of the device, and allows for timely shutdown before damage or destruction. A known method for reducing the current density during a short circuit is the implantation of a p++-doped region in the trench bottom, which is connected to the source potential.The resulting space charge region, which spreads in an n-drift region in the event of a short circuit, leads, with correct design of the p++ region, to the constriction of the current path between two trenches and thus to the limitation of the short-circuit current density by the so-called JFET effect.

[0008] In a V-trench MISFET semiconductor device with a flank angle a < 90°, the cell pitch increases significantly with decreasing steepness of the trench sidewall, thereby weakening the JFET effect occurring in neighboring p-doped areas in the bottom region of the trench and making a reduction of the short-circuit current density due to the JFET effect difficult or no longer acceptable.

[0009] Disclosure of the invention

[0010] In a first aspect, the invention relates to a semiconductor device, in particular a V-trench MISFET, comprising a substrate, in particular made of silicon carbide, a drift region, a p-body region arranged above it, and a source region, wherein the source region has a trench structure extending from it through the p-body region into the underlying drift region with several, preferably parallel, V-shaped trenches, and wherein a first, preferably highly p-doped, implantation region is formed in the bottom region of each trench, and wherein a second, preferably highly p-doped, implantation region is formed on one side of a side wall of each trench to enhance a JFET effect in the drift region between two adjacent V-shaped trenches.

[0011] The design according to the invention enables an enhancement of the JFET effect that develops between two adjacent trenches, thereby limiting the current in the event of a short circuit or achieving a lower short-circuit current density. In particular, the second implantation area reduces the distance between the implantation areas of two adjacent V-shaped trenches in the semiconductor device in a direction parallel to the cell pitch, thereby enhancing the JFET effect.

[0012] In a preferred embodiment, the second implantation area, or the second p++ area, extends along the entire length of the side wall of the respective V-shaped trench to the first implantation area. Advantageously, the second implantation area extends from a surface of the pBody area along one side of a side or flank of the respective V-shaped trench to the bottom of the trench. The second implantation area is further advantageously located directly adjacent to the first implantation area. It is also advantageous that the first and second implantation areas of a respective V-shaped trench are configured as a single, continuous area.

[0013] In a preferred embodiment, the dopant concentration and / or doping geometry of the respective first and second implantation regions of the respective V-shaped trench, and in particular of the first and second implantation regions arranged adjacent in the cell pitch direction, are coordinated such that a current path for increasing voltage between a drain and source electrode of the semiconductor device is pinched off by a space charge region spreading between adjacent implantation regions.

[0014] The first and second implantation areas are preferably formed in a substantially strip-like shape in a top view of the semiconductor device. Advantageously, the first and second implantation areas extend substantially parallel to a trench direction of the semiconductor device.

[0015] In an alternative embodiment, the first and second implantation areas of the semiconductor device are essentially configured and / or arranged in a checkerboard pattern. In this case, the first and second implantation areas are preferably interrupted in plan view parallel to the trench direction and offset from each other in the transverse direction, orthogonal to the trench direction.

[0016] The V-shaped trenches of the trench structure can be symmetrical in their cross-section. Alternatively, the trench structure can have asymmetrical V-shaped trenches. These have two sidewalls with different flank angles. This allows the cell pitch to be shortened compared to a structure with symmetrical trenches.

[0017] In a preferred embodiment, the trench sidewalls are aligned along crystal planes of high electron mobility. Preferably, the sidewalls of the respective V-shaped trench have a predefined crystal orientation and, in particular, a flank angle that is formed as an (0-33-8) plane or as the a- or m-plane of the 4H-SiC crystal. Such an orientation can be achieved using special etching and trenching post-treatment processes known per se. This mobility-enhancing measure allows for the best possible compromise between low area-specific resistivity (RDS), on*A and good short-circuit capability can be achieved. In particular, the problem of reduced width of the current-carrying MIS channel due to the additional implantation area provided according to the invention, by sacrificing a trench sidewall and thus the increase in effective channel resistance and area-specific resistance RDS, can be avoided. on *A will be compensated.

[0018] As an additional measure, the semiconductor device advantageously features a gate dielectric, which is configured as a high-k dielectric, preferably with a relative permittivity greater than SiO₂, and preferably comprising Al₂O₃, HfO₂, SisN₄, or AION. The high-k dielectric can be configured as a single layer or as a stacked dielectric. The latter advantageously comprises a thin insulating layer and a layer of a high-k material, preferably with a thickness of 30 to 120 nm. In a preferred embodiment, the dielectric is configured as a pure SiO₂ gate dielectric, which is produced or deposited by low-pressure galvanic vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or thermal oxidation.Furthermore, the thickness of the dielectric in the trench bottom can be advantageously selected differently from the thickness of the dielectric in the trench region, with a greater thickness preferably being selected in the trench bottom region. The combination of a thick insulator at the trench bottom and / or the p++ implantation area below the trench bottom improves the switching characteristics of the device by reducing the gate-drain capacitance.

[0019] Further advantages, features, and details of the invention will become apparent from the following description of preferred embodiments of the invention and from the drawings. Brief description of the drawings

[0020] Fig. 1a, b shows a section through a layer structure of a trench MISFET and a trench MISFET with a V-shaped trench structure according to the prior art;

[0021] Figs. 2a-c show a section through a layer structure of a trench MISFET according to the invention with a V-shaped trench structure and an associated top view according to a first and second embodiment;

[0022] Fig. 3 shows a section through a layer structure of a trench MISFET with an asymmetric V-shaped trench structure according to a further preferred embodiment;

[0023] Figures 4a-e show a preferred manufacturing process for a semiconductor device according to Figure 3; and

[0024] Fig. 5 shows a graph of the short-circuit strength with respect to the drain-source voltage of a design according to the invention compared to the prior art.

[0025] Embodiments of the invention

[0026] Identical elements or elements with the same function are designated with the same reference numerals in the figures. The invention is described below, in particular, for a unit cell of a transistor.

[0027] Figures 1a and 1b show a basic structure of a Power Trench MISFET 100" and a V-Trench MISFET 100' according to the prior art. These each have a substrate 102 contacted by a drain contact 101 with an optional buffer layer 103 and an n-doped drift layer or drift region 104 arranged above it, p-doped pBody regions 105 arranged above it, and a source region 106 with heavily n-doped (n++) regions, with a trench structure 107 extending from this into the underlying pBody regions 105 and drift layer 104. An inversion channel forms at the interface with a gate dielectric 108, which is located in the gate trench filled with Gate Meta II or polysilicon 109.

[0028] In the bottom region of each trench 107, the semiconductor device 100',100" comprises a first p-doped implantation area 110, which is arranged and configured to provide a space charge zone 113 in the drift position 104 during a short circuit, thus enabling a JFET effect between two adjacent trenches of the trench structure 107. This allows for the pinching off of the current path between two trenches 107 and therefore a limitation of the short-circuit current density.

[0029] One design parameter of the semiconductor device is the so-called pitch, which represents the minimum distance between two repeating unit cells in the transistor's cell array. Due to the significantly increased cell pitch p2 > p1 in a V-shaped trench according to Fig. 1b (cf. Fig. 1a), the distance between two adjacent trenches and their associated implantation regions 110 in the trench bottom is increased. This significantly weakens the development of the desired JFET effect in region 114 due to the space charge zones 113 forming at adjacent trenches. Consequently, a sufficient JFET effect to reduce the short-circuit current density to an acceptable value is no longer possible.

[0030] Figures 2a and 2b show a structure of a power semiconductor device 100 corresponding to Figure 1b, with a trench structure 107 having V-shaped trenches 107a. According to the invention, an additional second implantation area 111 is arranged on one side of a first side wall or flank 112a of each V-shaped trench 107a. This enables a strong JFET effect to be achieved in the region 114 of the drift position 104 between the respective trenches 107a, despite the increased pitch p2 caused by the V-shaped trench, since adjacent implantation areas or p++ regions 110, 111 are located closer together due to the additional implantation area 111, despite the increased pitch p2. The first and second implantation areas 110,111 of a respective trench 107a can be formed as a continuous implantation area at the respective trench 107a, as shown in Fig. 2a-c.Advantageously, the implantation area on the first trench sidewall 112a and at the bottom of the V-trenchment 107a is set to source potential (0 V). In the forward direction, the drain electrode 101 on the underside / back of the device 100 has a positive voltage. Thus, the p++n junction between the p++ implant of the trench sidewall 112a and the n-drift region 104 is reverse-biased, and the extent of the space charge region 113 increases with increasing drain potential. The same applies to the field-weakening p++ region 110 in the bottom of adjacent V-trenches, so that the resulting space charge regions 113 of adjacent V-trenches 107a approach each other with increasing drain-source voltage. The electrons must flow through the resulting JFET region 114 to get from the source region 106 via the channel region at the interface between the gate dielectric 108 and the p-body 105 and the drift region 104 to the drain contact 101.The resistance contribution of the JFET region 114 increases accordingly as the adjacent space charge regions 113 approach each other, since the current-carrying cross-sectional area decreases. A higher resistance at a fixed drain-source voltage leads to a reduction in the drain-source current compared to V-trough MISFETs without an additional implantation region 111 on the side wall 112a. By selectively designing the doping heights and profiles, as well as the pitch, the current path for increasing voltage between drain and source, and thus also in the case of a short circuit, can be constricted by the expanding space charge regions 113 and is then only weakly dependent on the drain-source voltage.

[0031] The second implantation site 111 on the side wall 112a of the V-shaped trench 107a can be produced using methods known per se, in particular by ion implantation with a dedicated injection angle, whereby the implantation energy, dose, and angle are coordinated. It is also possible to produce the implantation sites 110 and 111 simultaneously.

[0032] As shown in Figs. 2b and 2c, various arrangements are possible with regard to the geometric design of the first and second implanted areas 110, 111 and the resulting continuous p++ area. The projections of the surface contours of the V-shaped trench 107a are marked by 116. In particular, these can be arranged in strips parallel to the course of the V-shaped trenches 107a, as shown in Fig. 2b. Alternatively, the p++ areas can be arranged in a checkerboard pattern and offset from each other, as shown in Fig. 2c. The respective distances must be designed so that sufficient current containment is still ensured in the event of a short circuit and that the trench floor, especially its corners, is adequately protected from high electric fields at high drain-source voltage. A checkerboard arrangement is particularly advantageous in through-flow operation, as it improves the RDS.on *A contributes. In a checkerboard arrangement, it is further advantageous to arrange the strongly n++ doped regions of Source 106 at least sectionally on both sides of each V-shaped trench adjacent to the side walls 112a, 112b.

[0033] Since no active MIS channel is provided in the first sidewall 112a at points where the implantation area 111 borders, and therefore no current is conducted in the conductive state, the second sidewall 112b of the trench 107 essentially serves to form the channel region. All possible flank angles are conceivable with regard to the orientation of the respective sidewalls 112b and 112a. The (0-33-8) surface is particularly advantageous for V-trough MISFETs, as it possesses beneficial electrical properties for use in MIS structures. Such surfaces can be prepared by chlorine etching at high temperatures. However, the transfer of a V-shaped hard mask structure into the SiC surface by a reactive ion etching process and an additional post-treatment process is also conceivable. In addition to the comparatively shallow flank angles, the a- and m-planes of the 4H-SiC crystal can also be used as trench sidewalls 112b, 112a.

[0034] The performance of the semiconductor device 100 can be further enhanced by the use of so-called high-k dielectrics such as Al₂O₃, HfO₂, SisN₄, or AION, etc. Compared to the industrially produced SiO₂ gate dielectric, these materials possess a higher relative permittivity. This increases the electric field strength in the channel region, resulting in an increase in electron density in the conducting MIS channel due to the enhanced field effect. High-k gate dielectrics can be used individually or as a stacked gate dielectric, consisting of a thin insulating layer (< 10 nm) at the interface, e.g., SiO₂ or any other insulating material, plus any high-k material with a thickness preferably in the range of 30–120 nm.

[0035] The use of high-k materials in the gate dielectric encompasses all possible CMOS-compatible dielectrics with a relative permittivity greater than SiC > 2. These can be implemented individually or in combination with a near-interface SiCh interlayer, preferably below 10 nm. Most of these materials are deposited by atomic layer deposition (ALD). The ALD process offers the advantage of conformal and homogeneous layer deposition with precise layer thickness control. Furthermore, the ALD process offers the advantage that the passivation of the semiconductor / insulator interface can be carried out in situ at low temperatures. When combined with a SiO2 interlayer, in-situ deposition of all layers by ALD is preferable. Optionally, the SiO2 interlayer could be degraded by thermal oxidation or...The high-k material is produced using low-pressure kinetic polymerization (LPCVD) or plasma-enhanced kinetic polymerization (PECVD).

[0036] One possible alternative to high-k dielectrics is the use of pure SiO₂. x -Gate dielectric, e.g. with x=2, which is produced by LPCVD, PECVD, ALD or thermal oxidation.

[0037] Fig. 3 shows another preferred embodiment in which the semiconductor device has an asymmetric V-shaped groove 107a, which allows a reduced cell pitch p3 to be achieved. Since the first side wall 112a does not contribute to the current flow in the switched-on state in areas with the additional p++ implant 111 anyway, a steeper angle, for example a 90° angle, can be produced on this side wall by modifying the manufacturing process, which reduces not only the cell pitch but also the RDS, on*A can be reduced. In addition, this further improves the short-circuit resistance, as the distance between two adjacent p++ regions 110,111 is reduced.

[0038] Figures 4a-e schematically show a simplified manufacturing process for asymmetric V-groove structures 107. First, rectangular trench structures 117 are formed in the substrate 102 (Figure 4a). Then, a full-surface masking layer 118 is deposited using a conformal deposition process. This layer serves as a hard mask for the subsequent etching process and should exhibit the highest possible selectivity towards SiC during etching. In the next step, the hard mask is structured using photolithography and reactive ion etching, so that one side wall 117a of the rectangular trench profile 117 is exposed (see Figure 4c). The subsequent etching process serves to chamfer the exposed side wall 117a at an arbitrary angle (see Figure 4d). For example, the (O-33-8) crystal surface can be prepared on one side using a chlorine etching process. After removal of the hard mask 118, see Fig.4e, a conventional process flow can be used to manufacture trench MISFETs.

[0039] Fig. 5 shows an output characteristic curve field of an arrangement according to the invention compared to a prior art trench MISFET semiconductor device. As shown, the semiconductor device 100 according to the invention exhibits improved drain-source current saturation (curve K1) compared to a conventional V-trench MISFET (curve K2). This reduces the heating of the device in the event of a short circuit, thus ensuring timely turn-off. In the resistive region (operating region) of the MISFET, the measures to improve channel mobility manifest themselves in a steeper current rise, which is equivalent to a lower RDS value. on *A is.

[0040] In addition to the described application, especially for 4H-SiC MISFETs, the basic principles of this invention can be used for power trench MISFETs of any semiconductor material, especially for Si, GaN, etc.

[0041] Furthermore, the invention can be used not only with the described n-channel MISFET but also with p-channel MISFETs; for this purpose, all p-dopings must be replaced by n-dopings and vice versa, and the applied potentials must be adapted accordingly.

Claims

Claims 1. Semiconductor device, in particular a V-trench MISFET (100), comprising a substrate (102), a drift region (104), a p-body region (105) arranged above it, and a source region (106), wherein the source region (106) has a trench structure (107) extending from it through the p-body region (105) into the underlying drift region (104) with several, preferably parallel, V-shaped trenches (107a), and wherein a first p-doped implantation region (110) is formed in the bottom region of each trench (107a), characterized in that a second p-doped implantation region (111) for enhancing a JFET effect in the drift region (104) is formed on one side of a side wall (112a) of each trench (107a) between two adjacent V-shaped Trenches have been formed.

2. Semiconductor device according to claim 1, characterized in that the second implantation area (111) extends along the entire length of the side wall of the respective V-shaped trench (107a) up to the first implantation area (110).

3. Semiconductor device according to claim 1 or 2, characterized in that a dopant concentration and / or the doping geometry of the respective first and second implantation regions (110, 111) of adjacent V-shaped trenches (107a) is matched such that a current path for increasing voltage between a drain (101) and source region (106) of the semiconductor device is pinched off by a space charge region (113) spreading between adjacent implantation regions (110, 111).

4. Semiconductor device according to one of the preceding claims, characterized in that the respective first and second implantation areas (110,111) are formed in a strip shape in top view of the semiconductor device (100).

5. Semiconductor device according to one of claims 1 to 3, characterized in that the first and second implantation areas (110, 111) are arranged in a substantially checkerboard pattern in a top view of the semiconductor device (100), and are preferably interrupted in the longitudinal direction and offset from each other in the transverse direction.

6. Semiconductor device according to one of the preceding claims, characterized in that the current-carrying side wall (112b) of the respective V-shaped groove (107a) has a predefined crystal orientation and in particular a flank angle, such that the side wall is formed, for example, in the (0-33-8) plane of the SiC crystal, or in the a- or m-plane of the SiC crystal.

7. Semiconductor device according to one of the preceding claims, characterized in that the semiconductor device (100) has a gate dielectric (108) which is designed as a high-k dielectric with a relative permittivity greater than SiO2, preferably comprising Al2O3, HfO2, Si3N4 or AION, wherein the high-k dielectric is designed as a single or stacked dielectric consisting of a thin insulating layer and a high-k material with a thickness preferably in the range of 30 to 120 nm.

8. Semiconductor device according to claim 7, characterized in that the dielectric (108) is a pure SiOx gate dielectric produced by LPCVD, PECVD, ALD or thermal oxidation.

9. Semiconductor device according to claim 7 or 8, characterized in that the thickness of the dielectric in a bottom region of the trench is selected to be greater than in the remaining trench region.

10. Semiconductor device according to one of the preceding claims, characterized in that the trench structure (107) has symmetrical or asymmetrical V-shaped trenches.

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