Via-connected top substrate of a power module

Abstract

The invention relates to a power module (100) comprising a substrate (101), a number of semiconductor components (104), and a number of first spacers (112), wherein the substrate (101) has at least a top substrate (102) and a bottom substrate (103), wherein the top substrate (102) has an electrically insulating layer (110), in particular a ceramic layer (110.1), and one or more conductor structures (114), wherein the one or more first spacers (112) are arranged between the semiconductor components (104) and the top substrate (102). The top substrate (102) has a via (406) which is formed within the top substrate (102). The via (406) comprises a recess (204) through which an electrical connection is established by introducing a bond wire (404), a second spacer (602), or a clip (504) within the recess (204), each of which permitting a source potential of the semiconductor component (104) to be tapped via the first spacer (112).

Description

[0001] Description

[0002] title

[0003] Technical field

[0004] The invention relates to a power module comprising a substrate with a top substrate and a bottom substrate. The top substrate has a through-hole and is electrically connected to the bottom substrate through this through-hole. Furthermore, the invention relates to a method for producing the through-hole of the top substrate.

[0005] State of the art

[0006] In current technology, the source potential of SiC power semiconductors in power modules is typically tapped directly on the semiconductor device via wire bonds on the source Kelvin pad. These wire bonds lead to the top-side substrate (usually implemented as a DBC or rigid or flexible printed circuit board) and from there, the signal is taken to a control electronics / gate driver board.

[0007] From DE 102 023 114 094 A1, a power module is known which has the following features: a lower substrate and an upper substrate spaced apart from the lower substrate, a semiconductor chip arranged between the lower substrate and the upper substrate, a first power connection spaced apart from the semiconductor chip and connected to the lower substrate or the upper substrate, and a second power connection spaced apart from the semiconductor chip and connected to the lower substrate or the upper substrate.

[0008] From DE102019112489A1 a power module is known which has the following features:

[0009] The substrate features: a first direct-bonded copper (DBC) substrate comprising a first insulating layer, a first etched circuit layer on an inner surface, and a first heat transfer layer on an outer surface, wherein the first etched circuit layer comprises a high-side plate with a high-side terminal; a second direct-bonded copper (DBC) substrate comprising a second insulating layer, a second etched circuit layer on an inner surface, and a second heat transfer layer on an outer surface, wherein the second etched circuit layer comprises an output plate with an output terminal; a transistor chip on the top side with a collector side soldered to the plate on the top side; and a transistor chip on the bottom side with a collector side soldered to the output plate.wherein the high-side plate defines a first recessed notch arranged between the high-side transistor chip and the high-side board to concentrate a magnetic flux induced by a current in the high-side plate onto the first recessed notch; and wherein one of the first or second etched circuit layers further comprises a high-side gate track connected to the high-side transistor chip and overlapping the first recessed notch.

[0010] Disclosure of the invention

[0011] According to the invention, a power module comprising a substrate, a number of semiconductor devices, and a number of first spacers is proposed. The substrate has at least one top substrate and one bottom substrate. The top substrate has an electrically insulating layer, in particular a ceramic layer, and one or more conductor structures. The one or more spacers are arranged between the semiconductor devices and the top substrate. The top substrate has a via located within it. The via has a recess through which an electrical connection is made by inserting a bond wire, a second spacer, or a clip within the recess, each configured to tap a source potential of the semiconductor device via the first spacer.

[0012] An efficient tap of the source potential between the top substrate and the semiconductor components arranged on a bottom substrate is achieved by means of the through-hole plating proposed according to the invention. The through-hole plating of the top substrate is carried out by electrically contacting one or more conductor structures arranged above and below the top substrate by means of a blind hole and establishing an electrical connection by means of a bond wire, a second spacer or a clip inserted into the blind hole.

[0013] In an advantageous embodiment of the power module proposed according to the invention, the recess is designed as a blind hole.

[0014] In an advantageous embodiment of the power module proposed according to the invention, a second spacer is provided within the blind bore. The second spacer can, for example, be designed as a metal block. The metal block is, for example, inserted into the blind bore in such a way that the underside of the blind bore is led upwards in a column-like manner, whereby the metal block protrudes from a molding compound.

[0015] In a further advantageous embodiment of the power module according to the invention, the conductor structures are configured as one or more top-side conductor structures and one or more bottom-side conductor structures. The one or more top-side conductor structures are arranged in the Y-direction on the surface of the electrically insulating layer, and the one or more bottom-side conductor structures are arranged in the Y-direction on the underside of the insulating layer.

[0016] In a further advantageous embodiment of the power module according to the invention, the blind bore comprises a bore in the top conductor structure and the electrically insulating layer.

[0017] Alternatively, the blind hole drilling can also include the bottom conductor structure and the insulating layer.

[0018] In a further advantageous embodiment of the power module according to the invention, the several semiconductor devices are electrically interconnected to establish an electrical connection between the top-top structure and the semiconductor devices. In a further advantageous embodiment of the power module according to the invention, the power module has a package, in particular a mold package.

[0019] In a further advantageous embodiment of the power module according to the invention, the packaging has one or more openings.

[0020] Furthermore, the invention relates to a method for producing the through-hole plating of the top-side substrate of the power module according to the invention for optimal tapping of the source potential of one or more semiconductor devices arranged on the bottom-side substrate. The method comprises the following steps: a) providing a top-side substrate with one or more recesses, b) mounting the top-side substrate on one or more first spacers, and c) connecting the top-side conductor structure of the top-side substrate to the bottom-side conductor structure of the top-side substrate by at least one electrical connection.

[0021] In an advantageous further development of the method according to the invention, the electrical connection is contacted by introducing at least one bond wire through at least one bond wire connection.

[0022] In an advantageous further development of the method according to the invention, the electrical connection is made by inserting the clip by means of a clip connection or the second spacer by means of a material-bonded connection, in particular a soldered connection, a sintered connection, an adhesive connection or a welded connection.

[0023] Alternatively, process step c) can also be performed before process step b).

[0024] Advantages of the invention

[0025] The inventive embodiment of a power module with a top substrate, which advantageously implements a through-hole connection via an electrical connection between the top substrate and the bottom substrate achieved within a blind bore, enables efficient tapping of the source potential of the semiconductor device.

[0026] Advantageously, according to the invention, the source potential is efficiently tapped by routing a main current path past a tap point in sections. Tapping the source potential in this way has the advantage of improving the lifetime of the semiconductor device in the event of a short circuit. In particular, this design automatically reduces the current flowing in the semiconductor device in the event of a short circuit to such an extent that the semiconductor device has a survival time that allows control software to detect the short circuit and switch off the semiconductor device.

[0027] Furthermore, the solution according to the invention eliminates the connections between the source Kelvin pads and the top-side substrate. This leads to a simplification of the substrate layout on the top side and to an increase in the cost and robustness of the power module.

[0028] Brief description of the drawings

[0029] Embodiments of the invention are explained in more detail with reference to the drawings and the following description.

[0030] They show:

[0031] Figure 1 shows a schematic partial view of a power module.

[0032] Figure 2 is a schematic representation of an arrangement of a

[0033] Top surface substrate with a first bore in the Y direction,

[0034] Figure 3 shows a schematic top view of the arrangement of the top substrate with the first bore in the Y direction.

[0035] Figure 4 shows a schematic representation of an arrangement of the top substrate with the first hole with a through-hole and the insertion of a bond wire in the Y direction; Figure 5 shows a schematic representation of an arrangement of the top substrate with the first hole with a through-hole and the insertion of a clip in the Y direction.

[0036] Figure 6 shows a schematic representation of an arrangement of the top substrate with the first bore with a via and a second spacer in the Y direction.

[0037] Figure 7 shows a schematic representation of a method for producing a through-hole connection of the top-side substrate.

[0038] Embodiments of the invention

[0039] In the following description of embodiments of the invention, identical or similar elements are designated by the same reference numerals, and repeated descriptions of these elements are omitted in individual cases. The figures represent the subject matter of the invention only schematically.

[0040] Figure 1 shows a schematic partial view of an exemplary power module.

[0041] 100 with a mold packaging 116. The power module 100 has a substrate

[0042] Figure 1 shows a power module 100, which is formed from a top substrate 102 and a bottom substrate 103. Figure 1 shows that a number of semiconductor devices 104 are positioned along a longitudinal direction 118 of the power module 100 on the bottom substrate 103. These semiconductor devices 104 can be configured as different types of power transistors, such as MOSFETs or IGBTs. Figure 1 also shows that each of the semiconductor devices 104 has a source Kelvin pad 106 on its surface. The source Kelvin pad 106 is a special connection point that enables measurement of the source potential of the semiconductor device 104. A first spacer 112 is arranged above each semiconductor device 104. The first spacer 112 fulfills several functions in the power module 100.It creates a defined distance between the semiconductor devices 104 and other layers of the module, in particular between the semiconductor devices 104 and the upper substrate 102. This ensures insulation and efficient heat dissipation. Another important function is current flow: The current flows from the drain (bottom of the semiconductor device 104) through the semiconductor device 104 to the source (top of the semiconductor device 104), through the first spacer 112 to the underside of the DBC, namely the bottom-side conductor structure 203, and from there via the first spacer 112 and the bottom-side substrate 103 to the electric motor.

[0043] The top substrate 102 forms a layer of the substrate 101 of the power module 100 and is arranged above the first spacers 112. Figure 1 shows that the top substrate 102 has a number of conductor structures 114 on its surface.

[0044] Figures 2 to 6 below show a number of exemplary embodiments of the top substrate which enable efficient extraction of the source potential according to the solution according to the invention.

[0045] Figure 2 shows a schematic representation of an arrangement of a top-side substrate 102, comprising a first bore 205 in the Y-direction 212. Furthermore, it can be seen from Figure 2 that the top-side substrate 102 is formed from at least three layers. A first layer is a top-side conductor structure 202, a second layer is an electrically insulating layer 110, and a third layer is a bottom-side conductor structure 203. The electrically insulating layer 110 can, for example, be configured as a ceramic layer 110.1. In addition, the top-side substrate 102 has conductor structures 114. Here, the conductor structures 114 are configured as top-side conductor structures 202 and bottom-side conductor structures 203. Figure 2 further shows that the top conductor structure 202 is arranged on a surface 206 of the electrically insulating layer 110 and the bottom conductor structure 203 is arranged on a bottom surface 208 of the electrically insulating layer 110.

[0046] Furthermore, in Figure 2, a recess 204 is configured as a first bore 205, which provides a through-hole connection through a top-side conductor structure 202 and a through-hole connection 406 through the electrically insulating layer 110 as an exemplary blind bore 214. This blind bore 214 serves to attach a bond wire 404, a clip 504, or a second spacer 602 through it to enable an electrical connection for tapping the source potential.

[0047] Figure 3 shows a schematic top view of the arrangement of the top substrate 102 with the first bore 205. Figure 3 also shows that the top substrate 102 is formed from three layers. A first layer is a top conductor structure 202, a second layer is an electrically insulating layer 110, and a third layer is a bottom conductor structure 203. The electrically insulating layer 110 can, for example, be designed as a ceramic layer 110.1. Furthermore, the top substrate 102 has conductor structures 114. The conductor structures 114 are configured as a top conductor structure 202 and a bottom conductor structure 203. Figure 3 also shows that the top conductor structure 202 is arranged on a surface 206 of the electrically insulating layer 110, and the bottom conductor structure 203 is arranged below it.

[0048] Furthermore, Figure 3 shows that the first bore 205 is arranged, by way of example but not exclusively, within the center 302 of the top substrate 102, 108. Thus, the recess 204 is designed as a blind bore 205 and as a cylindrical borehole that extends through the top conductor structure 202 and the electrically insulating layer 110 and provides a view of the surface of the bottom conductor structure 203.

[0049] Figure 4 shows a schematic representation of an arrangement of a top-side substrate 102 comprising a first bore 205 with a via 406 and a bond wire 404 inserted in the Y-direction 212. Furthermore, it can be seen from Figure 4 that the top-side substrate 102 is formed from three layers. A first layer is a top-side conductor structure 202, a second layer is an electrically insulating layer 110, and a third layer is a bottom-side conductor structure 203. The electrically insulating layer 110 can, for example, be designed as a ceramic layer 110.1. In addition, the top-side substrate 102 has conductor structures 114. Here, the conductor structures 114 are configured as top-side conductor structures 202 and bottom-side conductor structures 203.Figure 4 further shows that the top conductor structure 202 is arranged on a surface 206 of the electrically insulating layer 110 and the bottom conductor structure 203 is arranged on a bottom surface 208 of the electrically insulating layer 110.

[0050] Furthermore, Figure 4 shows that the bond wire 404 runs via a bond wire connection 402 within the first bore 205, which is designed as a blind bore 214, to the electrical connection.

[0051] Figure 5 shows a schematic representation of an arrangement of a top-side substrate 102 comprising a first bore 205 with a via 406 and a clip 504 inserted in the Y-direction 212. Furthermore, it can be seen from Figure 5 that the top-side substrate 102 is formed from three layers. A first layer is a top-side conductor structure 202, a second layer is an electrically insulating layer 110, and a third layer is a bottom-side conductor structure 203. The electrically insulating layer 110 can, for example, be configured as a ceramic layer 110.1. In addition, the top-side substrate 102 has conductor structures 114. Here, the conductor structures 114 are configured as top-side conductor structures 202 and bottom-side conductor structures 203.Figure 5 further shows that the top conductor structure 202 is arranged on a surface 206 of the electrically insulating layer 110 and the bottom conductor structure 203 is arranged on a bottom surface 208 of the electrically insulating layer 110.

[0052] Figure 5 further shows that the clip 504 is arranged for electrical connection within the first bore 205, which is designed as a blind bore 214, by means of a clip connection 502.

[0053] Figure 6 shows a schematic representation of an arrangement of a top-side substrate 102 comprising a molded housing 116, a first bore 205 with a via 406, and a second spacer 602 in the Y-direction 212. Furthermore, it can be seen from Figure 6 that the top-side substrate 102 is formed from three layers. A first layer is a top-side conductor structure 202, a second layer is an electrically insulating layer 110, and a third layer is a bottom-side conductor structure 203. The electrically insulating layer 110 can, for example, be designed as a ceramic layer 110.1. In addition, the top-side substrate 102 has conductor structures 114. Here, the conductor structures 114 are configured as top-side conductor structures 202 and bottom-side conductor structures 203.Figure 6 further shows that the top conductor structure 202 is arranged on a surface 206 of the electrically insulating layer 110 and the bottom conductor structure 203 is arranged on a bottom surface 208 of the electrically insulating layer 110.

[0054] Furthermore, Figure 6 shows that the second spacer 602 is arranged for electrical connection within the first bore 205, which is designed as a blind bore 214.

[0055] The electrical connection can be made by attaching the clip 504 by means of a clip connection 502 or the second spacer 602 between the top conductor structure 202 and the bottom conductor structure 203, for example by means of a material-bonded connection, in particular a soldered connection, a sintered connection, an adhesive connection or a welded connection.

[0056] The top surface substrate 102 shown in Figures 1 to 6 can be designed, for example, as DCB 108 (Direct Copper Bonding), DBC (Direct Bonded Copper), DPC (Direct Plated Copper) or AMB (Active Metal Brazing) as well as a printed circuit board (PCB).

[0057] The choice of substrate material and manufacturing technology depends on various factors, such as the required thermal conductivity, electrical insulation, mechanical stability, and cost. For example, DCB, DBC, DPC, and AMB substrates offer good heat dissipation and reliable electrical insulation, while printed circuit boards (PCBs) may be a more cost-effective option. According to the invention, any top-side substrate 102 can be further processed to produce a recess 204 of the solution according to the invention.

[0058] Figure 7 schematically shows, as a block diagram, an exemplary method 700 according to the invention for producing a via 406 of the top-side substrate 102. In a first step, the top-side substrate 102 is provided with one or more recesses 204. The number of recesses 204 can be based on the number of semiconductor devices 104 in a power module 100 and on the number of required taps of source potentials. The one or more recesses 204 can be configured as the first bore 205 or the second bore as a blind bore 214.

[0059] In a second step of the inventive method 700, the top substrate 102 is installed 704 on one or more first spacers 112. In a third step of the inventive method 700, a top conductor structure 202 of the top substrate 102 is contacted 706 with a bottom conductor structure 203 of the top substrate 102 by at least one electrical connection. The electrical connection can be made by attaching the bond wire 404 by means of a bond wire connection 402, the clip 504 by means of a clip connection 502, or the second spacer 602 between the top conductor structure 202 and the bottom conductor structure 203, for example by means of a metallurgical connection, in particular a soldered connection, a sintered connection, an adhesive connection, or a welded connection.

[0060] The invention is not limited to the embodiments described here and the aspects highlighted therein. Rather, within the scope specified by the claims, a multitude of modifications are possible that fall within the bounds of what is considered skilled in the art.

Claims

Claims 1. Power module (100) comprising a substrate (101), a number of semiconductor devices (104) and a number of first spacers (112), wherein the substrate (101) has at least a top substrate (102, 108) and a bottom substrate (103), wherein the top substrate (102) has an electrically insulating layer (110), in particular a ceramic layer (110).1), and has one or more conductor structures (114), wherein the one or more first spacers (112) are arranged between the semiconductor devices (104) and the top substrate (102), wherein the top substrate (102) has a via (406) which is located within the top substrate (102), wherein a via (406) has a recess (204) through which an electrical connection passes by introducing a bond wire (404), a second spacer (602) or a clip (504) within the recess (204) and enables the tapping of a source potential of the semiconductor device (104) via the first spacer (112).

2. Power module (100) according to claim 1, wherein the recess (204) is designed as a blind hole (214).

3. Power module (100) according to claims 1 or 2, wherein the second spacer (602) is configured within the blind bore (214).

4. Power module (100) according to one of the preceding claims, wherein the conductor structures (114) are configured as one or more top-side conductor structures (202) and one or more bottom-side conductor structures (203), wherein the one or more top-side conductor structure(s) (202) is / are arranged in the Y-direction (212) on the surface (206) of the electrically insulating layer (110), wherein the one or more Sub-conductor structure(s) (203) in Y-direction (212) on the The underside (208) of the insulating layer (110) is / are arranged.

5. Power module (100) according to claims 2 or 3, wherein a blind bore (214) comprises a bore in the top conductor structure (202) and the insulating layer (110).

6. Power module (100) according to one of the preceding claims, wherein the multiple semiconductor devices (104) are electrically connected to each other to establish an electrical connection between the top conductor structure (202) and the semiconductor devices (104).

7. Power module (100) according to one of the preceding claims, wherein a power module (100) comprises a packaging (115), in particular a molded packaging (116).

8. Power module (100) according to claim 7, wherein the packaging (115) has one or more openings.

9. Method (700) for producing the via (406) of the top-side substrate (102, 108) of the power module (100) according to any of the preceding claims for optimal tapping of the source potential of one or more semiconductor devices (104) arranged on the bottom-side substrate (103), wherein the method (700) comprises: a) providing (702) a top-side substrate (102) with one or more recesses (204), b) installing (704) the top-side substrate (102, 108) on the one or more first spacer(s) (112), and c) contacting a top-side conductor structure (202) of the top-side substrate (102) with a bottom-side conductor structure (203) of the top-side substrate (102) by at least one electrical connection.

10. Method (700) according to claim 8, wherein the contacting (706) of the electrical connection is carried out by introducing at least one Bond wire (404) is connected by at least one bond wire connection (402).

11. Method (700) according to claim 9, wherein the contacting (706) of the electrical connection is carried out by inserting the clip (504) by means of a Clip connection (502) or of the second spacer (602) by means of a material-bonded connection, in particular a soldered connection, a sintered connection, an adhesive connection or a welded connection.

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