Semiconductor device

Abstract

The purpose of the present disclosure is to provide a semiconductor device that includes an SFP but can still short a load impedance at the second harmonic of an operating frequency. This semiconductor device comprises a semiconductor substrate, a source electrode and a drain electrode that are formed on an upper surface of the semiconductor substrate, a gate electrode that is formed on the upper surface of the semiconductor substrate between the source electrode and the drain electrode, a source field plate that is formed on the upper surface of the semiconductor substrate between the gate electrode and the drain electrode, and wiring that electrically connects the source field plate and the source electrode. A series resonance circuit is formed by the wiring and a parasitic capacitance between the drain electrode and the source electrode caused by the source field plate. The inductance of the wiring is adjusted such that the series resonance circuit resonates at the second harmonic of the operating frequency of the semiconductor device.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] In semiconductor devices used for power amplification and the like, there is a technology that utilizes harmonics such as second and third harmonics of the operating frequency to achieve high-efficiency operation. In this technology, the semiconductor device may be operated in class F to reduce power consumption due to harmonics. In class F operation, the load impedance seen from the semiconductor device to the load side is short-circuited for even harmonics and open-circuited for odd harmonics.

[0003] Non-Patent Document 1 discloses a method for connecting a series resonant circuit to the output terminal of a semiconductor device. The series resonant circuit is composed of a capacitor and a bond wire for connecting the capacitor to an external ground. By adjusting the capacitance of the capacitor and the inductance of the bond wire so that the series resonant circuit resonates at a frequency double the operating frequency, the load impedance can be short-circuited with respect to the double frequency.

[0004] K. Yamamoto et al., "A WCDMA Multiband Power Amplifier Module With Si-CMOS / GaAs-HBT Hybrid Power-Stage Configuration", IEEE Transactions on Microwave Theory and Techniques, vol.64, No.3, 2016.

[0005] A known method for alleviating the electric field between the gate and drain is to provide a source field plate (SFP) between the gate and drain electrodes, which has the same potential as the source electrode. While this method can increase the withstand voltage of the semiconductor device, it also generates parasitic capacitance between the drain and source.

[0006] Consider connecting a series resonant circuit to the output terminal of a semiconductor device with an SFP. In this case, the inductance of the bond wire must be reduced to compensate for the increase in drain-source capacitance due to the parasitic capacitance caused by the SFP. To reduce the inductance, the bond wire must be shortened, but there are manufacturing limitations. Therefore, even if the above-mentioned method is applied to a semiconductor device with an SFP, there is a problem in that the second harmonic resonance conditions cannot be achieved.

[0007] In order to solve the above-mentioned problems, an object of the present disclosure is to provide a semiconductor device that can short-circuit a load impedance for a wave twice the operating frequency even when the semiconductor device has an SFP.

[0008] An aspect of the present disclosure is preferably a semiconductor device comprising: a semiconductor substrate; a source electrode and a drain electrode formed on an upper surface of the semiconductor substrate; a gate electrode formed between the source electrode and the drain electrode on the upper surface of the semiconductor substrate; a source field plate formed between the gate electrode and the drain electrode on the upper surface of the semiconductor substrate; and wiring electrically connecting the source field plate and the source electrode, wherein a series resonant circuit is formed by the wiring and a parasitic capacitance between the drain electrode and the source electrode caused by the source field plate, and the inductance of the wiring is adjusted so that the series resonant circuit resonates at a frequency twice the operating frequency of the semiconductor device.

[0009] In the present disclosure, a series resonant circuit is formed by the drain-source parasitic capacitance C caused by the SFP and the wiring for connecting the SFP to the source electrode. By adjusting the inductance L so that the series resonant circuit resonates at a frequency doubled from the operating frequency, the load impedance can be short-circuited with respect to the frequency doubled from the operating frequency. This makes it possible to provide a semiconductor device that can short-circuit the load impedance with respect to the frequency doubled from the operating frequency even when the semiconductor device includes an SFP.

[0010] 1 is a top view of a semiconductor device according to a first embodiment; FIG. 2 is an equivalent circuit diagram of the semiconductor device according to the first embodiment; FIG. 3 is a top view of a semiconductor device according to a comparative example of the present disclosure; FIG. 4 is a top view of a semiconductor device according to a second embodiment; FIG. 5 is a top view of a semiconductor device according to a third embodiment; FIG. 6 is a top view of a semiconductor device according to a fourth embodiment; and FIG. 7 is a top view of a semiconductor device that combines the third and fourth embodiments.

[0011] Embodiments of the present disclosure will be described with reference to the drawings. The same or corresponding components will be designated by the same reference numerals, and repeated description may be omitted.

[0012] 1 is a top view of a semiconductor device 1 according to embodiment 1. The type of semiconductor device 1 is not particularly limited, but may be, for example, a high electron mobility transistor (HEMT), a heterojunction bipolar transistor (HBT), a field effect transistor (FET), or the like.

[0013] A drain electrode 4, source electrodes 5-1 and 5-2, and gate electrodes 6-1 and 6-2 are formed parallel to one another on the upper surface of a semiconductor substrate.

[0014] The semiconductor substrate includes a GaN electron transit layer and an AlGaN electron supply layer when the semiconductor device 1 is a GaN HEMT. However, the semiconductor substrate may be made of, for example, Si or other semiconductor materials.

[0015] A source electrode 5-1 (first source electrode) is disposed on one side of the drain electrode 4. A source electrode 5-2 (second source electrode) is disposed on the other side of the drain electrode 4.

[0016] The gate electrode 6-1 (first gate electrode) is disposed between the source electrode 5-1 and the drain electrode 4. The gate electrode 6-2 (second gate electrode) is disposed between the source electrode 5-2 and the drain electrode 4. The gate electrodes 6-1 and 6-2 are connected to each other outside the operating region 3. The operating region 3 is a region where the semiconductor device 1 operates as a transistor.

[0017] The source electrodes 5-1 and 5-2 are grounded electrodes. To ground the source electrodes 5-1 and 5-2, there is a method of electrically connecting the source electrodes 5-1 and 5-2 to a ground portion on the back surface via a through-hole that penetrates from the back surface to the top surface of the semiconductor substrate. Alternatively, there is a method of electrically connecting the source electrodes 5-1 and 5-2 to an external ground portion via a source terminal 15 (not shown).

[0018] In the following description, the source electrodes 5-1 and 5-2 are applicable to each other, and when there is no need to distinguish between them, they will simply be referred to as source electrodes 5. Only when there is a need to distinguish between them, will the respective reference symbols be used. This also applies to the gate electrodes 6-1 and 6-2, and the SFPs 7-1 and 7-2 described later.

[0019] The SFP 7-1 (first SFP) extends parallel to the gate electrode 6-1 and the drain electrode 4 between these electrodes. The SFP 7-2 (second SFP) extends parallel to the gate electrode 6-2 and the drain electrode 4 between these electrodes.

[0020] The SFPs 7-1 and 7-2 extend to the outside of the operating region 3. Outside the operating region 3, wiring 8 is drawn out from both sides of the SFP 7-1 and connected to the source electrode 5-1. Similarly, wiring 8 is drawn out from both sides of the SFP 7-2 and connected to the source electrode 5-2. The wiring 8 is made of, for example, Au.

[0021] The SFP 7 is electrically connected to the source electrode 5 by a wiring 8 and is grounded. By grounding the SFP 7, the electric field concentrated at the end of the gate electrode 6 on the drain electrode 4 side can be concentrated also at the end of the SFP 7 on the drain electrode 4 side. This makes it possible to alleviate the electric field between the gate and the drain.

[0022] The number of source electrodes 5, gate electrodes 6 and SFPs 7 does not necessarily have to be two. There may be one of each, or more than one.

[0023] 2 is an equivalent circuit diagram of the semiconductor device 1 according to the first embodiment. The gate terminal 16 is drawn from the gate electrode 6 and receives a gate input voltage from another device. An inductance Lg and a resistance Rg are connected in series to the gate terminal 16 in this order. The inductance Lg and the resistance Rg are respectively an inductance and a resistance resulting from the physical length of the gate electrode 6, etc. A capacitance Cpg is connected from the connection point between the inductance Lg and the resistance Rg to the source terminal 15. The capacitance Cpg is a capacitance generated between the portion of the gate electrode 6 that extends outside the operating region 3 and an external ground.

[0024] A capacitance Cdg is connected to the output side of the resistance Rg. The other end of the capacitance Cdg is connected to a drain-gate resistance Rdg. The capacitance Cdg can be regarded as a capacitance formed on the drain electrode 4 side in the depletion layer in the semiconductor layer directly below the gate electrode 6.

[0025] The output side of the resistor Rdg is connected to the drain terminal 14 via a series resistor Rd and inductance Ld. The drain terminal 14 is an output terminal that is drawn from the drain electrode 4 and is used to extract the power amplified by the semiconductor device 1 to the outside. The resistance Rd and the inductance Ld are respectively a resistance and an inductance that are caused by the physical length of the drain electrode 4, etc. A capacitance Cpd is connected from the connection point between the resistance Rd and the inductance Ld to the source terminal 15. The capacitance Cpd is a capacitance caused by wiring, such as the drain terminal 14, that is used to draw the drain electrode 4 to the outside.

[0026] A capacitance Cgs is connected in parallel with the capacitance Cdg to the output side of the resistance Rg. The capacitance Cgs can be considered to be a capacitance formed on the source electrode 5 side in the depletion layer in the semiconductor layer directly below the gate electrode 6. A channel resistance Ri is connected to the other end of the capacitance Cgs. The resistance Ri is connected to the source terminal 15 via a series circuit of a resistance Rs and an inductance Ls. The resistance Rs and the inductance Ls are the resistance and inductance resulting from the physical length of the wiring for connecting the source electrode 5 to an external ground part, etc.

[0027] A current source gm_tau, a series resonant circuit 19, a capacitance Cds, and a resistance Rds are connected in parallel to the midpoint of the resistance Rdg and the resistance Rd, and are connected to the source terminal 15 via a series circuit of a resistance Rs and an inductance Ls.

[0028] The current source gm_tau supplies a current according to the mutual conductance gm and the gate input voltage. The resistance Rds is the reciprocal of the drain conductance gds.

[0029] The region including the capacitance Cdg, resistance Rdg, capacitance Cgs, resistance Ri, current source gm_tau, capacitance Cds, and resistance Rds is a region where the essential operation of the transistor is performed, and is called the intrinsic region.

[0030] The drain-source parasitic capacitance C caused by the SFP 7 and the inductance L of the wiring 8 can be regarded as a series resonant circuit 19 connected to the load side of the current source gm_tau in the intrinsic region. In this embodiment, the inductance L of the wiring 8 is adjusted so that the series resonant circuit 19 resonates at a frequency twice the operating frequency of the semiconductor device 1.

[0031] Specifically, in the series resonant circuit 19, the inductance L is adjusted so that the double wave satisfies the resonance condition of (Equation 1). This makes it possible to make the load impedance of the double wave zero and short-circuit the double wave.

[0032]

[0033] In the above equation, f is the frequency of the double wave. The parasitic capacitance C between the drain and source caused by the SFP 7 can be known by simulation or the like.

[0034] The inductance L can be adjusted by the length, width, material, etc. of the wiring 8. When adjusting L by the length of the wiring 8, the wiring 8 has a length that is at least twice the length M of the gate electrode 6 extending within the operating region 3.

[0035] Generally, the length M of the gate electrode 6 has an upper limit depending on the operating frequency, and the upper limit becomes shorter as the operating frequency becomes higher. Therefore, the length of the wiring 8 required to realize the resonance condition of the second harmonic becomes shorter as the operating frequency becomes higher.

[0036] It should be noted that in order to achieve the resonance conditions for the second harmonic, it is only necessary to consider the capacitance C and inductance L of the series resonant circuit 19, and it is not necessary to consider the capacitance Cds and resistance Rds. This is because the series resonant circuit 19 is in a parallel relationship with the capacitance Cds and resistance Rds.

[0037] As described above, in this embodiment, the series resonant circuit 19 is formed by the drain-source parasitic capacitance C caused by the SFP 7 and the wiring 8 for connecting the SFP 7 to the source electrode 5. By adjusting the inductance L so that the series resonant circuit 19 resonates at a frequency double the operating frequency, the load impedance can be short-circuited with respect to the frequency double the operating frequency. This makes it possible to provide a semiconductor device that can short-circuit the load impedance with respect to the frequency double the operating frequency even when the semiconductor device has an SFP.

[0038] Furthermore, in this embodiment, the wiring 8 is arranged symmetrically in a planar view. This is a measure to maintain uniformity in the operation of the transistor. Generally, as the frequency approaches a high frequency, the influence of circuit elements of a size equivalent to the wavelength on the operating characteristics of a transistor becomes more significant. In this embodiment, for convenience, the wiring 8 drawn out from both sides of the SFP 7 is considered to be in parallel, and the inductance L is the combined inductance of the wiring 8 on both sides. However, in reality, a shift in the operating phase occurs between the longitudinal ends 6a and 6b of the gate electrode 6, and it is considered that a corresponding shift in the operating phase also occurs between the ends 7a and 7b of the SFP 7. By arranging the wiring 8 symmetrically in a planar view, as in this embodiment, the shift in the operating phase can be corrected.

[0039] Comparative Example Here, a conventional technique will be described as a comparative example of the present disclosure. The same reference numerals are used for components common to or corresponding to the present disclosure. Differences from the present disclosure will be mainly described here, and components common to or corresponding to the present disclosure will be described in the present disclosure.

[0040] 3 is a top view of a semiconductor device 50 according to a comparative example of the present disclosure. In the prior art, the SFP 7 and the source electrode 5 are also electrically connected by a wiring 58. However, the prior art lacks the technical idea of ​​short-circuiting the second harmonic wave using the series resonant circuit 19. Therefore, in the prior art, the wiring 58 connects the SFP 7 and the source electrode 5 via the shortest path. In this case, the resonant frequency of the series resonant circuit 19 becomes much higher than the second harmonic wave.

[0041] Second Embodiment Here, changes from the first embodiment will be described. Fig. 4 is a top view of a semiconductor device 1 according to the second embodiment. In this embodiment, a part of the wiring 8 is wound in a spiral shape. The spiral part can be formed by, for example, a spiral inductor 9. The spiral inductor 9 is formed of, for example, Au.

[0042] By winding a part of the wiring 8 in a spiral shape, the circuit size can be made smaller than in embodiment 1. This is particularly effective when the operating frequency is low, since the wiring 8 needs to be long.

[0043] It is also possible to connect the SFP 7 and the source electrode 5 using only the spiral inductor 9 .

[0044] Third Embodiment Here, changes from the second embodiment will be described. Fig. 5 is a top view of a semiconductor device 1 according to the third embodiment. In this embodiment, SFPs 7-1 and 7-2 are electrically connected by a wiring 8. Furthermore, source electrodes 5-1 and 5-2 are electrically connected by a wiring 8. By connecting the SFPs 7 to each other and the source electrodes 5 to each other in this manner, the drain-source parasitic capacitance C caused by the SFPs 7 is doubled compared to the second embodiment.

[0045] The SFPs 7-1 and 7-2 and the source electrodes 5-1 and 5-2 are electrically connected by a spiral inductor 9.

[0046] In this embodiment, the parasitic capacitance C is doubled compared to the second embodiment, so the inductance L can be halved and the wiring 8 and spiral inductor 9 can be shortened, thereby making it possible to further reduce the circuit dimensions compared to the second embodiment.

[0047] In this embodiment, the wiring 8 is drawn out from both sides of the SFPs 7-1 and 7-2 and the source electrodes 5-1 and 5-2. The effect of arranging the wiring 8 and the spiral inductor 9 symmetrically in a plan view is as described in the first embodiment.

[0048] Fourth Embodiment Here, changes from the second embodiment will be described. Fig. 6 is a top view of a semiconductor device 1 according to a fourth embodiment. In this embodiment, the wiring 8 is drawn out from only one side of the SFP 7. Note that, as in the second embodiment, a part of the wiring 8 is wound in a spiral shape by a spiral inductor 9.

[0049] When the wiring 8 is drawn out from both sides of the SFP 7 as in the second embodiment, the wiring 8 on each side is parallel in the equivalent circuit. Therefore, the inductance L in the series resonant circuit 19 is half the inductance of the wiring 8 on each side. By drawing out the wiring 8 from one side of the SFP 7 as in this embodiment, the inductance L can be doubled compared to when drawing out from both sides. Therefore, it becomes possible to support an even lower operating frequency than in the second embodiment. Furthermore, since the length of the wiring 8 is halved, it is also possible to miniaturize the circuit.

[0050] There is a concern that drawing out the wiring 8 from only one side of the SFP 7 may deteriorate the uniformity of transistor operation. However, if the operating frequency is low and the operating phase shift between the ends 6 a, 6 b of the gate electrode 6 is not large, the impact can be said to be small. For example, if the operating phase shift in the second harmonic is about 10° or less, the impact on the operating characteristics of the transistor is thought to be small.

[0051] The present disclosure is not limited to the above-described embodiments, and various modifications can be made in the implementation stage without departing from the spirit of the present disclosure. For example, the method for realizing the resonance condition for the second harmonic wave is not limited to the method based on (Equation 1). Any method that can ultimately realize the resonance condition for the second harmonic wave may be used, such as a method using simulation or other methods.

[0052] Furthermore, the respective embodiments and modifications may be combined as appropriate, and in that case, the combined effects can be obtained. For example, Figure 7 is a top view of a semiconductor device 1 that combines the third and fourth embodiments. Here, the third and fourth embodiments are combined, and the combined effects of the third and fourth embodiments can be obtained.

[0053] 1 semiconductor device, 3 operating region, 4 drain electrode, 5 source electrode, 5-1 first source electrode, 5-2 second source electrode, 6 gate electrode, 6-1 first gate electrode, 6-2 second gate electrode, 6a end, 6b end, 7 SFP (source field plate), 7-1 first SFP, 7-2 second SFP, 7a end, 7b end, 8 wiring, 9 spiral inductor, 14 drain terminal, 15 source terminal, 16 gate terminal, 19 series resonant circuit, 50 semiconductor device (comparative example), 58 wiring

Claims

1. A semiconductor device comprising: a semiconductor substrate; a source electrode and a drain electrode formed on an upper surface of the semiconductor substrate; a gate electrode formed between the source electrode and the drain electrode on the upper surface of the semiconductor substrate; a source field plate formed between the gate electrode and the drain electrode on the upper surface of the semiconductor substrate; and wiring electrically connecting the source field plate and the source electrode, wherein a series resonant circuit is formed by the wiring and a parasitic capacitance between the drain electrode and the source electrode caused by the source field plate, and the inductance of the wiring is adjusted so that the series resonant circuit resonates at twice the operating frequency of the semiconductor device.

2. The semiconductor device according to claim 1, wherein a portion of the wiring is wound in a spiral shape.

3. The semiconductor device according to claim 1 or 2, wherein the wiring is drawn out from both sides of the source field plate and connected to the source electrode, and is symmetrical in plan view.

4. The semiconductor device according to claim 3, wherein said wiring has a length at least twice as long as the length of said gate electrode.

5. The semiconductor device according to claim 1 or 2, wherein the source electrode has a first source electrode and a second source electrode, the gate electrode has a first gate electrode arranged between the first source electrode and the drain electrode, and a second gate electrode arranged between the second source electrode and the drain electrode, the source field plate has a first source field plate arranged between the drain electrode and the first gate electrode, and a second source field plate arranged between the drain electrode and the second gate electrode, and the first and second source field plates and the first and second source electrodes are connected by the wiring.

6. The semiconductor device according to claim 5, wherein the wirings are drawn out from both sides of the first and second source field plates and the first and second source electrodes, respectively, and are symmetrical in plan view.

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