Passive electronic component

Abstract

A passive electronic component 1 comprises: a substrate 10 having a first main surface 10a and a second main surface 10b that face each other in a thickness direction T; and a capacitor 20 disposed on the first main surface 10a of the substrate 10. The capacitor 20 includes a first internal electrode layer 31 provided on the first main surface 10a of the substrate 10, a first dielectric film 41 provided on the first internal electrode layer 31, and a second internal electrode layer 32 provided on the first dielectric film 41. In a plan view from the thickness direction T, corner portions of the first internal electrode layer 31 are rounded. In a cross-sectional view taken along the thickness direction T, a side surface of the first internal electrode layer 31 is inclined at an acute angle with respect to the first main surface 10a of the substrate 10.

Description

Passive Electronic Components

[0001] The present invention relates to passive electronic components.

[0002] Patent Document 1 discloses a chip capacitor including a substrate, a first external electrode arranged on the substrate, a second external electrode arranged on the substrate, a plurality of capacitor elements formed on the substrate and connected between the first external electrode and the second external electrode, and a plurality of fuses formed on the substrate and interposed between the plurality of capacitor elements and the first external electrode or the second external electrode, respectively, and capable of disconnecting the plurality of capacitor elements.

[0003] JP 2017-112393 A

[0004] Patent Document 1 describes that the method includes the steps of forming a lower electrode film on the substrate, forming a capacitance film on the lower electrode film, forming an upper electrode film on the capacitance film so as to face the lower electrode film, and dividing one of the upper electrode film and the lower electrode film into a plurality of electrode film portions (e.g., dividing by photolithography), and that the plurality of electrode film portions may face the other of the upper electrode film and the lower electrode film via the capacitance film, thereby forming the plurality of capacitor elements.

[0005] According to Patent Document 1, the above method can form a capacitor structure in which a capacitance film is sandwiched between a lower electrode film and an upper electrode film. Hereinafter, an electrode film such as a lower electrode film or an upper electrode film will also be referred to as an internal electrode layer, and the capacitance film will also be referred to as a dielectric film.

[0006] In the above method, forming an internal electrode layer on a substrate results in a step between the internal electrode layer and the substrate at its edge. When forming a dielectric film on the internal electrode layer in this state, the dielectric film is typically formed not only on the internal electrode layer but also on the substrate. However, the presence of a step at the edge of the internal electrode layer makes it difficult to uniformly form the dielectric film along the surface shapes of the substrate and the internal electrode layer, in other words, to form the dielectric film conformally. Specifically, defects such as voids (called "pores") forming inside the dielectric film or locally thinning the dielectric film are likely to occur near the corners of the internal electrode layer, which create a step with the substrate. As a result, the conformality of the dielectric film formed on the internal electrode layer is reduced, which may reduce the reliability of the capacitor.

[0007] The present invention has been made to solve the above problems, and aims to provide a passive electronic component having excellent conformality of a dielectric film provided on an internal electrode layer and having a highly reliable capacitor.

[0008] A passive electronic component of the present invention includes a substrate having a first main surface and a second main surface opposing each other in a thickness direction, and a capacitor disposed on the first main surface of the substrate. The capacitor includes a first internal electrode layer provided on the first main surface of the substrate, a first dielectric film provided on the first internal electrode layer, and a second internal electrode layer provided on the first dielectric film. In a plan view from the thickness direction, corners of the first internal electrode layer are rounded. In a cross-sectional view along the thickness direction, a side surface of the first internal electrode layer is inclined at an acute angle with respect to the first main surface of the substrate.

[0009] According to the present invention, it is possible to provide a passive electronic component having excellent conformality of the dielectric film provided on the internal electrode layer and having a highly reliable capacitor.

[0010] FIG. 1 is a cross-sectional view schematically showing an example of a passive electronic component according to a first embodiment of the present invention. FIG. 2 is a plan view schematically showing an example of a passive electronic component according to the first embodiment of the present invention. FIG. 3 is a plan view schematically showing an example of a first internal electrode layer located in a portion surrounded by a dashed line in FIG. 1. FIG. 4 is a cross-sectional view enlarging the portion surrounded by a dashed line in FIG. 1. FIG. 5 is a cross-sectional view schematically showing an example of a passive electronic component according to a first comparative embodiment outside the scope of the present invention. FIG. 6 is a plan view schematically showing an example of a first internal electrode layer located in a portion surrounded by a dashed line in FIG. 5. FIG. 7 is a cross-sectional view schematically showing another example of a passive electronic component according to a first comparative embodiment outside the scope of the present invention. FIG. 8 is a plan view schematically showing an example of a first internal electrode layer located in a portion surrounded by a dashed line in FIG. 7. FIG. 9A is a plan view schematically showing an example of the position of a second internal electrode layer formed above the first internal electrode layer shown in FIG. 8. 9B is a plan view schematically showing another example of the position of the second internal electrode layer formed above the first internal electrode layer shown in FIG. 8 . FIG. 10 is a plan view schematically showing an example of the position of the second internal electrode layer formed above the first internal electrode layer shown in FIG. 3 . FIG. 11 is a cross-sectional view schematically showing a step of forming an insulating layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 12 is a cross-sectional view schematically showing a step of forming a first internal electrode layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 13 is a cross-sectional view schematically showing a step of forming a first dielectric film in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 14 is a cross-sectional view schematically showing a step of forming a second internal electrode layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 15 is a cross-sectional view schematically showing a step of forming a through hole in the first dielectric film in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 16 is a cross-sectional view schematically showing a step of forming a resin protective layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 17 is a cross-sectional view schematically showing a step of forming a first external electrode and a second external electrode in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention.FIG. 18 is a cross-sectional view schematically showing an example of a passive electronic component according to a second embodiment of the present invention. FIG. 19 is a plan view schematically showing an example of a passive electronic component according to a third embodiment of the present invention. FIG. 20 is a cross-sectional view schematically showing an example of a passive electronic component according to a fourth embodiment of the present invention. FIG. 21 is a plan view of the passive electronic component shown in FIG. 20. FIG. 22 is a cross-sectional view schematically showing a step of forming an insulating layer in an example of a method for manufacturing a passive electronic component according to the fourth embodiment of the present invention. FIG. 23 is a cross-sectional view schematically showing a step of forming a first internal electrode layer in an example of a method for manufacturing a passive electronic component according to the fourth embodiment of the present invention. FIG. 24 is a cross-sectional view schematically showing a step of forming a first dielectric film in an example of a method for manufacturing a passive electronic component according to the fourth embodiment of the present invention. FIG. 25 is a cross-sectional view schematically showing a step of forming a second internal electrode layer in an example of a method for manufacturing a passive electronic component according to the fourth embodiment of the present invention. FIG. 26 is a cross-sectional view schematically showing a step of forming a second dielectric film in an example of a method for manufacturing a passive electronic component according to the fourth embodiment of the present invention. Fig. 27 is a cross-sectional view schematically showing a step of forming through holes in the first dielectric film and the second dielectric film in an example of a method for manufacturing a passive electronic component according to the fourth embodiment of the present invention. Fig. 28 is a cross-sectional view schematically showing a step of forming a third internal electrode layer in an example of a method for manufacturing a passive electronic component according to the fourth embodiment of the present invention. Fig. 29 is a cross-sectional view schematically showing a step of forming a through hole in the second dielectric film in an example of a method for manufacturing a passive electronic component according to the fourth embodiment of the present invention. Fig. 30 is a cross-sectional view schematically showing a step of forming a resin protective layer in an example of a method for manufacturing a passive electronic component according to the fourth embodiment of the present invention. Fig. 31 is a cross-sectional view schematically showing a step of forming first external electrodes and second external electrodes in an example of a method for manufacturing a passive electronic component according to the fourth embodiment of the present invention.

[0011] The passive electronic component of the present invention will be described below. Note that the present invention is not limited to the following configurations and may be modified as appropriate without departing from the spirit of the present invention. Furthermore, a combination of multiple individual preferred configurations described below also constitutes the present invention.

[0012] The following embodiments are merely examples, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, descriptions of matters common to the first embodiment will be omitted, and differences will be mainly described. In particular, similar effects resulting from similar configurations will not be mentioned one after the other for each embodiment.

[0013] In the following description, when there is no need to particularly distinguish between the embodiments, they will simply be referred to as "passive electronic components of the present invention."

[0014] In the following, an electronic component having a capacitor will be shown as an example of the passive electronic component of the present invention. The passive electronic component of the present invention may be a capacitor itself.

[0015] The drawings shown below are schematic diagrams, and the dimensions, aspect ratio, and other scales may differ from those of the actual product. In the drawings, the same or equivalent parts will be designated by the same reference numerals. In addition, the same elements will be designated by the same reference numerals in each drawing, and duplicate explanations will be omitted.

[0016] In this specification, unless otherwise specified, terms indicating the relationship between elements (e.g., "parallel," "perpendicular," "orthogonal," etc.) and terms indicating the shape of elements not only mean the strict literal aspects, but also mean a range that is substantially equivalent, for example, a range that includes a difference of about a few percent.

[0017] First Embodiment In a passive electronic component according to a first embodiment of the present invention, a capacitor includes a first internal electrode layer, a first dielectric film, and a second internal electrode layer.

[0018] FIG. 1 is a cross-sectional view schematically showing an example of a passive electronic component according to a first embodiment of the present invention.

[0019] In this specification, the length direction, width direction, and thickness direction of a passive electronic component are defined by arrows L, W, and T, respectively, as shown in Figure 1 etc. Here, the length direction L, width direction W, and thickness direction T are perpendicular to each other.

[0020] The passive electronic component 1 shown in FIG. 1 includes a substrate 10 and a capacitor 20 .

[0021] The substrate 10 has a first major surface 10a and a second major surface 10b that face each other in the thickness direction T.

[0022] Although not shown in FIG. 1, a charge trapping layer made of polycrystalline silicon or amorphous silicon may be provided on the first main surface 10a of the substrate 10.

[0023] The capacitor 20 is disposed on the first major surface 10 a of the substrate 10 .

[0024] The capacitor 20 includes a first internal electrode layer 31 provided on the first main surface 10a of the substrate 10, a first dielectric film 41 provided on the first internal electrode layer 31, and a second internal electrode layer 32 provided on the first dielectric film 41. Although not shown in Fig. 1, in the passive electronic component 1, a protective film (also referred to as a passivation film) may be provided on the first dielectric film 41 and the second internal electrode layer 32.

[0025] In the capacitor 20, a first internal electrode layer 31, a first dielectric film 41, and a second internal electrode layer 32 are laminated in this order to form a metal-insulator-metal (MIM) structure. In the capacitor 20, by applying a voltage between the first internal electrode layer 31 and the second internal electrode layer 32, charge can be stored in the first dielectric film 41.

[0026] 1 , the passive electronic component 1 may further include an insulating layer 15 between the substrate 10 and the capacitor 20. The passive electronic component 1 may further include a resin protective layer 50 covering the capacitor 20, a first external electrode 61 penetrating the resin protective layer 50 and connected to the first internal electrode layer 31 of the capacitor 20, and a second external electrode 62 penetrating the resin protective layer 50 and connected to the second internal electrode layer 32 of the capacitor 20.

[0027] Fig. 2 is a plan view schematically showing an example of a passive electronic component according to a first embodiment of the present invention. However, for convenience, Fig. 2 shows only the substrate 10, the first internal electrode layer 31, the second internal electrode layer 32, the first external electrode 61, and the second external electrode 62 of the passive electronic component 1 shown in Fig. 1. The same applies to the plan views of the subsequent passive electronic components.

[0028] Each component will be described in detail below.

[0029] The substrate 10 is not particularly limited, but is preferably a semiconductor substrate such as a silicon substrate or a gallium arsenide substrate, or an insulating substrate such as glass or alumina. In particular, the substrate 10 is preferably a silicon substrate, i.e., made of silicon.

[0030] The insulating layer 15 is preferably provided so as to cover the entire first main surface 10a of the substrate 10. The insulating layer 15 may be provided so as to cover a part of the first main surface 10a of the substrate 10, but it needs to be provided in an area that is larger than the first internal electrode layer 31 and overlaps the entire area of ​​the first internal electrode layer 31. When the substrate 10 is an insulating substrate such as glass or alumina, the insulating layer 15 does not need to be provided.

[0031] The material for the insulating layer 15 is not particularly limited, but is preferably SiO ２ , SiN, Al ２ O ３ , HfO ２ , Ta ２ O ５ , ZrO ２ Examples of insulating materials include:

[0032] The first internal electrode layers 31 are preferably provided at positions away from the ends of the substrate 10. In other words, the ends of the first internal electrode layers 31 are preferably located more inward than the ends of the substrate 10.

[0033] The material constituting the first internal electrode layer 31 is not particularly limited, but preferably includes conductive materials such as Cu, Ag, Au, Al, Ni, Cr, or Ti, or alloys containing at least one of these metals (e.g., AlSi, AlCu, AlSiCu, etc.). The same applies to materials constituting the internal electrode layers other than the first internal electrode layer 31.

[0034] The second internal electrode layer 32 is provided opposite to the first internal electrode layer 31 with the first dielectric film 41 interposed therebetween.

[0035] The first dielectric film 41 is preferably provided so as to cover the first internal electrode layer 31 except for the opening. In the example shown in Fig. 1, the first dielectric film 41 is also provided on the insulating layer 15. The end of the first dielectric film 41 may or may not extend to the end of the substrate 10.

[0036] The material for the first dielectric film 41 is not particularly limited, but is preferably SiO ２ , SiN, SiON, SiOC, SiOF, HfO ２ , HfSiO, Al ２ O ３ , Ta ２ O ５ The same applies to the materials constituting the dielectric films other than the first dielectric film 41.

[0037] When a protective film is provided on the first dielectric film 41 and the second internal electrode layer 32, the protective film is preferably provided so as to cover the first dielectric film 41 and the second internal electrode layer 32 except for the openings. The protective film enhances the passivation property of the first dielectric film 41. Note that the protective film does not necessarily have to be provided.

[0038] The material for forming the protective film is not particularly limited, but is preferably SiO ２ , SiN, and other insulating materials.

[0039] The resin protective layer 50 is provided so as to cover the capacitor 20 except for the openings. The resin protective layer 50 has openings that overlap the first internal electrode layers 31 and openings that overlap the second internal electrode layers 32. The provision of the resin protective layer 50 protects the first dielectric film 41 from external moisture and impact.

[0040] The material constituting the resin protective layer 50 is not particularly limited, but preferable examples include resin materials such as polyimide resin and resin in solder resist.

[0041] The material constituting the first external electrode 61 and the second external electrode 62 is not particularly limited, but preferably includes a conductive material such as Cu, Ni, Ag, Au, Al, or SnAg. The first external electrode 61 and the second external electrode 62 may have a single-layer structure or a multi-layer structure. The outermost surfaces of the first external electrode 61 and the second external electrode 62 are preferably made of Au, Sn, or SnAg.

[0042] FIG. 3 is a plan view schematically showing an example of a first internal electrode layer located in the area surrounded by the dashed line in FIG.

[0043] As shown in FIG. 3, in a plan view from the thickness direction T, the corners of the first internal electrode layer 31 are rounded.

[0044] FIG. 4 is an enlarged cross-sectional view of the portion surrounded by the dashed line in FIG.

[0045] As shown in FIG. 4 , in a cross-sectional view along the thickness direction T, the side surfaces of the first internal electrode layers 31 are inclined at an acute angle with respect to the first main surface 10 a of the substrate 10 .

[0046] Fig. 5 is a cross-sectional view schematically showing an example of a passive electronic component according to a first comparative example outside the scope of the present invention, and Fig. 6 is a plan view schematically showing an example of a first internal electrode layer located in a portion surrounded by a dashed line in Fig. 5.

[0047] In the passive electronic component 1a shown in FIG. 5, the corners of the first internal electrode layers 31 are not rounded but angular when viewed in a plan view from the thickness direction T, as shown in FIG.

[0048] Furthermore, as shown in FIG. 5 , in a cross-sectional view along the thickness direction T, the side surfaces of the first internal electrode layers 31 are perpendicular to the first main surface 10 a of the substrate 10 .

[0049] Therefore, in the passive electronic component 1 a shown in FIG. 5, voids G (see FIG. 5) called “voids” tend to occur inside the first dielectric film 41 near the corners of the first internal electrode layers 31 .

[0050] Fig. 7 is a cross-sectional view schematically showing another example of a passive electronic component according to a first comparative example outside the scope of the present invention, and Fig. 8 is a plan view schematically showing an example of a first internal electrode layer located in the area surrounded by a dashed line in Fig. 7.

[0051] In the passive electronic component 1b shown in FIG. 7, the corners of the first internal electrode layers 31 are not rounded but angular when viewed in a plan view from the thickness direction T, as shown in FIG.

[0052] On the other hand, as shown in FIG. 7, in a cross-sectional view along the thickness direction T, the side surfaces of the first internal electrode layers 31 are inclined at an acute angle with respect to the first main surface 10 a of the substrate 10 .

[0053] 8, the corners of the first internal electrode layer 31 are not rounded but angular, similar to the first internal electrode layer 31 shown in Fig. 6. Therefore, the first dielectric film 41 is likely to be formed locally thin near the corners of the first internal electrode layer 31.

[0054] Unlike the passive electronic component 1a shown in FIG. 5 and the passive electronic component 1b shown in FIG. 7, in the passive electronic component 1 shown in FIG. 1, the corners of the first internal electrode layers 31 are rounded in a plan view from the thickness direction T, and the side surfaces of the first internal electrode layers 31 are inclined at an acute angle with respect to the first main surface 10a of the substrate 10 in a cross-sectional view along the thickness direction T. This allows the first dielectric film 41 to be formed uniformly along the surface shapes of the substrate 10 and the first internal electrode layers 31, in other words, the first dielectric film 41 to be formed conformally. This makes it less likely that voids known as "voids" or locally thin portions will occur in the first dielectric film 41. This therefore increases the reliability of the capacitor 20.

[0055] Furthermore, since stress concentration at the corners of the first internal electrode layers 31 can be alleviated, it is possible to avoid defects such as peeling of the first internal electrode layers 31. Furthermore, since electric field concentration at the corners of the first internal electrode layers 31 can be alleviated, it is possible to increase the reliability of the capacitor 20.

[0056] Fig. 9A is a plan view schematically showing an example of the position of the second internal electrode layer formed above the first internal electrode layer shown in Fig. 8. Fig. 9B is a plan view schematically showing another example of the position of the second internal electrode layer formed above the first internal electrode layer shown in Fig. 8.

[0057] In order to increase the area where the capacitance of the capacitor 20 is formed, it is desirable to form the second internal electrode layer 32 so as to overlap the inclined side surface of the first internal electrode layer 31, as shown in Fig. 9A. However, if the corners of the first internal electrode layer 31 are sharp, in order to ensure the reliability of the capacitor 20, it is necessary to form the second internal electrode layer 32 so as to avoid the inclined side surface of the first internal electrode layer 31, as shown in Fig. 9B. This limits the area where the capacitance of the capacitor 20 is formed.

[0058] FIG. 10 is a plan view schematically showing an example of the position of the second internal electrode layer formed above the first internal electrode layer shown in FIG.

[0059] On the other hand, as shown in Fig. 10, if the corners of the first internal electrode layer 31 are rounded, there are no angular portions on the side surfaces of the first internal electrode layer 31, and therefore the second internal electrode layer 32 can be formed so as to overlap the inclined side surfaces of the first internal electrode layer 31. As a result, the distance between the upper and lower arrows in Fig. 10 can be reduced. Therefore, the area in which capacitance is formed can be expanded while ensuring the reliability of the capacitor 20.

[0060] 3 , in a plan view from the thickness direction T, the radius of curvature R1 of the corners of the first internal electrode layers 31 is preferably 5 times or more, more preferably 10 times or more, the thickness of the first internal electrode layers 31. If the radius of curvature R1 is smaller than 5 times the thickness of the first internal electrode layers 31, the conformality of the first dielectric films 41 formed on the upper parts of the first internal electrode layers 31 may be degraded. On the other hand, the radius of curvature R1 of the corners of the first internal electrode layers 31 is, for example, 30 times or less the thickness of the first internal electrode layers 31. If the radius of curvature R1 is larger than 30 times the thickness of the first internal electrode layers 31, the dimensional accuracy of the first internal electrode layers 31 may be degraded, and the deviation from the target capacitance value may be large.

[0061] 4, in a cross-sectional view along the thickness direction T, the angle α1 of the side surface of the first internal electrode layer 31 with respect to the first main surface 10a of the substrate 10 is preferably 30° or more and 75° or less, and more preferably 40° or more and 65° or less. If the angle α1 is smaller than 30°, the dimensional accuracy of the first internal electrode layer 31 may deteriorate, and the deviation from the target capacitance value may increase. Furthermore, if the angle α1 is larger than 75°, the conformality of the first dielectric film 41 formed on the upper part of the first internal electrode layer 31 may deteriorate.

[0062] In the passive electronic component 1 shown in Figure 1, when viewed in a plane from the thickness direction T, it is sufficient that at least some of the corners of the first internal electrode layer 31 are rounded, but it is preferable that all of the corners of the first internal electrode layer 31 are rounded.

[0063] In the passive electronic component 1 shown in Figure 1, when viewed in a cross section along the thickness direction T, it is sufficient that at least some of the side surfaces of the first internal electrode layer 31 are inclined at an acute angle relative to the first main surface 10a of the substrate 10, but it is preferable that all of the side surfaces of the first internal electrode layer 31 are inclined at an acute angle relative to the first main surface 10a of the substrate 10.

[0064] In the passive electronic component 1 shown in Figure 1, when viewed in a plane from the thickness direction T, the corners of the second internal electrode layer 32 may be rounded, and when viewed in a cross section along the thickness direction T, the side surface of the second internal electrode layer 32 may be inclined at an acute angle with respect to the first main surface 10a of the substrate 10.

[0065] 1 , if a protective film is provided on the first dielectric film 41 and on the second internal electrode layer 32, there is a risk of a defect similar to that of the first dielectric film 41. Therefore, if the corners of the second internal electrode layer 32 are rounded in a plan view from the thickness direction T, and if the side surfaces of the second internal electrode layer 32 are inclined at an acute angle with respect to the first main surface 10 a of the substrate 10 in a cross-sectional view along the thickness direction T, the defect of the protective film formed on the second internal electrode layer 32 can be avoided.

[0066] In a plan view from the thickness direction T, the radius of curvature R2 of the corners of the second internal electrode layers 32 is preferably 5 times or more, and more preferably 10 times or more, the thickness of the second internal electrode layers 32. On the other hand, the radius of curvature R2 of the corners of the second internal electrode layers 32 is, for example, 30 times or less the thickness of the second internal electrode layers 32. The radius of curvature R2 of the corners of the second internal electrode layers 32 may be the same as the radius of curvature R1 of the corners of the first internal electrode layers 31, or may be larger or smaller than the radius of curvature R1.

[0067] In a cross-sectional view along the thickness direction T, the angle α2 of the side surface of the second internal electrode layer 32 with respect to the first main surface 10a of the substrate 10 is preferably 30° or more and 75° or less, and more preferably 40° or more and 65° or less. The angle α2 of the side surface of the second internal electrode layer 32 with respect to the first main surface 10a of the substrate 10 may be the same as the angle α1 of the side surface of the first internal electrode layer 31 with respect to the first main surface 10a of the substrate 10, or may be larger than the angle α1, or may be smaller than the angle α1.

[0068] In the passive electronic component 1 shown in Figure 1, when viewed in a plane from the thickness direction T, if the corners of the second internal electrode layer 32 are rounded, it is sufficient that at least some of the corners of the second internal electrode layer 32 are rounded, but it is preferable that all of the corners of the second internal electrode layer 32 are rounded.

[0069] In the passive electronic component 1 shown in Figure 1, when viewed in a cross section along the thickness direction T, if the side surfaces of the second internal electrode layers 32 are inclined at an acute angle with respect to the first main surface 10a of the substrate 10, it is sufficient that at least some of the side surfaces of the second internal electrode layers 32 are inclined at an acute angle with respect to the first main surface 10a of the substrate 10, but it is preferable that all of the side surfaces of the second internal electrode layers 32 are inclined at an acute angle with respect to the first main surface 10a of the substrate 10.

[0070] The passive electronic component 1 shown in FIG. 1 is manufactured, for example, by the following method.

[0071] FIG. 11 is a cross-sectional view schematically showing a step of forming an insulating layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0072] As shown in FIG. 11, first, a substrate 10 is prepared.

[0073] Although not shown in FIG. 11 , a charge trapping layer made of polycrystalline silicon or amorphous silicon may be formed on the first main surface 10 a of the substrate 10 by a method such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0074] Next, an insulating layer 15 made of an insulating material is formed on the first main surface 10a of the substrate 10 by a method such as CVD or PVD. Thereafter, the insulating layer 15 is patterned by a combination of photolithography and etching. The step of forming the insulating layer 15 may be omitted.

[0075] FIG. 12 is a cross-sectional view schematically showing a step of forming a first internal electrode layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0076] 12, first internal electrode layers 31 made of a conductive material are formed by a method such as CVD or PVD so as to cover the structure shown in FIG. 11 from the first main surface 10a side of the substrate 10. Thereafter, the first internal electrode layers 31 are patterned by a combination of photolithography and etching.

[0077] At this time, photolithography is performed using a mask having a predetermined shape to round the corners of the first internal electrode layer 31. Furthermore, etching is performed so that the side surfaces of the first internal electrode layer 31 are inclined at an acute angle with respect to the first main surface 10a of the substrate 10.

[0078] FIG. 13 is a cross-sectional view schematically showing a step of forming a first dielectric film in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0079] 13, a first dielectric film 41 made of a dielectric material is formed by a method such as CVD, PVD, or atomic layer deposition (ALD) so as to cover the structure shown in FIG. 12 from the first main surface 10a side of the substrate 10. Thereafter, the first dielectric film 41 is patterned by a combination of photolithography and etching.

[0080] FIG. 14 is a cross-sectional view schematically showing a step of forming a second internal electrode layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0081] 14, second internal electrode layers 32 made of a conductive material are formed by a method such as CVD or PVD so as to cover the structure shown in FIG. 13 from the first main surface 10a side of the substrate 10. Thereafter, the second internal electrode layers 32 are patterned by a combination of photolithography and etching.

[0082] At this time, photolithography may be performed using a mask having a predetermined shape to round the corners of the second internal electrode layers 32. Furthermore, etching may be performed so that the side surfaces of the second internal electrode layers 32 are inclined at an acute angle with respect to the first main surface 10a of the substrate 10.

[0083] FIG. 15 is a cross-sectional view schematically showing a step of forming a through hole in the first dielectric film in the example of the method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0084] As shown in FIG. 15, a through-hole is formed through the first dielectric film 41 by a combination of photolithography and etching so that a part of the first internal electrode layer 31 is exposed.

[0085] Although not shown in Figure 15, a protective film made of an insulating material may be formed by a method such as CVD or PVD so as to cover the structure shown in Figure 15 from the first main surface 10a side of the substrate 10. Thereafter, the protective film is patterned by a combination of photolithography and etching. Specifically, the protective film is formed so as to cover the second internal electrode layers 32 and the first dielectric films 41 from the first main surface 10a side of the substrate 10. At this time, through holes are formed through the protective film so that parts of the second internal electrode layers 32 are exposed. Furthermore, through holes are formed through the protective film at positions overlapping the through holes in the first dielectric films 41 so that parts of the first internal electrode layers 31 are exposed.

[0086] FIG. 16 is a cross-sectional view schematically showing a step of forming a resin protective layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0087] 16, a resin protective layer 50 made of a resin material is formed by a method such as spin coating so as to cover the structure shown in FIG. 15 from the first main surface 10a side of the substrate 10. Thereafter, the resin protective layer 50 is patterned by using only photolithography if the resin material of the resin protective layer 50 is photosensitive, or by using a combination of photolithography and etching if the resin material of the resin protective layer 50 is non-photosensitive. At this time, through holes are provided through the resin protective layer 50 so that parts of the first internal electrode layers 31 and second internal electrode layers 32 are exposed.

[0088] FIG. 17 is a cross-sectional view schematically showing a step of forming a first external electrode and a second external electrode in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0089] 17 , the first external electrode 61 and the second external electrode 62 are formed by a method such as lift-off, plating, or etching. More specifically, the first external electrode 61 is formed so as to fill the through hole of the first dielectric film 41 and the through hole of the resin protective layer 50, and the second external electrode 62 is formed so as to fill the through hole of the resin protective layer 50.

[0090] Through the above steps, the capacitor 20 is formed.

[0091] If necessary, the substrate 10 may be thinned to a desired device thickness by back grinding.

[0092] In this way, the passive electronic component 1 is manufactured.

[0093] Second Embodiment A passive electronic component according to a second embodiment of the present invention further includes an electrostatic discharge (ESD) protection diode.

[0094] FIG. 18 is a cross-sectional view schematically showing an example of a passive electronic component according to a second embodiment of the present invention.

[0095] The passive electronic component 2 shown in FIG. 18 has a common configuration with the passive electronic component 1 shown in FIG. 1, except that it further includes an ESD protection diode 70 .

[0096] The ESD protection diode 70 is disposed inside the substrate 10 and is connected to the first internal electrode layer 31 and the second internal electrode layer 32, respectively.

[0097] The ESD protection diode 70 is not particularly limited, but may be, for example, a transient voltage suppressor (TVS) diode.

[0098] As in the passive electronic component 2 shown in FIG. 18, the ESD protection diode 70 is disposed inside the substrate 10, thereby improving the ESD breakdown voltage.

[0099] Third Embodiment In a passive electronic component according to a third embodiment of the present invention, two or more capacitors are arranged side by side on a first main surface of a substrate.

[0100] FIG. 19 is a plan view schematically showing an example of a passive electronic component according to a third embodiment of the present invention.

[0101] In the passive electronic component 3 shown in Fig. 19, two or more capacitors 20 are arranged side by side on the first main surface 10a (see Fig. 1, etc.) of the substrate 10. In the example shown in Fig. 19, two capacitors 20 are arranged on the first main surface 10a of the substrate 10, but three or more capacitors 20 may be arranged. This allows the multiple capacitors 20 to be arranged at high density.

[0102] 19, it is preferable that at least one set of capacitors 20 are arranged adjacent to each other in a plan view from the thickness direction T. In the example shown in Fig. 19, the internal electrode patterns of two capacitors 20 are arranged in line symmetry with respect to the longitudinal direction L.

[0103] When three or more capacitors 20 are arranged on the first main surface 10a of the substrate 10, it is preferable that two or more capacitors 20 are arranged adjacent to each other when viewed in a plane from the thickness direction T, and it is more preferable that all of the capacitors 20 are arranged adjacent to each other.

[0104] Fourth Embodiment In a passive electronic component according to a fourth embodiment of the present invention, the capacitor further includes a second dielectric film and a third internal electrode layer.

[0105] Fig. 20 is a cross-sectional view schematically showing an example of a passive electronic component according to a fourth embodiment of the present invention, and Fig. 21 is a plan view of the passive electronic component shown in Fig. 20.

[0106] The passive electronic component 4 shown in FIGS. 20 and 21 has a common configuration with the passive electronic component 1 shown in FIG. 1, except that the configuration of the capacitor 21 is different from the configuration of the capacitor 20.

[0107] The capacitor 21 includes a first internal electrode layer 31 provided on the first main surface 10a of the substrate 10, a first dielectric film 41 provided on the first internal electrode layer 31, and a second internal electrode layer 32 provided on the first dielectric film 41. The capacitor 21 further includes a second dielectric film 42 provided on the second internal electrode layer 32, and a third internal electrode layer 33 provided on the second dielectric film 42 and connected to the first internal electrode layer 31. Although not shown in Fig. 20 , in the passive electronic component 4, a protective film (also referred to as a passivation film) may be provided on the second dielectric film 42 and the third internal electrode layer 33.

[0108] In the capacitor 21, the first internal electrode layer 31, the first dielectric film 41, the second internal electrode layer 32, the second dielectric film 42, and the third internal electrode layer 33 are laminated in this order to form an MIM structure. Therefore, the capacitance density of the capacitor 21 can be made higher than that of the capacitor 20.

[0109] 20 and 21, three internal electrode layers and two dielectric films are stacked, but more internal electrode layers and dielectric films may be stacked. By increasing the number of stacked internal electrode layers and dielectric films, the capacitance density of the capacitor 21 can be further increased.

[0110] 20 and 21 , in a plan view from the thickness direction T, the corners of the first internal electrode layers 31 are rounded, and in a cross-sectional view along the thickness direction T, the side surfaces of the first internal electrode layers 31 are inclined at an acute angle with respect to the first main surface 10 a of the substrate 10. This provides the effects described in the first embodiment.

[0111] The preferred range of the radius of curvature R1 of the corners of the first internal electrode layers 31 in plan view from the thickness direction T is the same as in the first embodiment.

[0112] The preferred range of the angle α1 of the side surface of the first internal electrode layer 31 relative to the first main surface 10a of the substrate 10 in a cross section taken along the thickness direction T is the same as in the first embodiment.

[0113] In the passive electronic component 4 shown in Figures 20 and 21, when viewed in a plane from the thickness direction T, it is sufficient that at least some of the corners of the first internal electrode layer 31 are rounded, but it is preferable that all of the corners of the first internal electrode layer 31 are rounded.

[0114] In the passive electronic component 4 shown in Figures 20 and 21, when viewed in cross section along the thickness direction T, it is sufficient that at least some of the side surfaces of the first internal electrode layer 31 are inclined at an acute angle relative to the first main surface 10a of the substrate 10, but it is preferable that all of the side surfaces of the first internal electrode layer 31 are inclined at an acute angle relative to the first main surface 10a of the substrate 10.

[0115] In the passive electronic component 4 shown in Figures 20 and 21, when viewed in a plane from the thickness direction T, the corners of the second internal electrode layer 32 may be rounded, and when viewed in a cross-section along the thickness direction T, the side surfaces of the second internal electrode layer 32 may be inclined at an acute angle with respect to the first main surface 10a of the substrate 10.

[0116] 20 and 21 , the second dielectric film 42 is provided on the first dielectric film 41 and on the second internal electrode layer 32, and therefore there is a risk of the same problems occurring as with the first dielectric film 41. Therefore, if the corners of the second internal electrode layer 32 are rounded in plan view from the thickness direction T, and if the side surfaces of the second internal electrode layer 32 are inclined at an acute angle with respect to the first main surface 10 a of the substrate 10 in cross-sectional view along the thickness direction T, then the problems with the second dielectric film 42 formed on the second internal electrode layer 32 can be avoided.

[0117] The preferred range of the radius of curvature R2 of the corners of the second internal electrode layers 32 in a plan view from the thickness direction T is the same as that in the first embodiment. The radius of curvature R2 of the corners of the second internal electrode layers 32 may be the same as the radius of curvature R1 of the corners of the first internal electrode layers 31, or may be larger than the radius of curvature R1, or may be smaller than the radius of curvature R1.

[0118] In a cross-sectional view along the thickness direction T, the preferred numerical range of the angle α2 of the side surface of the second internal electrode layer 32 with respect to the first main surface 10a of the substrate 10 is the same as that in the first embodiment. The angle α2 of the side surface of the second internal electrode layer 32 with respect to the first main surface 10a of the substrate 10 may be the same as the angle α1 of the side surface of the first internal electrode layer 31 with respect to the first main surface 10a of the substrate 10, or may be greater than the angle α1, or may be smaller than the angle α1.

[0119] In the passive electronic component 4 shown in Figures 20 and 21, when viewed in a plane from the thickness direction T, if the corners of the second internal electrode layer 32 are rounded, it is sufficient that at least some of the corners of the second internal electrode layer 32 are rounded, but it is preferable that all of the corners of the second internal electrode layer 32 are rounded.

[0120] In the passive electronic component 4 shown in Figures 20 and 21, when viewed in a cross section along the thickness direction T, if the side surfaces of the second internal electrode layers 32 are inclined at an acute angle relative to the first main surface 10a of the substrate 10, it is sufficient that at least some of the side surfaces of the second internal electrode layers 32 are inclined at an acute angle relative to the first main surface 10a of the substrate 10, but it is preferable that all of the side surfaces of the second internal electrode layers 32 are inclined at an acute angle relative to the first main surface 10a of the substrate 10.

[0121] In the passive electronic component 4 shown in Figures 20 and 21, when viewed in a plane from the thickness direction T, the corners of the third internal electrode layer 33 may be rounded, and when viewed in a cross-section along the thickness direction T, the side surfaces of the third internal electrode layer 33 may be inclined at an acute angle with respect to the first main surface 10a of the substrate 10.

[0122] 20 and 21 , when a protective film is provided on the second dielectric film 42 and the third internal electrode layer 33, there is a risk of the same problem as with the first dielectric film 41. Therefore, if the corners of the third internal electrode layer 33 are rounded in plan view from the thickness direction T, and if the side surfaces of the third internal electrode layer 33 are inclined at an acute angle with respect to the first main surface 10 a of the substrate 10 in a cross-sectional view along the thickness direction T, the problem of the protective film formed on the third internal electrode layer 33 can be avoided.

[0123] In a plan view from the thickness direction T, the radius of curvature R3 of the corners of the third internal electrode layers 33 is preferably 5 times or more, more preferably 10 times or more, the thickness of the third internal electrode layers 33. On the other hand, the radius of curvature R3 of the corners of the third internal electrode layers 33 is, for example, 30 times or less the thickness of the third internal electrode layers 33. The radius of curvature R3 of the corners of the third internal electrode layers 33 may be the same as the radius of curvature R1 of the corners of the first internal electrode layers 31, or may be larger or smaller than the radius of curvature R1. Furthermore, the radius of curvature R3 of the corners of the third internal electrode layers 33 may be the same as the radius of curvature R2 of the corners of the second internal electrode layers 32, or may be larger or smaller than the radius of curvature R2.

[0124] In a cross-sectional view along the thickness direction T, the angle α3 of the side surface of the third internal electrode layer 33 with respect to the first main surface 10a of the substrate 10 is preferably 30° or more and 75° or less, and more preferably 40° or more and 65° or less. The angle α3 of the side surface of the third internal electrode layer 33 with respect to the first main surface 10a of the substrate 10 may be the same as the angle α1 of the side surface of the first internal electrode layer 31 with respect to the first main surface 10a of the substrate 10, or may be greater than the angle α1, or may be smaller than the angle α1. Furthermore, the angle α3 of the side surface of the third internal electrode layer 33 with respect to the first main surface 10a of the substrate 10 may be the same as the angle α2 of the side surface of the second internal electrode layer 32 with respect to the first main surface 10a of the substrate 10, or may be greater than the angle α2, or may be smaller than the angle α2.

[0125] In the passive electronic component 4 shown in Figures 20 and 21, when viewed in a plane from the thickness direction T, if the corners of the third internal electrode layer 33 are rounded, it is sufficient that at least some of the corners of the third internal electrode layer 33 are rounded, but it is preferable that all of the corners of the third internal electrode layer 33 are rounded.

[0126] In the passive electronic component 4 shown in Figures 20 and 21, when viewed in a cross section along the thickness direction T, if the side surfaces of the third internal electrode layer 33 are inclined at an acute angle with respect to the first main surface 10a of the substrate 10, it is sufficient that at least some of the side surfaces of the third internal electrode layer 33 are inclined at an acute angle with respect to the first main surface 10a of the substrate 10, but it is preferable that all of the side surfaces of the third internal electrode layer 33 are inclined at an acute angle with respect to the first main surface 10a of the substrate 10.

[0127] The passive electronic component 4 shown in FIG. 20 is manufactured, for example, by the following method.

[0128] FIG. 22 is a cross-sectional view schematically showing a step of forming an insulating layer in an example of a method for manufacturing a passive electronic component according to a fourth embodiment of the present invention.

[0129] In the step shown in FIG. 22, similarly to the step shown in FIG. 11, an insulating layer 15 is formed on the first main surface 10a of the substrate 10.

[0130] FIG. 23 is a cross-sectional view schematically showing a step of forming a first internal electrode layer in an example of a method for manufacturing a passive electronic component according to a fourth embodiment of the present invention.

[0131] In the step shown in FIG. 23, the first internal electrode layer 31 is formed in the same manner as in the step shown in FIG.

[0132] At this time, photolithography is performed using a mask having a predetermined shape to round the corners of the first internal electrode layer 31. Furthermore, etching is performed so that the side surfaces of the first internal electrode layer 31 are inclined at an acute angle with respect to the first main surface 10a of the substrate 10.

[0133] FIG. 24 is a cross-sectional view schematically showing a step of forming a first dielectric film in an example of a method for manufacturing a passive electronic component according to a fourth embodiment of the present invention.

[0134] In the step shown in FIG. 24, the first dielectric film 41 is formed in the same manner as in the step shown in FIG.

[0135] FIG. 25 is a cross-sectional view schematically showing a step of forming a second internal electrode layer in an example of a method for manufacturing a passive electronic component according to a fourth embodiment of the present invention.

[0136] In the step shown in FIG. 25, the second internal electrode layer 32 is formed in the same manner as in the step shown in FIG.

[0137] At this time, photolithography may be performed using a mask having a predetermined shape to round the corners of the second internal electrode layers 32. Furthermore, etching may be performed so that the side surfaces of the second internal electrode layers 32 are inclined at an acute angle with respect to the first main surface 10a of the substrate 10.

[0138] FIG. 26 is a cross-sectional view schematically showing a step of forming a second dielectric film in an example of a method for manufacturing a passive electronic component according to a fourth embodiment of the present invention.

[0139] 26, a second dielectric film 42 made of a dielectric material is formed by a method such as CVD, PVD, or ALD so as to cover the structure shown in FIG. 25 from the first main surface 10a side of the substrate 10. Thereafter, the second dielectric film 42 is patterned by a combination of photolithography and etching.

[0140] FIG. 27 is a cross-sectional view schematically showing a step of forming through holes in the first dielectric film and the second dielectric film in an example of a method for manufacturing a passive electronic component according to the fourth embodiment of the present invention.

[0141] As shown in FIG. 27, a through hole is formed through the first dielectric film 41 and the second dielectric film 42 by using a combination of photolithography and etching so that a portion of the first internal electrode layer 31 is exposed.

[0142] FIG. 28 is a cross-sectional view schematically showing a step of forming a third internal electrode layer in an example of a method for manufacturing a passive electronic component according to a fourth embodiment of the present invention.

[0143] As shown in Fig. 28 , a third internal electrode layer 33 made of a conductive material is formed by a method such as CVD or PVD so as to cover the structure shown in Fig. 27 from the first main surface 10a side of the substrate 10. As shown in Fig. 28 , the third internal electrode layer 33 is formed so as to fill the through holes of the first dielectric film 41 and the second dielectric film 42. Thereafter, the third internal electrode layer 33 is patterned by a combination of photolithography and etching. As shown in Fig. 28 , the third internal electrode layer 33 is formed so as to be connected to the first internal electrode layer 31.

[0144] At this time, photolithography may be performed using a mask having a predetermined shape to round the corners of the third internal electrode layers 33. Furthermore, etching may be performed so that the side surfaces of the third internal electrode layers 33 are inclined at an acute angle with respect to the first main surface 10a of the substrate 10.

[0145] FIG. 29 is a cross-sectional view schematically showing a step of forming a through hole in the second dielectric film in an example of a method for manufacturing a passive electronic component according to a fourth embodiment of the present invention.

[0146] As shown in FIG. 29, a through-hole is formed through the second dielectric film 42 by a combination of photolithography and etching so that a part of the second internal electrode layer 32 is exposed.

[0147] Although not shown in Figure 29, a protective film made of an insulating material may be formed by a method such as CVD or PVD so as to cover the structure shown in Figure 29 from the first main surface 10a side of the substrate 10. Thereafter, the protective film is patterned by a combination of photolithography and etching. Specifically, the protective film is formed so as to cover the third internal electrode layer 33 and the second dielectric film 42 from the first main surface 10a side of the substrate 10. At this time, through holes are formed through the protective film at positions overlapping the through holes of the second dielectric film 42 so as to expose portions of the second internal electrode layers 32. Furthermore, through holes are formed through the protective film so as to expose portions of the third internal electrode layers 33.

[0148] FIG. 30 is a cross-sectional view schematically showing a step of forming a resin protective layer in an example of a method for manufacturing a passive electronic component according to a fourth embodiment of the present invention.

[0149] In the step shown in FIG. 30, the resin protective layer 50 is formed in the same manner as in the step shown in FIG.

[0150] FIG. 31 is a cross-sectional view schematically showing a step of forming a first external electrode and a second external electrode in an example of a method for manufacturing a passive electronic component according to a fourth embodiment of the present invention.

[0151] In the step shown in FIG. 31, the first external electrode 61 and the second external electrode 62 are formed in the same manner as in the step shown in FIG.

[0152] Through the above steps, the capacitor 21 is formed.

[0153] If necessary, the substrate 10 may be thinned to a desired device thickness by back grinding.

[0154] In this way, the passive electronic component 4 is manufactured.

[0155] The passive electronic component of the present invention is not limited to the above-described embodiment, and various applications and modifications can be made within the scope of the present invention with respect to the configuration of the substrate or capacitor, manufacturing conditions, and the like.

[0156] In the passive electronic component of the present invention, the number of stacked internal electrode layers constituting the capacitor is not particularly limited, and may be two, three, or four or more. In either case, it is sufficient that the corners of the first internal electrode layer are rounded in a plan view from the thickness direction, and the side surfaces of the first internal electrode layer are inclined at an acute angle with respect to the first main surface of the substrate in a cross-sectional view along the thickness direction. With respect to the nth internal electrode layer (n is a natural number) from the second internal electrode layer onwards, the corners of the nth internal electrode layer may or may not be rounded in a plan view from the thickness direction. Furthermore, in a cross-sectional view along the thickness direction, the side surfaces of the nth internal electrode layer may or may not be inclined at an acute angle with respect to the first main surface of the substrate.

[0157] In the passive electronic component of the present invention, when two or more capacitors are arranged side by side on the first main surface of the substrate, at least one of the capacitors may be a capacitor within the scope of the present invention, and may include a capacitor according to a different embodiment.

[0158] The present specification discloses the following:

[0159] <1> A passive electronic component comprising: a substrate having a first main surface and a second main surface opposing each other in a thickness direction; and a capacitor arranged on the first main surface of the substrate, wherein the capacitor includes a first internal electrode layer provided on the first main surface of the substrate, a first dielectric film provided on the first internal electrode layer, and a second internal electrode layer provided on the first dielectric film, wherein corners of the first internal electrode layer are rounded in a plan view from the thickness direction, and a side surface of the first internal electrode layer is inclined at an acute angle with respect to the first main surface of the substrate in a cross-sectional view along the thickness direction.

[0160] <2> The passive electronic component according to <1>, wherein, in a plan view from the thickness direction, corners of the second internal electrode layer are rounded, and in a cross-sectional view along the thickness direction, side surfaces of the second internal electrode layer are inclined at an acute angle with respect to the first main surface of the substrate.

[0161] <3> The passive electronic component according to <1> or <2>, further comprising ESD protection diodes arranged inside the substrate and connected to the first internal electrode layer and the second internal electrode layer, respectively.

[0162] <4> The passive electronic component according to any one of <1> to <3>, wherein two or more of the capacitors are arranged side by side on the first main surface of the substrate.

[0163] <5> The passive electronic component according to <4>, wherein at least one pair of the capacitors are arranged adjacent to each other in a plan view in the thickness direction.

[0164] <6> The passive electronic component according to any one of <1> to <5>, wherein the capacitor further includes a second dielectric film provided on the second internal electrode layer, and a third internal electrode layer provided on the second dielectric film and connected to the first internal electrode layer.

[0165] <7> The passive electronic component according to <6>, wherein corners of the third internal electrode layer are rounded in a plan view from the thickness direction, and a side surface of the third internal electrode layer is inclined at an acute angle with respect to the first main surface of the substrate in a cross-sectional view along the thickness direction.

[0166] <8> The passive electronic component according to any one of <1> to <7>, wherein, in a plan view from the thickness direction, a radius of curvature of a corner of the first internal electrode layer is 5 times or more the thickness of the first internal electrode layer.

[0167] <9> The passive electronic component according to any one of <1> to <8>, wherein, in a cross-sectional view along the thickness direction, an angle of a side surface of the first internal electrode layer with respect to the first main surface of the substrate is 30° or more and 75° or less.

[0168] REFERENCE SIGNS 1, 1a, 1b, 2, 3, 4 Passive electronic component 10 Substrate 10a First main surface 10b Second main surface 15 Insulating layer 20, 21 Capacitor 31 First internal electrode layer 32 Second internal electrode layer 33 Third internal electrode layer 41 First dielectric film 42 Second dielectric film 50 Resin protective layer 61 First external electrode 62 Second external electrode 70 ESD protection diode G Air gap L Length direction T Thickness direction W Width direction

Claims

a substrate having a first main surface and a second main surface opposing each other in a thickness direction; a capacitor disposed on the first major surface of the substrate; the capacitor includes a first internal electrode layer provided on the first main surface of the substrate, a first dielectric film provided on the first internal electrode layer, and a second internal electrode layer provided on the first dielectric film, When viewed from above in the thickness direction, the corners of the first internal electrode layers are rounded, a side surface of the first internal electrode layer inclined at an acute angle with respect to the first main surface of the substrate in a cross-sectional view along the thickness direction; 　 When viewed from above in the thickness direction, the corners of the second internal electrode layers are rounded, 2. The passive electronic component according to claim 1, wherein, in a cross-sectional view along the thickness direction, a side surface of the second internal electrode layer is inclined at an acute angle with respect to the first main surface of the substrate.

3. The passive electronic component according to claim 1, further comprising ESD protection diodes disposed inside the substrate and connected to the first internal electrode layer and the second internal electrode layer, respectively.

4. The passive electronic component according to claim 1, wherein two or more of the capacitors are arranged side by side on the first main surface of the substrate. 　 The passive electronic component according to claim 4 , wherein at least one set of the capacitors are arranged adjacent to each other in a plan view in the thickness direction. 　 The passive electronic component according to any one of claims 1 to 5, wherein the capacitor further includes a second dielectric film provided on the second internal electrode layer, and a third internal electrode layer provided on the second dielectric film and connected to the first internal electrode layer. 　 When viewed from above in the thickness direction, the corners of the third internal electrode layers are rounded, 7. The passive electronic component according to claim 6, wherein, in a cross-sectional view along the thickness direction, a side surface of the third internal electrode layer is inclined at an acute angle with respect to the first main surface of the substrate. 　 A passive electronic component according to any one of claims 1 to 7, wherein, in a plan view from the thickness direction, the radius of curvature of the corners of the first internal electrode layer is 5 times or more the thickness of the first internal electrode layer. 　 A passive electronic component according to any one of claims 1 to 8, wherein, in a cross-sectional view along the thickness direction, an angle of the side surface of the first internal electrode layer relative to the first main surface of the substrate is 30° or more and 75° or less.

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