Waveguide located over deep oxide filled trench and method of making thereof

Abstract

An optical device includes a substrate containing a trench, an oxide secondary cladding containing a first portion filling the trench and having a planar top surface, an oxide primary cladding located on the planar top surface of the oxide secondary cladding, and a first waveguide core embedded in the oxide primary cladding.

Description

WAVEGUIDE LOCATED OVER DEEP OXIDE FILLED TRENCH AND METHOD OF MAKING THEREOFBACKGROUND

[0001] Photonic integrated circuits, such as silicon photonic integrated circuits, can be used in many systems, such as quantum communication systems and optical quantum computing systems. These quantum mechanics-based systems are distinguished from “classical” systems by their reliance on quantum states, such as quantum bits (qubits). To achieve the desired functions and performance, a quantum mechanics-based system may integrate many passive and active photonic devices, modules, and subsystems into the same system. For example, an optical quantum computer may need to integrate passive and active photonic integrated circuits and other optical and electrical components, such as optical fibers or other low-loss optical interconnects, control circuits, and classical processing units, into a same system, to reliably generate, manipulate (e.g., entangle), and detect hundreds, thousands, or even millions of qubits for computing and error corrections, while achieving the desired functions and performance.SUMMARY

[0002] According to certain embodiments, an optical device includes a substrate containing a trench, an oxide secondary cladding containing a first portion filling the trench and having a planar top surface, an oxide primary cladding located on the planar top surface of the oxide secondary cladding, and a first waveguide core embedded in the oxide primary cladding.

[0003] According to certain embodiments, a method comprises forming a trench in a substrate; forming a first oxide layer having a first portion located over a top surface of the substrate and a second portion partially filling the trench; removing at least a part of the first portion of the first oxide layer from over the top surface of the substrate, while leaving the second portion in the trench; forming a second oxide layer having a first portion located over a top surface of the substrate and a second portion located in a recess in the second portion of the first oxide layer in the trench; and planarizing the second oxide layer to remove the first portion of the second oxide layer from over the top surface of the substrate, while leaving the second portion of the second oxide layer in the trench.

[0004] According to certain embodiments, a method comprises: forming a plurality of trenches in a semiconductor substrate, wherein the plurality of trenches are laterally separated from each other by remaining semiconductor fin portions of the semiconductor substrate; and oxidizing the fin portions to convert the semiconductor fin portions to semiconductor oxide fin portions and to completely fill the plurality of trenches with the semiconductor oxide to form a continuous semiconductor oxide fill region in the semiconductor substrate.

[0005] In some embodiments a system may include a first photonic integrated circuit (PIC) die that includes a substrate including an optical fiber alignment structure formed thereon;, a single photon generator on the substrate and configured to generate single photons, an optical waveguide on the substrate and configured to transport the single photons, a spot size converter coupled to the optical waveguide and aligned with the optical fiber alignment structure, and an optical fiber including a first fiber end that is positioned on the optical fiber alignment structure and is coupled to the first end of the spot size converter. The spot size converter may have a first end and a second end, and may include an oxide layer characterized by a first refractive index, a waveguide core in the oxide layer, and a cladding layer surrounding the oxide layer. The waveguide core may be tapered and may have a first cross-section at the first end of the spot size converter and a second cross-section at the second end of the spot size converter, where the first cross-section may be smaller than the second cross-section. The cladding layer having a second refractive index lower than the first refractive index of the oxide layer

[0006] In some embodiments, the system may include an optical fiber positioned on the optical fiber alignment structure and optically coupled to the first end of the spot size converter, where the optical fiber is secured to the optical fiber alignment structure by the cladding layer. The optical fiber may include a single-mode optical fiber or a multi-mode optical fiber. In some embodiments, a center of a fiber core of the optical fiber may be vertically offset from a center of the waveguide core at the first end of the spot size converter. In some embodiments, a diameter of a fiber core of the optical fiber is smaller than the first width of the oxide layer at the first end of the spot size converter. In some embodiments, a coupling efficiency from the optical fiber to the second end of the spot size converter is greater than 95% for both transverse electric mode light and transverse magnetic mode light.

[0007] In some embodiments, a difference between the first refractive index and the second refractive index is between about 0.0015 and about 0.01 or higher. In some embodiments, at least a portion of the oxide layer of the spot size converter may be taperedsuch that a first width of the oxide layer at the first end of the spot size converter is smaller than a second width of the oxide layer at the second end of the spot size converter. In some embodiments, the optical waveguide may be configured to transport qubits, qudits, entangled states of qubits, logical qubits, or a combination thereof. The optical fiber alignment structure may include, for example, a V-groove.

[0008] In some embodiments, the waveguide core may include silicon nitride, the oxide layer may include silicon oxide, and the cladding layer may include an epoxy. A coupling efficiency between the first fiber end of the optical fiber and the optical waveguide is greater than 95% for both transverse electric mode light and transverse magnetic mode light. In some embodiments, the first PIC die may include a heater configured to tune the second refractive index of the cladding layer of the spot size converter.

[0009] In some embodiments, the first PIC die may include an oxide slab at the first end of the spot size converter, the oxide slab connecting the oxide layer at the first end of the spot size converter to an oxide region supported by the substrate. In some embodiments, the first PIC die may include a plurality of oxide ribs connecting the oxide layer of the spot size converter to an oxide region supported by the substrate. In some embodiments, the system may include a second PIC die, where the second PIC die may include a second spot size converter coupled to a second fiber end of the optical fiber. The second PIC die may include a routing waveguide, a beam splitter, a filter, a delay line, a fusion gate, a polarization splitter, a polarization rotator, an optical switch, a single photon detector, a dispersion compensator, a photodetector, or a combination thereof.

[0010] This summary is neither intended to identify key or essential features of the claimed subject matter, nor is it intended to be used in isolation to determine the scope of the claimed subject matter. The subject matter should be understood by reference to appropriate portions of the entire specification of this disclosure, any or all drawings, and each claim. The foregoing, together with other features and examples, will be described in more detail below in the following specification, claims, and accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Aspects of the present disclosure are illustrated by way of example. Non-limiting and non-exhaustive aspects are described with reference to the following figures, whereinlike reference numerals refer to like parts throughout the various figures unless otherwise specified.

[0012] FIG. 1A is a top view of an example of an optical module including a photonic integrated circuit die coupled to optical fibers according to certain embodiments.

[0013] FIG. IB is a cross-sectional view of the example package shown in FIG. 1A according to certain embodiments.

[0014] FIG. 1C is another across-sectional view of the example package shown in FIG. 1 according to certain embodiments.

[0015] FIG. 2 is a simplified block diagram of an example of a quantum computing system according to some embodiments.

[0016] FIG. 3 illustrates an example of a subsystem for generating entangled quantum states (e.g., resource states or logical qubits) according to certain embodiments.

[0017] FIG. 4A is a top view of an example of a wafer-scale module including multiple EPIC die stacks on a handle wafer according to certain embodiments.

[0018] FIG. 4B illustrates an example of a system including multiple wafer-scale modules interconnected using optical fibers according to certain embodiments.

[0019] FIG. 5 is a cross-sectional view of an example of a wafer-scale module according to certain embodiments.

[0020] FIGS. 6A-6C illustrate an example of a structure including a spot size converter according to certain embodiments.

[0021] FIG. 7A illustrates an example of a spot size converter according to certain embodiments.

[0022] FIG. 7B illustrates simulated coupling efficiencies of examples of spot size converters having different core sizes according to certain embodiments.

[0023] FIG. 8 illustrates an example of a structure that includes a spot size converter having a lower-index secondary cladding layer according to certain embodiments.

[0024] FIGS. 9A-9C illustrate an example of a structure including a spot size converter according to certain embodiments.

[0025] FIGS. 10A-10C illustrate another example of a structure including a spot size converter according to certain embodiments.

[0026] FIG. HA illustrates an example of a mode field of a guided optical mode in an optical fiber according to certain embodiments.

[0027] FIG. 1 IB illustrates an example of a mode field of a guided optical mode converted by a spot size converter according to certain embodiments.

[0028] FIG. 12A illustrates an example of a spot size converter including a lower-index secondary cladding layer according to certain embodiments.

[0029] FIG. 12B includes a curve showing the simulated coupling efficiency of an example of a spot size converter as a function of the primary cladding layer thickness.

[0030] FIG. 13 A illustrates the simulated coupling efficiency of an example of a spot size converter as a function of the width of a tapered core of the spot size converter at the smaller end and the height (and width) of a primary cladding layer of the spot size converter according to certain embodiments.

[0031] FIG. 13B illustrates the simulated coupling efficiency of an example of a spot size converter as a function of the width of a tapered core of the spot size converter at the smaller end according to certain embodiments.

[0032] FIG. 13C illustrates the simulated coupling efficiency of an example of a spot size converter as a function of the height (and width) of a primary cladding layer of the spot size converter according to certain embodiments.

[0033] FIG. 14 illustrates the simulated coupling efficiency of an example of a spot size converter as a function of the refractive index contrast between the primary cladding layer and the secondary cladding layer of the spot size converter according to certain embodiments.

[0034] FIGS. 15A and 15B illustrate an example of a spot size converter including a lower- index secondary cladding layer according to certain embodiments. FIG. 15C illustrates the simulated coupling efficiency of an example of a spot size converter as a function of a gap between an optical fiber and the spot size converter or the recess of a tapered core of the spot size converter from the tip of spot size converter according to certain embodiments.

[0035] FIGS. 16A-16C illustrate examples of spot size converters according to certain embodiments.

[0036] FIG. 17 A illustrates an example of an array of spot size converters for coupling light between an array of optical fibers and an array of waveguides according to certain embodiments.

[0037] FIGS. 17B and 17C illustrate an example of a spot size converter in the array of spot size converters of FIG. 17A according to certain embodiments.

[0038] FIG. 18 illustrates an example of a structure including a spot size converter and a heater according to certain embodiments.

[0039] FIG. 19 is a flowchart illustrating an example of a process for fabricating a low- loss spot size converter for optically coupling an optical fiber to an optical waveguide according to certain embodiments.

[0040] FIG. 20 is a simplified block diagram of an example of a system including two or more dies or wafers according to certain embodiments.

[0041] FIGS. 21A - 21H illustrate side cross-sectional views of steps in a method of a first alternative embodiment of the present disclosure.

[0042] FIGS. 22A - 22K illustrate side cross-sectional views of steps in a method of a second alternative embodiment of the present disclosure.

[0043] FIGS. 23 A - 23G illustrate side cross-sectional views of steps in a method of a third alternative embodiment of the present disclosure.

[0044] FIGS. 24A - 24C illustrate side cross-sectional views of steps in a method of a fourth alternative embodiment of the present disclosure.

[0045] FIGS. 25 A and 25B illustrate side cross-sectional views of steps of methods of alternative embodiments in which the substrate comprises a bulk silicon substrate.

[0046] FIGS. 26A and 26B illustrate side cross-sectional views of steps of methods of the alternative embodiments in which the substrate comprises a silicon on insulator (SOI) substrate.

[0047] FIGS. 27A - 27E illustrate side cross-sectional views of steps of a method of forming waveguide over the oxide filled trench of the first, second, third or fourth alternativeembodiments.DETAILED DESCRIPTION

[0048] Techniques disclosed herein relate generally to coupling light between optical fibers and photonic integrated circuits. More specifically, disclosed herein are techniques for reducing coupling losses at interfaces between optical fibers and components in the photonic integrated circuits (e.g., waveguides) to, for example, about 30 mdB / facet or lower, in order to reduce the total loss in a system (e.g., an optical quantum computing system) that may include many fiber links between modules. Various inventive embodiments are described herein, including methods, processes, systems, devices, circuits, packages, modules, units, wafers, dies, networks, cells, and the like.

[0049] Many optical systems may integrate passive and active photonic integrated circuits and other optical and electrical components, such as optical fibers or other low-loss optical interconnects. These circuits and components may have different dimensions and other properties (e.g., refractive indices). Therefore, light may propagate in these circuits and components in optical modes having different mode sizes. Optical couplers, such as spot size converters or other mode converters, may be used to connect these circuits and components. In a system that may include many of these optical couplers on a same signal path, the total loss caused by these couplers may be high. Thus, these optical couplers may not be suitable for transporting optical signals in, for example, optical quantum computing systems where single photons or entangled photons are generated, manipulated, transported, and detected.

[0050] According to certain embodiments, to match the mode sizes of an optical fiber (e.g., a single mode fiber) and a waveguide thereby reducing the coupling loss at the interface between the optical fiber and the waveguide, a coupler including a spot size converter (SSC) that includes a cantilever having a tapered waveguide core (e.g., SiN or Si) surrounded by a primary cladding material (e.g., oxide) layer and a secondary cladding material (e.g., an epoxy or a low K dielectric) having a slightly lower refractive index than the primary cladding material may be used to gradually change the mode size of the optical mode to match the mode sizes of the optical fiber and the waveguide. The tapered waveguide core of the cantilever may be tapered linearly or nonlinearly. In some embodiments, the refractive index contrast between the primary cladding material and the secondary cladding material may be within a certain range (e.g., between about 0.0015 and about 0.01 or higher).

[0051] In some embodiments, the SSC may have an inversely tapered (or straight and then inversely tapered) primary cladding layer for the waveguide. In some embodiments, the SSC may include a thermal controller (e.g., a heater) configured to adjust the local temperature and thus the index contrast between the primary cladding material and the secondary cladding material at a room temperature or at cryogenic temperatures. In some embodiments, additional oxide structures may be used to connect the tip of the cantilever to other oxide regions to provide better mechanical support and reliability. In some embodiments, the waveguide (e.g., SiN waveguide) can be vertically off-centered in an oxide (e.g., SiCh) slab or a square-shaped waveguide. Parameters such as dimensions of the tapered waveguide, dimensions of the primary cladding, and the index contrast can be selected to achieve better performance.

[0052] Techniques disclosed herein can drastically reduce the coupling loss, for example, to less than about 30 mdB / facet or lower (e.g., about 7 mdB / facet). The SSC disclosed herein can also achieve polarization independent coupling, can be used at cryogenic temperatures, and can be mechanically robust, and thus can be used in optical quantum computing systems, optical quantum communication systems, or other systems that need very low-loss coupling between fibers and waveguides. The SSC disclosed herein may be used to couple photons from an optical fiber to a waveguide, from a waveguide to an optical fiber, from one waveguide to another waveguide, and the like, by matching the optical mode fields of the optical components to be connected.

[0053] As used herein, a “qubit” (or quantum bit) refers to a quantum system with an associated quantum state that can be used to encode information. A quantum state can be used to encode one bit of information if the quantum state space can be modeled as a (complex) two-dimensional vector space, with one dimension in the vector space being mapped to logical value 0 and the other to logical value 1. In contrast to classical bits, a qubit can have a state that is a superposition of logical values 0 and 1. More generally, a “qudit” can be any quantum system having a quantum state space that can be modeled as a (complex) n-dimensional vector space (for any integer n), which can be used to encode n bits of information. For the sake of clarity of description, the term “qubit” is used herein, although in some embodiments the system can also employ quantum information carriers that encode information in a manner that is not necessarily associated with a binary bit, such as a qudit. Qubits (or qudits) can be implemented in a variety of quantum systems. Examples of qubits include: polarization states of photons; presence of photons in waveguides; or energy statesof atoms, ions, nuclei, or photons. Other examples may include other engineered quantum systems such as flux qubits, phase qubits, or charge qubits (e.g., formed from a superconducting Josephson junction); topological qubits (e.g., Majorana fermions); or spin qubits formed from vacancy centers (e.g., nitrogen vacancies in diamond). A physical qubit may be a physical device that behaves as a two-state quantum system. In one example, a qubit can be “dual-rail encoded” such that the logical value of the qubit is encoded by the occupation of one of two modes of the quantum system.

[0054] As used herein, a “resource state” refers to an entangled state of a number of qubits in a non-separable entangled state (which is an entangled state that cannot be decomposed into smaller separate entangled states). In various embodiments, the number of qubits of a resource state can be a small number (e.g., two or more, or any number up to about 20) or a larger number (as large as desired).

[0055] As used herein, a "logical qubit" refers to a physical or abstract qubit that has a long enough coherence time to be usable by quantum logic gates. A logical qubit may specify how a single qubit should behave in a quantum algorithm, subject to quantum logic operations by quantum logic gates. Due to issues such as stability, decoherence, fault tolerance, and scalability associated with a physical qubit that includes a single two-state quantum system, physical qubits may not be used to reliably encode and retain information for a sufficiently long period of time to be useful. Therefore, quantum error correction may need to be used to produce scalable quantum computers, where many physical qubits may be used to create a single, error-tolerant logical qubit. Depending on the error-correction scheme used and the error rates of each physical qubit, a single logical qubit may be formed using a large number (e.g., tens, hundreds, thousands, or more) of physical qubits. As used in the following sections, the term “qubit” generally refers to a physical qubit, whereas all references to logical qubits include the qualifier “logical.”

[0056] As used herein, a "quantum system" may include particles (such as atoms, ions, nuclei, and / or photons) or engineered quantum systems, such as flux qubits, phase qubits, or charge qubits (e.g., formed from a superconducting Josephson junction), topological qubits (e.g., majorana fermions), spin qubits formed from vacancy centers (e.g., nitrogen vacancies in diamond), qubits otherwise encoded in multiple quantum systems (e.g., Gottesman-Kitaev- Preskill (GKP) encoded qubits), entangled states of qubits, and the like.

[0057] As used herein, “fusion” (or “a fusion operation” or “fusing”) refers to a two-qubit entangling measurement. A “fusion gate” is a structure that receives two input qubits, each of which is typically part of an entangled state of qubits. The fusion gate may perform a projective measurement operation on the input qubits to produce either one (e.g., in “type I fusion”) or zero (e.g., in “type II fusion”) output qubit in a manner such that the initial two entangled states of qubits are fused into a single entangled state of qubits. Fusion gates are specific examples of a general class of two-qubit entangling measurements and are particularly suited for photonic architectures.

[0058] Several illustrative embodiments will now be described with respect to the accompanying drawings. The ensuing description provides embodiment(s) only and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the embodiment(s) will provide those skilled in the art with an enabling description for implementing one or more embodiments. It is understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, for the purposes of explanation, specific details are set forth in order to provide a thorough understanding of certain inventive embodiments. However, it will be apparent that various embodiments may be practiced without these specific details. The figures and description are not intended to be restrictive. The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0059] An optical system, such as an optical quantum computing system or an optical quantum communication system, may integrate passive and active photonic integrated circuits and other optical and electrical components, such as optical fibers or other low-loss optical interconnects, control circuits, and processing units, into a same system to reliably generate, manipulate (e.g., entangle), and detect hundreds, thousands, or even millions of qubits for computing and error corrections.

[0060] FIG. 1A is a top view of an example of an optical module 100 including a photonic integrated circuit (PIC) die 130 coupled to optical fibers 150 according to certain embodiments. In the illustrated example, optical module 100 includes PIC die 130, an electrical integrated circuit (EIC) die 140, a printed circuit board (PCB) 120, one or more electrical connectors 122, and optical fibers 150 on a silicon handle wafer 110. Even thoughFIG. 1A only shows one PIC / EIC (EPIC) die stack, multiple EPIC die stacks may be included in optical module 100. PCB 120 may be attached to silicon handle wafer 110, e.g., using an epoxy or through fusion bonding or hybrid bonding, depending on the material of PCB 120. In some embodiments, one or more PCBs 120 may be attached to silicon handle wafer 110 at different horizontal and / or vertical locations. An EPIC die stack includes EIC die 140 bonded face-to-face with PIC die 130 (e.g., by fusion bonding or hybrid bonding) such that the PICs may directly face the EICs and the substrates of PIC die 130 and EIC die 140 are on opposite sides of the EPIC die stack. The EPIC die stack may be bonded to silicon handle wafer 110 by, for example, fusion bonding. EIC die 140 may be electrically connected to PCB 120 through bonding wires 142, where the bonding pads and bonding wires may only be at the top (north) and bottom (south) sides of the EPIC die stack. The left (west) and right (east) sides of the EPIC die stack may be coupled with optical fibers 150, where optical fibers 150 may be attached to PCB 120 through harnesses 152. PCB 120 may also include electrical connectors 122 and some other electronic components, such as voltage regulators, power management ICs, decoupling capacitors, etc.

[0061] FIG. IB is a cross-sectional view of optical module 100 along a line A-A shown in FIG. 1A according to certain embodiments. In the example shown in FIG. IB, PCB 120 and the PIC / EIC die stack are bonded to a top surface of silicon handle wafer 110. PCB 120 may include multiple layers of interconnect traces or planes connected through vias. Electronic components, such as electrical connector 122 and decoupling capacitors 124 may be soldered on the top surface of PCB 120. PCB 120 may also include solder pads 126 on the top surface of PCB 120. The PIC / EIC die stack may include PIC die 130 and EIC die 140. PIC die 130 may include a back surface 1 3 bonded to silicon handle wafer 110. PIC die 130 may also include a front surface 131 that may include circuits or pads. EIC die 140 may include a back surface 143 that may include a redistribution layers and bonding pads 148. EIC die 140 may also include a front surface 141 that may include circuits or pads. EIC die 140 and PIC die 130 may be bonded face-to-face with each other such that front surface 131 of PIC die 130 and front surface 141 of EIC die 140 may directly face each other and the interconnections can be short. PIC die 130 may include waveguides 132 and 136, and other photonic integrated circuits, such as single photon generators, switches, waveguide couplers, and photodetectors 134. EIC die 140 may include some through-silicon vias (TSVs) 146 and control logic circuits 144. For example, a photodetector 134 may detect a single photon from waveguide 132, and send the detection result to control logic circuit 144, which maydetermine whether and how to tune waveguide 136 (e.g., to turn on or off an optical switch). Bonding pads 148 may be connected to control logic circuits 144 through TSVs, and may also be connected to solder pads 126 on PCB 120 through bonding wires 142.

[0062] FIG. 1C is another cross-sectional view of optical module 100 along a line B-B shown in FIG. 1 A according to certain embodiments. In the example shown in FIG. 1C, in the B-B direction, optical fibers 150 may be attached to PCB 120 through harnesses 152. Optical fibers 150 may fit in V-grooves formed on PIC die 130, where the V-grooves may align with the waveguides on PIC die 130. Therefore, when assembled, the cores of optical fibers may align with corresponding cores of the waveguides on PIC die 1 0. Optical fibers 150 may be used to send photons into optical module 100, couple photons out of optical module 100, or loop photons from optical module 100 back into optical module 100. The photons may include pump photons, data communication signals (e.g., control signals), quantum states, and the like.

[0063] FIG. 2 is a simplified block diagram of an example of a quantum computing system 200 according to some embodiments. Quantum computing system 200 may include one or more optical modules 100 described above. Quantum computing system 200 may implement, for example, measurement-based quantum computing (MBQC) or fusion-based quantum computing (FBQC). Some embodiments of quantum computing system 200 may use photonic physical qubits to generate a fault-tolerant cluster state that can be used to represent logical qubits for MBQC, while other embodiments of quantum computing system 200 may generate measurement data reflecting entanglement structures for fault-tolerant FBQC. In the illustrated example, quantum computing system 200 may include resource state generator(s) 210, delay circuits 220, switch circuits 230, detectors 240, and one or more classical processing units 250.

[0064] Resource state generators 210 may include one or more resource state generators (RSGs). The RSGs may autonomously operate, with no data input needed. Each RSG may generate one resource state per clock cycle (which can be, e.g., shorter than about Ins, about 1 ns, or longer than about 1 ns). Each resource state may include multiple (e.g., 7 or 9) entangled physical qubits. The resource state can be output to delay circuits 220 at a rate of, for example, about nxN photons per clock cycle, where n is the number of qubits in each resource state and N is the number of RSGs. Resource state generators 210 can also send classical data output (e.g., indicating success or failure of various elements of the resource state generation process) to classical processing unit 250 via a data path 222. In someembodiments, resource state generators 210 can be maintained at cryogenic temperatures (e.g., 4 K). Delay circuit 220 can include optical fibers, other waveguides, optical memory, or other components to delay or store photons corresponding to particular qubits by appropriate delay times, such as 1 clock cycle, L clock cycles, and L2clock cycles, where L may be any integer number. Delay circuits 220 may not need to operate at cryogenic temperatures. Photons exiting delay circuits 220 can be delivered to switch circuits 230 via, for example, optical fibers, on-chip waveguides, or any other type of waveguides or optical interconnects.

[0065] Switch circuits 230 may include active switches and waveguides to perform mode coupling, mode swapping, phase shift, and other operations on the qubits. In various embodiments, switch circuits 230 may perform mode coupling operations associated with fusion operations as described below and / or basis selection operations associated with measurement of individual qubits. In some embodiments, switch circuits 230 may be dynamically reconfigurable in response to control signals from classical processing units 250, and thus quantum computing system 200 may perform different computations by reconfiguring switches in switch circuits 230. Switch circuits 230 may deliver output photons to detectors 240 via, for example, optical fibers, on-chip waveguides, or any other type of optical interconnects.

[0066] Detectors 240 may include photon detectors capable of detecting single or multiple photons. Each photon detector may be coupled to one waveguide and may generate an output (classical) signal indicating whether a photon was detected. In some embodiments, some or all detectors 240 may be capable of counting photons, and the output signal from each detector 240 may indicate the number of photons detected by the detector 240. In some embodiments, detectors 240 may operate at cryogenic temperatures. Detectors 240 may provide classical output signals indicating the number of photons, or binary signals indicating whether a photon was detected, to classical processing unit 250 via a signal path 224, such as optical fibers.

[0067] Classical processing unit 250 may be a classical computer system that is capable of communicating with resource state generator(s) 210, switch circuits 230, and detectors 240 using classical digital logic signals. In some embodiments, classical processing unit 250 may determine appropriate settings for switch circuits 230 based on a particular quantum computation (or program) to be executed. Classical processing unit 250 may receive feedback signals (e.g., measurement outcomes) from resource state generators 210 and detectors 240 and can determine the result of the computation based on the feedback signals. In someembodiments, classical processing unit 250 can use feedback signals to modify subsequent control signals sent to switch circuits 230. Operation of classical processing unit 250 may incorporate error correction algorithms and other techniques.

[0068] Quantum computing system 200 of FIG. 2 is illustrative, and variations and modifications are possible. Blocks shown separately can be combined, or a single block can be implemented using multiple distinct components. Resource state generator(s) 210, delay circuits 220, switch circuits 230, and detectors 240 can implement the circuits descried above and below for generating entanglement structures. For instance, delay circuits 220 may implement delay lines for resource state fusion, while switch circuits 230 may implement reconfigurable switches and mode couplers associated with reconfigurable fusion, and detectors 240 may implement destructive measurements associated with fusion operations. Quantum computing system 200 is just one example of a quantum computing system or another photonic system that can use the wafer-scale modules described herein. Those skilled in the art will appreciate that many different systems can be implemented using the waferscale modules that each include PIC or EPIC dies bonded to and optically coupled to an optical backplane having low-loss waveguides.

[0069] A qubit used in a quantum system may be physically realized using a pair of waveguides into which a single photon is introduced. Qubits can be operated upon using mode couplers (e.g., beam splitters), variable phase shifters, photon detectors, and the like. For instance, entanglement between two (or more) qubits can be created by providing mode couplers between waveguides associated with different qubits. As also described above, physical qubits may suffer from loss and / or noise. Consequently, relying on single physical qubits (e.g., a photon propagating in a pair of waveguides) when performing a quantum computation may result in an unacceptably high error rate. To provide fault tolerance, photonic quantum computers can be designed to operate on one or more logical qubits, where a logical qubit is a multi-qubit quantum system in an entangled state that enables error correction (also referred to herein as an error correcting code). For example, in some embodiments, the structure of the error correcting code can be represented as a graph in three dimensions. In the context of quantum computing, logical qubits can improve robustness by supporting error detection and error correction. Logical qubits may also be used in other contexts, such as quantum communication.

[0070] FIG. 3 illustrates an example of a subsystem 300 for generating entangled quantum states (e.g., resource states or logical qubits) according to certain embodiments.Subsystem 300 may include a wafer-scale module 310 that includes multiple EPIC die stacks 312 bonded to an optical backplane 316. Wafer-scale module 310 may be an example of optical module 100 or resource state generator 210. EPIC die stacks 312 may be manufactured and bonded to optical backplane 316 as described in details above and below. Wafer-scale module 310 may also include a plurality of PCBs 314 (e.g., an electrical backplane). The EIC dies in EPIC die stacks 312 may be electrically connected to PCBs 314 using, for example, wire bonding. EPIC die stacks 312 may be used to, for example, generate, manipulate, transport, and detect qubits or entangled states of qubits for optical quantum computing or optical quantum communication. For example, EPIC die stacks 312 may include single photon generators, mode couplers, fusion gates, beam splitters, switches, single photon detectors or multi-photon detectors, waveguides, delay lines, modulators, optical switches, ring oscillators, couplers, photodiode-based photodetectors for receiving data and timing signals, and the like, as described above and below. EPIC die stacks 312 may be optically connected together through optical fibers, optical waveguides in optical backplane 316, free-space optical interconnects, and / or other optical interconnects.

[0071] Wafer-scale module 310 may be connected to a distribution network 320 through optical fibers 360. Optical fibers 360 may be coupled to EPIC die stacks 312 through grating couplers (or edge couplers) and / or optical backplane 316. Distribution network 320 may be connected to one or more pump laser sources 340 and a control unit 330 (e.g., through an optical transceiver 350). Control unit 330 may include, for example, a classical computing system. In some embodiments, control unit 330 and / or distribution network 320 may be used to control two or more wafer-scale modules 310. Optical fibers 360 may be used to, for example, send pump laser pulses from pump laser sources 340 to EPIC die stacks 312 for single photon generation, send control data from control unit 330 and optical transceiver 350 to EPIC die stacks 312 (e.g., to control the switches), send measurement data from EPIC die stacks 312 to optical transceiver 350 and control unit 330, and the like.

[0072] In one example, each EPIC die stack 312 may include a single photon generator that includes waveguides, ring oscillators, interferometers, couplers, optical switches, WDM filters, single photon detectors, and the like that form multiple multiplexed photon pair sources to deterministically generate single photons through a nonlinear optical process (e.g., spontaneous four-wave mixing (SFWM), spontaneous parametric down-conversion (SPDC), second harmonic generation, etc.). In one embodiment, each photon pair source may include a micro-ring-based SFWM heralded photon source (HPS), where the detection of one photonof a pair of photons generated during the nonlinear process by a single photon detector (e.g., a superconductive nanowire single photon detector (SNSPD)) may herald the existence of the other photon in the pair that may be used to implement a qubit or generate an entangled resource state. Other classes of photon sources that do not use a nonlinear material may also be employed, such as those that employ atomic and / or artificial atomic systems (e.g., quantum dot sources, color centers in crystals, etc.). The operations of some photon sources may be non-deterministic (also sometimes referred to as “stochastic”) such that a given pump pulse may or may not produce a pair of photons. In such photon sources, coherent spatial and / or temporal multiplexing of several non-deterministic photon sources may be performed to increase the probability of having one photon in any given cycle. When the number of multiplexed non-deterministic photon sources is large, the probability of having one photon in any given cycle may be about 100%.

[0073] As illustrated in FIG. 3, wafer-scale module 310 may also be coupled to one or more optical fibers 362. The one or more optical fibers 362 may be used to transmit single photons, qubits, or entangled states of qubits between different wafer-scale modules 310 or may be used to loop qubits back to the same wafer-scale module after a delay. As described above and below, in some embodiments, optical fibers 362 may be coupled to waveguides in optical backplane 316 through low-loss couplers. In some embodiments, optical fibers 362 may be used as a long delay line for delaying the qubits to perform time-like resource state fusion operations. In some embodiments, optical fibers 362 may also be used for data communication or for transmitting pump laser pulses.

[0074] As described above, a plurality of EPIC die stacks may be bonded to a handle wafer, for example, by fusion bonding or oxide bonding, to form a wafer-scale module. The plurality of EPIC die stacks may be used to, for example, generate, manipulate, and detect qubits for optical quantum computing. In some embodiments, multiple wafer-scale modules may be connected through fiber cables, free-space optical interconnects, or other optical interconnects to form a subsystem or a system for larger scale quantum state generation, manipulation, and detection.

[0075] FIG. 4A is a top view of an example of a wafer-scale module 410 including multiple EPIC die stacks 414 on a handle wafer 412 according to certain embodiments. Wafer-scale module 410 may be an example of optical module 100, resource state generator 210, or subsystem 300. EPIC die stacks 414 may each include a PIC die and an EIC die, and may be manufactured and bonded to handle wafer 412 (e.g., including an optical backplaneor another optical interposer) as described above. An EPIC die stack 414 may be optically connected to another EPIC die stack 414 through one or more optical fibers, one or more optical waveguides in the optical interposer, one or more free-space optical interconnects, or other optical interconnects. Wafer-scale module 410 may also include a plurality of PCBs 416. The EIC dies in EPIC die stacks 414 may be electrically connected to PCBs 416 using, for example, wire bonding. EPIC die stacks 414 may be used to, for example, generate, manipulate, and / or detect qubits (e.g., photonic qubits that employ one or more photons) or entangled states of qubits for optical quantum computing.

[0076] FIG. 4B illustrates an example of a system 400 including multiple wafer-scale modules 410 interconnected using optical fibers according to certain embodiments. As described above with respect to FIG. 4A, each wafer-scale module 410 may include multiple EPIC die stacks. Optical fibers may be used to provide inter-wafer and / or intra-wafer optical interconnects. For example, optical fibers 420 may be used to connect EPIC die stacks 414 on a same wafer-scale module 410, while optical fibers 430 may be used as interconnects between wafer-scale modules 410. System 400 may be used to perform, for example, qubit generation, manipulation, and / or detection at a larger scale.

[0077] FIG. 5 is a cross-sectional view of an example of a wafer-scale module 500 (e.g., subsystem 300 or wafer-scale module 410) according to certain embodiments. As shown in FIG. 5, wafer-scale module 500 may include multiple EPIC die stacks 512, multiple PCBs 514, and optical fiber bundles. EPIC die stacks 512 may be optically connected to each other or other wafer-scale modules through an optical backplane 516, and may be electrically connected to PCBs 514 through bonding wires 522. Optical backplane 516 may include a dielectric layer 518 that includes one or more waveguide layers formed therein. The one or more waveguide layers may include low-loss waveguides 524 for transmitting, delaying, or storing single photons, qubits, qudits, resource states, or other entangled states. For example, waveguides 524 may include pairs of waveguides used to implement or transmit qubits and / or entangled qubits (e.g., resource states or larger entangled states of qubits). Photons may be coupled from one waveguide to another waveguide or from one waveguide layer to another waveguide layer through, for example, waveguide couplers. Photons may also be coupled from waveguides 524 in optical backplane 516 to waveguides in EPIC die stacks 512 through other waveguide layers and waveguide couplers in optical backplane 516 and / or EPIC die stacks 512. The waveguide couplers can be any type of waveguide coupler, e.g., adiabatic and / or evanescent waveguide couplers.

[0078] In the illustrated example, each EPIC die stack 512 may include a grating coupler for receiving pump light and / or data communication signals from an optical fiber 560. Optical fibers 562 may be coupled to waveguides 524 in optical backplane 516 through optical input / output ports that may include, for example, V-groove alignment structures and low-loss couplers, such as a tapered structure, a subwavelength grating, an edge coupler, and the like.. Optical fibers 562 may be connected to other wafer-scale modules 500 or may be connected to different portions of wafer-scale module 500 (e.g., loop photons or qubits from wafer-scale module 500 back to wafer-scale module 500 after a delay).

[0079] FIGS. 6A-6C illustrate an example of a structure 600 including a spot size converter 622 (also referred to as herein an optical mode transformer, a fiber-to-waveguide coupler, or a coupler) according to certain embodiments. Spot size converter 622 can be used to, for example, couple light between EPIC die stacks 312 of FIG. 3, couple light between wafer-scale modules 410 of FIG. 4, couple light between two ports of a wafer-scale module 410 of FIG. 4, or couple light from optical fibers 562 to waveguides 524 or from waveguides 524 to optical fibers 562 in wafer-scale module 500 of FIG. 5. FIG. 6A shows an x-y crosssection of structure 600. FIG. 6B shows a y-z cross-section of structure 600. FIG. 6C shows an x-z cross-section of structure 600. In the illustrated example, structure 600 includes a substrate 610 (e.g., a silicon substrate) that may include a V-groove 612 formed therein.Oxide layers 620, waveguides (e.g., a waveguide 628), and other photonic integrated circuits may be formed on substrate 610 using semiconductor processing techniques. Oxide layers 620 may include one or more oxide layers (e.g., SiO ) deposited on substrate 610. The waveguides may include a waveguide core (e.g., SiN or Si) and waveguide cladding layers (e.g., one or more oxide layers 620). An optical fiber 630 may be coupled to waveguide 628 through spot size converter 622. Optical fiber 630 may include a fiber core 632 and a fiber cladding layer 634, where fiber core 632 and fiber cladding layer 634 may both have a circular- shaped cross-section. Fiber core 632 may have a refractive index higher than the refractive index of fiber cladding layer 634, such that light may propagate within fiber core 632 through total internal reflection. Optical fiber 630 may be positioned in V-groove 612.

[0080] Spot size converter 622 may include a core 624 and a cladding layer 626. Core 624 may include a high index material (e.g., SiN or Si). Cladding layer 626 may include a low-index material, such as silicon oxide. The size of core 624 at one end of spot size converter 622 may match the size of the waveguide core of waveguide 628. Core 624 of spot size converter 622 may be inversely tapered from the fiber-waveguide interface to waveguide628, where the size of core 624 in the x direction may gradually increase along the z direction as shown in FIG. 6C. The size of core 624 in the y direction may be constant or may vary along the z direction. The height of cladding layer 626 (in the y direction) may be constant, and the width of cladding layer 626 (in the x direction) may be constant or may vary along the z direction. Spot size converter 622 may include a cantilever portion. The cantilever portion may be formed by, for example, forming cladding layer 626 and core 624 on a buried oxide layer formed on substrate 610, and then selectively etching substrate 610 under spot size converter 622 to form an undercut region that may have a V-shape, the undercut region may be a part of the V-groove 612 or may be aligned with V-groove 612, such that fiber core 632 may align with core 624 of spot size converter 622.

[0081] Fiber core 632 of optical fiber 630 may have a cross-sectional area greater than the cross-sectional area of waveguide core of waveguide 628. The guided mode in optical fiber 630 may have a mode size (e.g., diameter) about a few microns, while the waveguide core may have a sub-micron linear dimension. Due to the large mode size mismatch, coupling losses from optical fiber 630 directly to waveguide 628 can be about 15 dB or higher. Spot size converter 622 may be used to reduce the coupling loss. Due to the small size of the tapered portion of core 624, the optical mode at the tapered portion may be weakly confined in core 624, and thus the size of the optical mode may increase in both the horizontal and vertical directions. At the interface between optical fiber 630 and spot size converter 622, core 624 may have the smallest size, and thus the optical mode may be less confined and thus may have a large size that may match the size of the optical mode of optical fiber 630. As the size of core 624 gradually increases along the z direction, the optical mode may be more and more confined in core 624 and thus the mode size may gradually decrease. At the interface between spot size converter 622 and waveguide 628, the optical mode may be reduced to have a size matching the mode size of waveguide 628. Therefore, the coupling efficiency between optical fiber 630 and waveguide 628 may be improved by spot size converter 622.

[0082] FIG. 7A illustrates an example of a spot size converter 700. Spot size converter 700 may be an example of spot size converter 622. FIG. 7A shows a cross-section of a cantilever portion of spot size converter 700, which may include a core 712 embedded in a cladding layer 710. Cladding layer 710 may include an oxide, such as silicon oxide. Core 712 may include a high-index material, such as SiN or Si. FIG. 7A also shows a fiber core 720, which may have a size much larger than core 712.

[0083] FIG. 7B includes a diagram 705 illustrating simulated coupling efficiencies of examples of spot size converters 700 having different core sizes. In the illustrated example, the fiber may be an SMF-28 fiber, core 712 of spot size converter 700 may include SiN, cladding layer 710 of spot size converter 700 may include silicon oxide, and the optical mode guided by the optical fiber may be transverse electric (TE) mode and may have a wavelength about 1550 nm. FIG. 7B shows the simulated coupling efficiencies of spot size converters 700 with a width of core 712 varying from about 50 nm to about 500nm and a height of core 712 varying from about 50 nm to about 500 nm. FIG. 7B shows that the maximum coupling efficiency of spot size converter 700 may be about 94.4%, and thus the minimum coupling loss is about 250 mdB.

[0084] As described above, optical quantum computing systems, such as system 400, may include waveguides, delay lines, switches, filters, photodetectors, single photon generation circuits, single photon detectors, resource state generation circuits, logical qubit detection circuits, and the like. Therefore, there may be many transitions between fibers and waveguides on a signal path. For example, pump photons may be coupled from a fiber to a waveguide that is coupled to a heralded single photon source (HSPS). The HSPS may generate a photon pair through a nonlinear process (e.g., SFWM). The two photons in the photon pair may be separated by, for example, a wavelength-division multiplexer (WDM), where one photon (heralding photon) of the photon pair detected by a single photon detector (e.g., an SNSPD) may herald the existence of the other photon (signal photon) in the pair. The signal photons may be used to implement qubits or to generate various entangled resource states and error-corrected photonic logical qubits. The qubits, resource states, and logic qubits may be delayed, fused, switched, and detected. The connections between die stacks or wafer-scale modules and the long delay lines may be implemented using low-loss optical fibers. Because of the many transitions between fibers and waveguides on a signal path, the total coupling loss can be high even if the coupling efficiency at each facet between a fiber and a waveguide can be as high as shown in FIG. 7B. In order to reduce the total loss, the coupling loss between a fiber and a waveguide may need to be further reduced.

[0085] According to certain embodiments, to better match the mode sizes of an optical fiber (e.g., a single mode fiber) and a waveguide thereby reducing the coupling loss at the interface between the optical fiber and the waveguide, a spot size converter that includes a cantilever having a tapered core (e.g., SiN or Si) surrounded by a primary cladding material (e.g., oxide) layer and a layer of a secondary cladding material (e.g., an epoxy, such as NTTE3810) having a slightly lower refractive index than the primary cladding material may be used to gradually change the mode size of the optical mode to match the mode sizes of the optical fiber and the waveguide. The tapered core may be tapered linearly or nonlinearly. The index contrast between the primary cladding material and the secondary cladding material may be within a certain range (e.g., between about 0.0015 and about 0.01 or higher). The spot size converter may have an inversely tapered (or straight and then inversely tapered, or sectionally changed) primary cladding layer for the waveguide. Parameters such as dimensions of the tapered core, dimensions of the primary cladding, and the index contrast between the primary cladding material and the secondary cladding material can be selected to achieve better performance.

[0086] FIG. 8 illustrates an example of a structure 800 that includes a spot size converter 822 having a lower- index secondary cladding layer 840 according to certain embodiments. Structure 800 may include a substrate 810 (e.g., a silicon substrate) with a V-groove 812 formed thereon by, for example, selectively etching regions of substrate 810 under spot size converter 822 to form an isotropic undercut region. Spot size converter 822 may be formed in one or more oxide layers 820 and may be used to couple light from an optical fiber 830 into a waveguide in oxide layers 820, where the core of the waveguide may be smaller than a fiber core 832 of optical fiber 830. As illustrated, spot size converter 822 may include a core 824 surrounded by a primary cladding layer 826. Core 824 may be tapered as described above and below. Primary cladding layer 826 may have a cross-sectional size greater than the cross- sectional size of fiber core 832. Primary cladding layer 826 may be surrounded by a secondary cladding layer 840, which may include a material having a refractive index slightly lower than the refractive index of primary cladding layer 826. Secondary cladding layer 840 may include an organic material, such as an epoxy (e.g., NTT E3810), and may be applied (e.g., injected or otherwise deposited) after optical fiber 830 is positioned on V-groove 812 and aligned with spot size converter 822. Secondary cladding layer 840 may fill gaps in the vicinity of spot size converter 822, and may also help to secure optical fiber 830 on V-groove 812.

[0087] Compared with structure 600 where air gaps may surround cladding layer 626, structure 800 may have a low refractive index contrast between primary cladding layer 826 and its surrounding media (e.g., secondary cladding layer 840). Therefore, the optical mode field size in spot size converter 822 may be larger than the optical mode field size in spot size converter 622, and thus may better match with optical mode field size of optical fiber 830.

[0088] FIGS. 9A-9C illustrate an example of a structure 900 including a spot size converter 922 according to certain embodiments. Spot size converter 922 can be used to, for example, couple light between EPIC die stacks 312 of FIG. 3, couple light between waferscale modules 410 of FIG. 4, couple light between two ports of a wafer-scale module 410 of FIG. 4, or couple light from optical fibers 562 to waveguides 524 or from waveguides 524 to optical fibers 562 in wafer-scale module 500 of FIG. 5. FIG. 9A shows an x-y cross-section of a portion of structure 900. FIG. 9B shows a y-z cross-section of a portion of structure 900. FIG. 9C shows an x-z cross-section of a portion of structure 900. In the illustrated example, structure 900 includes a substrate 910 (e.g., a silicon handle wafer). Oxide layers 920, waveguides (e.g., a waveguide 950), and other photonic integrated circuits may be formed on substrate 910 using semiconductor processing techniques. Oxide layers 920 may include one or more oxide layers (e.g., SiOi) deposited on substrate 910, such as a buried oxide (BOX) layer 926 and an oxide layer 928 deposited on substrate 910 before the deposition of the waveguide core layer, and an oxide layer 927 and an oxide layer 925 deposited after the formation of waveguide cores (e.g., after patterning the waveguide core layer). Waveguide 950 may include a waveguide core (e.g., SiN or Si) and waveguide cladding layers (e.g., oxide layers 925-928).

[0089] An optical fiber 930 may be coupled to waveguide 950 through spot size converter 922. Optical fiber 930 may include a fiber core 932 and may be positioned in a V- groove (an undercut region) formed in substrate 910 under spot size converter 922 such that fiber core 932 may be aligned with spot size converter 922. Fiber core 932 may have a diameter about a few microns, whereas waveguide core of waveguide 950 may have a linear dimension about a few hundred nanometers. Therefore, direct coupling between optical fiber 930 and waveguide 950 may have a low coupling efficiency.

[0090] Spot size converter 922 may include a core 924 and a cladding layer formed by oxide layers 920 (e.g., oxide layers 925-928). Core 924 may be formed in the waveguide core layer and may include a high index material (e.g., SiN or Si). The cladding layer may be formed by etching oxide layers 925-928. The size of core 924 at one end of spot size converter 922 may match the size of the waveguide core of waveguide 950. Core 924 of spot size converter 922 may be inversely tapered from an end closer to optical fiber 930 to an end closer to waveguide 950, where the width of core 924 in the x direction may gradually increase along the z direction as shown in FIG. 9C. The height of core 924 in the y direction may be constant along the z direction as shown in FIG. 9B or may vary along the z direction.The height of the cladding layer (in the y direction) of spot size converter 922 may also be constant along the z direction as shown in FIG. 9B or may vary along the z direction. Spot size converter 922 may include a cantilever portion above the undercut region of substrate 910. The cantilever portion may be formed by, for example, forming oxide layers 920 and core 924 on substrate 910 and selectively etching substrate 910 under spot size converter 922 to form an undercut region that may have a V-shape. The width of the cladding layer (in the x direction) of the cantilever portion of spot size converter 922 may also be inversely tapered along the z direction as shown in FIG. 9C. The cantilever portion of spot size converter 922 may have a non-zero distance from optical fiber 930. In some embodiments, core 924 may be recessed from the end of spot size converter 922 that is close to optical fiber 930.

[0091] In the example shown in FIGS. 9A-9C, the cladding layer of spot size converter 922 may be surrounded by a secondary cladding layer 940, which may include a material having a refractive index slightly lower than the refractive index of the cladding layer (e.g., oxide layers 920). Secondary cladding layer 940 may include an organic material, such as an epoxy, and may be applied (e.g., injected or otherwise deposited) after optical fiber 930 is positioned on the V-groove and aligned with spot size converter 922. Secondary cladding layer 940 may fill gaps in the vicinity of spot size converter 922 and may also secure optical fiber 930 on the V-groove.

[0092] As described above, due to the small size of the tapered portion of core 924 and the low index contrast between oxide layers 920 and secondary cladding layer 940, the optical mode at the cantilever portion of spot size converter 922 may be weakly confined in core 924, and thus the size of the optical mode may increase in both the horizontal and vertical directions. Core 924 of spot size converter 922 at the end closer to optical fiber 930 may have the smallest size, and thus the optical mode may be less confined and thus may have a large size that may match the size of the optical mode of optical fiber 930. As the size of core 924 gradually increases along the z direction, the optical mode may be more and more confined in core 924 and thus the mode size may gradually decrease. At the interface between spot size converter 922 and waveguide 950, the optical mode may be reduced to have a size matching the mode size of waveguide 950. Therefore, the coupling efficiency between optical fiber 930 and waveguide 950 may be improved by spot size converter 922.

[0093] FIGS. 10A-10C illustrate another example of a structure 1000 including a spot size converter 1022 according to certain embodiments. FIG. 10A shows an x-y cross-section of a portion of structure 1000 and a zoom-in view of a smaller portion. FIG. 10B shows an x-z cross-section of a portion of structure 1000. FIG. 10C shows a y-z cross-section of a portion of structure 1000. In the illustrated example, structure 1000 includes a substrate 1010 (e.g., a silicon handle wafer). One or more oxide layers 1020, waveguides (e.g., a waveguide 1050), and other photonic integrated circuits may be formed on substrate 1010 using semiconductor processing techniques. Waveguide 1050 may include a waveguide core (e.g., SiN or Si) and waveguide cladding layers (e.g., oxide layers 1020).

[0094] An optical fiber 1030 may be coupled to waveguide 1050 through spot size converter 1022. Optical fiber 1030 may include a fiber core 1032 and may be positioned in a V-groove or U-groove (e.g., an undercut region 1012) formed in substrate 1010 under spot size converter 1022, such that fiber core 1032 may be aligned with spot size converter 1022. Fiber core 1032 may have a diameter about a few microns, whereas waveguide core of waveguide 1050 may have a linear dimension about a few hundred nanometers. Therefore, direct coupling between optical fiber 1030 and waveguide 1050 may have a low coupling efficiency.

[0095] Spot size converter 1022 may include a core 1024 and a cladding layer (e.g., oxide layers 1020). Core 1024 may be formed in a waveguide core layer and may include a high index material (e.g., SiN or Si). The size of core 1024 at one end of spot size converter 1022 may match the size of the waveguide core of waveguide 1050. Core 1024 of spot size converter 1022 may be inversely tapered from an end closer to optical fiber 1030 to an end closer to waveguide 1050, where the width of core 1024 in the x direction may gradually increase along the z direction as shown in FIG. 10B. The height of core 1024 in the y direction may be constant along the z direction as shown in FIG. 10C or may vary along the z direction. The height of the cladding layer (in the y direction) of spot size converter 1022 may also be constant along the z direction as shown in FIG. 10C or may vary along the z direction. Spot size converter 1022 may include a cantilever portion above the undercut region 1012 of substrate 1010. The cantilever portion may be formed by, for example, forming oxide layers 1020 and core 1024 on substrate 1010, and then selectively etching substrate 1010 under spot size converter 1022 to form an undercut region 1012 that may have a V-shape or U-shape. The width of the cladding layer (in the x direction) of the cantilever portion of spot size converter 1022 may be constant at a first portion of spot size converter 1022 that is closer to optical fiber 1030, and may also be inversely tapered along the z direction in a second portion 1026 of spot size converter 1022 as shown in FIG. 10B. The cantilever portion of spot size converter 1022 may have a non-zero distance from optical fiber1030. In some embodiments, core 1024 may be recessed from the end of spot size converter 1022 that is close to optical fiber 1030. In the illustrated example, oxide ribs 1028 may be formed in oxide layers 1020 between the cantilever portion of spot size converter 1022 and other regions of oxide layers 1020 to provide mechanical support for spot size converter 1022.

[0096] In the example shown in FIGS. 10A-10C, the cladding layer (e.g., oxide layers 1020) of spot size converter 1022 may be surrounded by a secondary cladding layer 1040, which may include a material having a refractive index slightly lower than the refractive index of the cladding layer. Secondary cladding layer 1040 may include an organic material, such as an epoxy, and may be applied (e.g., injected or otherwise deposited) after optical fiber 1030 is positioned on the V-groove or U-groove and aligned with spot size converter 1022. Secondary cladding layer 1040 may fill gaps in the vicinity of spot size converter 1022, including undercut region 1012.

[0097] As described above, due to the small size of the tapered core 1024 and the low index contrast between cladding layer (e.g., oxide layers 1020) and secondary cladding layer 1040, the optical mode at the cantilever portion of spot size converter 1022 may be weakly confined in core 1024, and thus the size of the optical mode may increase in both the horizontal and vertical directions. Core 1024 of spot size converter 1022 at the end closer to optical fiber 1030 may have the smallest size, and thus the optical mode may be less confined and thus may have a large size that may match the size of the optical mode of optical fiber 1030. As the size of core 1024 gradually increases along the z direction, the optical mode may be more and more confined in core 1024 and thus the mode size may gradually decrease. At the interface between spot size converter 1022 and waveguide 1050, the optical mode may be reduced to have a size matching the mode size of waveguide 1050. Therefore, the coupling efficiency between optical fiber 1030 and waveguide 1050 may be improved by spot size converter 1022.

[0098] FIG. 11 A illustrates an example of a mode field 1110 of a guided optical mode in an optical fiber according to certain embodiments. In the illustrated example, the optical fiber may include an SMF-28 fiber, and the wavelength of the guided optical mode may be about 1550 nm. FIG. HA shows that the diameter of mode field 1 110 may be about a few microns.

[0099] FIG. 1 IB illustrates an example of a mode field 1120 of a guided optical mode converted by a spot size converter (e.g., spot size converter 822, 922, or 1022) according tocertain embodiments. In the illustrated example, the cross-sectional area of the primary cladding layer (SiC ) of the spot size converter may be about 7.7 pm x 7.7 pm. The tapered waveguide core (SiN) of the spot size converter may be in the center of primary cladding layer. The tip of the tapered waveguide core (SiN) of the spot size converter may have a size about 80 nm x 80 nm. The refractive index difference between the primary cladding layer and the secondary cladding layer may be about 0.003. FIG. 1 IB shows that the spot size (diameter) of the guided optical mode may be about less than about 500 nm x 500 nm. The coupling efficiency may be as high as 99.8% (or a loss about 8 mdB), which may be further optimized by tuning, for example, the dimension of the primary cladding layer and the dimension of the core of the spot size converter, and the refractive indices of the core, the primary cladding layer, and the secondary cladding layer.

[0100] FIG. 12A illustrates an example of a spot size converter 1200 including a lower- index secondary cladding layer 1220 according to certain embodiments. As described above and shown in FIG. 12A, spot size converter 1200 may be used to couple light from an optical fiber having a fiber core 1230 to a waveguide (e.g., a SiN waveguide) in a primary cladding layer 1210 (e.g., SiO2). Primary cladding layer 1210 may be surrounded by secondary cladding layer 1220, such as an epoxy or another organic or inorganic material having a lower refractive index than primary cladding layer 1210. Primary cladding layer 1210 may have a width Woand a height Ho. A tapered core 1212 of spot size converter 1200 may have a height Hcand a width Wcat the smaller end.

[0101] FIG. 12B includes a curve 1250 showing the simulated coupling efficiency of spot size converter 1200 as a function of the primary cladding layer thickness. In the illustrated example, the optical fiber may include an SMF-28 fiber, the guided optical mode may be TE mode, and the wavelength of the guided optical mode may be about 1550 nm. The width Wcof tapered core 1212 at the smaller end may be about 210 nm, and the height Hcof tapered core 1212 may be about 350 nm. The width Woand the height Hoof primary cladding layer 1210 (SiO2) may be about the same. The refractive index contrast between primary cladding layer 1210 and secondary cladding layer 1220 may be about 0.003. FIG. 12B shows that, when the width Woand the height Hoof primary cladding layer 1210 (SiO2) is about 18 pm, the coupling efficiency may be about 96.5% (or a loss about 150 mdB), which may be further optimized by tuning other parameters. The performance of spot size converter 1200 for TM mode may be about the same.

[0102] FIG. 13A includes a diagram 1300 illustrating the simulated coupling efficiency of spot size converter 1200 as a function of the width Wcof tapered core 1212 at the smaller end and the height Ho(and width Wo) of primary cladding layer 1210 (SiCb) of spot size converter 1200. In the illustrated example, the optical fiber may include an SMF-28 fiber, the guided optical mode may be TE mode, and the wavelength of the guided optical mode may be about 1550 nm. The height Hcof tapered core 1212 may be about 350 nm. The width Woand the height Hoof primary cladding layer 1210 (SiC ) may be about the same. The refractive index contrast between primary cladding layer 1210 and secondary cladding layer 1220 may be about 0.003. FIG. 13A shows that, when the width Wcof tapered core 1212 at the smaller end is about 120 nm and the width Woand the height Hoof primary cladding layer 1210 (SiC>2) is about 8.8 m, the coupling efficiency can be greater than 99% (or a loss less than about 43 mdB).

[0103] FIG. 13B includes a curve 1310 illustrating the simulated coupling efficiency of spot size converter 1200 as a function of the width Wcof tapered core 1212 at the smaller end when the height Hoand width Woof primary cladding layer 1210 are fixed (e.g., about 8.8 pm) and the height Hcof tapered core 1212 is fixed (e.g., about 350 nm). Curve 1310 shows that, when the height Hoand width Woof primary cladding layer 1210 are fixed at about 8.8 pm, the coupling efficiency of spot size converter 1200 may be the highest (e.g., greater than about 99.5%) when the width Wcof tapered core 1212 at the smaller end is about 120 nm.

[0104] FIG. 13C includes a curve 1320 illustrating the simulated coupling efficiency of spot size converter 1200 as a function of the height Ho(and width Wo) of primary cladding layer 1210 when the width Wcof tapered core 1212 at the smaller end is fixed (e.g., about 120 nm) and the height Hcof tapered core 1212 is fixed (e.g., about 350 nm). Curve 1320 shows that, when the width Wcof tapered core 1212 at the smaller end is fixed at about 120 nm and the height Hcof tapered core 1212 is about 350 nm, the coupling efficiency of spot size converter 1200 may be the highest (e.g., greater than about 99.6%) when the height Ho(and width Wo) of primary cladding layer 1210 is between about 8 and about 9.5 pm.

[0105] FIG. 14 includes a chart 1400 illustrating the simulated coupling efficiency of spot size converter 1200 as a function of the refractive index contrast between the primary cladding layer 1210 and the secondary cladding layer 1220. In the illustrated example, the optical fiber may include an SMF-28 fiber, the guided optical mode may be TE mode, and the wavelength of the guided optical mode may be about 1550 nm. The width Wcof tapered core1212 at the smaller end may be about 120 nm, and the height Hcof tapered core 1212 may be about 350 nm. The width Woand the height Hoof primary cladding layer 1210 (SiCh) may be about the same. A curve 1410 shows the simulated coupling efficiency of spot size converter 1200 as a function of the refractive index contrast between the primary cladding layer 1210 and the secondary cladding layer 1220 when the width Woand the height Hoof primary cladding layer 1210 is about 6 pm. A curve 1420 shows the simulated coupling efficiency of spot size converter 1200 as a function of the refractive index contrast between the primary cladding layer 1210 and the secondary cladding layer 1220 when the width Woand the height Ho of primary cladding layer 1210 is about 9 pm. A curve 1430 shows the simulated coupling efficiency of spot size converter 1200 as a function of the refractive index contrast between the primary cladding layer 1210 and the secondary cladding layer 1220 when the width Woand the height Hoof primary cladding layer 1210 is about 12 pm.

[0106] Curves 1410-1430 show that the maximum coupling efficiency may be achieved when the refractive index contrast is between about 0.0015 and about 0.01 or higher, where the peak coupling efficiency may be achieved when the refractive index contrast is about 0.003. The peak coupling efficiency may be achieved when the width Woand the height Hoof primary cladding layer 1210 is about 9 pm. A flatter coupling efficiency as a function of the refractive index contrast may be obtained when the width Woand the height Hoof primary cladding layer 1210 is larger, at the cost of a lower peak coupling efficiency. Even though not shown in FIGS. 12B-14, the performance of spot size converter 1200 may be about the same for TM mode and TE mode.

[0107] FIGS. 15A and 15B illustrate an example of a spot size converter 1500 including a lower-index secondary cladding layer 1520 according to certain embodiments. Spot size converter 1500 may be used to couple light from an optical fiber 1530 having a fiber core 1532 to a waveguide core (e.g., SiN) in a primary cladding layer 1510 (e.g., SiO2). Primary cladding layer 1510 may be surrounded by secondary cladding layer 1520, such as an epoxy or another organic or inorganic material having a lower refractive index than primary cladding layer 1510. In the illustrated example, there may be a gap between an optical fiber 1530 and the tip of spot size converter 1500, and a tapered core 1512 of spot size converter 1500 may be recessed from the tip of spot size converter 1500.

[0108] FIG. 15C illustrates the simulated coupling efficiency of spot size converter 1500 as a function of a gap between optical fiber 1530 and spot size converter 1500 or the recess oftapered core 1512 from the tip of spot size converter 1500. A curve 1550 in FIG. 15C shows the simulated coupling efficiency of spot size converter 1500 as a function of the recess of tapered core 1512 from the tip of spot size converter 1500. A curve 1560 in FIG. 15C shows the simulated coupling efficiency of spot size converter 1500 as a function of the gap between optical fiber 1530 and spot size converter 1500. FIG. 15C shows that the coupling efficiency may be reduced when the gap and / or the recess increase.

[0109] FIGS. 16A-16C illustrate examples of spot size converters according to certain embodiments. FIG. 16A shows a spot size converter 1600 including a tapered core 1620 in the center of an oxide slab 1610 (the primary cladding layer). Below and above oxide slab 1610 is secondary cladding layers 1630, which may have a refractive index lower than the refractive index of oxide slab 1610. A fiber core 1640 may be aligned with tapered core 1620, where the center of fiber core 1640 may align with the center of tapered core 1620.

[0110] FIG. 16B shows a spot size converter 1602 including a tapered core 1622 in a primary cladding layer 1612. Primary cladding layer 1612 is surrounded by a secondary cladding layer 1632. Primary cladding layer 1612 may have a square or a rectangular cross- sectional area. Secondary cladding layer 1632 may have a refractive index slightly lower (e.g., about 0.003)) than the refractive index of primary cladding layer 1612. The center of tapered core 1622 may be vertically (in the y direction) offset from the center of primary cladding layer 1612. The center of a fiber core 1642 may align with the center of primary cladding layer 1612. Fiber core 1642 may be aligned with tapered core 1622 in the x direction, but may be offset from tapered core 1622 in the y direction.

[0111] FIG. 16C shows a spot size converter 1604 including a tapered core 1624 in an oxide slab 1614 (the primary cladding layer). Below and above oxide slab 1614 is secondary cladding layers 1634, which may have a refractive index slightly lower (e.g., about 0.003) than the refractive index of the primary cladding layer (e.g., oxide slab 1614). The center of tapered core 1624 may be vertically (in the y direction) offset from the center of the primary cladding layer. The center of a fiber core 1644 may align with the center of the primary cladding layer, but may be offset from the center of tapered core 1622 in the y direction.

[0112] FIG. 17A illustrates an example of a structure 1700 including an array of spot size converters 1740 for coupling light between an array of optical fibers and an array of waveguides according to certain embodiments. FIG. 17B is a zoom-in top view of an example of a spot size converter 1740 in the array of spot size converters 1740 of FIG. 17A.FIG. 17C is a cross-sectional view of an example of a spot size converter 1740 in the array of spot size converters 1740 of FIG. 17A. Structure 1700 may include a substrate 1710 (e.g., a silicon handle wafer), one or more oxide layers 1730 formed on substrate 1710, an array of waveguide cores 1760 formed on a waveguide core layer within oxide layers 1730. Structure 1700 may also include an array of spot size converters 1740 formed in oxide layers 1730.

[0113] Each spot size converter 1740 may include a cantilever portion formed by etching regions 1732 of the one or more oxide layers 1730 and etching portions of substrate 1710 under spot size converters 1740 to form undercut regions 1720, where each undercut region 1720 may have a V-shape or U-shape and may be used as a fiber alignment structure to align and position an optical fiber. Each spot size converter 1740 may include a core 1750 formed in the waveguide core layer, where the width of core 1750 in the x direction may be inversely tapered (e.g., increase linearly or nonlinearly) in the z direction. The width of oxide layers 1730 in the x direction in the cantilever portion may also be inversely tapered (e.g., gradually increase) in the z direction or may be constant first and then inversely tapered (as shown by regions 1744) along the z direction. A region 1734 of oxide layers 1730 may not be etched, and thus may mechanically connect the cantilever portions of spot size converters 1740 to other unetched portions of oxide layers 1730 supported by substrate 1710 to provide mechanical support for the cantilever portions of spot size converters 1740, thereby increasing the stability and reliability of spot size converters 1740.

[0114] As shown in FIG. 17C, a secondary cladding material may be deposited on a spot size converter 1740 to fill the gaps surrounding oxide layers 1730 (primary cladding layer) to form a secondary cladding layer 1770. As described above, the secondary cladding material may include an epoxy or another organic or inorganic material that has a refractive index slightly lower than the refractive index of oxide layers 1730, such as about 0.003 lower than the refractive index of oxide layers 1730. The secondary cladding material may at least partially fill the undercut regions 1720 and may help to secure optical fibers on the V-grooves or U-grooves.

[0115] FIG. 18 illustrates an example of a structure 1800 including a spot size converter 1840 and a heater 1860 according to certain embodiments. Structure 1800 may be similar to, for example, structure 800, 900, 1000, or 1700 described above. Structure 1800 may include a substrate 1810 and a plurality of oxide layers 1830 formed on substrate 1810. Spot size converter 1840 may be formed in oxide layers 1830 by etching through oxide layers 1830 in some regions and further etching substrate 1810 through an isotropic etching process to forman undercut region 1820. Thus, spot size converter 1840 may include a cantilever portion on top of undercut region 1820. Undercut region 1820 may have a V-shape or a U-shape and may be used as a fiber alignment structure for positioning and aligning an optical fiber. Spot size converter 1840 may include a tapered core 1842 having a higher refractive index than oxide layers 1830, which may be a primary cladding layer for spot size converter 1840. A secondary cladding layer 1850 may be deposited on spot size converter 1840 after an optical fiber is positioned and aligned with spot size converter 1840. Secondary cladding layer 1850 may include an organic or inorganic material having a refractive index slightly lower than the refractive index of oxide layers 1830 as described above. Secondary cladding layer 1850 may surround spot size converter 1840 and may at least partially fill undercut region 1820.

[0116] As described above, the coupling efficiency of spot size converter 1840 may be improved by tuning the refractive index contrast between oxide layers 1830 and secondary cladding layer 1850. In some optical quantum computing systems, at least some of the photonic integrated circuits may need to operate at cryogenic temperature (e.g., at about 4K). According to certain embodiments, a heater 1860 (e.g., a Ni-Si heater) may be formed in oxide layers 1830 to control the local temperature at spot size converter 1840, thereby tuning the refractive index of secondary cladding layer 1850 (and / or the primary cladding layer) and thus the refractive index contrast. In the illustrated example, heater 1860 may be formed on a buried oxide layer 1832 formed on substrate 1810 and may be controlled by a controller through metal layers and vias formed in oxide layers 1830.

[0117] FIG. 19 is a flowchart 1900 illustrating an example of a process for fabricating a low-loss spot size converter for optically coupling an optical fiber to an optical waveguide according to certain embodiments. It should be appreciated that the specific operations illustrated in FIG. 19 provide a particular process of fabricating a spot size converter for optically coupling two optical components having different optical mode sizes. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the operations outlined above in a different order. Moreover, the individual operations illustrated in FIG. 19 may include multiple substeps that may be performed in various sequences as appropriate to the individual operation. Furthermore, additional operations may be added or some operations may not need to be performed, depending on the particular applications. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0118] Operations at block 1910 may include forming one or more oxide layers on a substrate. The substrate may include, for example, a silicon substrate, and the one or more oxide layers may include silicon oxide. The silicon oxide may be deposited on the substrate, or may be formed on the substrate by oxidizing a layer of the silicon substrate, such as by implanting oxygen ions into the silicon substrate. For example, the one or more oxide layers may include a buried oxide layer. In some embodiments, the silicon oxide may be deposited by high-density plasma chemical vapor deposition (HDP-CVD) of silicon-based dielectric materials, such as tetraorthosilicate (TEOS).

[0119] Operations at block 1920 may include forming a patterned waveguide core layer on the one or more oxide layers. The patterned waveguide core layer may include a high refractive index material, such as SiN or Si, and may be formed by depositing a layer of the high refractive index material using various deposition techniques and then patterning the layer of the high refractive index material using photolithography techniques. The patterned waveguide core layer may form the core of waveguides or other photonic integrated circuits described above. The patterned waveguide core layer may include a tapered portion, where the width of the tapered portion may gradually change (increase or decrease), either linearly or nonlinearly.

[0120] At block 1930, additional oxide layers may be deposited on the patterned waveguide layer to cover the waveguide layer. As described above, the oxide layers may be deposited, for example, by high-density plasma chemical vapor deposition of silicon-based dielectric materials, such as tetraorthosilicate. The oxide layers above and below the patterned waveguide core layer and the patterned waveguide core layer may form waveguides on the substrate, where the oxide layers may be the primary cladding layer of the waveguides. The oxide layers and the tapered portion of the patterned waveguide core layer may form a spot size converter. In some embodiments, other structures, such as heaters, single photon generators, scattering mitigation structures, switches, photon detectors, and other photonic integrated circuits, may be formed in the oxide layers.

[0121] At block 1940, portions of the oxide layers may be etched to form apertures in the oxide layers. For example, a patterned etch mask layer may be formed on the oxide layers and dry or wet etching processes may be performed to remove the exposed portions of the oxide layers. In some embodiments, after the oxide etching, the oxide layers surrounding the tapered portion of the waveguide core layer may have a tapered shape where the width of the oxide layers may gradually increase as shown in, for example, FIG. 9C. In someembodiments, after the oxide etching, the oxide layers surrounding the tapered portion of the waveguide core layer may be constant in one section and may be tapered in another section as shown in, for example, FIG. 10B, 17A, or 17B.

[0122] At block 1950, portions of the substrate may be etched to form undercut regions in the substrate. For example, the undercut regions may be formed by isotropic etching (e.g., wet etching) of the substrate through the apertures in the oxide layers. An undercut region may have a V-shape or U-shape and may be used as a fiber alignment structure. The tapered waveguide core layer and the surrounding oxide layers on an undercut region may form a cantilever portion of a spot size converter. As described above with respect to, for example, FIG. 10B, 17A, or 17B, in some embodiments, the oxide layers may be patterned such that some portions of the oxide layers may connect the cantilever portion to other portions of the oxide layers supported by the substrate to provide mechanical support for the cantilever portion.

[0123] At block 1960, an optical fiber may be positioned on the fiber alignment structure. Because the fiber alignment structure may align with the cantilever portion of the spot size converter, the optical fiber on the fiber alignment structure may align with the spot size converter as well. In some embodiments, there may be a gap between the tip of the optical fiber and the tip of the cantilever portion.

[0124] At block 1970, a secondary cladding material (e.g., an epoxy such as NTT E3810) having a refractive index lower than a refractive index of the oxide layers may be deposited on the cantilever portion of the spot size converter and may fill gaps in the etched regions. The secondary cladding material may be on top and bottom of the cantilever portion or may surround the cantilever portion, and may help to shape (e.g., expand) the optical field of the optical mode in the spot size converter to better match the optical fields of the optical modes in the optical fiber and the waveguides.

[0125] FIG. 20 is a simplified block diagram of an example of a system 2000 including two or more dies or wafers according to certain embodiments. In the illustrated example, a first die 2010 (or a wafer or another module) may include a photonic integrated circuit 2012 that may include, for example, single photon generators, mode couplers, fusion gates, beam splitters, switches, single photon detectors or multi-photon detectors, waveguides, delay lines, modulators, optical switches, ring oscillators, couplers, photodiode-based photodetectors for receiving data and timing signals, and the like, as described above. First die 2010 may alsoinclude multiple low-loss spot size converters 2014 optically coupled to photonic integrated circuit 2012. Low-loss spot size converters 2014 may be examples of low-loss spot size converters described above and may be used to couple light from a fiber (e.g., a fiber 2015, 2016, or 2018) to photonic integrated circuit 2012 or from photonic integrated circuit 2012 to a fiber (e.g., fiber 2015, 2016, or 2018). For example, a low-loss spot size converter 2014 may be used to couple light between photonic integrated circuit 2012 and fiber 2016, which may be connected to another die, wafer, or module. Two low-loss spot size converters 2014 may he used to couple light between two portions of photonic integrated circuit 2012 through a fiber 2018.

[0126] Similarly, a second die 2020 (or a wafer or another module) may include a photonic integrated circuit 2022 that may include, for example, single photon generators, mode couplers, fusion gates, beam splitters, switches, single photon detectors or multi-photon detectors, waveguides, delay lines, modulators, optical switches, ring oscillators, couplers, photodiode-based photodetectors for receiving data and timing signals, and the like, as described above. Second die 2020 may also include multiple low-loss spot size converters 2024 optically coupled to photonic integrated circuit 2022. Low-loss spot size converters 2024 may be examples of low-loss spot size converters described above and may be used to couple light from a fiber (e.g., fiber 2015, 2026, or 2028) to photonic integrated circuit 2022 or from photonic integrated circuit 2022 to a fiber (e.g., fiber 2015, 2026, or 2028). For example, a low-loss spot size converter 2024 may be used to couple light between photonic integrated circuit 2022 and fiber 2026, which may be connected to another die, wafer, or module. Two low-loss spot size converters 2024 may be used to couple light between two portions of photonic integrated circuit 2022 through a fiber 2028. A low-loss spot size converters 2024 and a low-loss spot size converters 2014 may both be coupled to a fiber 2015, and thus may optically couple photonic integrated circuit 2012 to photonic integrated circuit 2022.

[0127] In the alternative embodiments described below, the above descried secondary cladding may comprise an oxide material, such as an inorganic oxide material, for example silicon oxide. The silicon oxide may comprise stoichiometric silicon dioxide (i.e., silicon dioxide) or non-stoichiometric silicon oxide in which the atomic ratio of silicon to oxygen is different than 1:2, such as silicon-rich silicon oxide in which the atomic ratio of silicon to oxygen is greater than 1 :2, such as 1.01:2 to 1 : 1. The secondary cladding is first formed in a trench in a substrate. The primary cladding and the waveguide core of the spot size converterare then formed over the oxide secondary cladding. The methods of the alternative embodiments avoid performing the difficult undercut etch under the primary cladding to form the V-groove and forming the cantilevered spot size converter which may be subject to mechanical strain. These methods of the alternative embodiments also permit use of an inorganic oxide secondary cladding, such as a silicon oxide secondary cladding, in place of an organic secondary cladding.

[0128] FIGS. 21A - 21H illustrate the steps in a method of a first alternative embodiment of the present disclosure. Referring to FIG. 21 A, a substrate 2110 is provided. The substrate may comprise any suitable substrate, such as a semiconductor substrate, for example a silicon substrate (e.g., bulk silicon wafer) or a silicon on insulator (SOI) substrate. A optional pad oxide (e.g., silicon oxide) layer 2111 may be formed over the top surface of the substrate 2110. A planarization stop layer is formed over the top surface of the substrate 2110. In one embodiment, the planarization stop layer comprises a chemical mechanical polishing (CMP) stop layer 2160. If the pad oxide layer 21 11 is present, then the CMP stop layer 2160 may be formed on the pad oxide layer 2111. The CMP stop layer 2160 may comprise any material which functions as a stopping layer during a CMP process and which has a different composition than the oxide secondary cladding to be formed in a subsequent step. For example, the CMP stop layer 2160 may comprise silicon nitride, silicon oxynitride or a dielectric metal oxide, such as aluminum oxide.

[0129] Referring to FIG. 21B, a photolithography masking layer, such as a photoresist layer, is formed over the CMP stop layer 2160 and patterned (e.g., exposed and developed) to form a photolithography mask 2162 with an opening in the area of the above described V- groove.

[0130] Referring to FIG. 21C, the CMP stop layer 2160, the pad oxide layer 2111 and the substrate 2110 are etched using the photolithography masking layer 2162 as mask to form a trench 21 12 in the substrate 21 10. The trench 2112 extends through the CMP stop layer 2160 and the pad oxide layer 2111 and into the substrate 2110. The trench 2112 may have tapered sidewalls to form the above described V-groove or straight vertical sidewalls. The trench 2112 may have any suitable dimensions. For example, it may have a width of 10 to 100 microns, such as 20 to 50 microns, and a depth of 5 to 50 microns, such as 10 to 20 microns, to permit coupling of the above described optical fiber to the spot size converter without the edge of the optical fiber overlapping the edge surface of the substrate 2110. The photolithography mask 2162 is then removed by ashing or by selective etching.

[0131] Referring to FIG. 21D, a first oxide layer 2164 is formed over the substrate 2110. The first oxide layer 2164 may comprise an inorganic oxide layer, such as a silicon oxide layer, deposited by any suitable conformal deposition method, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The first oxide layer 2164 has a first portion located over a top surface of the substrate 2110 (e.g., on the CMP stop layer 2160 located over the substrate 2110) and a second portion partially filling the trench 2112. A recess 2112R remains in the trench 2112 over the top surface of the first oxide layer 2164. If the trench 21 12 has tapered sidewalls, then the conformality of the first oxide layer 2164 to the trench sidewalls may be improved.

[0132] Referring to FIG. 21E, at least a part of the first portion of the first oxide layer 2164 is removed from over the top surface of the substrate 2110 (e.g., from over the top surface of the CMP stop layer 2160), while leaving the second portion in the trench 2112. The first portion of the first oxide layer 2164 may be completely removed by a first CMP step using the CMP stop layer 2160 as a stopping layer for the CMP process. Alternatively, the top part of the first portion of the first oxide layer 2164 may be removed by a timed first CMP step while leaving a bottom portion of the first portion of the first oxide layer 2164 over the CMP stop layer 2160.

[0133] Referring to FIG. 21F, a second oxide layer 2166 is formed over the substrate 2110. The second oxide layer 2166 may comprise an inorganic oxide layer, such as a silicon oxide layer, which is deposited by CVD or ALD using the first oxide layer 2164 as a seed, which improves the growth of the second oxide layer 2166. Alternatively, the second oxide layer 2166 may be deposited by a non-conformal deposition method, such as spin coating or sputtering. The second oxide layer 2166 has a first portion located over a top surface of the substrate 2110 (e.g., on the CMP stop layer 2160 located over the substrate 2110) and a second portion located in the recess 2112R in the second portion of the first oxide layer 2164 in the trench 2112.

[0134] Referring FIG. 21G, the second oxide layer 2166 is planarized to remove the first portion of the second oxide layer 2166 from over the top surface of the substrate 2110 (e.g., from over the CMP stop layer 2160), while leaving the second portion of the second oxide layer 2166 in the trench 2112 (e.g., in the recess 2112R in the second portion of the first oxide layer 2164 in the trench 2112). In this embodiment, the first portion of the second oxide layer 2166 is removed by a second CMP step using the CMP stop layer 2160 as a stopping layer for the CMP process. If any part of the first portion of the first oxide layer2164 remains over the CMP stop layer 2160 after the first CMP step shown in FIG. 21E, then this part of the first portion of the first oxide layer 2164 is also removed by the second CMP step. Thus, the second CMP step stops on the CMP stop layer 2160.

[0135] The second portion of the second oxide layer 2166 in the trench 2112 has a planar top surface. The planar top surface of the second portion of the second oxide layer 2166 is coplanar with a top surface of the CMP stop layer 2160. The combination of the second portion of the first oxide layer 2164 and the second portion of the second oxide layer 2166 filling the trench (e.g., the V-groove) 2112 and having the planar top surface comprises a first portion (e.g., lower portion) of an oxide secondary cladding 2140. While two oxide layers and two planarization steps are described above, in other embodiments, three or more oxide layers and respective planarization steps may be used to form the oxide secondary cladding 2140.

[0136] Referring FIG. 21H, the oxide secondary cladding 2140 may be annealed at a relatively high temperature (e.g., above 500 degrees Celsius) to improve the quality of the oxide secondary cladding 2140. The anneal may comprise a furnace, flash lamp and / or laser anneal in vacuum or in an ambient, such as oxygen (e.g., air), nitrogen and / or inert gas (e.g., argon or another noble gas) ambient. In an alternative embodiment, the first and second oxide layers 2164 and 2166 may be annealed separately after their deposition.

[0137] FIGS. 22A - 22K illustrate the steps in a method of a second alternative embodiment of the present disclosure. The same reference numbers in FIGS. 22 A - 22K correspond to the same layers as in FIGS. 21 A - 21H.

[0138] Referring to FIGS. 22A to 22D, the steps described above with respect to respective FIGS. 21 A to 21D are performed to form the first oxide layer 2164 in the trench 2112 and over the top surface of the substrate 2110.

[0139] Referring to FIG. 22E, in the second alternative embodiment, the step of removing at least a part of the first portion of the first oxide layer 2164 comprises forming a mask layer 2270 in the recess 2112R in the second portion of the first oxide layer 2164 located in the trench 2112, while exposing the first portion of the first oxide layer 2164. In this embodiment, the mask layer 2270 may comprise a non-conformal optical planarization layer which is formed over the first oxide layer 2164 and fills the entire volume of the recess 2112R. The optical planarization layer may comprise an organic layer, such as a spin-on amorphous carbon layer.

[0140] Referring to FIG. 22F, if a portion of the mask layer 2270 is formed over the top surface of the first portion of the second oxide layer 2164, then the mask layer 2270 may be etched back (i.e., thinned by etching) to expose the top surface of the first portion of the second oxide layer 2164. The step of etching back the mask layer 2270 leaves a patterned mask layer T 1 in the recess 2112R in the second portion of the first oxide layer 2164 located in the trench 2112. Alternatively, if the patterned mask layer 2272 is deposited only in the recess 2112R, then the etch back step of FIG. 22F may be omitted.

[0141] Referring to FIG. 22G, the step of removing at least the part of the first portion of the first oxide layer 2164 further comprises etching back the first portion of the first oxide layer that is exposed by the patterned mask layer 2272. The patterned mask layer 2272 is used as an etch mask to prevent etching of the second portion of the first oxide layer 2164 located in the recess 2111R.

[0142] Referring to FIG. 22H, the patterned mask layer l is removed by ashing or by selective etching.

[0143] Referring to FIGS. 221 to 22K, the steps described above with respective FIGS. 21F to 21H are performed to form the oxide secondary cladding 2140 in the trench 2112 in the substrate 2110.

[0144] FIGS. 23 A - 23G illustrate the steps in a method of a third alternative embodiment of the present disclosure. The same reference numbers in FIGS. 23A - 23G correspond to the same layers as in FIGS. 21 A - 21H.

[0145] Referring to FIGS. 23A and 23B, the steps described above with respective FIGS 21 A to 2 ID are performed to form the first oxide layer 2164 in the trench 2112 and over the top surface of the substrate 2110.

[0146] Referring to FIG. 23C, in the third alternative embodiment, the step of removing at least a part of the first portion of the first oxide layer 2164 comprises forming a patterned mask layer 2372 in the recess 2112R in the second portion of the first oxide layer 2164 located in the trench 2112, while exposing the first portion of the first oxide layer 2164. In this embodiment, the pattered mask layer 2372 may comprise a portion of a negative tone photoresist layer which is formed over the first oxide layer 2164 and fills the entire volume of the recess 2112R. The negative tone photoresist layer is exposed through a photomask and developed to leave the patterned mask layer 2372 portion of the negative tone photoresist layer in the recess 2112R in the second portion of the first oxide layer 2164 located in thetrench 2112.

[0147] Referring to FIG. 23D, at least a part of the thickness of the first portion of the first oxide layer 2164 is then removed by etching using the patterned mask layer 2372 as an etch mask. The patterned mask layer 2372 is then removed by ashing or by selective etching.

[0148] Referring to FIGS. 23E to 23G, the steps described above with respective FIGS. 21F to 21H are performed to form the oxide secondary cladding 2140 in the trench 2112 in the substrate 2110.

[0149] FIGS. 24A - 24C illustrate the steps in a method of a fourth alternative embodiment of the present disclosure. The same reference numbers in FIGS. 24 A - 24C correspond to the same layers as in FIGS. 21 A - 21H.

[0150] Referring to FIG. 24A, a semiconductor substrate 2110, such as a silicon substrate, is provided. Alternatively, other semiconductor substrates, such as a compound semiconductor substrate may be used.

[0151] Referring to FIG. 24B, a plurality of trenches 2412 are formed in the semiconductor substrate 2110. The plurality of trenches 2412 are laterally separated from each other by remaining semiconductor fin portions 2413 of the semiconductor substrate 2412. The plurality of trenches 2412 may be formed by photolithography and etching, such as reactive ion etching.

[0152] Referring to FIG. 24C, the semiconductor fin portions 2413 are oxidized to convert the semiconductor fin portions to semiconductor oxide fin portions. The oxidation may comprise wet or dry oxidation in a water vapor, air or pure oxygen ambient at an elevated temperature sufficient to oxidize the semiconductor fin portions to semiconductor oxide fin portions. The formation of semiconductor oxide fin portions completely fills the plurality of trenches 2412 with the semiconductor oxide to form a continuous semiconductor oxide fill region 2140 in the semiconductor substrate 2110.

[0153] In one embodiment, the semiconductor oxide fill region 2140 may comprise the above described oxide secondary cladding of the spot size converter. However, the method of the fourth alternative embodiment may alternatively be used to form a continuous semiconductor oxide fill region 2140 in the semiconductor substrate 2110 in any optical or electronic device.

[0154] In one embodiment, the semiconductor substrate 2110 comprises a siliconsubstrate, and the continuous semiconductor oxide fill region 2140 comprises a silicon oxide fill region.

[0155] In one embodiment, the semiconductor fins 2413 comprise silicon fins which extend along a <100> crystallographic direction, have width of 1 micron or less (e.g., 0.1 to 1 microns) and an aspect ratio of at least 10, such as 10 to 100, to reduce the corner rounding effect. In one embodiment, the trench 2412 depth is at least 10 microns, such as 10 to 50 microns, and a ratio of the trench 2412 width to the silicon fin 2413 width is between 0.45 and 0.47, such as about 0.46, to completely fill the trenches with silicon oxide fill region 2140, because silicon volume laterally expands when oxidized to silicon oxide.

[0156] FIGS. 25 A and 25B illustrate a configuration of the alternative embodiments in which the substrate 21 10 comprises a bulk silicon substrate 21 10. FIG. 25 A illustrates the starting structures of the first through third alternative embodiments shown in FIGS. 21 A, 22A and 23 A, and FIG. 25B illustrates the final structure of the first through fourth embodiments in which the oxide secondary cladding 2140 is formed in the trench(es) 2112 or 2412 in the bulk silicon substrate 21 10.

[0157] FIGS. 26A and 26B illustrate another configuration of the alternative embodiments in which the substrate comprises a silicon on insulator (SOI) substrate 2170. The silicon on insulator substrate 2170 includes a bulk silicon substrate 2110, a buried oxide (e.g., silicon oxide) layer 2180 and a relatively thin silicon device layer 2182. FIG. 26A illustrates the starting structures of the first through third alternative embodiments on the SOI substrate 2170, and FIG. 26B illustrates the final structure of the first through fourth embodiments in which the oxide secondary cladding 2140 is formed in the trench 2112 in at least the silicon device layer 2182. Optionally, the trench 2112 may extend into the buried oxide layer 2180, or through the buried oxide layer 2180 and into a top part of the bulk silicon substrate 2110. In these cases, the oxide secondary cladding 2140 may extend into the buried oxide layer 2180, or through the buried oxide layer 2180 and into the top part of the bulk silicon substrate 2110.

[0158] FIGS. 27A - 27E illustrate a method of forming waveguide, such as the above described spot size converter, over the oxide filled trench of the first, second, third or fourth alternative embodiment described above. The spot size converter T1 1 of the alternative embodiments may be formed over the bulk silicon substrate 2110 shown in FIG. 25B, or over the SOI substrate 2170 shown in FIG. 26B.

[0159] Referring to FIG. 27 A, the oxide secondary cladding 2140 is formed over the SOI substrate 2170 of FIGS. 26A and 26B. However, as noted above, the oxide secondary cladding 2140 may alternatively be formed over the bulk silicon substrate 21 10 of FIGS. 25 A and 25B.

[0160] Referring to FIG. 27B, additional waveguides 2750 and / or other photonic devices may optionally be formed over the substrate 2110. For example, the buried oxide 2180 may function as a bottom cladding of the additional waveguides 2750. The silicon device layer 2182 may be photolithographically patterned to form additional silicon waveguide cores 2751 of the additional waveguides 2750. Alternatively, if a bulk silicon substrate is used, then an additional silicon layer may be deposited and patterned to form the additional silicon waveguide cores 2751.

[0161] Subsequently, a top cladding layer (e.g., silicon oxide layer) 2792 is deposited over the top and sides of the additional silicon waveguide cores 2751. The top cladding layer 2792 may be planarized by etch back or CMP with the planar top surface of the oxide secondary cladding 2740. The buried oxide 2180 and the top cladding layer 2792 together form the cladding of the additional waveguides 2750.

[0162] Referring to FIG. 27C, a lower primary cladding layer 2726L is formed over the planar top surface of the oxide secondary cladding 2140 and over the planar top surface of the top cladding layer 2792 of the additional waveguides 2750. The lower primary cladding layer 2726L may comprise a silicon oxide layer.

[0163] A primary waveguide core layer 2724L is then deposited over the lower primary cladding layer 2726L. The primary waveguide core layer 2724L may comprise the same or different material from the additional waveguide cores 2751. In one embodiment, the primary waveguide core layer 2724L may comprise a silicon nitride layer.

[0164] Referring to FIG. 27D, the primary waveguide core layer 2724L is photolithographically patterned to form the primary waveguide core 2724. The primary waveguide core 2724 may comprise a silicon nitride core. Thus, the primary waveguide core 2724 is formed on the lower cladding layer 2726L.

[0165] Referring to FIG. 27E, an upper cladding layer 2726U is deposited on the lower cladding layer 2726L and in contact with a top surface and sidewalls of the primary waveguide core 2724. The upper cladding layer 2726U may comprise a silicon oxide layer.

[0166] The lower primary cladding layer 2762L functions as the lower part of theprimary cladding 2762 of the spot size converter 2722. The upper primary cladding layer 2762U functions as the upper part of the primary cladding 2762 of the spot size converter 2722. An optional second portion (e.g., upper portion) of an oxide secondary cladding may be formed over the upper part of the primary cladding 2762, as described in the prior embodiments.

[0167] In one embodiment, the refractive index of the oxide secondary cladding 2140 is lower than a refractive index of the oxide primary cladding 2726. For example, the oxide secondary cladding 2140 may comprise a first silicon oxide material having a first composition and a first density; the oxide primary cladding 2726 may comprise a second silicon oxide material having a second composition and a second density; and at least one of the first composition and the first density may be different from a corresponding one of the second composition and the second density. For example, the oxide secondary cladding 2140 may be deposited by a different deposition method and / or by using different deposition parameters (e.g., different plasma power for a plasma enhanced CVD deposition method) in the same type of deposition method, and / or using different precursors (e.g., having a different amount of carbon and / or hydrogen) which result in a composition and / or density difference. The composition difference may comprise a difference in silicon to oxygen ratio and / or a different amount of hydrogen and / or carbon dopant incorporated into the silicon oxide.

[0168] According to an embodiment, the optical device shown in FIG. 27E comprises a substrate 2110 or 2170 comprising a trench 21 12; an oxide secondary cladding 2140 comprising a lower portion filling the trench 2112 and having a planar top surface; an oxide primary cladding 2762 located on the planar top surface of the oxide secondary cladding 2140; and a first (e.g., primary) waveguide core 2724 embedded in the oxide primary cladding 2726.

[0169] According to any one or more embodiments above, the optical device includes the spot size converter 1722 which is optically coupled to the above described optical fiber which does not contact the substrate 2110 or 2170. According to any one or more embodiments above, the first waveguide core 2724 comprises a silicon nitride core.

[0170] According to any one or more embodiments above, the refractive index of the oxide secondary cladding 2140 is lower than a refractive index of the oxide primary cladding 2726; the oxide secondary cladding 2140 comprises a first silicon oxide material having a first composition and a first density; the oxide primary cladding 2726 comprises a secondsilicon oxide material having a second composition and a second density; and at least one of the first composition and the first density is different from a corresponding one of the second composition and the second density.

[0171] According to any one or more embodiments above, the trench 2112 has tapered sidewalls (e.g., having a taper angle greater than zero and less than 90 degrees relative to a vertical direction normal to the top surface of the substrate) such that the top of the trench 2110 is wider than a bottom of the trench 2110 (e.g., such that the trench has a V-groove shape described above); the oxide primary cladding 2762 comprises a first silicon oxide material and the oxide secondary cladding 2140 comprises a second silicon oxide material having a lower refractive index than the first silicon oxide material; the substrate 2110 comprises a bulk silicon substrate or a silicon on insulator substrate; and the first (e.g., primary) waveguide core 2724 comprises a silicon core or a silicon nitride core.

[0172] According to any one or more embodiments above, the first waveguide core 2724 comprises the silicon nitride core, and the optical device further comprises a silicon second (e.g., additional) waveguide core 2751 that is located over a top surface of the substrate 21 10, and that is laterally spaced from the trench 2112 and from the first portion of the oxide secondary cladding 2140 filling the trench 2112.

[0173] According to any one or more embodiments above, the trench 2112 is at least 10 microns deep, and the first (e.g., lower) portion of the oxide secondary cladding 2140 filling the trench has a thickness of at least 10 microns.

[0174] According to any one or more embodiments above, the oxide primary cladding 2726 comprises a first silicon oxide layer 2726L located on the planar top surface of the oxide secondary cladding 2140 and contacting a bottom surface of the first waveguide core 2724; and a second silicon oxide layer 2726U located on the first silicon oxide layer 2726L and contacting a top surface and sidewalls of the first waveguide core 2724.

[0175] According to any one or more embodiments above, the first silicon oxide layer 2726L laterally extends past sidewalls of the trench 2112 and past sidewalls of the first portion of the oxide secondary cladding 2140 filling the trench.

[0176] According to any one or more embodiments above, a second (e.g., additional) waveguide core 2751 is located over a top surface of the substrate 2110, and is laterally spaced from the trench 2112 and from the first portion of the oxide secondary cladding 2140 filling the trench; a third silicon oxide cladding layer 2180 (i.e., bottom cladding of theadditional waveguide 2150) is located between the top surface of the substrate 2110 and a bottom surface of the second waveguide core 2751; and a fourth silicon oxide gap fill cladding layer 2792 (i.e., top cladding of the additional waveguide 2150) is located on the third silicon oxide cladding layer 2180 and contacts a top surface and sidewalls of the second waveguide core 2751 to form the additional waveguide 2750.

[0177] According to another embodiment, a method comprises forming a trench in a substrate; forming a first oxide layer having a first portion located over a top surface of the substrate and a second portion partially filling the trench; removing at least a part of the first portion of the first oxide layer from over the top surface of the substrate, while leaving the second portion in the trench; forming a second oxide layer having a first portion located over a top surface of the substrate and a second portion located in a recess in the second portion of the first oxide layer in the trench; and planarizing the second oxide layer to remove the first portion of the second oxide layer from over the top surface of the substrate, while leaving the second portion of the second oxide layer in the trench.

[0178] According to any one or more embodiments above, the second portion of the second oxide layer in the trench has a planar top surface.

[0179] According to any one or more embodiments above, the method also includes forming a planarization stop layer over the top surface of the substrate prior to forming the first oxide layer; and forming the trench through the planarization stop layer.

[0180] According to any one or more embodiments above, the planar top surface of the second portion of the second oxide layer is coplanar with a top surface of the planarization stop layer.

[0181] According to any one or more embodiments above, the step of planarizing the second oxide layer comprises a chemical mechanical polishing step which stops on the planarization stop layer.

[0182] According to any one or more embodiments above, the planarization stop layer comprises silicon nitride, the first oxide layer comprises silicon oxide, and the second oxide layer comprises silicon oxide.

[0183] According to any one or more embodiments above, the step of removing at least a part of the first portion of the first oxide layer comprises another chemical mechanical polishing step.

[0184] According to any one or more embodiments above, the step of removing at least a part of the first portion of the first oxide layer comprises: forming a patterned mask layer in the recess in the second portion of the first oxide layer in the trench while exposing the first portion of the first oxide layer; etching back the first portion of the first oxide layer exposed by the patterned mask layer; and removing the patterned mask layer.

[0185] According to any one or more embodiments above, the step of forming the patterned mask layer comprises forming an optical planarization layer over the first oxide layer, and etching back the optical planarization layer to leave the patterned mask layer portion of the planarization layer in the recess in the second portion of the first oxide layer in the trench.

[0186] According to any one or more embodiments above, the step of forming the patterned mask layer comprises forming a negative tone photoresist layer over the first oxide layer, and exposing and developing the negative tone photoresist layer to leave the patterned mask portion of the negative tone photoresist layer in the recess in the second portion of the first oxide layer in the trench.

[0187] According to any one or more embodiments above, the method also comprises forming a lower cladding layer over the planar top surface; forming a silicon nitride waveguide core on the lower cladding layer; and forming an upper cladding layer on the lower cladding layer and contacting a top surface and sidewalls of the silicon nitride waveguide core.

[0188] According to another embodiment, a method comprises forming a plurality of trenches in a semiconductor substrate, wherein the plurality of trenches are laterally separated from each other by remaining semiconductor fin portions of the semiconductor substrate; and oxidizing the fin portions to convert the semiconductor fin portions to semiconductor oxide fin portions and to completely fill the plurality of trenches with the semiconductor oxide to form a continuous semiconductor oxide fill region in the semiconductor substrate.

[0189] According to any one or more embodiments above, the semiconductor substrate comprises a silicon substrate, and the continuous semiconductor oxide fill region comprises a silicon oxide fill region.

[0190] According to any one or more embodiments above, the semiconductor fins comprise silicon fins which extend along a <100> direction and have width of 1 micron or less.

[0191] According to any one or more embodiments above, a depth of the plurality of the trenches is at least 10 microns, and a ratio of a width of the plurality of trenches to a width of the semiconductor fins is between 0.45 and 0.47.

[0192] According to any one or more embodiments above, the method further comprises forming a lower silicon oxide cladding layer over the silicon oxide fill region, wherein the silicon oxide fill region has a refractive index that is lower than a refractive index of the lower silicon oxide cladding layer; forming a silicon nitride waveguide core on the lower silicon oxide cladding layer; and forming an upper silicon oxide cladding layer on the lower silicon oxide cladding layer and contacting a top surface and sidewalls of the silicon nitride waveguide core.

[0193] It will be apparent to those skilled in the art that substantial variations may be made in accordance with specific implementations. For example, customized hardware might also be used, and / or particular elements might be implemented in hardware, software (including portable software, such as applets, etc.), or both. Further, connection to other computing devices such as network input / output devices may be employed.

[0194] With reference to the appended figures, components that can include memory can include non-transitory machine-readable media. The terms “machine-readable medium” and “computer-readable medium” as used herein refer to any storage medium that participates in providing data that causes a machine to operate in a specific fashion. In embodiments provided hereinabove, various machine-readable media might be involved in providing instructions / code to processors and / or other device(s) for execution. Additionally or alternatively, the machine-readable media might be used to store and / or carry such instructions / code. In many implementations, a computer-readable medium is a physical and / or tangible storage medium. Such a medium may take many forms, including, but not limited to, non-volatile media, volatile media, and transmission media. Common forms of computer-readable media include, for example, magnetic and / or optical media, punch cards, paper tape, any other physical medium with patterns of holes, a RAM, a programmable readonly memory (PROM), an erasable programmable read-only memory (EPROM), a FLASH- EPROM, any other memory chip or cartridge, a carrier wave as described hereinafter, or any other medium from which a computer can read instructions and / or code.

[0195] The methods, systems, and devices discussed herein are examples. Various embodiments may omit, substitute, or add various procedures or components as appropriate.For instance, features described with respect to certain embodiments may be combined in various other embodiments. Different aspects and elements of the embodiments may be combined in a similar manner. The various components of the figures provided herein can be embodied in hardware and / or software. Also, technology evolves and, thus, many of the elements are examples that do not limit the scope of the disclosure to those specific examples.

[0196] It has proven convenient at times, principally for reasons of common usage, to refer to such signals as bits, information, values, elements, symbols, characters, variables, terms, numbers, numerals, or the like. It should be understood, however, that all of these or similar terms are to be associated with appropriate physical quantities and are merely convenient labels. Unless specifically stated otherwise, as is apparent from the discussion above, it is appreciated that throughout this specification discussions utilizing terms such as “processing,” “computing,” “calculating,” “determining,” “ascertaining,” “identifying,” “associating,” “measuring,” “performing,” or the like refer to actions or processes of a specific apparatus, such as a special purpose computer or a similar special purpose electronic computing device. In the context of this specification, therefore, a special purpose computer or a similar special purpose electronic computing device is capable of manipulating or transforming signals, typically represented as physical electronic, electrical, or magnetic quantities within memories, registers, or other information storage devices, transmission devices, or display devices of the special purpose computer or similar special purpose electronic computing device.

[0197] Those of skill in the art will appreciate that information and signals used to communicate the messages described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0198] Terms “and,” “or,” and “an / or,” as used herein, may include a variety of meanings that also is expected to depend at least in part upon the context in which such terms are used. Typically, “or” if used to associate a list, such as A, B, or C, is intended to mean A, B, and C, here used in the inclusive sense, as well as A, B, or C, here used in the exclusive sense. In addition, the term “one or more” as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe some combination of features, structures, or characteristics. However, it should be noted that this is merely anillustrative example and claimed subject matter is not limited to this example. Furthermore, the term “at least one of’ if used to associate a list, such as A, B, or C, can be interpreted to mean A, B, C, or any combination of A, B, and / or C, such as AB, AC, BC, AA, AAB, ABC, AABBCCC, and the like.

[0199] Reference throughout this specification to “one example,” “an example,” “certain examples,” or “exemplary implementation” means that a particular feature, structure, or characteristic described in connection with the feature and / or example may be included in at least one feature and / or example of claimed subject matter. Thus, the appearances of the phrase “in one example,” “an example,” “in certain examples,” “in certain implementations,” or other like phrases in various places throughout this specification are not necessarily all referring to the same feature, example, and / or limitation. Furthermore, the particular features, structures, or characteristics may be combined in one or more examples and / or features.

[0200] In some implementations, operations or processing may involve physical manipulation of physical quantities. Typically, although not necessarily, such quantities may take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, or otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to such signals as bits, data, values, elements, symbols, characters, terms, numbers, numerals, or the like. It should be understood, however, that all of these or similar terms are to be associated with appropriate physical quantities and are merely convenient labels. Unless specifically stated otherwise, as apparent from the discussion herein, it is appreciated that throughout this specification discussions utilizing terms such as “processing,” “computing,” “calculating,” “determining,” or the like refer to actions or processes of a specific apparatus, such as a special purpose computer, special purpose computing apparatus or a similar special purpose electronic computing device. In the context of this specification, therefore, a special purpose computer or a similar special purpose electronic computing device is capable of manipulating or transforming signals, typically represented as physical electronic or magnetic quantities within memories, registers, or other information storage devices, transmission devices, or display devices of the special purpose computer or similar special purpose electronic computing device.

[0201] In the preceding detailed description, numerous specific details have been set forth to provide a thorough understanding of claimed subject matter. However, it will be understood by those skilled in the art that claimed subject matter may be practiced without these specific details. In other instances, methods and apparatuses that would be known byone of ordinary skill have not been described in detail so as not to obscure claimed subject matter. Therefore, it is intended that the claimed subject matter is not limited to the particular examples disclosed, but that such claimed subject matter may also include all aspects falling within the scope of appended claims, and equivalents thereof.

Claims

Claims1. An optical device, comprising: a substrate comprising a trench; an oxide secondary cladding comprising a first portion filling the trench and having a planar top surface; an oxide primary cladding located on the planar top surface of the oxide secondary cladding; and a first waveguide core embedded in the oxide primary cladding.

2. The optical device of claim 1 , wherein the optical device comprises a spot size converter which is optically coupled to an optical fiber which does not contact the substrate.

3. The optical device of claim 1, wherein the first waveguide core comprises a silicon nitride core.

4. The optical device of claim 1, wherein: a refractive index of the oxide secondary cladding is lower than a refractive index of the oxide primary cladding; the oxide secondary cladding comprises a first silicon oxide material having a first composition and a first density; the oxide primary cladding comprises a second silicon oxide material having a second composition and a second density; and at least one of the first composition and the first density is different from a corresponding one of the second composition and the second density.

5. The optical device of claim 4, wherein: the trench has tapered sidewalls such that the top of the trench is wider than a bottom of the trench; the oxide primary cladding comprises a first silicon oxide material; the oxide secondary cladding comprises a second silicon oxide material having a lower refractive index than the first silicon oxide material; the substrate comprises a silicon substrate or a silicon on insulator substrate; and the first waveguide core comprises a silicon core or a silicon nitride core.

6. The optical device of claim 5, wherein the first waveguide core comprises the silicon nitride core, and further comprising a silicon second waveguide core that is located over a top surface of the substrate and that is laterally spaced from the trench and from the first portion of the oxide secondary cladding filling the trench.

7. The optical device of claim 1, wherein the trench is at least 10 microns deep, and the first portion of the oxide secondary cladding filling the trench has a thickness of at least 10 microns.

8. The optical device of claim 1, wherein the oxide primary cladding comprises: a first silicon oxide layer located on the planar top surface of the oxide secondary cladding and contacting a bottom surface of the first waveguide core; and a second silicon oxide layer located on the first silicon oxide layer and contacting a top surface and sidewalls of the first waveguide core.

9. The optical device of claim 8, wherein the first silicon oxide layer laterally extends past sidewalls of the trench and past sidewalls of the first portion of the oxide secondary cladding filling the trench.

10. The optical device of claim 9, further comprising: a second waveguide core located over a top surface of the substrate and laterally spaced from the trench and from the first portion of the oxide secondary cladding filling the trench; a third silicon oxide cladding layer located between the top surface of the substrate and a bottom surface of the second waveguide core; and a fourth silicon oxide gap fill cladding layer located on the third silicon oxide cladding layer and contacting a top surface and sidewalls of the second waveguide core.1 1. A method, comprising: forming a trench in a substrate; forming a first oxide layer having a first portion located over a top surface of the substrate and a second portion partially filling the trench; removing at least a part of the first portion of the first oxide layer from over the topsurface of the substrate, while leaving the second portion in the trench; forming a second oxide layer having a first portion located over a top surface of the substrate and a second portion located in a recess in the second portion of the first oxide layer in the trench; and planarizing the second oxide layer to remove the first portion of the second oxide layer from over the top surface of the substrate, while leaving the second portion of the second oxide layer in the trench.

12. The method of claim 11 , wherein the second portion of the second oxide layer in the trench has a planar top surface.

13. The method of claim 12, further comprising: forming a planarization stop layer over the top surface of the substrate prior to forming the first oxide layer; and forming the trench through the planarization stop layer.

14. The method of claim 13, wherein the planar top surface of the second portion of the second oxide layer is coplanar with a top surface of the planarization stop layer.

15. The method of claim 14, wherein the step of planarizing the second oxide layer comprises a chemical mechanical polishing step which stops on the planarization stop layer.

16. The method of claim 15, wherein the planarization stop layer comprises silicon nitride, the first oxide layer comprises silicon oxide, and the second oxide layer comprises silicon oxide.

17. The method of claim 15, wherein the step of removing at least a part of the first portion of the first oxide layer comprises another chemical mechanical polishing step.

18. The method of claim 15, wherein the step of removing at least a part of the first portion of the first oxide layer comprises: forming a patterned mask layer in the recess in the second portion of the first oxide layer in the trench while exposing the first portion of the first oxide layer; etching back the first portion of the first oxide layer exposed by the patterned masklayer; and removing the patterned mask layer.

19. The method of claim 18, wherein the step of forming the patterned mask layer comprises forming an optical planarization layer over the first oxide layer, and etching back the optical planarization layer to leave the patterned mask layer portion of the planarization layer in the recess in the second portion of the first oxide layer in the trench.

20. The method of claim 18, wherein the step of forming the patterned mask layer comprises forming a negative tone photoresist layer over the first oxide layer, and exposing and developing the negative tone photoresist layer to leave the patterned mask portion of the negative tone photoresist layer in the recess in the second portion of the first oxide layer in the trench.

21. The method of claim 12, further comprising: forming a lower cladding layer over the planar top surface; forming a silicon nitride waveguide core on the lower cladding layer; and forming an upper cladding layer on the lower cladding layer and contacting a top surface and sidewalls of the silicon nitride waveguide core.

22. A method, comprising: forming a plurality of trenches in a semiconductor substrate, wherein the plurality of trenches are laterally separated from each other by remaining semiconductor fin portions of the semiconductor substrate; and oxidizing the fin portions to convert the semiconductor fin portions to semiconductor oxide fin portions and to completely fill the plurality of trenches with the semiconductor oxide to form a continuous semiconductor oxide fill region in the semiconductor substrate.

23. The method of claim 22, wherein the semiconductor substrate comprises a silicon substrate, and the continuous semiconductor oxide fill region comprises a silicon oxide fill region.

24. The method of claim 23, wherein the semiconductor fins comprise silicon fins which extend along a <100> direction and have width of 1 micron or less.

25. The method of claim 24, wherein a depth of the plurality of the trenches is at least 10 microns, and a ratio of a width of the plurality of trenches to a width of the semiconductor fins is between 0.45 and 0.47.

26. The method of claim 23, further comprising: forming a lower silicon oxide cladding layer over the silicon oxide fill region, wherein the silicon oxide fill region has a refractive index that is lower than a refractive index of the lower silicon oxide cladding layer; forming a silicon nitride waveguide core on the lower silicon oxide cladding layer; and forming an upper silicon oxide cladding layer on the lower silicon oxide cladding layer and contacting a top surface and sidewalls of the silicon nitride waveguide core.

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