Solid state circuit breaker

Abstract

An automatic controlled circuit fault interruption system and method implements: a solid-state circuit breaker (SSCB) connecting a power source to a load. The SSCB includes two back-to-back switches in a common-source connected, bi-directional configuration and are configurable using connected gate drive circuitry in one of: a conducting (ON) state, non-conducting (OFF) state and an "intermediate" conducting state between on and off states. The gate drive circuitry operably connects to fault condition sensors including a current sensor for detecting an overcurrent condition, a voltage sensor for detecting an overvoltage condition and a direct current flow rate of change (di / dt) sensor such as a Rogowski coil configured in an instantaneous fault trip circuit. Based on signals from the current, voltage and di / dt sensors, the gate driver circuit provides an active impedance control of the switching transistors. The SSCB provides for a primary power path fault protection without electromechanical switch or fuse.

Description

(23-BAE-0488PCT) SOLID STATE CIRCUIT BREAKER CROSS REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims benefit of United States Provisional Application No. 63 / 662,662 filed on June 21, 2024, all of the contents and disclosure of which are incorporated herein by reference. BACKGROUND

[0002] This disclosure is directed to power control systems and devices generally, and more particularly to a bi-directional solid state circuit breaker device, system and method for controlling circuit breakers used to detect circuit faults and protect electronic circuits, devices and systems.

[0003] Design of high-voltage circuit interruption with electro-mechanical contactors is size, weight, performance and cost (i.e., SWAP-C) prohibitive. Further, the development and design of a multi-stage fault response circuit is SWAP-C prohibitive. SUMMARY

[0004] A high-voltage circuit fault interruption system implementing a solid state circuit breaker device and method for a vehicle such as an electrified aircraft or aerospace vehicle.

[0005] A solid-state circuit breaker (SSCB) device and system connected in circuits to protect those circuits from damage due to fault conditions with no electromechanical switches or fuses in series with the breaker device for fault protection.

[0006] In an embodiment, the SSCB is a solid state circuit breaker connected between a DC power source and a load device, the SSCB can be bidirectional consisting of: a series-connected pair of solid-state switches on both the positive rail and the negative rails, each switch having asource, gate and drain and a body-diode connected between the source and drain of each switch with diode cathode connected to the drain.

[0007] In an embodiment, the SSCB is a solid state circuit breaker connected between a DC power source and a load device, the SSCB can be unidirectional consisting of: a single solid-state switch on both the positive rail and the negative rails, the switch having a source, gate and drain and a body-diode connected between the source and drain of each switch with diode cathode connected to the drain.

[0008] A high-voltage circuit interruption system and method implements the SSCB, a controller, and a corresponding gate driver(s) responsive to sensors for providing automatic control for circuit interruption, and gate voltage drive control for switching the SSCB transistors into ON / OFF operating states.

[0009] A high-voltage circuit interruption system and method implements the SSCB, a controller, and a corresponding gate driver(s) responsive to sensors for providing automatic control for circuit interruption, and gate voltage drive control for providing active impedance control (i.e., linear-mode operation) in the ohmic-region / linear-mode of the SSCB transistors to provide an “intermediate” operating state for load connect, load disconnect, etc. operations.

[0010] A high-voltage circuit interruption system and method implements the SSCB integrated with a voltage sense function at load side of both switches.

[0011] A high-voltage circuit interruption system and method implements the SSCB integrated with a current sense function.

[0012] A high-voltage circuit interruption system and method implements the SSCB integrated with a direct di / dt (DC current rate of change or derivative current) sensing device, e.g., provided using a Rogowski coil, with analog / digital instantaneous fault trip circuitry.

[0013] According to an aspect, there is provided a solid state circuit breaker (SSCB) comprising: a first Field Effect Transistor (FET), the first FET including a gate terminal, a drain terminal and a source terminal and including a body diode in a first orientation, the drain terminal connecting to a terminal of a direct current (DC) power source configured to supply a direct current for powering a load device; a second FET connected in-series to the first FET, the second FET including a gate, a drain and a source terminal and including a body diode in a second orientation; a first circuit for detecting an instantaneous rate of change of current flow to the load device, the first circuit disposed in a non-contacting arrangement with a conductor connecting the drain terminal of the second FET to the load device; and a first gate driver circuit operatively connected to each the first FET and second FET for receiving signals from the first circuit, and responsively apply a gate voltage to the gate terminal of the first FET and the gate terminal of the second FET to provide active impedance control of the SSCB.

[0014] In this aspect, the active impedance control of the SSCB comprises one or more of: an ON-state of each the first FET and second FET to provide a low resistance, full current flow path through the SSCB; an OFF-state of each the first FET and second FET to prevent current flow through the SSCB; and a linear region of each the first FET and second FET to provide a high resistance path through the SSCB, the high resistance path being a current flow path having a resistance value between an ON-state FET resistance value and an OFF-state FET resistance value.

[0015] In a further embodiment, there is provided a solid state circuit breaker (SSCB). The SSCB comprises: a first Field Effect Transistor (FET), the first FET including a gate terminal, a drain terminal and a source terminal and including a body diode in a first orientation, the drain terminal connecting to a terminal of a direct current (DC) power source configured to supply a direct current for powering a load device; a circuit for detecting an instantaneous rate of change of current flow to the load device, the rate of change current detecting circuit disposed in a non- contacting arrangement with a conductor connecting the drain terminal of the first FET to the load device and providing a circuit output; and a gate driver circuit operatively connected to the first FET for receiving output signals from the circuit, and responsively apply a gate voltage to the gate terminal of the first FET to provide active impedance control of the SSCB.

[0016] Further to this aspect, the circuit output connects to a first terminal of the connected load device and the SSCB further comprises: a return path, the return path comprising: a second FET including a gate terminal, a drain terminal and a source terminal and including a body diode; a second circuit for detecting an instantaneous rate of change of current flow, the second circuit disposed in a non-contacting arrangement with a conductor connecting the drain terminal of the second FET to the second terminal of the connected load device and providing an output; and a second gate driver circuit operatively connected to the second FET for receiving signals output from the second circuit, and responsively apply a gate voltage to the gate terminal of the second FET to provide the active impedance control of the SSCB.

[0017] Further features as well as the structure and operation of various embodiments are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG.1A depicts a bi-directional solid state circuit breaker for providing high-voltage circuit protection for an electronics system in a vehicle according to an embodiment of the disclosure;

[0019] FIG.1B depicts a uni-directional solid state circuit breaker for providing high-voltage circuit protection for an electronics system in a vehicle according to an embodiment of the disclosure;

[0020] FIG.2 is a schematic block diagram depicting an alternate embodiment of the SSCB showing processing components driven by low-voltage signals in a low-voltage domain and processing components driven by higher-voltage signals in a high-voltage domain for driving the solid state circuit breaker switches;

[0021] FIG.3 is a detailed embodiment of a fast di / dt (current rate of change) sensor circuit operating as an analog circuit to engage instantaneous fault trip response to the gate driver for controlling the switches of the solid state circuit breaker;

[0022] FIG.4 is a detailed circuit diagram of the current sensor circuit operating to measure the current flowing in the SSCB circuit conductor in the system of FIG.1A according to an embodiment;

[0023] FIG.5 is a detailed circuit diagram of a single gate driver driving a single transistor switch and including associated switch fault management circuit operating to generate gate drive signals to render multi-stage operation in accordance with an embodiment of the invention; and

[0024] FIG.6 is a diagram conceptually depicting the tripping characteristics of a high-voltage circuit interruption device such as mechanical breaker, high-speed fuses as compared to the solid-state circuit breaker of FIG.1A for multiple rated currents. DETAILED DESCRIPTION

[0025] The present disclosure is directed to a solid-state circuit breaker (SSCB) for a high-voltage circuit protection system and method implementing a bidirectional solid state breaker circuit.

[0026] In a non-limiting, exemplary implementation, the solid-state circuit breaker is operable in conjunction with a Power Distribution Management System (PDMS) which can be a line replaceable unit for a sustainable vehicle engine architecture compliant with the Revolutionary Innovation for Sustainable Engines (RISE) platform.

[0027] FIG.1A depicts a bi-directional solid state circuit breaker 20 for providing high-voltage circuit protection for an electronics system 10 including a high-voltage direct current (DC) power source 30 providing DC power to a high-voltage DC circuit load or load device 75. As shown in FIG.1A, the bi-directional SSCB 20 includes a series-connected pair of solid-statefield-effect transistors (FET) switching devices (switches) on both the positive voltage rail and the negative voltage rails. One terminal of a first switch of the pair connects to a first terminal of the high-voltage direct current (DC) power source 30 via a current conductor 31 and a terminal of a second switch connects to a first terminal of the high-voltage circuit load 75 via a current conductor 74 to provide a high-voltage circuit protection along a first or positive DC rail circuit path 21 between the input source and load. A similarly configured bi-directional solid state circuit breaker 20' includes a series-connected pair of solid state FET switching devices with one terminal of a first switch of the pair connecting to a second terminal 76 of the high-voltage circuit load 75 via a current conductor 76 and one terminal of the second switch connecting to a second terminal of the high-voltage direct current (DC) power source 30 via a current conductor 29 to provide further high-voltage circuit protection for the electronics system 10 along a second or negative DC rail circuit path 22 between the load and source. Each switch device of a switch pair having a source, gate and drain and a body-diode connected between the source and drain of each switch with diode cathode connected to the drain.

[0028] As shown in FIG.1B, a uni-directional SSCB 80 including a single FET switch device is connected on one DC rail and a second FET switch device connected on the second DC rail can accomplish the same goal of high-voltage circuit protection.

[0029] In a non-limiting embodiment depicted in FIG.1A, the high-voltage power source 30 is an energy storage system (ESS) such as a DC power generator or one or more battery banks, battery packs or individual batteries such as Li-ion, lead-acid, or other battery types. In alternative embodiments, the one or more batteries may be combined with any other suitable energy storage devices, such as capacitors, ultracapacitors, supercapacitors, and the like. The circuit load can be any circuit or device requiring a high-voltage DC input. For non-limiting purposes of discussion, “high-voltage” can refer to a direct current (DC) voltage of greater than 50 VDC, but could be 120 VDC, 200 VDC, 400 V DC, 800 V DC or greater. In an exemplary, non-limiting embodiment, electronic system 10 can be any high-voltage DC aircraft system and the circuit load 75 can be a bus bar or distribution bus, propulsion motors, electrified vehicles, maritime vehicles, turbines, avionic, equipment or any other high-voltage electrical system.

[0030] As shown in FIG.1A, the bi-directional SSCB 20 includes: a pair of solid-state switches 15A, 15B in a common-source connected configuration in which each solid state switch 15A, 15B consists of a metal oxide semiconductor field effect transistor (MOSFET) switching device including a source (S), gate (G) and drain (D) terminals. As shown, in a non-limiting embodiment, the source terminal (S) of each solid state switch 15A, 15B of the pair are connected to provide a common source connection 25, however, a common-drain configuration can be implemented. In the embodiment depicted, the SSCB 20 switching transistors are connected in reverse configuration (Drain-Source) and (Source-Drain) rendering their operation bi-directional. As shown in FIG.1A, each MOSFET 15A, 15B includes a body diode 28 which is the parasitic device intrinsic to the MOSFET device’s structure and is connected in reverse configuration between the source terminal (S) and drain terminal (D) of each switch 15A, 15B with the diode cathode connected to the drain terminal (D) in each. It is understood that the SSCB 20 switching transistor is a MOSFET, however, can be a JFET or other FET-type device, and in other embodiments, can be a bipolar junction transistor (BJTs, IGBTs) or like semiconductor switching device.

[0031] Further, as shown in FIG.1A, connected to each respective gate terminal (G) of the common-source connected pair of solid-state MOSFET switches 15A, 15B is a respective gate driver circuit 60A, 60B. Gate driver circuit 60A is connected to and receives signals from the drain and / or source terminals of MOSFET 15A and provides an output conductor connected to the gate terminal of solid-state switch device 15A for outputting a control signal 61A used for adaptively controlling an impedance state of MOSFET 15A. Similarly, gate driver circuit 60B is connected to and receives signals from the drain and / or source terminals of MOSFET 15B and provides an output conductor connected to the gate terminal of solid-state switch device 15B for outputting a control signal 61B used for adaptively controlling an impedance state of MOSFET 15B. It is understood that an impedance state is alternately referred to as a resistance state that additionally takes into account any capacitance and inductance in the circuits, devices, and load. Thus, for each MOSFET switch 15A, 15B, based in part on voltages obtained at their respective gate, drain and source terminals, each of the gate driver circuit 60A, 60B is configured to apply a respective bias voltage VGS(control signals 61A, 61B, respectively) that is used to control the amount of current flow through a respective switch 15A, 15B, i.e., provide for active impedancecontrol of the SSCB where the switching MOSFETs can operate in an ON (conducting) state, an OFF (non-conducting) state or an INTERMEDIATE (linear mode) state, i.e., operable in an ohmic-region of operation.

[0032] In an embodiment, active impedance control is achieved by operating switches in linear mode and is advantageous for load connect, load pre-charging and load disconnect operations. More particularly, an applied VGS bias voltage 61A, 61B to a SSCB switch 15A, 15B can render the respective switches in a sequence of states, e.g., a completely open or non-conductive state, an “intermediate” or linearly resistive state that can limit current flow through the SSCB 20 and a completely closed, conductive state. For example, upon disconnecting a source or a load device (which command can originate by the PDMS), the SSCB can utilize a two-level turn off to minimize overshoot of any residual current. In an embodiment, a solid-state switching transistor can be an NPN-type semiconductor structure, where the voltage between the gate and source, i.e., VGS is equal to zero (i.e., VGS = 0), the voltage between the drain and source (VDS) is greater than the device’s pinch-off voltage !", i.e., VDS > !"; and where the current drawn at the drain terminal ID = IDSS (current, drain-to-source, saturated) is the current through the device when VGS = 0. In an embodiment, the NPN-type semiconductor structure results in zero current flow (ID = 0 amps) through the device when the device is at pinch-off, i.e., where VGS << !", where VDS < VBD where VBD is the body diode voltage drop.

[0033] As known, the size of the switching device determines the range of current and assumes a depletion-mode FET device that conducts until a negative voltage is applied to the gate relative to the source. In a transistor mode of operation based on transistor parameter characteristics where the VGS << V#there results a channel pinch-off (e.g., channel off or cutoff) where the device is characterized by a high impedance (e.g., > 10 kOhm) and where no IDS current flows. In an INTERMEDIATE mode of operation, the transistors are controlled to operate in a current limiting (linear) or ohmic region governed by the relation VDS sat = VGS – VP with different current vs. voltage curves based on a value of VGS. In this INTERMEDIATE mode, impedance values can range from between 100 Ohms – 1kOhms. Additionally, in the saturation region of operation where the device is characterized by a low impedance (e.g., < 1 Ohm) there results inenabling a constant full current flow until a breakdown region is reached when VDS exceeds a certain threshold.

[0034] Respective gate driver circuits 60A, 60B are further operably connected to fault detection circuitry that operate to detect faulty operating conditions that can trigger SSCB operation. For example, gate driver circuit 60A receives an input control signal 62 for further controlling the gate driver output control signal 61A based on control signals received from one or more fault detection and logic circuits; and similarly, gate driver circuit 60B further receives the input control signal 62 for further controlling the gate driver output control signal 61B based on control signals received from one or more fault detection and logic circuits. In an embodiment, control signal 62 can control the respective gate driver 60A, 60B to output the respective control signal 61A, 61B to render MOSFET switch 15A in either a completely “ON” or low-impedance full current conducting (i.e., closed) state, or in an “OFF” or high-impedance, non-current conducting (i.e., open circuit) state, or in the linear-mode (ohmic region) “INTERMEDIATE” state (an ON state) however with higher impedance characteristics in the current flow path through the SSCB device. Utilizing the linear mode of the bidirectional switches in the SSCB, the higher resistance through the device acts as a snubber to suppress voltage transients.

[0035] In the MOSFET switching device configuration shown in FIG.1A, the circuit protection for the electronics system 10 facilitates energy flow that is bi-directional, i.e., the power source 30, in conjunction with the circuit load 75, operates in both charging and discharging scenarios along a corresponding circuit path 21, 22. Therefore, the system and method of circuit protection for electronics system 10 described herein may operate to improve balance for charging and discharging current from the battery / battery pack(s), e.g., in response to unbalance current or thermal conditions. In the bi-directional embodiment, rather than a respective gate driver 60A, 60B assigned to each respective MOSFET switch 15A, 15B, there may be a single gate driver controlling both MOSFET switches of the pair.

[0036] With more particularity, as shown in FIG.1A, connecting the “load”-side in series with the drain terminal D of switch 15B of the SSCB is a direct di / dt (DC current rate of change) sensing device 50 and connected in series with the di / dt sensing device 50 is a current sensecircuit device 35 for sensing the amount of current flow through the switches 15A, 15B and through positive rail circuit path 21 that is to be consumed by the load circuit 75. The sensed current flow value at current sense circuit device 35 is further output as sensed current signal 39 to an overcurrent (OC) fault detection circuit 36 which implements logic for detecting an over- current fault condition and asserting a corresponding OC fault condition signal 37 when a fault is detected. The current sense circuit device 35 provides a further current sense measurement signal 38 for receipt as an input to a local controller or processor circuit 100 for further processing where the controller 100 is a microprocessor with built-in logic that is local to the SSCBs 20, 20' and is shown linked via bus lines 120 to an external system controller (not shown) via a communications interface 110. Processor 100 can include a digital to analog converter (DAC) in order to provide a gate driver signal suitable for adaptive impedance control rendering the SSCB switches in a particular state or configuration. In an embodiment, the SSCB circuit 20 includes a positive conductor line 71 that connects the load-side current sense circuit 35 to a first terminal 74 of the output high-voltage circuit load 75 at circuit path 21. Similarly, the bi-directional SSCB circuit 20' includes a similar negative conductor line 72 connecting an output of a further current sense circuit 35' at the output of the series-connected pair of solid state FET switching devices 15A' and 15B' along a return circuit path 22 to a second terminal 76 of the output high-voltage circuit load 75 at return circuit path 22. In an optional embodiment, an optional common mode current sense circuit 80 is provided that is situated around the conductors and PCB wire traces and not in line with the conductors. The common mode current sense circuit 80 detects signals that are common to both lines (in the same direction) to both circuit paths 21, 22 and minimizes the signals that are different. For example, if 10 amperes are present on conductor line 71 and the same 10 amperes returned on conductor line 72 those signals could cancel inside common mode current sense circuit 80. On the other hand, if 10 amperes was present on 71 and then due to a fault in the system those amperes returned via some other path to the source, the common mode current sense measures 10 amperes and inform the local control processor 100 via output line 82.

[0037] Further as shown in FIG.1A, disposed in parallel with the input power supply source 30 and connected at one end to the positive DC high-voltage rail terminal 31 and at a second end to a negative high-voltage rail terminal 29 is an input voltage sense circuit 40A for sensing a drain voltage “VD1” at the drain of the first MOSFET switch 15A; and similarly, disposed in parallelwith both the optional common mode current sense circuit 80 and output high-voltage circuit load 75 and connected in between positive conductor line 71 and negative conductor line 72 is a load voltage sense circuit 40B for sensing a drain voltage “VD2” at the output of current sense circuit 35 connected in the series with the di / dt current rate of change sensing circuit 50 and drain of the second MOSFET switch 15B. The input voltage sense circuit device 40A is configured for sensing the voltage VD1 across the power source at the input to the SSCB MOSFET switch 15A and the load voltage sense circuit device 40B is configured for sensing the voltage VD2 driving the load 75 at the output of the SSCB MOSFET switch 15B. Based on these sensed voltage values at circuit locations VD1 and VD2 of FIG.1A from respective voltage sensing circuit devices 40A, 40B, the voltage across both SSCB MOSFET switches is easily obtained. These voltages are monitored to compute the differential voltage VDIFF which can be used for fast fault detecting purposes where VDIFF= |VD1 - VD2|. In an embodiment, as shown in FIG.1A, the respective sensed voltage values VD1, VD2 from respective voltage sensing circuit devices 40A, 40B are output as respective sensed voltage signals 43A, 43B for receipt at the local controller or processor 100 for computing the differential voltage VDIFF for various operations. The sensed voltage value from voltage sense circuit device 40A is also output as a sensed voltage signal 41A for receipt at an associated overvoltage (OV) fault detection circuit 42A, and similarly the sensed voltage value from load voltage sense circuit device 40B is also output as a sensed voltage signal 41B for receipt at an overvoltage (OV) fault detection circuit 42B. Both (OV) fault detection circuits 42A, 42B implement logic for detecting an over-voltage fault condition and responsively assert a respective corresponding over-voltage fault condition signal 44A, 44B used for input to the local controller or processor 100. These signal 44A, 44B can be further processed by controller circuit 100 for comparison and as a potential result to responsively generate fault condition signal 47 for controlling both SSCB 20 and / or SSCB 20'. In an embodiment, OV fault detection circuit 42A compares the sensed rail voltages (i.e., voltage across the terminals of input power source 30) and OV fault detection circuit 42B compares the sensed voltage across the terminals of load circuit or device 75 against a respective, programmable voltage threshold (e.g., different voltage thresholds for on-state and off-state) over which is indicative of an overvoltage fault condition. The corresponding asserted over-voltage (OV) fault condition signals 44A, 44B are input to the controller circuit 100, e.g., in order to adaptively control SSCB operation. As further shown in FIG.1A, in an embodiment, furthersensed voltage values 43A, 43B from respective voltage sensing circuit devices 40A, 40B are input to the local controller or processor 100 for further processing, and output over voltage fault condition signals 44A, 44B are input to the local controller or processor 100 for further processing. As an example, the local controller 100 processes these over voltage fault condition signals and can adjust the sources of the system to re-establish bus regulation at an appropriate voltage. If that doesn’t work, the fault condition can drive the controller to open SSBs to prevent cascading damage, e.g., contain the overvoltage to a certain node.

[0038] Further, as shown in FIG.1A, connecting the drain terminal (D) of MOSFET switch 15B of the SSCB 20 to an input terminal of the current sense circuit 35 at first circuit path 21 is a DC $% current flow rate of change detector, i.e., $& current rate of change sensing circuit 50. The DC $% $% current flow rate of change sensed at $& current rate of change sensing circuit 50 is output as a $& $% current rate of change sense signalfor receipt at an over- $& fault detection circuit 52$% implementing logic for detecting an excessive $& fault condition and asserting a respective $% $% corresponding over- $& fault condition signal 57 when an excessive $& current rate of change fault $% condition is detected for input to a logic circuit 65. The over- $& fault detection circuit 52 can $% further output a corresponding over- $& fault condition signal 53 for receipt and further processing by the local controller or processor circuit 100. For example, local controller or microprocessor 100 can receive signal 53 to perform additional calculations, e.g. redundant fault detection, use the di / dt measurement and integrate it to obtain an alternate measurement, etc. $%

[0039] In an embodiment, the $& current rate of change sensing circuit 50 includes a Rogowski coil that is operable for direct contactless current measuring at the drain terminal output of $% switch 15B of the SSCB 20. It is understood that the circuit location of the $& current rate of change sensing circuit 50 and current sensing circuit 35 and corresponding connected fault detection circuits can be interchanged while maintaining functionality as described. Further, it should be understood that the configuration of SSCB 20 may be modified to include one or both$% the current sensing and $& current rate of change sensing devices on the source side of the system 10 (i.e., connecting the first MOSFET 15A).

[0040] As shown in the embodiment of FIG.1A, the further logic circuit 65 consists of an OR gate (or similar logic device) and receives asserted OC (over-current) fault condition signal 37 $% $% from OC fault circuit 36, receives the asserted over- $& fault condition signal 57 from over- $& fault detection circuit 52 and further receives a fault Open / Close control command (CMD) signal 47 that may be generated by the microprocessor 100. A further signal 46 is an analog cross- breaker signal linkage that allows the analog logic to check itself, e.g., check whether both sides have an overcurrent fault, i.e., check if one fault on the positive rail can be checked against a fault on the negative rail. Based on one or more asserted signals 37, 46, 47, 57, logic circuit 65 will responsively generate the gate driver control signal 62 for input to the respective gate drivers 60A, 60B used to control the OFF (open switch), the linearly resistive INTERMEDIATE state, or the ON (closed switch) state of respective MOSFET switches 15A, 15B of SSCB 20.

[0041] In the high-voltage circuit protection for the electronics system 10 as shown in FIG.1A, the local controller or processor 100 receives and processes signals for generating the further control signal 46 that is also input to the logic circuit 65 and logic circuit 65' for controlling the SSCB state(s). Further, controller or processor device 100 receives: the respective voltage sense signals 43A, 43B from respective voltage sensing circuit devices 40A, 40B, any OV (over- voltage) fault detection signal 44A, 44B from OV fault detection circuits 42A, 42B respectively, the measured current output signal 38 from current sense circuit 35, any asserted OC (over- $% current) fault detection signal 33 from OC fault detection circuit 36, and any asserted over- $& $% fault condition signal 53 from the over- $& fault detection circuit 52 and, in response, based on these received signals, implements logic for asserting the control signal 47 which is a command adapted to either open or close both MOSFET switches of SSCB 20 or render them in a linear- resistive state.

[0042] As further shown in FIG.1A, communications interface 110 provides communications to / from an interface to another circuit or system that can issue a command to control operation ofthe SSCB 20. The electronics system 10 can include a data / address bus 120 in physical communication with the local controller or processor 100 to relay one or more external- generated command or control signals for receipt at the local controller 100. These externally- generated commands can be from an aircraft / aerospace vehicle subsystem(s) which can be processed by the logic invoked at the controller for further generating further output control signal 47 used to adaptively control the opening (OFF) or closing (ON) of the MOSFET switches or render the switches in the INTERMEDIATE (i.e., linear resistive) operating mode.

[0043] As further shown in FIG.1A, connecting across the terminals of the power supply source device 30 is a transient voltage suppressor (TVS) device, e.g., which can include a varactor or like transient voltage suppression device, circuit or system 73A and include additional connected TVS devices 73B, 73C each configured to connect a respective terminal of TVS device 73A to ground to further suppress transient spikes in the power electronics circuits, i.e., suppress any transient spikes of voltage or current of short duration (e.g., nanoseconds to milliseconds) which can be introduced into the system 10 such as by inductive load switching or faulty contacts in switches and connectors. Similarly, connecting across the terminals of the load circuit 75 is a further transient voltage suppressor device 73E and can include additional connected TVS devices 73F, 73G each configured to connect a respective terminal of TVS device 73E to ground to further suppress transient spikes in the power electronics circuits, i.e., suppress any further transient spikes of voltage or current of short duration which can be introduced into the system 10 such as by inductive load switching or faulty contacts in switches and connectors at the load. These TVS devices provide an over-voltage protection by clamping the voltage at a fixed voltage, e.g., while the over-voltage fault commands the gate driver to OPEN a switch.

[0044] As further shown in FIG.1A, in the embodiment of a bi-directional SSCB for electronics system 10, there is further configured a second SSCB 20' connected along the second negative- rail circuit path 22 of the electronics system 10. As shown in FIG.1A, the SSCB 20' connected to the opposing terminal 29 of the high-voltage DC source input 30 and terminal 76 of DC load circuit 75 along second path 22 includes identical elements that are configured identically as the SCCB 20 connected along first positive-rail circuit path 21 for providing similar bi-directional high-voltage DC circuit fault protection. For example, the SSCB circuit 20' includes seriesconnected pair of MOSFET switches 15A', 15B' which, in a non-limiting embodiment, can be connected in a common-source configuration as shown, and includes similar associated sensing circuitry to control respective gate drivers 60A', 60B' used to control the pair of MOSFET switches 15A', 15B' to render them in an open (OFF), closed (ON) or a third impedance (INTERMEDIATE) state. As shown in FIG.1A, SSCB circuit 20' employs the input and load voltage sensing circuits 40A, 40B respectively, and corresponding connected OV fault detection circuits 42A, 42B which generate the respective OV fault condition signal 44A, 44B for receipt and processing at local controller or microprocessor 100. Additionally connected to the load-side in series with the drain terminal D of switch 15B' of the SSCB is a direct di / dt (DC current rate of change) sensing device 50' and connected in series with the di / dt sensing device 50' is a further current sense circuit device 35' for sensing the amount of current flow through the switches 15A', 15B' and through negative rail circuit path 22 that is connected to the load circuit 75 through common mode current sense circuit 80. Current sensing device 35' for sensing current input to the SSCB switches along the negative return path 22 generates a corresponding current measurement signal 38' for receipt and processing at the local controller 100 and further generates a corresponding current measurement signal 39' for receipt by a corresponding overcurrent fault circuit 36' that implements logic to detect an OC (overcurrent) fault and assert $% OC fault detection signals 33' and 37'. Similarly, the direct $& rate of change current sensing $% circuit 50' detects an instantaneous rate of change of current flow and outputs this value as $&$% current rate of change signal 51'. Sensed $& current rate of change signal 51' is received at a$% further over- $& current rate of change fault detection device 52' which generates corresponding $% over- $& current rate of change fault detection signals 53' and 57'. In an embodiment, a corresponding logic circuit 65' which can be an OR gate (or similar logic gate(s)) receives the asserted signals 37', 46, 47, 57' and logic circuit 65' processes these received signals and responsively generate the respective gate driver control signal 62' for input to the gate drivers 60A', 60B' used to control the OFF (open switch), linearly resistive INTERMEDIATE state, or the ON (closed switch) state of respective MOSFET switches 15A', 15B' of SSCB 20'. It should be understood that the configuration of SSCB 20' may be modified to include one or both the$% current sensing and $& current rate of change sensing devices on the source side of the system 10 (i.e., connecting the first MOSFET 15A').

[0045] As further shown in FIG.1A, the local controller or processor device 100 is configured to further receive: respective voltage sense signals 43A', 43B' from the respective voltage sense circuits of SSCB 20, a measured current output signal 38' from the identical current sense circuit 35' of SSCB 20', an asserted OC (overcurrent) fault detection signal 33' from the identical OC $% fault detection circuit 36', an asserted $& current rate of change sense signal output 53' from the $% identical $& fault detection circuita common mode current sense circuit output 82 and, in response, based on these received signals, implements logic for asserting the signals through communications interface 110. In an embodiment, the local controller 100 can send information to the comm interface via a signal path 120. The comm interface leads to the system controller, and the information contained in 120 can be voltage, current, fault status, and / or operational status (open / closed). The system controller on the other side of the comm interface may have its own reasoning for asserting a change of breaker state.

[0046] As before, the communications data / address bus 120 in physical communication with the local controller or processor 100 can further relay one or more external-generated command or control signals for receipt at the local controller 100. These external-generated command signals can be from an aircraft / aerospace vehicle subsystem(s) which can be processed by the logic invoked at the controller.

[0047] FIG.1B depicts a SSCB circuit diagram 10' of an alternate embodiment which is identical to the SSCB circuit diagram embodiment 10 of FIG.1A, however instead of a series connected pair of SSCB MOSFET switching devices, there is only provided a single switch, e.g., MOSFET switch 15B in the first or positive voltage rail path 21 and only a single switch, e.g., MOSFET switch 15B' in the second or negative voltage rail path 22. Operation of the current sensing $% circuit, input voltage and load voltage sensing circuits, $& current rate of change sensing circuit,$% and respective over-voltage, over-current fault and over- $& fault condition sensing are identical in the alternate SSCB circuit 10' shown in FIG.1B.

[0048] As mentioned, each SSCB 20 / 20' is integrated into an electronic system of an aircraft / aerospace vehicle to provide overcurrent protection such as circuit interrupts when faults (e.g., short circuits, thermal overload, etc.) are present in the system 10 such as a system in the Revolutionary Innovation for Sustainable Engines (RISE) engine platform, e.g., for mobile or automotive, maritime vehicles, aircraft, aerospace vehicles, or for use in any high-voltage, high- current electronic system. Exemplary faults to be protected against include but are not limited to: an excessive di / dt, I2t fault, a line to line over current (e.g., positive rail to negative rail short), a line to ground over current (e.g., breakdown of insulation), an over temperature fault (e.g., at the power modules) or an over voltage fault. For example, if a short-circuit fault occurs at a connection to the power source battery / battery bank(s) 30, the SSCB(s) 20 / 20' may sense a current (such as by the current sensing circuit 35) that indicates a fault, and the corresponding OC fault detection circuit 36 identifies the current as a short-circuit fault. For example, in response to fault detection, the SSCB(s) 20 / 20' can turn off the solid state switches 15A, 15B / 15A', 15B' via the respective gate driver circuits 60A, 60B / 60A', 60B' associated therewith. In one embodiment, if a short-circuit fault occurs at the high-voltage DC load circuit 75, e.g., a high power short to a ground or to chassis or similar type short, the SSCB(s) 20 / 20' may sense an $% abnormal change in current flow, e.g., such as by the $& current rate of change sensing circuit, $% and the corresponding$& current rate of change circuit can identify the change in $% current as a short-circuit fault and in response, assert the $& fault condition signal 57 which can be used as a command to either open or close both MOSFET switches 15A, 15B via the respective corresponding gate driver circuits 60A, 60B of SSCB 20 or first render the switches 15A, 15B in a resistive state prior to turning them off (OPEN). In an embodiment, the SSCB devices 20 / 20' transition from an ON state to a linear (resistive) state to the OFF state with the linear state being of a short duration en-route to the OFF state, e.g., when clearing a fault. That is, in an embodiment, the gate driver circuits of the SSCB devices 20 / 20' are programmed to provide a multi-stage operation wherein from a closed conducting state, upon detecting an over-$% voltage, over-current or over- $& current rate of change fault, the gate drivers are configured to transit the SSCB MOSFET switches from the closed (conducting) state to a resistive state and then finally to an open (non-conducting) state.

[0049] More particularly, in an embodiment, the fault interruption process using the direct $% sensing of $& current rate of change sensing circuit 50 / 50' integrated within the SSCB 20 / 20' in the system 10 is fast, i.e., providing automatic circuit interruption by gate voltage control on the order of 50 ns - 1 micro-second (µs), thereby providing for instantaneous fault trip circuit protection. Further, the SSCB implementations according to embodiments herein do not require use of any conventional electro-mechanical switching, nor mechanical circuit breakers or contactors, nor conventional fuses. Further, no voltage clamping or snubber circuit device is series with the load circuit is required for fault protection; only aa parallel-connected TVS is provided for over-voltage protection.

[0050] FIG.2 is a schematic block diagram depicting an alternate embodiment of the bi- directional configured SSCB 200 showing processing components driven by low-voltage signals in a low-voltage (i.e., digital) domain 201 and processing components driven by higher-voltage signals in a high-voltage (i.e., analog) domain 202 for driving the solid state circuit breaker switches, e.g., a MOSFETs 15A, 15B (or like JFET solid state switching devices). As shown, a first circuit configuration 200A of low-domain and high domain signal processing operates first SSCB switching MOSFET 15A, while a similarly configured second circuit 200B of low-domain and high domain signal processing operates the second SSCB switching MOSFET 15B. As shown in FIG.2, the low-voltage input signals include the sensed current measurement obtained by a current sensor 235, which in one embodiment is a contactless current sensing device such as a CT452 (Allegro Microsystems, Inc.) which senses current flow at the input conductor to the SSCB and translates the sensed magnetic field into a linear analog output voltage which is a measurement of the drain-source current IDS through the respective MOSFET. The measured current signal is input to an amplification and OC fault detection device 236 that generates an IDS over (OC) fault signal 37 indicating detection or not of an overcurrent fault condition where too much current is being drawn through the SSCB, or a no fault (under-current) condition. Thissignal is input to a logic gate such as an OR gate 245. Likewise, the low-voltage input signals $% include the sensed current rate of change $& measurement obtained by the current rate of change $% $& sensor 250, which in onea contactless current sensing device such as a$% Rogowski coil configured to sense a rate change in current flow with respect to time ( $&) at the output conductor of the SSCB and which correlates sensed current to a flow rate of change and is output as a linear output voltage measurement of the rate of change of the drain-source current $% IDS through the respective MOSFET. The measured $& current rate of change signal is input to an $% amplification and $& fault detection device 252 that generates an over-di / dt fault signal 257 $% indicating detection or not of a $& rate of change current fault condition where too much current$% per unit time is being drawnthe SSCB, or a no $& current fault condition. This over-di / dt signal 257 is input to the logic OR gate 245.the low-voltage input signals include the OV fault condition signal (OV trip) 241 indicating that the differential voltage across the HVDC positive-rail circuit path and HVDC negative-rail circuit path exceeds a pre-set threshold. This OV trip signal 241 is output from signal isolation circuit 220 in response to detecting the differential voltage across the high-voltage DC positive-rail circuit path and HVDC negative-rail circuit path exceeds a set threshold at VDIFF OV (over-voltage) fault detection latch w / Reset circuit block 270 processing signals in the high-voltage domain 202 in which case a high-voltage domain OV fault trip signal 240 is generated. The high-voltage domain OV fault trip signal 240 is input to the signal isolation block 220 to responsively convert it into a low-voltage domain level OV trip signal 241 input to logic OR gate 245. With respect to the signal isolation circuit block 220, this block can further receive a MOS fault reset signal 271 which will cause generation of a reset signal 274 in the high-voltage domain and reset the latch at the VDIFF OV (over-voltage) fault detection latch circuit block 270. The fault reset signal 271 can additionally be asserted for input to each fault detection amplification block 236 and 252 to latch these fault detect devices.

[0051] In low-voltage domain processing 201, at first circuit configuration 200A, the respective asserted fault signals 37, 241 and 257 are processed by a logic gate, e.g., OR gate 245, to assert a MOSFET fault detect signal 261 used by the gate driver 260 to initiate a turning off of thecorresponding MOSFET switch 15A due to a presence of any of the detected faults. Alternatively, or in addition, MOSFET fault detect signal 261 can be asserted and input to the local controller or processor (not shown) for further processing. Further, in response to receipt of respective asserted fault signals 37, 241 and 257, the OR gate 245 further generates a signal(s) input to a processing block 264 to provide either a signal 267 which can include either a differential signal including MOS GD IN-_277 and MOS GD IN+ 278 signals or a single-ended input (not shown) that function as a gate driver input signal for controlling gate driver operations, e.g., for rendering the SSCB 20 in a corresponding ON / INTERMEDIATE / OFF state. Gate driver circuit 260 can further generate MOS gate driver indicator signals (not shown) to indicate the gate driver is operation ready or indicate a gate driver fault condition.

[0052] As shown in FIG.2, the gate driver 260 generates MOS GD OUT+ signal 286 which is a gate drive input power signal processed to generate a higher voltage drive output power signal. This drive output power signal 286 can be boosted by an optional booster circuit 289 that output gate drive signal 291A that operates (OPEN / CLOSES) the switch 15A. Similar processes at second circuit configuration 200B generates a boosted output gate drive signal 291B that operates (OPEN / CLOSES) the switch 15B. That is, these output drive signals 291A, 291B are output as respective gate-source signals to control the gate-source voltage of each respective SSCB MOSFET switch 15A, 15B into one of: the closed (ON) or fully conducting state to provide a full current conducting path through the common-source connected path 225 of the SSCB, or open (OFF) to prevent current conducting through the common-source connected path 225 of the SSCB. $%

[0053] In an embodiment, in view of FIG.3, a fast $& (current rate of change) sensing circuit 50 consisting of a Rogowski coil 113 is implemented at a conductor 77 of circuit path 21 connecting the SSCB MOSFET switch 15B drain terminal (D) output to the load device 75 of FIG.1A. In $% the embodiment depicted, the Rogowski coil provides a non-contacting direct $& DC current rate of change sensing measurement at the drain current output conductor 77 of the second MOSFET switch 15B of the SSCB 20 of FIG.1A.

[0054] In an embodiment, the Rogowski coil 113 is a coreless helical coil or toroid of wire around but not contacting the conductor 77 being measured. In the embodiment shown, the circuit conductor 77 can be a connection to a terminal of a DC bus bar through which current from the source flows through SSCB 20 as current ID. The Rogowski coil 113 is a closed circuit outputting an EMF voltage between two terminals 152 where the EMF voltage (e.g., V_coil) is proportional to the rate of change of the magnetic flux, i.e., rate of change of current, running $% through the encircled conductor and provides a highly linear relationship between V_coil and $&. While the system response time speed is limited by the speed of the analog circuitry(amplification and comparators), however the response time of the Rogowski coil is of light rendering system detection speeds being fast (on the order of 106(MHz) or 10-9(ns)) to detect current minute changes (e.g., microamperes / sec).

[0055] In an embodiment, the Rogowski coil sensing circuit is modeled as a transformer with mutual inductance that responds to rates of change of the received MOSFET switch drain current ID. The coil is further modeled as including a series inductor LS and resistor RS and provides an output voltage VRO corresponding to charge stored at a connected capacitor CS at the output of the coil. The Rogowski coil conductor geometry results in an induced voltage proportional to the rate of change of current (i.e. di / dt). This output voltage can be a differential signal fed directly as input to analog instrumentation having one or more components to as filtering, $% amplification, and a fast $& current rate of change fault detection circuit including a comparator circuit for comparing an output voltage signal against a threshold to detect an over-di / dt fault. When the coil output voltage signal exceeds a voltage threshold value Vth, a comparator will trip $% and assert a fault signal 57 which is input to logic circuitry used to control the gate driver used to turn OFF the MOSFET switch(es) of SSCB 20.

[0056] FIG.3 is a detailed embodiment of a fast di / dt sensor circuit 50 operating as an analog circuit to engage instantaneous fault trip response to the gate driver for controlling the switches $% of solid state circuit breaker 20. As shown in FIG.3, the $& current rate of change sensing circuit Rogowski coil sensor 113 is used in a configuration to measure a high rate of change of currenton the order of MegaAmps / sec to detect abnormal rise in DC current at the output conductor of the SSCB 20 that feeds load circuit 75.

[0057] More particularly, the Rogowski coil 113 is used in the high-current DC electronics system 10 and can be placed to encircle the DC current-carrying circuit conductor 77 that is the $% SSCB output current path feeding the load for direct $& fault detection. The coil 113 measures a differential voltage proportional to a rate of change of drain terminal current at MOSFET 15B and the voltage output of the coil terminals 152 is a low-level output signal that is input to a differential signal conditioning circuit 155 including balancing capacitors and operational amplifier stages. As shown in FIG.3, differential signal conditioning balancing circuit 155 $% includes charging capacitors providing a sensed low-level positive going $& signal V+ 161 and a $% sensed low-level negative going $& signal V- 162 which can be input to the controller or processor 100 for further recording or for further computing or processing. The low-level $% positive going $& signal V+ 161 output of the Rogowski coil 113 charges a first capacitor 158 and is further received as an input voltage to an instrumentation amplifier 160 while the low-level $% negative going $& signal V- 162 output of the Rogowski coil 113 charges a second capacitor 159 and is further received as a second input voltage to the instrumentation amplifier 160. In an embodiment, instrumentation amplifier 160 includes a configuration of operational amplifiers and resistors forming a buffered differential amplifier of high CMMR and a high input impedance. This circuit amplifier 160 configuration is able to obtain to amplify the low-level $% signals to provide a single output signal 154 that is a measure of and is proportional to the $& rateof change of the current sensed by the Rogowski coil 113. This output signal 154 is to a $% connected fault detection stage 190 including the $& current rate of change fault detection circuit for positive and / or negative slope detection. $%

[0058] As shown in FIG.3, the $& (current rate of change) fault detection stage 190 for detecting a fault condition at the SSCB output includes further analog signal conditioning circuitry including a pair of comparator circuits each respective circuit consisting of an operationalamplifier 172, 174 configured as a comparator. In an embodiment, the analog circuitry of FIG.3 is configured to have a very small built-in processing delay (e.g., determined based on natural response times of gain op-amps, comparators, etc.) that provide a virtually instantaneous fault response time (such as 200 ns or 1 µs). Analog condition circuitry of fault detection stage 190 with the comparator 172 having a first negative terminal input receiving the single output signal 154 and the comparator 174 having a first positive terminal input receiving the single output signal 154. Each respective comparator 172, 174 is configured to receive a further different set threshold value at a second input thereof. When comparator circuit 172 is tripped, the output signal is a negative sloped output signal 181 and when comparator circuit 174 is tripped, the output signal is a positive sloped output signal 183. Depending on which comparator trips, either output signal 181, 183 is input to a fault detection comparator 192 which compares the output signal 181, 183 against a fault voltage reference signal level 194 set to indicate the presence of a $% $% $& current fault. The comparator 192 will assert and latch a $& current fault detection signal 157 when either the positive going or negative going output signal 181, 183 exceeds the fault voltage $% reference signal level 192. This $& current fault detection signal 157 corresponds to signal 57 used control the gate driver circuits, e.g., to render the paired MOSFETs of SSCB in an OFF state.

[0059] As further shown in FIG.3, in an optional embodiment, the electronics system 10 is able $% to reset the $& current rate of change fault detection circuit 152 by receiving a fault reset command signal 185, such as may be generated by the controller or processor and received at a latched fault signal resent transistor 187. In an embodiment, to reset the fault after gate-driver reset or switch state change, the system asserts a fault reset command signal 185 that turns on transistor 187 to pull the comparator voltage down to reset the fault detect comparator 192 and reset fault detect signal 157.

[0060] FIG.4 is a detailed circuit diagram of the current sensor circuit 35 operating to measure the current flowing in the SSCB circuit conductor 71 in the electronics system 10 of FIG.1A. In a non-limiting embodiment, the current sensor 35 is a contactless current measurement device such as a coreless current sensor that does not impede the current path, however it can be a shunt device or a transformer for sensing current. The current sensor 35 and associated signalconditioning circuitry 233 measures the magnetic field at the conductor and correlates the magnetic field strength to a voltage in a linear output. In an embodiment, a contactless current measurement device situated at a surface of printed circuit board and disposed in proximity (e.g., vertically above) but not touching conductor wire 71. In a non-limiting example, the contactless current measurement device is a high-bandwidth low noise current sensor in an integrated circuit. Alternately, a coreless current sensor may be implemented, e.g., a shunt or transformer, and a contactless- current sensing method may be implemented.

[0061] Returning to FIG.4, the contactless current measurement device 35 generates an output voltage signal 242 which is a correlated measurement of the sensed current that can be directly compared against a threshold value to detect an overcurrent fault. As shown in FIG.4, this output signal 242 can be output as a measured current signal for input to the controller or processor 100 for further recording or for further computing or processing. This output signal 242 is further input to a connected fault detection stage 290 including the OC fault detection circuit for over-current fault detection.

[0062] As shown in FIG.4, the current fault detection stage 290 for detecting an OC fault condition at the SSCB includes a comparator circuit consisting of an operational amplifier 272 configured as a comparator with the comparator 272 having a first negative terminal input receiving the single output signal 242. The comparator 272 is configured to receive a threshold value at a second input thereof which is a fault voltage reference signal 292 set at a voltage level to indicate the presence of an OC current fault condition. The comparator 272 will assert and latch an OC current fault detection signal 37 when the output signal 242 exceeds the fault voltage reference signal level 292. This OC over current fault detection signal 37 is used control the gate driver circuits, e.g., to render the paired MOSFETs of SSCB in an OFF state.

[0063] As further shown in FIG.4, in an optional embodiment, the electronics system 10 is able to reset the OC fault detection stage 290 by receiving a fault reset command signal 285, such as may be generated by the controller or processor and received at a latched fault signal resent transistor 287. In an embodiment, to reset the fault after gate-driver reset or switch state change, the system can further assert a fault reset command signal 285 that turns on transistor 287 to pullthe comparator voltage down to reset the fault detect comparator 272 and reset OC fault detect signal 37.

[0064] In an embodiment, the current fault detection stage 290 of FIG.4 can be adapted as a voltage sense circuit 40A, 40B for sensing the MOSFET switch drain voltages VD1, VD2 used to compute the differential voltage across the SSCB.

[0065] FIG.5 is a detailed circuit diagram of a single gate driver driving a single transistor switch and including associated switch fault management circuit 300 operating to generate gate drive signals to render multi-stage operation, e.g., the OFF / ON states and the INTERMEDIATE resistive state of the MOSFET switch thereof SSCB 20 of FIG.1A. The gate driver 60 may integrate isolation functionality or a separate isolator stage may be used. For example, FIG.5 additionally depicts a signal isolator (high-voltage to low-voltage) circuit 320 that receives isolated voltage rails for digital controls and non-isolated voltage rails to drive the switch open or closed. Signal isolator circuit 320 can act as a buffer and passes signals between high-voltage and low-voltage sides that will be isolated, e.g., voltages, OV fault detection, etc.. Further, while the gate driver inputs are shown as a single-ended inputs, the gate driver circuit can be operable to require a differential input, or, inputs including pulse-width modified (PWM) signals, analog range signals, etc..

[0066] In a non-limiting, illustrative embodiment, the gate driver circuit is an isolated gate driver 60 driven by low-voltage signals in a low-voltage domain 301 and processing those signals to provide gate control voltage outputs for driving the solid state circuit breaker switches, e.g., a MOSFET 15, in a high-voltage domain 302. The low-voltage input signals include at least a drive input power signal (IN+) 312. Drive input power signal 312 is processed to generate a higher voltage drive output power signal 351. This drive output power signal 351 can be boosted by an optional booster circuit 350 that output commands powered by switches connected to V+ DRV and V- DRV switch gate drive voltages. These output drive signals are output as a gate- source signal along input conductor 361 to control the gate-source voltage of SSCB MOSFET switch 15 state into one of: the closed (ON) or fully conducting state to provide a full current conducting path through the SSCB, or depending upon the drive output power signal 351, theINTERMEDIATE state for placing the MOSFET switch in the linear region of operation to provide a resistive path to limit current through the SSCB.

[0067] In an embodiment, the source voltage 370 is the ground reference on the high-voltage for either unidirectional or bidirectional SSCB embodiments. In response to the receipt and processing of the drive output power signal, the booster stage 350 can generate a drive output return signal 352 which is received at the gate driver 60 which responsively generates a corresponding drive input return signal (IN-) 342 for further processing, e.g., by the controller or processor in the low voltage domain.

[0068] Further received at gate driver 60 is a drive reset signal 314 that is generated by the local controller processor (not shown) in order to return the MOSFET switch 15 into the opened (OFF) state to prevent current flow through the SSCB from a previously conducting, e.g., (ON) state.

[0069] Further, the gate driver circuit 60 can provide fault detect response on both low-voltage and high-voltage domains. For example, in an embodiment, received at the gate driver circuit 60 is one of: a respective asserted di / dt fault condition signal 157 or asserted OC fault condition $% signal 37 in response to a respective sensed $& current rate of change value or a sensed currentvalue exceeding a rated threshold.not shown, gate driver can further receive a detected over-voltage (OV) fault command and / or an over-current, over-di / dt current rate of change fault conditions or any additional fault signal that can also be the cause of a fault response (e.g., a controller fault, a temperature fault). The respective asserted fault detection signal 157, 37, is received at the isolated gate driver 60 of the switch fault management circuit 300. In response to receipt of either the asserted di / dt fault condition signal 157 or asserted OC fault condition signal 37 or OV fault condition signal (not shown), the isolated gate driver circuit 60 is responsively commanded to OPEN the attached switch and render the MOSFET switch in an OFF, high- resistance state thereby terminating / preventing current flow through the SSCB.

[0070] Further, as shown in FIG.5, the gate driver circuit 60 includes a switch to pull-down IN+ signal 312 to GND upon a fault detection. While the gate driver circuit embodiment has IN-signal 342 at GND already, this will cause the gate driver output signal 351 to command the MOSFET switch 15 OPEN. For example, fault detect signal 157, 37 can be received at a pull down transistor 325 which removes the drive input power signal 312 and render the MOSFET switch 15 into the opened (OFF) state to terminate any current flow through the SSCB. Further, the gate voltage drive output power input conductor 361 to the gate terminal line has a switch to pull-down VGS to a negative V- DRV voltage. This is a MOSFET or JFET switch pinch-off voltage, which OPENS the switch 15. Thus, simultaneously, the received fault detect signal 157, 37 can be received at the signal isolator 320 which responsively generates a corresponding fault detect signal 345 in the high-voltage domain 302 that is received at gate voltage pull down transistor 355 to a negative drive voltage at conductor 361 and render the MOSFET switch 15 into the opened (OFF) state to terminate any current flow through the SSCB.

[0071] FIG.6 is a diagram 400 depicting the tripping characteristics of a high-voltage circuit interruption device such as mechanical breaker, high-speed fuses as compared to the solid-state circuit breaker of FIG.1A for multiple rated currents. For example, for certain rated currents through a mechanical breaker, a typical fast fault response time 902 to thermally trip the mechanical circuit breaker can range from the millisecond to hundred of millisecond ranges, while a fast fault response time 905 to magnetically trip the mechanical circuit breaker can be less than 10s of milliseconds. Further shown in FIG.6, for certain rated currents through a high- speed fuse-type breaker, a typical fast fault response time 912 to thermally trip the high-speed fuse can range in the microsecond range up to a hundred microseconds. However, as shown in FIG.6, for certain rated currents through a high-speed solid-state circuit breaker such as shown in FIG.1A, a fast fault response time 915 to thermally trip the SSCB can be less than one microsecond and can range from between 50 nanoseconds to 1 microsecond. Thus FIG.6 shows the improvement of implementing the solid-state circuit breaker device in combination with the fast trip fault circuit that provides circuit protection orders of magnitude faster than the other traditional high-voltage protection devices.

[0072] In accordance with a first aspect, a solid state circuit breaker (SSCB) comprises a first Field Effect Transistor (FET), the first FET including a gate, a drain and a source terminal and including a body diode in a first orientation, the drain terminal connecting to a terminal of adirect current (DC) power source configured to supply a direct current for powering a load device; a second FET connected in-series to the first FET, the second FET including a gate, a drain and a source terminal and including a body diode in a second orientation; a first circuit for detecting an instantaneous rate of change of current flow to the load device, the first circuit disposed in a non-contacting arrangement with a conductor connecting the drain terminal of the second FET to the load device; and a first gate driver circuit operatively connected to each the first FET and second FET for receiving signals from the first circuit, and responsively apply a gate voltage to the gate terminal of the first FET and the gate terminal of the second FET to provide active impedance control of the SSCB.

[0073] In accordance with a second aspect, the SSCB according to the first aspect wherein the active impedance control is an SSCB state comprising one of: an ON-state of each the first FET and second FET to provide a low impedance, full current flow path through the SSCB; an OFF- state of each the first FET and second FET to prevent current flow through the SSCB; and a linear region of each the first FET and second FET to provide a linear resistive path through the SSCB, the linear resistive path being a current flow path having an impedance value between an ON-state FET impedance value and an OFF-state FET impedance value.

[0074] In accordance with a third aspect, the SSCB according to the second aspect wherein the first circuit for detecting an instantaneous rate of change of current flow comprises: a di / dt fault logic circuit to detect when a sensed rate of change of current through the source terminal and drain terminal of each of the series connected first FET and second FET that exceeds a pre- determined current rate of change value and assert an over di / dt fault condition signal in response to the detecting.

[0075] In accordance with a fourth aspect, the SSCB according to the third aspect wherein the first circuit for detecting an instantaneous rate of change of current flow comprises: a coreless Rogowski coil situated proximate the drain terminal of the second FET for detecting an induced voltage proportional to a rate of change of the current flow through the drain terminal of the second FET, and a comparator circuit for comparing the induced voltage against a threshold todetect the over di / dt fault condition and asserting the over di / dt fault condition signal when the induced voltage exceeds the threshold.

[0076] In accordance with a fifth aspect, the SSCB according to any one of the first to fourth aspects further comprising: a common mode current sense circuit connected in parallel to the load device.

[0077] In accordance with a sixth aspect, the SSCB according to the fourth aspect further comprising: a first voltage sense circuit connecting across a first terminal and a second terminal of the DC power source for sensing the voltage across the DC power source; a second voltage sense circuit connecting across a first terminal and a second terminal of the DC load device for sensing the voltage across the load device; and a current sense circuit having an input connecting to an output of the first circuit for detecting an instantaneous rate of change of current flow, and having an output connecting to a first terminal of the connected load device; the first gate driver circuit further receiving signals from each the first and second voltage sense circuit and the current sense circuit and further responsively applying a gate voltage to the gate terminal of the first FET and second FET to provide the active impedance control of the SSCB.

[0078] In accordance with a seventh aspect, the SSCB according to the sixth aspect further comprising: an overvoltage fault logic circuit connecting the first and second voltage sense circuit, the overvoltage fault logic circuit configured to detect when a sensed voltage across the DC power source exceeds a pre-determined value and detect when a time duration for when a sensed voltage across the load device exceeds a pre-determined value and assert an overvoltage condition signal in response to the detecting.

[0079] In accordance with an eighth aspect, the SSCB according to the seventh aspect wherein the overvoltage fault logic circuit comprises: a circuit to detect a time duration of the voltage sensed across the DC power source or load device; and a circuit to compare the detected time duration against a pre-determined threshold time indicating an over voltage fault condition, the overvoltage fault logic circuit asserting an over voltage fault condition signal when the detectedduration voltage sensed across the DC power source or load device exceeds the pre-determined threshold time.

[0080] In accordance with a ninth aspect, the SSCB according to the eighth aspect wherein the current sense circuit further comprises: an overcurrent fault logic circuit to detect when a sensed current flow through both the first FET and second FET exceeds a pre-determined value and time duration and assert an overcurrent condition signal in response to the detecting.

[0081] In accordance with a tenth aspect, the SSCB according to the ninth aspect further comprising: a logic circuit receiving one or more the over di / dt fault condition signal, the overcurrent condition signal, or the overvoltage condition signal and responsively assert the gate voltage to the gate terminal of the first FET and second FET to configure the first FET and second FET within the linear region or to turn the first FET and second FET off.

[0082] In accordance with an eleventh aspect, the SSCB according to any one of the sixth to tenth aspects wherein the SSCB further comprises: a return path, the return path comprising: a third FET, the third FET including a gate terminal, a drain terminal and a source terminal and including a body diode in the first orientation; a fourth FET connected in-series to the third FET, the fourth FET including a gate terminal, a drain terminal and a source terminal and including a body diode in the second orientation; a second circuit for detecting an instantaneous rate of change of current flow to the load device, the second circuit disposed in a non-contacting arrangement with a conductor connecting the drain terminal of the fourth FET to the second terminal of the connected load device; and a second gate driver circuit operatively connected to each the third FET and fourth FET for receiving signals from the second circuit, and responsively apply a gate voltage to the gate terminal of the third FET and the gate terminal of the fourth FET to provide the active impedance control of the return path of the SSCB.

[0083] In accordance with a twelfth aspect, the SSCB according to the eleventh aspect wherein the active impedance control is an SSCB state comprising one of: an ON-state of each the third FET and fourth FET to provide a low impedance, full current flow path through the SSCB; an OFF-state of each the third FET and fourth FET to prevent current flow through the SSCB; anda linear region of each the third FET and fourth FET to provide a linear resistive path through the SSCB, the linear resistive path being a current flow path having an impedance value between an ON-state FET impedance value and an OFF-state FET impedance value.

[0084] In accordance with a thirteenth aspect, the SSCB according to the twelfth aspect wherein the second circuit for detecting an instantaneous rate of change of current flow comprises: a further di / dt fault logic circuit to detect when a sensed rate of change of current through the source terminal and drain terminal of the series connected third FET and fourth FET that exceeds a pre-determined current rate of change value and assert an over di / dt fault condition signal in response to the detecting.

[0085] In accordance with a fourteenth aspect, the SSCB according to the thirteenth aspect wherein the second circuit for detecting an instantaneous rate of change of current flow comprises: a coreless Rogowski coil situated proximate the drain terminal of the fourth FET for detecting an induced voltage proportional to a rate of change of the current flow through the drain terminal of the fourth FET, and a comparator circuit for comparing the induced voltage against a threshold to detect the over di / dt fault condition and asserting the over di / dt fault condition signal when the induced voltage exceeds the threshold.

[0086] In accordance with a fifteenth aspect, the SSCB according to the thirteenth aspect or fourteenth aspect further comprising: a common mode current sense circuit connected in parallel to the load device.

[0087] In accordance with a sixteenth aspect, the SSCB according to the fourteenth aspect or fifteenth aspect further comprising: a second current sense circuit having an input connecting to a second terminal of the DC power source and having an output connecting to the drain terminal of the third FET; and the second gate driver circuit operatively connected to each the third FET and fourth FET for receiving signals from each the first and second voltage sense circuit and the second current sense circuit, and responsively apply a gate voltage to the gate terminal of the third FET and the gate terminal of the fourth FET to provide active impedance control of the SSCB.

[0088] In accordance with a seventeenth aspect, the SSCB according to the sixteenth aspect wherein the second current sense circuit further comprises: a further overcurrent fault logic circuit to detect when a sensed current flow through both the source terminal and drain terminal of the third FET and fourth FET exceeds a pre-determined value and time duration and assert an overcurrent condition signal in response to the detecting.

[0089] In accordance with an eighteenth aspect, the SSCB according to the seventeenth aspect further comprising: a logic circuit receiving each the over di / dt fault condition signal, the overcurrent condition signal, and the overvoltage condition signal and responsively assert the gate voltage to the gate terminal of the third FET and fourth FET to configure the third FET and fourth FET within the linear region or turn the third FET and fourth FET off.

[0090] In accordance with a nineteenth aspect, the SSCB according to any one of the sixth to eighteenth aspects further comprising: an overvoltage protection circuit connecting across the first terminal and the second terminal of the DC power source.

[0091] In accordance with a twentieth aspect, the SSCB according to any one of the sixth to eighteenth aspects further comprising: an overvoltage protection circuit connecting across the first terminal and second terminal of the connected load device.

[0092] In accordance with a twenty-first aspect, the SSCB according to the eleventh aspect further comprises: a control circuit receiving externally generated signals and responsively applying a gate voltage to place each the first FET, second FET, third FET and fourth FET in an ON-state or OFF-state.

[0093] In accordance with a twenty-second aspect, the SSCB according to any one of the first to twenty-first aspects absent a series connected fuse or mechanical switch.

[0094] In accordance with a twenty-third aspect, a solid state circuit breaker (SSCB) comprises: a first Field Effect Transistor (FET), the first FET including a gate, a drain and a source terminal and including a body diode in a first orientation, the drain terminal connecting to a terminal of a direct current (DC) power source configured to supply a direct current for powering a load device; a circuit for detecting an instantaneous rate of change of current flow to the load device, the rate of change current detecting circuit disposed in a non-contacting arrangement with a conductor connecting the drain terminal of the first FET to the load device and providing a circuit output; and a gate driver circuit operatively connected to the first FET for receiving output signals from the circuit, and responsively apply a gate voltage to the gate terminal of the first FET to provide active impedance control of the SSCB.

[0095] In accordance with a twenty-fourth aspect, the SSCB according to the twenty-third aspect wherein the circuit output connects to a first terminal of the connected load device and the SSCB further comprises: a return path, the return path comprising: a second FET including a gate terminal, a drain terminal and a source terminal and including a body diode; a second circuit for detecting an instantaneous rate of change of current flow, the second circuit disposed in a non- contacting arrangement with a conductor connecting the drain terminal of the second FET to the second terminal of the connected load device and providing an output; and a second gate driver circuit operatively connected to the second FET for receiving signals output from the second circuit, and responsively apply a gate voltage to the gate terminal of the second FET to provide the active impedance control of the SSCB.

[0096] In accordance with a twenty-fifth aspect, the SSCB according to the twenty-fourth aspect wherein the active impedance control is an SSCB state comprising on of: an ON-state of each first FET and second FET to provide a low impedance, full current flow path through the SSCB; an OFF-state of each the first FET and second FET to prevent current flow through the SSCB; and a linear region of each the first FET and second FET to provide a linear resistive path through the SSCB, the linear resistive path being a current flow path having an impedance value between an ON-state FET impedance value and an OFF-state FET impedance value.

[0097] As described herein, aspects of the present disclosure may include one or more electrical, pneumatic, hydraulic, or other similar secondary components and / or systems therein.

[0098] The present disclosure is therefore contemplated and will be understood to include any necessary operational components thereof. For example, electrical components will be understood to include any suitable and necessary wiring, fuses, or the like for normal operation thereof. Similarly, any pneumatic systems provided may include any secondary or peripheral components such as air hoses, compressors, valves, meters, or the like. It will be further understood that any connections between various components not explicitly described herein may be made through any suitable means including mechanical fasteners, or more permanent attachment means, such as welding or the like. Alternatively, where feasible and / or desirable, various components of the present disclosure may be integrally formed as a single unit.

[0099] Various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

[0100] While various inventive aspects have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and / or structures for performing the function and / or obtaining the results and / or one or more of the advantages described herein, and each of such variations and / or modifications is deemed to be within the scope of the inventive aspects described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and / or configurations will depend upon the specific application or applications for which the inventive teachings is / are used. Those skilled in the art will recognize or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive aspects described herein. It is, therefore, to be understood that the foregoing aspects are presented by way of example only and that, within the scope of the appended claims and equivalents thereto,inventive aspects may be practiced otherwise than as specifically described and claimed. Inventive aspects of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.

[0101] The above-described aspects of the disclosure can be implemented in any of numerous ways. For example, aspects of technology disclosed herein may be implemented using hardware, software, or a combination thereof. When implemented in software, the software code or instructions can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers. Furthermore, the instructions or software code can be stored in at least one non-transitory computer readable storage medium.

[0102] As used herein, the term “processor” may include a single core processor, a multi-core processor, multiple processors located in a single device, or multiple processors in wired or wireless communication with each other and distributed over a network of devices, the Internet, or the cloud. Accordingly, as used herein, functions, features or instructions performed or configured to be performed by a “processor”, may include the performance of the functions, features or instructions by a single core processor, may include performance of the functions, features or instructions collectively or collaboratively by multiple cores of a multi-core processor, or may include performance of the functions, features or instructions collectively or collaboratively by multiple processors, where each processor or core is not required to perform every function, feature or instruction individually. For example, a single FPGA may be used, or multiple FPGAs may be used to achieve the functions, features or instructions described herein.

[0103] The various methods or processes outlined herein may be coded as software / instructions that is executable on one or more processors that employ any one of a variety of operating systems or platforms. Additionally, such software may be written using any of a number of suitable programming languages and / or programming or scripting tools, and also may becompiled as executable machine language code or intermediate code that is executed on a framework or virtual machine.

[0104] In this respect, various inventive concepts may be embodied as a computer readable storage medium (or multiple computer readable storage media) (e.g., a computer memory, one or more floppy discs, compact discs, optical discs, magnetic tapes, flash memories, USB flash drives, SD cards, circuit configurations in Field Programmable Gate Arrays or other semiconductor devices, or other non-transitory medium or tangible computer storage medium) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement the various embodiments of the disclosure discussed above. The computer readable medium or media can be transportable, such that the program or programs stored thereon can be loaded onto one or more different computers or other processors to implement various aspects of the present disclosure as discussed above.

[0105] The terms “program” or “software” or “instructions” are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that can be employed to program a computer or other processor to implement various aspects of embodiments as discussed above. Additionally, it should be appreciated that according to one aspect, one or more computer programs that when executed perform methods of the present disclosure need not reside on a single computer or processor, but may be distributed in a modular fashion amongst a number of different computers or processors to implement various aspects of the present disclosure.

[0106] Computer-executable instructions may be in many forms, such as program modules, executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Typically, the functionality of the program modules may be combined or distributed as desired in various embodiments. As such, one aspect or embodiment of the present disclosure may be a computer program product including least one non-transitory computer readable storage medium in operative communication with a processor, the storage medium having instructions stored thereon that, when executed by the processor,implement a method or process described herein, wherein the instructions comprise the steps to perform the method(s) or process(es) detailed herein.

[0107] Also, data structures may be stored in computer-readable media in any suitable form. For simplicity of illustration, data structures may be shown to have fields that are related through location in the data structure. Such relationships may likewise be achieved by assigning storage for the fields with locations in a computer-readable medium that convey relationship between the fields. However, any suitable mechanism may be used to establish a relationship between information in fields of a data structure, including through the use of pointers, tags or other mechanisms that establish relationship between data elements.

[0108] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0109] The articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.” The phrase “and / or,” as used herein in the specification and in the claims (if at all), should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and / or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and / or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc. As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisteditems. Only terms clearly indicated to the contrary, such as “only one of” or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e. “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.

[0110] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and / or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

[0111] While components of the present disclosure are described herein in relation to each other, it is possible for one of the components disclosed herein to include inventive subject matter, if claimed alone or used alone. In keeping with the above example, if the disclosed embodiments teach the features of components A and B, then there may be inventive subject matter in the combination of A and B, A alone, or B alone, unless otherwise stated herein.

[0112] When a feature or element is herein referred to as being “on” another feature or element, it can be directly on the other feature or element or intervening features and / or elements may also be present. In contrast, when a feature or element is referred to as being “directly on” anotherfeature or element, there are no intervening features or elements present. It will also be understood that, when a feature or element is referred to as being “connected”, “attached” or “coupled” to another feature or element, it can be directly connected, attached or coupled to the other feature or element or intervening features or elements may be present. In contrast, when a feature or element is referred to as being “directly connected”, “directly attached” or “directly coupled” to another feature or element, there are no intervening features or elements present. Although described or shown with respect to one embodiment, the features and elements so described or shown can apply to other embodiments. It will also be appreciated by those of skill in the art that references to a structure or feature that is disposed “adjacent” another feature may have portions that overlap or underlie the adjacent feature.

[0113] Although the terms “first” and “second” may be used herein to describe various features / elements, these features / elements should not be limited by these terms, unless the context indicates otherwise. These terms may be used to distinguish one feature / element from another feature / element. Thus, a first feature / element discussed herein could be termed a second feature / element, and similarly, a second feature / element discussed herein could be termed a first feature / element without departing from the teachings of the present invention.

[0114] If this specification states a component, feature, structure, or characteristic “may”, “might”, or “could” be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.

[0115] As used herein in the specification and claims, including as used in the examples and unless otherwise expressly specified, all numbers may be read as if prefaced by the word “about” or “approximately,” even if the term does not expressly appear. The phrase “about” or “approximately” may be used when describing magnitude and / or position to indicate that the value and / or position described is within a reasonable expected range of values and / or positions. For example, a numeric value may have a value that is + / −0.1% of the stated value (or range of values), + / −1% of the stated value (or range of values), + / −2% of the stated value (or range ofvalues), + / −5% of the stated value (or range of values), + / −10% of the stated value (or range of values), etc. Any numerical range recited herein is intended to include all sub-ranges subsumed therein.

[0116] Additionally, the method of performing the present disclosure may occur in a sequence different than those described herein. Accordingly, no sequence of the method should be read as a limitation unless explicitly stated. It is recognizable that performing some of the steps of the method in a different order could achieve a similar result. Additionally, the features may be performed at the same time.

[0117] In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of” and “consisting essentially of” shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures.

[0118] To the extent that the present disclosure has utilized the term “invention” in various titles or sections of this specification, this term was included as required by the formatting requirements of word document submissions pursuant the guidelines / requirements of the United States Patent and Trademark Office and shall not, in any manner, be considered a disavowal of any subject matter.

[0119] In the foregoing description, certain terms have been used for brevity, clearness, and understanding. No unnecessary limitations are to be implied therefrom beyond the requirement of the prior art because such terms are used for descriptive purposes and are intended to be broadly construed.

[0120] Moreover, the description and illustration of various aspects of the disclosure are examples and the disclosure is not limited to the exact details shown or described. The terminology used herein is for the purpose of describing particular aspects only and is notintended to be limiting the scope of the disclosure and is not intended to be exhaustive. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure.

Claims

CLAIMS 1. A solid state circuit breaker (SSCB) comprising: a first Field Effect Transistor (FET), the first FET including a gate terminal, a drain terminal and a source terminal and including a body diode in a first orientation, the drain terminal connecting to a terminal of a direct current (DC) power source configured to supply a direct current for powering a load device; a second FET connected in-series to the first FET, the second FET including a gate, a drain and a source terminal and including a body diode in a second orientation; a first circuit for detecting an instantaneous rate of change of current flow to said load device, said first circuit disposed in a non-contacting arrangement with a conductor connecting the drain terminal of said second FET to the load device; and a first gate driver circuit operatively connected to each said first FET and second FET for receiving signals from said first circuit, and responsively apply a gate voltage to the gate terminal of the first FET and the gate terminal of said second FET to provide active impedance control of said SSCB.

2. The SSCB of Claim 1, wherein the active impedance control is an SSCB state comprising one of: an ON-state of each said first FET and second FET to provide a low impedance, full current flow path through the SSCB; an OFF-state of each said first FET and second FET to prevent current flow through the SSCB; and a linear region of each said first FET and second FET to provide a linear resistive path through the SSCB, the linear resistive path being a current flow path having an impedance value between an ON-state FET impedance value and an OFF-state FET impedance value.

3. The SSCB of Claim 2, wherein the first circuit for detecting an instantaneous rate of change of current flow comprises: a di / dt fault logic circuit to detect when a sensed rate of change of current through the source terminal and drain terminal of each of said series connected first FET and second FETthat exceeds a pre-determined current rate of change value and assert an over di / dt fault condition signal in response to said detecting.

4. The SSCB of Claim 3, wherein the first circuit for detecting an instantaneous rate of change of current flow comprises: a coreless Rogowski coil situated proximate the drain terminal of said second FET for detecting an induced voltage proportional to a rate of change of the current flow through the drain terminal of said second FET, and a comparator circuit for comparing the induced voltage against a threshold to detect the over di / dt fault condition and asserting the over di / dt fault condition signal when the induced voltage exceeds the threshold.

5. The SSCB of any one of Claims 1 to 4, further comprising: a common mode current sense circuit connected in parallel to said load device.

6. The SSCB of Claim 4, further comprising: a first voltage sense circuit connecting across a first terminal and a second terminal of said DC power source for sensing the voltage across the DC power source; a second voltage sense circuit connecting across a first terminal and a second terminal of said DC load device for sensing the voltage across the load device; and a current sense circuit having an input connecting to an output of the first circuit for detecting an instantaneous rate of change of current flow, and having an output connecting to a first terminal of the connected load device; the first gate driver circuit further receiving signals from each said first and second voltage sense circuit and said current sense circuit and further responsively applying a gate voltage to the gate terminal of the first FET and second FET to provide said active impedance control of said SSCB.

7. The SSCB of Claim 6, further comprising: an overvoltage fault logic circuit connecting the first and second voltage sense circuit, the overvoltage fault logic circuit configured to detect when a sensed voltage across the DC powersource exceeds a pre-determined value and detect when a time duration for when a sensed voltage across the load device exceeds a pre-determined value and assert an overvoltage condition signal in response to said detecting.

8. The SSCB of Claim 7, wherein the overvoltage fault logic circuit comprises: a circuit to detect a time duration of the voltage sensed across the DC power source or load device; and a circuit to compare the detected time duration against a pre-determined threshold time indicating an over voltage fault condition, the overvoltage fault logic circuit asserting an over voltage fault condition signal when the detected duration voltage sensed across the DC power source or load device exceeds said pre-determined threshold time.

9. The SSCB of Claim 8, the current sense circuit further comprising: an overcurrent fault logic circuit to detect when a sensed current flow through both the first FET and second FET exceeds a pre-determined value and time duration and assert an overcurrent condition signal in response to said detecting.

10. The SSCB of Claim 9, further comprising: a logic circuit receiving one or more said over di / dt fault condition signal, said overcurrent condition signal, or said overvoltage condition signal and responsively assert said gate voltage to the gate terminal of the first FET and second FET to configure said first FET and second FET within the linear region or to turn said first FET and second FET off.

11. The SSCB of any one of Claims 6 to 10, wherein the SSCB further comprises: a return path, the return path comprising: a third FET, the third FET including a gate terminal, a drain terminal and a source terminal and including a body diode in the first orientation; a fourth FET connected in-series to the third FET, the fourth FET including a gate terminal, a drain terminal and a source terminal and including a body diode in the second orientation;a second circuit for detecting an instantaneous rate of change of current flow to said load device, said second circuit disposed in a non-contacting arrangement with a conductor connecting the drain terminal of said fourth FET to the second terminal of said connected load device; and a second gate driver circuit operatively connected to each said third FET and fourth FET for receiving signals from said second circuit, and responsively apply a gate voltage to the gate terminal of the third FET and the gate terminal of said fourth FET to provide the active impedance control of the return path of said SSCB.

12. The SSCB of Claim 11, wherein the active impedance control is an SSCB state comprising one of: an ON-state of each said third FET and fourth FET to provide a low impedance, full current flow path through the SSCB; an OFF-state of each said third FET and fourth FET to prevent current flow through the SSCB; and a linear region of each said third FET and fourth FET to provide a linear resistive path through the SSCB, the linear resistive path being a current flow path having an impedance value between an ON-state FET impedance value and an OFF-state FET impedance value.

13. The SSCB of Claim 12, wherein the second circuit for detecting an instantaneous rate of change of current flow comprises: a further di / dt fault logic circuit to detect when a sensed rate of change of current through the source terminal and drain terminal of said series connected third FET and fourth FET that exceeds a pre-determined current rate of change value and assert an over di / dt fault condition signal in response to said detecting.

14. The SSCB of Claim 13, wherein the second circuit for detecting an instantaneous rate of change of current flow comprises: a coreless Rogowski coil situated proximate the drain terminal of said fourth FET for detecting an induced voltage proportional to a rate of change of the current flow through the drain terminal of said fourth FET, anda comparator circuit for comparing the induced voltage against a threshold to detect the over di / dt fault condition and asserting the over di / dt fault condition signal when the induced voltage exceeds the threshold.

15. The SSCB of Claim 13 or Claim 14, further comprising: a common mode current sense circuit connected in parallel to said load device.

16. The SSCB of Claim 14 or Claim 15, further comprising: a second current sense circuit having an input connecting to a second terminal of said DC power source and having an output connecting to the drain terminal of said third FET; and the second gate driver circuit operatively connected to each said third FET and fourth FET for receiving signals from each said first and second voltage sense circuit and said second current sense circuit, and responsively apply a gate voltage to the gate terminal of said third FET and the gate terminal of said fourth FET to provide active impedance control of said SSCB.

17. The SSCB of Claim 16, wherein the second current sense circuit further comprising: a further overcurrent fault logic circuit to detect when a sensed current flow through both the source terminal and drain terminal of said third FET and fourth FET exceeds a pre- determined value and time duration and assert an overcurrent condition signal in response to said detecting.

18. The SSCB of Claim 17, further comprising: a logic circuit receiving each said over di / dt fault condition signal, said overcurrent condition signal, and said overvoltage condition signal and responsively assert said gate voltage to the gate terminal of said third FET and fourth FET to configure said third FET and fourth FET within the linear region or turn said third FET and fourth FET off.

19. The SSCB of any one of Claims 6 to 18, further comprising: an overvoltage protection circuit connecting across the first terminal and the second terminal of the DC power source.

20. The SSCB of any one of Claims 6 to 18, further comprising: an overvoltage protection circuit connecting across the first terminal and second terminal of the connected load device.

21. The SSCB of Claim 11, further comprising a control circuit receiving externally generated signals and responsively applying a gate voltage to place each said first FET, second FET, third FET and fourth FET in an ON-state or OFF-state.

22. The SSCB of any one of Claims 1 to 21, absent a series connected fuse or mechanical switch.

23. A solid state circuit breaker (SSCB) comprising: a first Field Effect Transistor (FET), the first FET including a gate terminal, a drain terminal and a source terminal and including a body diode in a first orientation, the drain terminal connecting to a terminal of a direct current (DC) power source configured to supply a direct current for powering a load device; a circuit for detecting an instantaneous rate of change of current flow to said load device, said rate of change current detecting circuit disposed in a non-contacting arrangement with a conductor connecting the drain terminal of said first FET to the load device and providing a circuit output; and a gate driver circuit operatively connected to said first FET for receiving output signals from said circuit, and responsively apply a gate voltage to the gate terminal of the first FET to provide active impedance control of said SSCB.

24. The SSCB of Claim 23, wherein the circuit output connects to a first terminal of the connected load device, said SSCB further comprising: a return path, the return path comprising: a second FET including a gate terminal, a drain terminal and a source terminal and including a body diode;a second circuit for detecting an instantaneous rate of change of current flow, said second circuit disposed in a non-contacting arrangement with a conductor connecting the drain terminal of said second FET to the second terminal of said connected load device and providing an output; and a second gate driver circuit operatively connected to said second FET for receiving signals output from said second circuit, and responsively apply a gate voltage to the gate terminal of the second FET to provide the active impedance control of said SSCB.

25. The SSCB of Claim 24, wherein the active impedance control is an SSCB state comprising on of: an ON-state of each first FET and second FET to provide a low impedance, full current flow path through the SSCB; an OFF-state of each said first FET and second FET to prevent current flow through the SSCB; and a linear region of each said first FET and second FET to provide a linear resistive path through the SSCB, the linear resistive path being a current flow path having an impedance value between an ON-state FET impedance value and an OFF-state FET impedance value.

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