Display substrate and preparation method therefor, and display apparatus

Abstract

Provided is a display substrate, comprising: a base substrate; a driving circuit layer located on the base substrate; and a light-emitting device layer located on the side of the driving circuit layer away from the base substrate. The light-emitting device layer comprises a plurality of light-emitting devices, wherein each light-emitting device comprises a first electrode, a light-emitting functional component located on the side of the first electrode away from the base substrate, and a second electrode located on the side of the light-emitting functional component away from the base substrate. The light-emitting device layer comprises at least one light-emitting unit, the light-emitting unit comprising at least two light-emitting devices, wherein the at least two light-emitting devices are sequentially connected in series, and the light-emitting devices are configured to emit light from the second electrode side. The base substrate has a first surface facing the light-emitting device layer, and the light-emitting functional component comprises a first light-emitting surface close to the first surface, and a second light-emitting surface away from the first surface, wherein the orthographic projection of the first light-emitting surface on the base substrate is located in the orthographic projection of the second light-emitting surface on the base substrate, and the area of the first light-emitting surface is less than the area of the second light-emitting surface.

Description

Display substrate, manufacturing method thereof and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a display substrate, a manufacturing method thereof and a display device. BACKGROUND

[0002] Micro Light-Emitting Diode (Micro LED) is a light-emitting diode with a micron-level size. Since the size of the Micro LED is small, it can be used as a pixel on a display panel. A display substrate prepared by using the Micro LED can be referred to as a Micro LED display substrate. In a Micro LED product, the Micro LED technology is to miniaturize the size of an existing LED to less than 100 um, which is about 1% of the size of the existing LED. Then, through a mass transfer technology, the Micro LED with a micron level is transferred to a driving substrate, thereby forming various Micro LED displays with different sizes.

[0003] The above information disclosed in this section is only for the understanding of the background of the inventive concept of the present disclosure, and therefore, the above information can include information which does not constitute the prior art.

[0004] SUMMARY

[0005] In one aspect, a display substrate is provided, the display substrate comprising:

[0006] a substrate substrate;

[0007] a driving circuit layer on the substrate substrate; and

[0008] a light emitting device layer on a side of the driving circuit layer distal to the substrate substrate, the light emitting device layer comprising a plurality of light emitting devices, each of the light emitting devices comprising a first electrode, a light emitting functional portion on a side of the first electrode distal to the substrate substrate, and a second electrode on a side of the light emitting functional portion distal to the substrate substrate, the light emitting device layer comprising at least one light emitting unit, the at least one light emitting unit comprising at least two of the light emitting devices, the at least two light emitting devices being connected in series in sequence,

[0009] wherein the light emitting device is configured to emit light from the second electrode side, the substrate substrate has a first surface facing the light emitting device layer, the light emitting functional portion comprises a first light emitting surface proximate to the first surface and a second light emitting surface distal to the first surface, a footprint of the first light emitting surface on the substrate substrate is located within a footprint of the second light emitting surface on the substrate substrate, and an area of the first light emitting surface is smaller than an area of the second light emitting surface.

[0010] According to some exemplary embodiments, a shape of a cross section of the light emitting functional portion perpendicular to the first surface is an inverted trapezoid.

[0011] According to some exemplary embodiments, the light emitting functional portion has a first side surface intersecting the first surface of the substrate, and an angle of a corner between the first side surface of the light emitting functional portion and the first surface of the substrate is 50-70°.

[0012] According to some exemplary embodiments, the first electrode is provided with a first bonding pad on a side close to the driving circuit layer, the driving circuit layer is provided with a second bonding pad on a side close to the first electrode, the first bonding pad is electrically connected to the second bonding pad, the light emitting device is electrically connected to the driving circuit layer through the first bonding pad and the second bonding pad, and a normal projection of the first bonding pad on the substrate is located within a normal projection of the second bonding pad on the substrate.

[0013] According to some exemplary embodiments, the light emitting unit further comprises at least one bridge portion, in two adjacent and electrically connected light emitting devices, a first electrode of one light emitting device is electrically connected to a second electrode of another light emitting device through the bridge portion.

[0014] According to some exemplary embodiments, the display substrate further comprises a first passivation layer, the first passivation layer is located between the first electrode and the light emitting functional portion, the first passivation layer extends from the first side surface of the light emitting functional portion to a plane of the light emitting functional portion facing the substrate, and the first passivation layer has a first via hole exposing a part of the plane of the light emitting functional portion facing the substrate.

[0015] The first electrode is connected to the light emitting functional portion through the first via hole, a normal projection of the first electrode on the substrate partially coincides with a normal projection of the first passivation layer on the substrate, and the first electrode has a first groove on a side facing the substrate.

[0016] The first bonding pad is located in the first groove of the first electrode.

[0017] According to some exemplary embodiments, the display substrate further comprises a reflection portion, the reflection portion covers at least a part of the first side surface of the light emitting functional portion.

[0018] According to some exemplary embodiments, the reflection portion is located on a side of the first passivation layer away from the light emitting functional portion, and the reflection portion and the first electrode are located in the same layer.

[0019] According to some exemplary embodiments, the reflective portion and the first electrical connection are integrated, and a normal projection of the reflective portion and the first electrode on the substrate substrate covers a normal projection of the light-emitting functional portion on the substrate substrate.

[0020] According to some exemplary embodiments, the driving circuit layer further comprises a connection terminal on a side of the second bonding pad close to the substrate substrate, the connection terminal is electrically connected to the first electrode of the light-emitting device through the second bonding pad and the first bonding pad; and

[0021] In two adjacent and electrically connected light-emitting devices, the connection terminal electrically connected to one of the light-emitting devices has an extension portion, at least a part of a normal projection of the extension portion on the substrate substrate does not overlap with a normal projection of the second bonding pad on the substrate substrate, and a part of the extension portion protruding relative to the second bonding pad is electrically connected to the second electrode of the other light-emitting device through the bridge portion.

[0022] According to some exemplary embodiments, further comprising a first planarization layer on a side of the light-emitting device layer away from the substrate substrate, the first planarization layer comprises a plurality of planarization portions, the planarization portions cover side surfaces of the light-emitting device, the first bonding pad and the second bonding pad, the planarization portions have a first opening, and the first opening exposes at least a part of the second electrode of the light-emitting device; and

[0023] The bridge portion is on a side of the first planarization layer away from the substrate substrate, one end of the bridge portion is electrically connected to the second electrode of one of the light-emitting devices through the first opening, and the other end of the bridge portion extends along a surface of the planarization layer and is electrically connected to the first electrode of the adjacent light-emitting device through the connection terminal.

[0024] According to some exemplary embodiments, the display substrate further comprises a light-blocking portion, a normal projection of the light-blocking portion on the substrate substrate is located between normal projections of two adjacent first openings on the substrate substrate; and

[0025] The light-blocking portion is farther away from the substrate substrate than a plane of the light-emitting device away from the substrate substrate, the light-emitting device is configured to emit third color light, and the light-blocking portion is configured to absorb or reflect third color light.

[0026] According to some exemplary embodiments, the light-blocking portion is located between two adjacent planarization portions, and the light-blocking portion is located on a side of the bridge portion away from the substrate substrate; and

[0027] The light-blocking portion is closer to the plane of the substrate than the light-emitting device is to the plane of the substrate.

[0028] According to some exemplary embodiments, the display substrate further comprises a color conversion portion, the color conversion portion is located between two adjacent light-blocking portions, the color conversion portion covers the light-emitting device;

[0029] The light-blocking portion is spaced apart from the adjacent planarization portion, and a part of the color conversion portion is arranged outside the side surface of the light-emitting device; and

[0030] The color conversion portion comprises a first color conversion portion and a second color conversion portion, the first color conversion portion is configured to convert third color light into first color light, and the second color conversion portion is configured to convert third color light into second color light.

[0031] According to some exemplary embodiments, the display substrate further comprises a second planarization layer located on the side of the first planarization layer away from the substrate, and the light-blocking portion is located on the side of the second planarization layer away from the substrate, and the plane of the light-blocking portion is farther away from the plane of the substrate than the plane of the light-emitting device is to the plane of the substrate.

[0032] According to some exemplary embodiments, the display substrate further comprises a second passivation layer located between the first electrode and the light-emitting functional portion, the second passivation layer covers at least a first side surface of the light-emitting functional portion, the second passivation layer has a first via hole, the first via hole exposes a part of the plane of the light-emitting functional portion facing the substrate, and the first electrode is connected to the light-emitting functional portion through the first via hole;

[0033] The bridge portion comprises a first bridge portion and a second bridge portion, the first bridge portion is located on the side of the second passivation layer close to the substrate, the first bridge portion is electrically connected to the adjacent first electrode, the second bridge portion is located on the side of the second passivation layer away from the substrate, and the second bridge portion is electrically connected to the adjacent second electrode;

[0034] The second passivation layer further has a second via hole, and the first bridge portion and the second bridge portion are electrically connected through the second via hole; and

[0035] In two adjacent light-emitting devices that are electrically connected, the first electrode of one light-emitting device is electrically connected to the second electrode of the other light-emitting device through the first bridge portion and the second bridge portion.

[0036] According to some exemplary embodiments, the first bridge portion and the first electrode are located in the same layer, and the first bridge portion is connected to the adjacent first electrode as an integral structure.

[0037] According to some exemplary embodiments, the material of the second bridge portion includes a transparent conductive material, and a projection of the second bridge portion on the substrate substrate covers a projection of the second electrode on the substrate substrate.

[0038] According to some exemplary embodiments, the material of the second bridge portion includes a metal conductive material, a projection of the second bridge portion on the substrate substrate partially overlaps with a projection of the second electrode on the substrate substrate, and the projection of the second bridge portion on the substrate substrate does not overlap with a projection of the light emitting functional portion on the substrate substrate.

[0039] According to some exemplary embodiments, the display substrate further includes a reflective layer between the light emitting device layer and the driving circuit layer, the reflective layer covers at least part of the side surface of the light emitting device.

[0040] According to some exemplary embodiments, the display substrate further includes a third passivation layer between the reflective layer and the first electrode, the third passivation layer includes a plurality of third vias;

[0041] The reflective layer includes a plurality of reflective portions arranged at intervals, and the plurality of reflective portions are electrically connected to the plurality of first electrodes through the plurality of third vias; and

[0042] The first bonding pad is located on the side of the reflective layer close to the substrate substrate, and the first bonding pad is electrically connected to the first electrode through the reflective portion.

[0043] According to some exemplary embodiments, the display substrate further includes a third planarization layer between the light emitting device layer and the driving circuit layer, the third planarization layer fills at least part of the spacing region between two adjacent light emitting devices.

[0044] According to some exemplary embodiments, the surface of the third planarization layer close to the substrate substrate is closer to the substrate substrate than the surface of the light emitting device close to the substrate substrate; and

[0045] The third planarization layer has a fourth via, the fourth via exposes at least part of the first electrode, and the first bonding pad is electrically connected to the first electrode through the fourth via.

[0046] According to some exemplary embodiments, the light emitting device is configured to emit third color light, and the third planarization layer is configured to absorb or reflect the third color light.

[0047] In yet another aspect, a method for manufacturing a display substrate is provided, comprising the steps of:

[0048] providing a substrate base plate;

[0049] forming a driving circuit layer on the substrate base plate;

[0050] forming a light emitting device layer on a side of the driving circuit layer distal to the substrate base plate, the light emitting device layer comprising a plurality of light emitting devices, each of the light emitting devices comprising a first electrode, a light emitting functional portion on a side of the first electrode distal to the substrate base plate, and a second electrode on a side of the light emitting functional portion distal to the substrate base plate, the light emitting device layer comprising at least one light emitting unit, the at least one light emitting unit comprising at least two of the light emitting devices, the at least two light emitting devices being connected in series in sequence,

[0051] wherein the light emitting device is configured to emit light from the side of the second electrode, the substrate base plate has a first surface facing the light emitting device layer, and a cross section of the light emitting functional portion perpendicular to the first surface has an inverted trapezoidal shape.

[0052] According to some exemplary embodiments, forming the light emitting device layer on the side of the driving circuit layer distal to the substrate base plate comprises:

[0053] providing a light emitting diode epitaxial wafer comprising an epitaxial substrate, a buffer layer on the epitaxial substrate, a first semiconductor layer on a side of the buffer layer distal to the epitaxial substrate, a light emitting layer on a side of the first semiconductor layer distal to the epitaxial substrate, a second semiconductor layer on a side of the light emitting layer distal to the epitaxial substrate, and a second electrode layer on a side of the second semiconductor layer distal to the epitaxial substrate;

[0054] providing a carrier substrate, forming a glue layer on the carrier substrate, and attaching at least one of the light emitting diode epitaxial wafers comprising the second electrode layer and the bridge layer to the carrier substrate;

[0055] removing the epitaxial substrate and the buffer layer;

[0056] patterning the first semiconductor layer, the light emitting layer, the second semiconductor layer and the second electrode layer to form a plurality of the second electrodes, a plurality of the second semiconductor portions on a side of the plurality of the second electrodes away from the carrier substrate, a plurality of the light emitting portions on a side of the plurality of the second semiconductor portions away from the carrier substrate, a plurality of the first semiconductor portions on a side of the plurality of the light emitting portions away from the carrier substrate;

[0057] forming a first electrode on a side of the first semiconductor portion away from the carrier substrate, and forming a first bonding pad on a side of the first electrode away from the carrier substrate;

[0058] forming a plurality of second bonding pads on a side of the driving circuit layer away from the substrate, the driving circuit layer comprising connection terminals electrically connected to the second bonding pads, a portion of the connection terminals having epitaxial portions, at least a portion of a footprint of the epitaxial portions on the substrate does not overlap with a footprint of the second bonding pads on the substrate, the driving circuit layer comprising sixth vias exposing the epitaxial portions of the connection terminals;

[0059] bonding the first bonding pad on the carrier substrate to the second bonding pad on the substrate, and removing the carrier substrate and the adhesive layer; and

[0060] forming a bridge portion on a side of the second electrode away from the substrate, one end of the bridge portion being electrically connected to the second electrode of one of the light emitting devices, the other end of the bridge portion being electrically connected to the epitaxial portion of the connection terminal electrically connected to another of the light emitting devices through the sixth via.

[0061] According to some exemplary embodiments, forming a light emitting device layer on a side of the driving circuit layer away from the substrate comprises:

[0062] providing a light emitting diode epitaxial wafer, the light emitting diode epitaxial wafer comprising an epitaxial substrate, a buffer layer on the epitaxial substrate, a first semiconductor layer on a side of the buffer layer away from the epitaxial substrate, a light emitting layer on a side of the first semiconductor layer away from the epitaxial substrate, a second semiconductor layer on a side of the light emitting layer away from the epitaxial substrate, a second electrode layer on a side of the second semiconductor layer away from the epitaxial substrate, and a bridge layer on a side of the second electrode layer away from the epitaxial substrate;

[0063] providing a carrier substrate, and attaching at least one of the light emitting diode epitaxial wafers comprising the second electrode layer and the bridge layer to the carrier substrate;

[0064] removing the epitaxial substrate and the buffer layer;

[0065] patterning the first semiconductor layer, the light emitting layer, the second semiconductor layer and the second electrode layer to form a plurality of the second electrodes, a plurality of the second semiconductor portions located on a side of the plurality of the second electrodes away from the carrier substrate, a plurality of the light emitting portions located on a side of the plurality of the second semiconductor portions away from the carrier substrate, and a plurality of the first semiconductor portions located on a side of the plurality of the light emitting portions away from the carrier substrate;

[0066] patterning the bridge layer to form a plurality of the second bridge portions arranged at intervals;

[0067] forming a second passivation layer on a side of the first semiconductor portions away from the carrier substrate, the second passivation layer having a first via and a second via, the first via exposing at least a portion of the first semiconductor portions, and the second via exposing at least a portion of the second bridge portions;

[0068] forming a first electrode and a first bridge portion on a side of the second passivation layer away from the carrier substrate, the first electrode being connected to the first semiconductor portions through the first via, and the first bridge portion being electrically connected to the second bridge portions through the second via;

[0069] forming a first bonding pad on a side of the first electrode away from the carrier substrate;

[0070] forming a plurality of second bonding pads on a side of the drive circuit layer away from the substrate;

[0071] bonding the first bonding pad on the carrier substrate to the second bonding pad on the substrate.

[0072] In yet another aspect, there is provided a display device comprising the display substrate as in any of the preceding aspects. BRIEF DESCRIPTION OF DRAWINGS

[0073] The features and advantages of the present disclosure will become more apparent from the detailed description of example embodiments thereof in conjunction with the accompanying drawings.

[0074] FIG. 1 schematically illustrates a plan view of a display substrate according to some embodiments of the present disclosure.

[0075] FIG. 2A schematically illustrates a cross-sectional view of a display substrate taken along AA’ in FIG. 1 according to some embodiments of the present disclosure.

[0076] FIG. 2B schematically illustrates a cross-sectional view of a display substrate taken along BB’ in FIG. 1 according to some embodiments of the present disclosure.

[0077] FIG. 2C schematically illustrates a cross-sectional view of the display substrate taken along CC’ in FIG. 1, according to some embodiments of the present disclosure.

[0078] FIG. 2D schematically illustrates a cross-sectional view of the display substrate taken along AA’ in FIG. 1, according to some embodiments of the present disclosure.

[0079] FIG. 3 schematically illustrates a magnified view of a light emitting device and a first bonding pad in the display substrate, according to some embodiments of the present disclosure.

[0080] FIG. 4 schematically illustrates a cross-sectional view of a driving circuit layer of the display substrate, according to some embodiments of the present disclosure.

[0081] FIG. 5 schematically illustrates a magnified view of a light emitting device and a first bonding pad in the display substrate, according to some embodiments of the present disclosure.

[0082] FIG. 6 schematically illustrates a cross-sectional view of the display substrate taken along AA’ in FIG. 1, according to some embodiments of the present disclosure.

[0083] FIG. 7 schematically illustrates a cross-sectional view of the display substrate taken along NN’ in FIG. 1, according to some embodiments of the present disclosure.

[0084] FIG. 8 schematically illustrates a cross-sectional view of the display substrate taken along NN’ in FIG. 1, according to some embodiments of the present disclosure.

[0085] FIG. 9 schematically illustrates a cross-sectional view of the display substrate taken along NN’ in FIG. 1, according to some embodiments of the present disclosure.

[0086] FIG. 10 schematically illustrates a cross-sectional view of the display substrate taken along NN’ in FIG. 1, according to some embodiments of the present disclosure.

[0087] FIG. 11 is an equivalent circuit diagram of one pixel circuit of a display substrate, according to some example embodiments of the present disclosure.

[0088] FIG. 12A schematically illustrates a flowchart of a method of manufacturing a display substrate, according to embodiments of the present disclosure.

[0089] FIG. 12B schematically illustrates a flowchart of forming a light emitting device layer in a method of manufacturing a display substrate, according to embodiments of the present disclosure.

[0090] FIG. 12C schematically illustrates a flowchart of forming a light emitting device layer in a method of manufacturing a display substrate, according to embodiments of the present disclosure.

[0091] FIGS. 13A-13N schematically illustrate process diagrams of forming a display substrate, according to some embodiments of the present disclosure.

[0092] FIGS. 14A-14Q schematically illustrate process diagrams of forming a display substrate according to some embodiments of the present disclosure.

[0093] FIGS. 15A-15D schematically illustrate process diagrams of forming a display substrate according to some embodiments of the present disclosure.

[0094] FIGS. 16A-16B schematically illustrate process diagrams of forming a display substrate according to some embodiments of the present disclosure.

[0095] FIGS. 17A-17E schematically illustrate process diagrams of forming a display substrate according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0096] In order to make the purposes, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the protection scope of the present disclosure.

[0097] It should be noted that in the drawings, the size and relative size of the elements can be exaggerated and / or simplified for the sake of clarity and / or description. Thus, the size and relative size of the various elements in the drawings are not necessarily to scale. In the description and drawings, identical or similar reference signs indicate identical or similar parts.

[0098] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, it can be directly on, directly connected to, or directly coupled to the other element, or intervening elements can be present. In contrast, when an element is described as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. Other terms of description used herein, such as "between," "directly between," "adjacent to," "directly adjacent to," or "on" can be interpreted in a like fashion. In addition, the term "connected" can refer to physical or electrical connectivity, communicative connectivity, and / or fluidic connectivity. Furthermore, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to include only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated items.

[0099] It should be noted that, although the terms "first," "second," etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer and / or section from another element, component, region, layer and / or section. Thus, a first element, component, region, layer and / or section discussed below could be termed a second element, component, region, layer and / or section without departing from the teachings of the present disclosure.

[0100] Spatially relative terms, such as "on", "above", "left", "right", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device described is turned over, elements described as "below" or "under" other elements or features would then be oriented "above" the other elements or features. Likewise, if devices are turned over, elements described as "above" other elements or features would then be oriented "below" the other elements or features.

[0101] In this document, the terms“substantially,”“approximately,”“near- ly,”“about,” and other similar terms are used as terms of approximation and not as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. Considering, for example, process variations, measurement difficulties, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system),“about” or“approximately,” as used herein includes the stated value and means a range of values determined to be acceptable by one of ordinary skill in the art to the particular value. For example,“about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0102] It should be noted that, in this document, the expression“same layer” refers to a layer structure formed by using a same film forming process to form a film layer for forming a specific pattern, and then patterning the film layer by a one-time patterning process using a same mask plate. Depending on the specific pattern, the one-time patterning process can include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, the multiple elements, components, structures and / or parts located in the“same layer” are composed of the same material and are formed by the same one-time patterning process, and generally, the multiple elements, components, structures and / or parts located in the“same layer” have substantially the same thickness.

[0103] It should be understood by those skilled in the art that, in this document, unless otherwise specified, the expression“height” or“thickness” refers to the dimension along the surface of each film layer disposed perpendicularly to the display substrate, i.e., the dimension along the light-out direction of the display substrate, or the dimension along the normal direction of the display device.

[0104] In this document, the expression“transistor” can be a triode, a thin film transistor or a field effect transistor or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the control pole, one of the poles is referred to as the first pole and the other pole is referred to as the second pole. In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be the drain and the second pole can be the source, or the first pole can be the source and the second pole can be the drain.

[0105] FIG. 1 schematically shows a plan view of a display substrate according to some embodiments of the present disclosure. FIG. 2A schematically shows a cross-sectional view of the display substrate taken along AA’ in FIG. 1 according to some embodiments of the present disclosure. FIG. 3 schematically shows an enlarged view of a light emitting device and a first bonding pad in the display substrate according to some embodiments of the present disclosure.

[0106] With reference to FIGS. 1, 2A and 3, the display substrate includes a substrate 100, a driving circuit layer 200 and a light emitting device layer 300. The driving circuit layer 200 is located on the substrate 100, and the light emitting device layer 300 is located on a side of the driving circuit layer 200 away from the substrate 100 and is electrically connected to the driving circuit layer 200.

[0107] The light emitting device layer 300 includes a plurality of light emitting devices 310 arranged in an array along a first direction X and a second direction Y. The light emitting device 310 includes a first electrode 311 located on the driving circuit layer 200, a light emitting functional part 312 located on a side of the first electrode 311 away from the substrate 100, and a second electrode 313 located on a side of the light emitting functional part 312 away from the substrate 100. The light emitting device layer 300 includes at least one light emitting unit 300G, and the light emitting unit 300G includes at least two light emitting devices 310. The light emitting devices 310 in the light emitting unit 300G are connected in series.

[0108] The light emitting device 310 is configured to emit light from the side of the second electrode 313, i.e., the light emitting device 310 is a vertical emission type light emitting device. The substrate 100 has a first surface 100a facing the light emitting device layer 300. The light emitting functional part 312 includes a first light emitting surface 312m close to the first surface 100a and a second light emitting surface 312n away from the first surface 100a. The first light emitting surface 312m is located on the second light emitting surface 312n in a projection on the substrate 100, and the area of the first light emitting surface 312n is smaller than the area of the second light emitting surface 312m.

[0109] In the display substrate of the embodiments of the present disclosure, two light emitting devices 310 are connected in series as one light emitting unit 300G, so that high voltage driving of the light emitting device 310 can be achieved, which is beneficial to reduce the power consumption of the display substrate. On the other hand, the second electrode 313 of the light emitting device 310 is located on a side of the first electrode 311 away from the substrate 100, i.e., the light emitting device 310 is a vertical type light emitting device. Compared with a flip chip type light emitting device, the light emitting area of the light emitting device 310 can be significantly improved. In addition, by designing the structure of the light emitting functional part 312, the first light emitting surface 312m is located on the second light emitting surface 312n in a projection on the substrate 100, and the area of the first light emitting surface 312n is smaller than the area of the second light emitting surface 312m, which can further improve the light emitting area and light emitting efficiency of the light emitting device 310.

[0110] According to some exemplary embodiments, the shape of the light-emitting functional part 312 perpendicular to the cross section of the first surface 100a is an inverted trapezoid, that is, along the light-emitting direction of the light-emitting device 310 (i.e., the direction in which the light-emitting device 310 is away from the first surface 100a), the area of the light-emitting functional part 312 parallel to the first surface 100a successively increases, which is conducive to achieving a higher light-emitting efficiency.

[0111] According to some exemplary embodiments, the light-emitting functional part 312 has a first side surface 312a intersecting the first surface 100a of the substrate substrate 100, and the angle β between the first side surface 312a of the light-emitting functional part 312 and the first surface 100a of the substrate substrate 100 is 50°-70°. For example, the angle β between the first side surface 312a of the light-emitting functional part 312 and the first surface 100a of the substrate substrate 100 is 55°, 60°, or 65°, etc. The inventors have found that when the angle β between the first side surface 312a of the light-emitting functional part 312 and the first surface 100a of the substrate substrate 100 is within the range of 50°-70°, the light-emitting device 310 can have a larger light-emitting efficiency and a larger light-emitting area.

[0112] For example, the light-emitting device 310 can be a micro light-emitting diode (Micro LED), and the light-emitting functional part 312 includes a first semiconductor part 3121 on the first electrode 311, a light-emitting part 3122 on the side of the first semiconductor part 3121 away from the first electrode 311, and a second semiconductor part 3123 on the side of the light-emitting part 3122 away from the substrate substrate 100.

[0113] For example, one of the first semiconductor part 3121 and the second semiconductor part 3123 is an N-type semiconductor part, and the other is a P-type semiconductor part. The material of the N-type semiconductor part can include N-type gallium nitride, and the material of the P-type semiconductor part can include P-type gallium nitride.

[0114] For example, the first semiconductor part 3121 includes N-type gallium nitride, and the second semiconductor part 3123 includes P-type gallium nitride.

[0115] For example, the light-emitting part 3123 can include a multiple quantum well (MQW) structure, which can be a periodic structure in which gallium nitride (GaN) and indium gallium nitride (InGaN) are alternately arranged, but is not limited thereto.

[0116] According to some exemplary embodiments, referring to FIG. 1, the size of the light-emitting device 310 along the first direction X and the second direction Y is 5-100 μm, and in order to meet the demand for high resolution, the size of the light-emitting device 310 can be 5-20 μm, for example, 15 μm.

[0117] According to some exemplary embodiments, in combination with reference to FIGS. 2A and 3, the first electrode 311 is provided with a first bonding pad PAD1 close to one side of the driving circuit layer 200, the driving circuit layer 200 is provided with a second bonding pad PAD2 close to one side of the first electrode 311, the first bonding pad PAD1 is electrically connected with the second bonding pad PAD2, the light emitting device 310 is electrically connected with the driving circuit layer 200 through the first bonding pad PAD1 and the second bonding pad PAD2, considering the fluctuation of the bonding alignment accuracy, in order to improve the bonding yield, the second bonding pad PAD2 can be set to be slightly larger than the first bonding pad PAD1, that is, the orthographic projection of the first bonding pad PAD1 on the substrate substrate 100 is located within the orthographic projection of the second bonding pad PAD2 on the substrate substrate 100. For example, the bonding alignment accuracy is 1-5 μm, and the edge of the second bonding pad PAD2 protrudes from the edge of the first bonding pad PAD1 by a distance of 1-5 μm.

[0118] FIG. 4 schematically shows a cross-sectional view of a driving circuit layer of a display substrate according to some embodiments of the present disclosure.

[0119] According to some example embodiments, referring to FIG. 4, the driving circuit layer 200 includes a barrier layer BAR on the substrate 100, a first buffer layer BUF1 on a side of the barrier layer BAR distal from the substrate 100, a first active layer ACT1 on a side of the buffer layer distal from the substrate 100, a first gate insulating layer GI1 on a side of the first active layer ACT1 distal from the substrate 100, a first gate metal layer Gate1 on a side of the first gate insulating layer GI1 distal from the substrate 100, a second gate insulating layer GI2 on a side of the first gate metal layer Gate1 distal from the substrate 100, a second gate metal layer Gate2 on a side of the second gate insulating layer GI2 distal from the substrate 100, a first interlayer dielectric ILD1 on a side of the second gate metal layer Gate2 distal from the substrate 100, a second buffer layer BUF2 on a side of the first interlayer dielectric ILD1 distal from the substrate 100, a second active layer ACT2 on a side of the second buffer layer BUF2 distal from the substrate 100, a third gate insulating layer GI3 on a side of the second active layer ACT2 distal from the substrate 100, a third gate metal layer Gate3 on a side of the third gate insulating layer GI3 distal from the substrate 100, a second interlayer dielectric ILD2 on a side of the third gate metal layer Gate3 distal from the substrate 100, a first source-drain metal layer SD1 on a side of the second interlayer dielectric ILD2 distal from the substrate 100, a fourth planarization layer PLN4 on a side of the first source-drain metal layer SD1 distal from the substrate 100, a fourth passivation layer PV4 on a side of the fourth planarization layer PLN4 distal from the substrate 100, a second source-drain metal layer SD2 on a side of the fourth passivation layer PV4 distal from the substrate 100, a fifth planarization layer PLN5 on a side of the second source-drain metal layer SD2 distal from the substrate 100, a fifth passivation layer PV5 on a side of the fifth planarization layer PLN5 distal from the substrate 100, a third source-drain metal layer SD3 on a side of the fifth passivation layer PV5 distal from the substrate 100, a sixth planarization layer PLN6 on a side of the third source-drain metal layer SD3 distal from the substrate 100, and a sixth passivation layer PV6 on a side of the sixth planarization layer PLN6 distal from the substrate 100.

[0120] In some embodiments, the material of the first active layer ACT1 can include low-temperature polysilicon, and the material of the second active layer ACT2 can include metal-oxide semiconductor material.

[0121] According to some example embodiments, referring to FIG. 4, the display substrate further includes a bonding layer BL on a side of the sixth passivation layer PV6 distal from the substrate 100, the bonding layer BL including a plurality of second bonding pads PAD2, the second bonding pads PAD2 electrically connected with the third source-drain metal layer SD3 through fifth vias V5 in the sixth planarization layer PLN6 and the sixth passivation layer PV6.

[0122] According to some exemplary embodiments, in combination with reference to FIG. 2A and FIG. 3, the light emitting unit 300G further comprises at least one bridge 610, in two adjacent and electrically connected light emitting devices 310, the first electrode 311 of one light emitting device 310 is electrically connected to the second electrode 313 of the other light emitting device 310 through the bridge 610, so as to realize the series connection of each light emitting device 310 in the light emitting unit 300G.

[0123] According to some exemplary embodiments, in combination with reference to FIG. 2A and FIG. 3, the display substrate further comprises a first passivation layer PV1, the first passivation layer PV1 is located between the first electrode 311 and the light emitting functional part 312, the first passivation layer PV1 extends from the first side surface 312a of the light emitting functional part 312 to the plane of the light emitting functional part 312 facing the substrate substrate 100, the first passivation layer PV1 has a first via V1, the first via V1 exposes a part of the plane of the light emitting functional part 312 facing the substrate substrate 100, and the first electrode 311 is connected to the light emitting functional part 312 through the first via V1.

[0124] The orthographic projection of the first via V1 on the substrate substrate 100 is within the orthographic projection of the first electrode 311 on the substrate substrate 100, the orthographic projection of the first electrode 311 on the substrate substrate 100 covers the orthographic projection of the first via V1 on the substrate substrate 100, and the orthographic projection of the first electrode 311 on the substrate substrate 100 partially coincides with the orthographic projection of the first passivation layer PV1 on the substrate substrate 100. Therefore, the first passivation layer PV1 has a step between the plane close to the substrate substrate 100 and the surface of the first electrode 311 exposed by the first via V1, and further makes the first electrode 311 have a first groove G1 on the side facing the substrate substrate 100, which is recessed away from the substrate substrate 100.

[0125] In order to ensure the flatness of the first bonding pad PAD1, the first bonding pad PAD1 is arranged in the first groove G1 of the first electrode 311, and the orthographic projection of the first bonding pad PAD1 on the substrate substrate 100 is within the orthographic projection of the groove bottom of the first groove G1 away from the substrate substrate 100 on the substrate substrate 100. By this arrangement, the first bonding pad PAD1 can have a flat surface on the side close to the substrate substrate 100, so as to effectively improve the bonding yield between the first bonding pad PAD1 and the second bonding pad PAD2.

[0126] FIG. 5 schematically shows an enlarged view of a light emitting device and a first bonding pad in a display substrate according to some embodiments of the present disclosure.

[0127] According to some exemplary embodiments, referring to FIG. 2A and FIG. 5, the display substrate further comprises a reflection part REF covering at least part of the first side surface 312a of the light emitting functional part 312. The reflection part REF is configured to reflect the light generated in the light emitting functional part 312 so that the light is only emitted from the side of the second electrode 313 of the light emitting device 310, which on one hand can improve the light emitting efficiency of the light emitting device 310, and on the other hand can effectively improve the crosstalk problem between adjacent light emitting devices 310.

[0128] According to some exemplary embodiments, referring to FIG. 5, the reflection part REF is located on the side of the first passivation layer PV1 away from the light emitting functional part 312, and the reflection part REF and the first electrode 311 are located in the same layer. That is, the reflection part REF and the first electrode 311 are formed by the same film forming process and patterning process, which can simplify the preparation process of the display substrate and reduce the manufacturing cost of the display substrate.

[0129] According to some exemplary embodiments, the reflection part REF and the first electrode 311 can comprise a metal material with high reflectivity, for example, the reflection part REF and the first electrode 311 have a titanium / aluminum / titanium stacked structure.

[0130] According to some exemplary embodiments, referring to FIG. 2A and FIG. 5, the reflection part REF and the first electrode 311 are connected as an integral structure, and the orthographic projection of the reflection part REF and the first electrode 311 on the substrate 100 covers the orthographic projection of the light emitting functional part 312 on the substrate 100. The reflection part REF and the first electrode 311 connected as an integral structure completely cover the first side surface 312a of the light emitting functional part 312 and the plane close to the substrate 100, which can further improve the light emitting efficiency of the light emitting device 310.

[0131] According to some exemplary embodiments, referring to FIG. 2A and FIG. 3, the driving circuit layer 200 further comprises a connection terminal 400 located on the side of the second bonding pad PAD2 close to the substrate 100, and the connection terminal 400 is electrically connected to the first electrode 311 of the light emitting device 310 through the second bonding pad PAD2 and the first bonding pad PAD1. In two adjacent and electrically connected light emitting devices 310, the connection terminal 400 electrically connected to one light emitting device 310 has an extension part 410, at least part of the orthographic projection of the extension part 410 on the substrate 100 does not overlap with the orthographic projection of the second bonding pad PAD2 on the substrate 100, and the part of the extension part 410 protruding compared to the second bonding pad PAD2 is electrically connected to the second electrode 313 of the other light emitting device 310 through the bridge part 610.

[0132] According to some exemplary embodiments, referring to FIG. 2A and FIG. 4 in conjunction, the connection terminal 400 is located in the third source-drain metal layer SD3, the sixth passivation layer PV6 and the sixth planarization layer PLN6 has the fifth via V5, the second bonding pad PAD2 is electrically connected with the connection terminal 400 through the fifth via V5.

[0133] According to some exemplary embodiments, referring to FIG. 2A and FIG. 3 in conjunction, the display substrate further comprises a first planarization layer PLN1, the first planarization layer PLN1 is located on the side of the light emitting device layer 300 away from the substrate 100, the first planarization layer PLN1 comprises a plurality of planarization portions 500, the planarization portions 500 cover the side surfaces of the light emitting device 310, the first bonding pad PAD1 and the second bonding pad PAD2, the planarization portions 500 have a first opening K1, the first opening K1 exposes at least a part of the second electrode 313 of the light emitting device 310. The bridge portion 610 is located on the side of the first planarization layer PLN1 away from the substrate 100, one end of the bridge portion 610 is electrically connected with the second electrode 313 of one light emitting device 310 through the first opening K1, the other end of the bridge portion 610 extends along the surface of the planarization layer and is electrically connected with the first electrode 311 of the adjacent light emitting device 310 through the connection terminal 400.

[0134] The orthographic projection of the first bonding pad PAD1 on the substrate 100 is within the orthographic projection of the second bonding pad PAD2 on the substrate 100, and the orthographic projection of the first bonding pad PAD1 on the substrate 100 is within the orthographic projection of the light emitting device 310 on the substrate 100, that is, the edge of the first bonding pad PAD1 is recessed inward compared with the edge of the light emitting device 310 and the edge of the second bonding pad PAD2, by arranging the planarization portions 500 at the side surfaces of the light emitting device 310, the first bonding pad PAD1 and the second bonding pad PAD2, the planarization portions 500 fill the step at the side surfaces of the light emitting device 310, the first bonding pad PAD1 and the second bonding pad PAD2, and further arranging the bridge portion 610 on the side of the planarization portions 500 away from the substrate 100, the bridge portion 610 extends along the surface of the planarization portions 500, thereby realizing the series connection of the two adjacent light emitting devices 310, and such arrangement can greatly reduce the risk of disconnection of the bridge portion 610 and thus causing display defects.

[0135] According to some exemplary embodiments, referring to FIG. 2A, the outer side edge of the projection of the planarization portion 500 on the substrate 100 encircles the edge of the projection of the light emitting device 310 on the substrate 100, the outer side edge of the projection of the planarization portion 500 on the substrate 100 encircles the edge of the projection of the first bonding pad PAD1 on the substrate 100, and the outer side edge of the projection of the planarization portion 500 on the substrate 100 encircles the edge of the projection of the second bonding pad PAD2 on the substrate 100. That is, the planarization portion 500 completely covers the side surface of the light emitting device 310, the side surface of the first bonding pad PAD1, and the side surface of the second bonding pad PAD2.

[0136] According to some exemplary embodiments, the distance between the edge of the projection of the planarization portion 500 on the substrate 100 and the edge of the projection of the light emitting device 310 on the substrate 100 is greater than or equal to 5 μm, so as to avoid the problem that the planarization portion 500 cannot completely cover the light emitting device 310, the first bonding pad PAD1, and the second bonding pad PAD2 due to the bonding process fluctuation of the first bonding pad PAD1 and the second bonding pad PAD2. Of course, the size of the distance is set according to the bonding process precision, and when the bonding precision is reduced to ±1 μm, the distance is greater than or equal to 3 μm.

[0137] According to some exemplary embodiments, the planarization portion 500 is farther away from the plane of the substrate 100 than the light emitting device 310. For example, the thickness of the planarization portion 500 is 6-8 μm.

[0138] According to some exemplary embodiments, the included angle γ1 between the side surface of the planarization portion 500 at the first opening K1 and the surface of the light emitting device 310 exposed by the first opening K1 is an obtuse angle. In this way, the problem that the bridge portion 610 is disconnected at the corner extending from the plane of the light emitting device 310 away from the substrate 100 to the side surface of the planarization portion 500 at the first opening K1 can be effectively avoided.

[0139] According to some exemplary embodiments, the included angle γ2 between the side surface of the planarization portion 500 surrounding the light emitting device 310 and the plane of the planarization portion 500 close to the substrate 100 is an acute angle. In this way, the problem that the bridge portion 610 is disconnected at the corner extending from the side surface of the planarization portion 500 surrounding the light emitting device 310 to the plane of the driving circuit layer 200 away from the substrate 100 can be effectively avoided.

[0140] According to some exemplary embodiments, referring to FIG. 2A, the display substrate further comprises a packaging layer TFE between the first planarization layer PLN1 and the light emitting device layer 300. The packaging layer TFE, the sixth passivation layer PV6 and the sixth planarization layer PLN6 have a sixth via V6, and the bridge portion 610 is electrically connected to the epitaxial portion 410 of the connection terminal 400 through the sixth via V6. The packaging layer TFE and the planarization portion 500 have a first opening K1, and the first opening K1 exposes at least a portion of the light emitting device 310.

[0141] According to some exemplary embodiments, the packaging layer TFE comprises a first packaging layer away from the substrate 100 and a second packaging layer away from the substrate 100 on a side of the first packaging layer. The first packaging layer is formed by an atomic layer deposition process, and the second packaging layer is formed by a chemical vapor deposition process. The first packaging layer formed by the atomic layer deposition process has good step coverage and conformality, so that the packaging layer TFE can completely cover the side surface of the light emitting device 310, the side surface of the first bonding pad PAD1 and the side surface of the second bonding pad PAD2, that is, the packaging layer TFE extends from the plane of the light emitting device 310 away from the substrate 100, along the side surface of the light emitting device 310, the plane of the light emitting device 310 close to the substrate 100, the side surface of the first bonding pad PAD1, the plane of the second bonding pad PAD2 away from the substrate 100, the side surface of the second bonding pad PAD2, and continuously extends to the plane of the driving circuit layer 200 away from the substrate 100. In this way, the packaging reliability can be effectively improved.

[0142] According to some exemplary embodiments, referring to FIG. 2A, the display substrate further comprises a light blocking portion BANK, and a projection of the light blocking portion BANK on the substrate 100 is located between the projections of two adjacent first openings K1 on the substrate 100. The plane of the light blocking portion BANK away from the substrate 100 is farther away from the substrate 100 than the plane of the light emitting device 310 away from the substrate 100, the light emitting device 310 is configured to emit third color light, and the light blocking portion BANK is configured to absorb the third color light. By providing the light blocking portion BANK, the crosstalk problem of adjacent light emitting devices 310 can be effectively improved.

[0143] According to some exemplary embodiments, the light blocking portion BANK is configured to reflect the third color light, which can further improve the light emitting efficiency of the light emitting device 310 while improving the crosstalk problem of adjacent light emitting devices 310

[0144] According to some exemplary embodiments, referring to FIG. 2A, the light blocking part BANK is arranged apart from the adjacent light emitting device 310, and the side surface of the light blocking part BANK and the plane of the light blocking part BANK close to the substrate 100 form an acute angle. For example, the distance between the orthographic projection of the light blocking part BANK on the substrate 100 and the orthographic projection of the adjacent light emitting device 310 on the substrate 100 is 0-5 μm, and the angle between the side surface of the light blocking part BANK and the plane of the light blocking part BANK close to the substrate 100 is 40-70°. By comprehensively setting the distance between the light blocking part BANK and the adjacent light emitting device 310 and the angle between the side surface of the light blocking part BANK and the plane of the light blocking part BANK close to the substrate 100, the light emitting efficiency of the light emitting device 310 can be improved.

[0145] According to some exemplary embodiments, referring to FIG. 2A, the light blocking part BANK is located between two adjacent planarization parts 500, and the light blocking part BANK is located on the side of the bridge part 610 away from the substrate 100. The plane of the light blocking part BANK close to the substrate 100 is closer to the substrate 100 than the plane of the light emitting device 310 close to the substrate 100. That is, one end of the light blocking part BANK is located on the side of the light emitting device 310 close to the substrate 100, and the other end of the light blocking part BANK is located on the side of the light emitting device 310 away from the substrate 100, so that the light blocking part BANK can achieve better effects of improving crosstalk and improving light emitting efficiency.

[0146] According to some exemplary embodiments, referring to FIG. 2A, the display substrate further comprises a color conversion layer 700, and the color conversion layer 700 comprises a color conversion part 710, the color conversion part 710 is located between two adjacent light blocking parts BANK, and the color conversion part 710 covers the light emitting device 310. The light blocking part BANK is arranged apart from the adjacent planarization part 500, and a part of the color conversion part 710 is located at the gap between the planarization part 500 and the light blocking part BANK, that is, is arranged around the side surface of the light emitting device 310. That is, the color conversion part 710 covers the light emitting side of the light emitting device 310 and the circumferential side of the light emitting device 310, and such arrangement can effectively improve the color conversion efficiency of the color conversion part 710.

[0147] FIG. 2B schematically shows a cross-sectional view of the display substrate taken along BB' in FIG. 1 according to some embodiments of the present disclosure. FIG. 2C schematically shows a cross-sectional view of the display substrate taken along CC' in FIG. 1 according to some embodiments of the present disclosure.

[0148] According to some exemplary embodiments, in combination with reference to FIG. 1, FIG. 2A and FIG. 2B, the light emitting unit 300G includes a first light emitting unit 301G, a second light emitting unit 302G and a third light emitting unit 303G. The color conversion part 710 includes a first color conversion part 711 and a second color conversion part 712, the first color conversion part 711 is at least partially overlapped with the first light emitting unit 301G in the orthographic projection on the substrate 100, the first color conversion part 711 is used for converting the third color light into the first color light, the second color conversion part 712 is at least partially overlapped with the second light emitting unit 302G in the orthographic projection on the substrate 100, the second color conversion part 712 is used for converting the third color light into the second color light. Thus, the color display of the display substrate is realized.

[0149] According to some exemplary embodiments, in combination with reference to FIG. 1 and FIG. 2C, the color conversion layer 700 further includes a light transmission part 730, the light transmission part 730 is located between two adjacent light blocking parts BANK, the light transmission part 730 is at least partially overlapped with the first light emitting unit 301G in the orthographic projection on the substrate 100, the light transmission part 730 is used for transmitting the third color light.

[0150] According to some exemplary embodiments, in combination with reference to FIG. 1 and FIG. 2C, the light transmission part 730 is further doped with scattering particles, the light transmission part 730 can improve the light type of the light emitting device 310 of the first light emitting unit 301G, and improve the light emitting efficiency.

[0151] According to some exemplary embodiments, the first color is red, the second color is green, and the third color is blue.

[0152] According to some exemplary embodiments, the color conversion layer 700 is further provided with an inorganic barrier layer away from the substrate 100 and close to the substrate 100, which is used for isolating the color conversion layer 700 from other film layers. The material of the inorganic barrier layer includes silicon nitride or silicon carbon nitride.

[0153] According to some exemplary embodiments, the material of the first color conversion part 711 includes quantum dot material or fluorescent material for converting the third color light into the first color light. The material of the second color conversion part 712 includes quantum dot material or fluorescent material for converting the third color light into the second color light.

[0154] According to some exemplary embodiments, referring to FIGS. 2A, 2B and 2C, the display substrate further comprises a color filter layer CF located on the side of the color conversion layer 700 away from the substrate 100, the color filter layer CF comprising a first color filter part CF1, a second color filter part CF2 and a third color filter part CF3. The first color filter part CF1 is located on the side of the first color conversion part 711 away from the substrate 100, the second color filter part CF2 is located on the side of the second color conversion part 712 away from the substrate 100, and the third color filter part CF3 is located on the side of the light-transmissive part 730 away from the substrate 100.

[0155] According to some exemplary embodiments, referring to FIGS. 2A, 2B and 2C, the display substrate further comprises a black matrix layer BM filling the interval regions in the color filter layer CF.

[0156] According to some exemplary embodiments, referring to FIG. 2A, the display substrate further comprises an organic protective layer OC located on the side of the black matrix layer BM and the color filter layer CF away from the substrate 100.

[0157] FIG. 2D schematically shows a cross-sectional view of the display substrate taken along AA’ in FIG. 1 according to some embodiments of the present disclosure.

[0158] According to some exemplary embodiments, referring to FIG. 2D, the light-blocking part BANK completely fills the interval regions between adjacent planarization parts 500, the orthogonal projection of the light-blocking part BANK on the substrate 100 overlaps with the orthogonal projection of the planarization part 500 on the substrate 100, and the orthogonal projection of the light-blocking part BANK on the substrate 100 is spaced apart from the orthogonal projection of the first opening K1 on the substrate 100. The color conversion part 710 is located between adjacent light-blocking parts BANK, and the color conversion part 710 is located on the side of the light-emitting device 310 away from the substrate 100.

[0159] FIG. 6 schematically shows a cross-sectional view of the display substrate taken along AA’ in FIG. 1 according to some embodiments of the present disclosure.

[0160] According to some exemplary embodiments, referring to FIG. 6, the display substrate further comprises a second planarization layer PLN2 located on the side of the first planarization layer PLN1 away from the substrate 100, and the light-blocking part BANK is located on the side of the second planarization layer PLN2 away from the substrate 100. The plane of the light-blocking part BANK close to the substrate 100 is farther away from the substrate 100 than the plane of the light-emitting device 310 close to the substrate 100. In this way, the thickness of the light-blocking part BANK can be reduced, thereby reducing the process difficulty of forming the light-blocking part BANK.

[0161] FIG. 7 schematically shows a cross-sectional view of the display substrate taken along NN’ in FIG. 1 according to some embodiments of the present disclosure.

[0162] According to some exemplary embodiments, referring to FIG. 7, the display substrate further comprises a second passivation layer PV2, the second passivation layer PV2 is located between the first electrode 311 and the light-emitting functional part 312, the second passivation layer PV2 covers at least the first side surface 312a of the light-emitting functional part 312, the second passivation layer PV2 has a first via V1, the first via V1 exposes a part of the plane of the light-emitting functional part 312 facing the substrate 100, and the first electrode 311 is connected with the light-emitting functional part 312 through the first via V1.

[0163] The bridge part 610 comprises a first bridge part 611 and a second bridge part 612, the first bridge part 611 is located on the side of the second passivation layer PV2 close to the substrate 100, the first bridge part 611 is electrically connected with the adjacent first electrode 311, and the second bridge part 612 is located on the side of the second passivation layer PV2 away from the substrate 100, the second bridge part 612 is electrically connected with the adjacent second electrode 313. The second passivation layer PV2 also has a second via V2, one end of the first bridge part 611 is electrically connected with the adjacent first electrode 311, and the other end extends along the surface of the second passivation layer PV2 until it is electrically connected with the second bridge part 612 through the second via V2. In the two adjacent light-emitting devices 310, the first electrode 311 of one light-emitting device 310 is electrically connected with the second electrode 313 of the other light-emitting device 310 through the first bridge part 611 and the second bridge part 612.

[0164] According to some exemplary embodiments, referring to FIG. 7, the second passivation layer PV2 has a plurality of first passivation parts PV21 and a plurality of second passivation parts PV22, the first passivation part PV21 covers the first side surface 312a of the light-emitting functional part 312, the side surface of the second electrode 313, and a part of the plane of the light-emitting functional part 312 close to the substrate 100, and the first via V1 is located in the first passivation part PV21. The second passivation part PV22 is connected between the two adjacent first passivation parts PV21 away from the substrate 100, and the second via V2 is located in the second passivation part PV22. The second passivation part PV22 also has a protruding part PV221 protruding away from the substrate 100, which separates the two adjacent second bridge parts 612. The plane of the protruding part PV221 away from the substrate 100 is substantially flush with the plane of the second bridge part 612 away from the substrate 100.

[0165] According to some exemplary embodiments, referring to FIG. 7, the first bridge part 611 and the first electrode 311 are located in the same layer, and the first bridge part 611 and the adjacent first electrode 311 are connected as an integral structure. The first bridge part 611 and the first electrode 311 are formed by the same film-forming process and patterning process, which can simplify the preparation process of the display substrate and reduce the manufacturing cost of the display substrate.

[0166] According to some exemplary embodiments, referring to FIG. 7, the material of the second bridge 612 comprises a transparent conductive material, the orthogonal projection of the second bridge 612 on the substrate 100 covers the orthogonal projection of the second electrode 313 on the substrate 100. A portion of the second bridge 612 is electrically connected to the second electrode 313 away from the surface of the substrate 100, and another portion of the second bridge 612 is electrically connected to the first bridge 611 through the second via V2 in the second passivation layer PV2.

[0167] Exemplarily, the material of the second bridge 612 comprises indium tin oxide.

[0168] FIG. 8 schematically shows a cross-sectional view of a display substrate taken along NN’ in FIG. 1 according to some embodiments of the present disclosure.

[0169] According to some exemplary embodiments, referring to FIG. 8, the material of the second bridge 612 comprises a metallic conductive material, the orthogonal projection of the second bridge 612 on the substrate 100 partially overlaps with the orthogonal projection of the second electrode 313 on the substrate 100, and the orthogonal projection of the second bridge 612 on the substrate 100 does not overlap with the orthogonal projection of the light emitting functional part 312 on the substrate 100. For example, the second bridge 612 has a second opening K2, the orthogonal projection of the second opening K2 on the substrate 100 substantially coincides with the orthogonal projection of the light emitting functional part 312 on the substrate 100.

[0170] Exemplarily, the material of the second bridge 612 comprises at least one of molybdenum, molybdenum alloy, copper and aluminum. For example, the second bridge 612 is a single-layer molybdenum film layer, a stacked film layer of molybdenum alloy / copper / molybdenum alloy, or a stacked film layer of molybdenum / aluminum / molybdenum. The thickness of the second bridge 612 can be 2000-9000 angstroms.

[0171] According to some exemplary embodiments, referring to FIG. 7, the display substrate further comprises a third passivation layer PV3 located on the side of the first electrode 311 close to the substrate 100, the third passivation layer PV3 has a plurality of third vias V3, the third vias V3 expose at least a portion of the first electrode 311, and the first bonding pad PAD1 is electrically connected to the first electrode 311 through the third vias V3.

[0172] FIG. 9 schematically shows a cross-sectional view of a display substrate taken along NN’ in FIG. 1 according to some embodiments of the present disclosure.

[0173] According to some exemplary embodiments, referring to FIG. 9, the display substrate further comprises a reflective layer REL between the light emitting device layer 300 and the driving circuit layer 200, the reflective layer REL covers at least part of the side surface of the light emitting device 310. The reflective layer REL is used to emit the light generated in the light emitting device 310, so that the light can be emitted from the side of the second electrode 313 of the light emitting device 310, thereby improving the light emitting efficiency of the light emitting device 310.

[0174] According to some exemplary embodiments, referring to FIG. 9, the display substrate further comprises a third passivation layer PV3 between the reflective layer REL and the first electrode 311, the third passivation layer PV3 comprises a plurality of third vias V3, the third vias V3 expose at least part of the first electrode 311. The reflective layer REL comprises a metal material, the reflective layer REL comprises a plurality of reflective portions REF arranged at intervals, the plurality of reflective portions REF are respectively electrically connected to the plurality of first electrodes 311 through the plurality of third vias V3.

[0175] According to some exemplary embodiments, referring to FIG. 9, the third passivation layer PV3 has a second groove G2 between the adjacent light emitting devices 310, the second groove G2 is recessed away from the substrate 100, the reflective portion REF extends along the groove wall of the second groove G2 from the side of the third passivation layer PV3 away from the light emitting device 310 until it contacts the groove bottom of the second groove G2, and the orthogonal projection of the reflective portion REF on the substrate 100 covers the orthogonal projection of the light emitting device 310 on the substrate 100.

[0176] According to some exemplary embodiments, referring to FIG. 9, the reflective layer REL further comprises an insulating protective layer PL on the side of the reflective layer REL close to the substrate 100, the insulating protective layer PL has a plurality of seventh vias V7, the seventh vias V7 expose at least part of the plane of the reflective portion REF close to the substrate 100, the first bonding pad PAD1 is on the side of the reflective layer REL close to the substrate 100, and the first bonding pad PAD1 is electrically connected to the reflective portion REF through the seventh vias V7, that is, the first bonding pad PAD1 is electrically connected to the first electrode 311 of the light emitting device 310 through the reflective portion REF.

[0177] According to some exemplary embodiments, the material of the reflective layer REL comprises a metal with high reflectivity, for example, the material of the reflective layer REL comprises at least one of silver and aluminum. For another example, the reflective layer REL is a stack film layer of indium tin oxide / silver / indium tin oxide, a stack film layer of titanium nitride / aluminum / titanium, or a stack film layer of titanium / aluminum / titanium.

[0178] FIG. 10 schematically shows a cross-sectional view of a display substrate taken along the NN’ in FIG. 1 according to some embodiments of the present disclosure.

[0179] According to some exemplary embodiments, referring to FIG. 10, the display substrate further comprises a third planarization layer PLN3 between the light emitting device layer 300 and the driving circuit layer 200, the third planarization layer PLN3 fills at least part of the spacing region between two adjacent light emitting devices 310. The planarization layer arranged between the adjacent light emitting devices 310 can improve the intensity of each light emitting device 310 arranged in spacing.

[0180] According to some exemplary embodiments, referring to FIG. 10, the third planarization layer PLN3 has a third passivation layer PV3 between the third planarization layer PLN3 and the first electrode 311, the third passivation layer PV3 has a second groove G2 between the adjacent light emitting devices 310, the second groove G2 is recessed away from the substrate 100, and the planarization layer completely fills the second groove G2.

[0181] According to some exemplary embodiments, referring to FIG. 10, the surface of the third planarization layer PLN3 close to the substrate 100 is closer to the substrate 100 than the surface of the light emitting device 310 close to the substrate 100. For example, the plane of the third planarization layer PLN3 close to the substrate 100 is closer to the substrate 100 than the surface of the third passivation layer PV3 close to the substrate 100. The third planarization layer PLN3 has a fourth via V4, the fourth via V4 of the third planarization layer PLN3 is in communication with the third via V3 of the third passivation layer PV3, the fourth via V4 and the third via V3 expose at least part of the first electrode 311, and the first bonding pad PAD1 is electrically connected to the first electrode 311 through the fourth via V4 and the third via V3.

[0182] According to some exemplary embodiments, referring to FIG. 10, the thickness of the third planarization layer PLN3 is 3-8 μm.

[0183] According to some exemplary embodiments, referring to FIG. 10, the light emitting device 310 is configured to emit light of a third color, and the third planarization layer PLN3 is configured to absorb or reflect light of the third color. By configuring the material or structure of the third planarization layer PLN3, the third planarization layer PLN3 can reflect or absorb the light emitted by the light emitting device 310, thereby improving the light emitting efficiency of the light emitting device 310 and improving the crosstalk between the adjacent light emitting devices 310.

[0184] FIG. 11 is an equivalent circuit diagram of one pixel circuit of a display substrate according to some exemplary embodiments of the present disclosure.

[0185] According to some exemplary embodiments, in combination with reference to FIG. 1 and FIG. 11, the driving circuit layer comprises a plurality of pixel circuits, the plurality of pixel circuits are electrically connected with a plurality of light emitting units, the light emitting unit comprises N light emitting devices, the pixel circuit comprises a pixel driving circuit and N-1 current control circuits, N is an integer greater than 1.

[0186] The pixel driving circuit is configured to generate a driving current and output the driving current through a driving current output terminal; a first electrode of the first light emitting device is electrically connected with the driving current output terminal; a second electrode of the nth light emitting device and a first electrode of the (n+1)th light emitting device are both electrically connected with an nth display node, and a second electrode of the Nth light emitting device is electrically connected with a first voltage terminal; n is a positive integer less than N; the nth current control circuit is electrically connected with the nth display node and configured to control the nth display node to provide an nth control current.

[0187] The pixel circuit of the embodiment of the present disclosure drives N light emitting devices in series through one pixel driving circuit, realizes that the driving transistor in the pixel driving circuit and the light emitting control transistor in the driving current path share, only one set of driving transistor has power consumption loss, so as to achieve the purpose of reducing power consumption.

[0188] In at least one embodiment of the present disclosure, N is equal to 4 is taken as an example for illustration, but is not limited thereto; in actual operation, N can be an integer greater than 1.

[0189] In at least one embodiment of the present disclosure, the light emitting device can be a Micro LED (micro light emitting diode), a Mini LED (mini light emitting diode), or an OLED (organic light emitting diode), the first electrode of the light emitting device can be an anode, and the second electrode of the light emitting device can be a cathode, but is not limited thereto.

[0190] Optionally, the first voltage terminal can be a first low voltage terminal, but is not limited thereto.

[0191] In at least one embodiment of the present disclosure, the light emitting device is a current driven device, and the required current for reaching the required brightness of the device is inputted to achieve the required brightness, and the pixel circuit of at least one embodiment of the present disclosure drives N light emitting devices through a driving transistor in a pixel driving circuit, so as to reduce power consumption.

[0192] For example, when the required brightness (L255) needs to be achieved, each light emitting device needs a driving current Id to achieve the required brightness, and only one driving transistor is needed to provide the driving current Id, compared with the power consumption of the related pixel driving circuit, the original power consumption can be reduced by 25%-50%, and the purpose of reducing the power consumption of the backplane is achieved.

[0193] Referring to FIG. 11, in some embodiments, the phase-connected pixel circuit and the light emitting unit can include a pixel driving circuit 10, a first light emitting device E1, a second light emitting device E2, a third light emitting device E3, a fourth light emitting device E4, a first current control circuit 11, a second current control circuit 12, and a third current control circuit 13.

[0194] The pixel driving circuit 10 is configured to generate a driving current and output the driving current through a driving current output terminal OT; a first electrode of the first light emitting device E1 is electrically connected to the driving current output terminal OT; a second electrode of the first light emitting device E1 and a first electrode of the second light emitting device E2 are both electrically connected to a first display node NX1; a second electrode of the second light emitting device E2 and a first electrode of the third light emitting device E3 are both electrically connected to a second display node NX2; a second electrode of the third light emitting device E3 and a first electrode of the fourth light emitting device E4 are both electrically connected to a third display node NX3; a second electrode of the fourth light emitting device E4 is electrically connected to a first voltage terminal V1; the first current control circuit 11 is electrically connected to the first display node NX1 and configured to control a first control current to be provided to the first display node NX1; the second current control circuit 12 is electrically connected to the second display node NX2 and configured to control a second control current to be provided to the second display node NX2; and the third current control circuit 13 is electrically connected to the third display node NX3 and configured to control a third control current to be provided to the third display node NX3.

[0195] In at least one embodiment of the present disclosure, the nth current control circuit includes an nth write control circuit, an nth energy storage circuit, an nth inverted energy storage circuit, an nth on-off control circuit, and an nth control circuit.

[0196] The nth write control circuit is electrically connected to an (n+1)th scan terminal, an (n+1)th inverted scan terminal, an nth control node, an nth inverted control node, an (n+1)th data line, and an (n+1)th inverted data line, respectively, and is configured to write a data voltage provided by the (n+1)th data line to the nth control node under control of an (n+1)th scan signal provided by the (n+1)th scan terminal, and write a data voltage provided by the (n+1)th inverted data line to the nth inverted control node under control of an (n+1)th inverted scan signal provided by the (n+1)th inverted scan terminal.

[0197] The nth energy storage circuit is electrically connected to the nth control node and configured to maintain a potential of the nth control node.

[0198] The nth inverted energy storage circuit is electrically connected to the nth inverted control node and configured to maintain a potential of the nth inverted control node.

[0199] The nth on-off control circuit is electrically connected with the nth control node, the nth inverse control node, the nth+1 power voltage terminal, the nth+1 low voltage terminal and the nth intermediate node, and is configured to control the nth+1 power voltage terminal and the nth intermediate node to be connected or disconnected under the control of the potential of the nth control node, and control the nth+1 low voltage terminal and the nth intermediate node to be connected or disconnected under the control of the potential of the nth inverse control node.

[0200] The nth control circuit is electrically connected with the nth+1 light-emitting control terminal, the nth intermediate node and the nth display node, and is configured to control the nth intermediate node and the nth display node to be connected or disconnected under the control of the nth+1 light-emitting control signal provided by the nth+1 light-emitting control terminal.

[0201] FIG. 12A schematically shows a flowchart of a preparation method of a display substrate according to an embodiment of the present disclosure.

[0202] According to some exemplary embodiments, the preparation method of the display substrate includes steps S10-S30.

[0203] In step S10, a substrate is provided.

[0204] In step S20, a driving circuit layer is formed on the substrate.

[0205] In step S30, a light-emitting device layer is formed on a side of the driving circuit layer away from the substrate, the light-emitting device layer including a plurality of light-emitting devices, each of the light-emitting devices including a first electrode, a light-emitting functional part on a side of the first electrode away from the substrate, and a second electrode on a side of the light-emitting functional part away from the substrate, the light-emitting device layer including at least one light-emitting unit, each of the light-emitting units including at least two light-emitting devices connected in series, wherein the light-emitting devices are configured to emit light from the side of the second electrode, the substrate has a first surface facing the light-emitting device layer, and a cross section of the light-emitting functional part perpendicular to the first surface has an inverted trapezoidal shape.

[0206] FIG. 12B schematically shows a flowchart of forming a light-emitting device layer in a preparation method of a display substrate according to an embodiment of the present disclosure.

[0207] According to some exemplary embodiments, forming the light-emitting device layer on the side of the driving circuit layer away from the substrate includes steps S310-S380.

[0208] In step S310, a light emitting diode epitaxial wafer is provided, the light emitting diode epitaxial wafer comprising an epitaxial substrate, a buffer layer on the epitaxial substrate, a first semiconductor layer on a side of the buffer layer distal to the epitaxial substrate, a light emitting layer on a side of the first semiconductor layer distal to the epitaxial substrate, a second semiconductor layer on a side of the light emitting layer distal to the epitaxial substrate, and a second electrode layer on a side of the second semiconductor layer distal to the epitaxial substrate.

[0209] In step S320, a carrier substrate is provided, a glue layer is formed on the carrier substrate, and at least one light emitting diode epitaxial wafer having a second electrode layer and a bridge layer formed thereon is attached to the carrier substrate.

[0210] In step S330, the epitaxial substrate and the buffer layer are removed.

[0211] In step S340, the first semiconductor layer, the light emitting layer, the second semiconductor layer, and the second electrode layer are patterned to form a plurality of second electrodes, a plurality of second semiconductor portions on a side of the plurality of second electrodes distal to the carrier substrate, a plurality of light emitting portions on a side of the plurality of second semiconductor portions distal to the carrier substrate, and a plurality of first semiconductor portions on a side of the plurality of light emitting portions distal to the carrier substrate.

[0212] In step S350, a first electrode is formed on a side of the first semiconductor portion distal to the carrier substrate, and a first bonding pad is formed on a side of the first electrode distal to the carrier substrate.

[0213] In step S360, a plurality of second bonding pads are formed on a side of a driving circuit layer distal to the substrate substrate, the driving circuit layer comprising connection terminals, the connection terminals being electrically connected to the second bonding pads, a portion of the connection terminals having epitaxial portions, at least a portion of a footprint of the epitaxial portions on the substrate substrate not overlapping a footprint of the second bonding pads on the substrate substrate, the driving circuit layer comprising sixth vias, the sixth vias exposing the epitaxial portions of the connection terminals.

[0214] In step S370, the first bonding pad on the carrier substrate is bonded to the second bonding pad on the substrate substrate, and the carrier substrate and the glue layer are removed.

[0215] In step S380, a bridge portion is formed on a side of the second electrode distal to the substrate substrate, one end of the bridge portion being electrically connected to the second electrode of one light emitting device, and the other end of the bridge portion being electrically connected to the epitaxial portion of the connection terminal of the adjacent other light emitting device through the sixth via. FIGS. 13A-13N schematically show a forming process of a display substrate according to some embodiments of the present disclosure.

[0216] Referring to FIG. 13A, a light emitting diode wafer is provided, which includes an epitaxial substrate SUB1, a buffer layer BUF on the epitaxial substrate SUB1, a first semiconductor layer SEL1 on the buffer layer BUF away from the epitaxial substrate SUB1, a light emitting layer LUM on the first semiconductor layer SEL1 away from the epitaxial substrate SUB1, a second semiconductor layer SEL2 on the light emitting layer LUM away from the epitaxial substrate SUB1, and a second electrode layer 313a on the second semiconductor layer SEL2 away from the epitaxial substrate SUB1.

[0217] For example, the second electrode layer 313a includes indium tin oxide, and has a thickness of 1000 angstroms.

[0218] For example, the step of forming the second electrode layer 313a includes forming an indium tin oxide thin film by a physical vapor deposition process, and performing a thermal annealing process on the deposited indium tin oxide thin film to form an ohmic contact between the second electrode layer 313a and the second semiconductor layer SEL2.

[0219] Referring to FIG. 13B, a carrier substrate SUB2 is provided, a separation adhesive layer AL1 is formed on the carrier substrate SUB2, a sticky adhesive layer AL2 is formed on the separation adhesive layer AL1 away from the carrier substrate SUB2, and at least one light emitting diode wafer having the second electrode layer 313a is attached to the carrier substrate SUB2, wherein the second electrode layer 313a is attached to the sticky adhesive layer AL2 of the carrier substrate SUB2. Then, the epitaxial substrate SUB1 and the buffer layer are removed to expose the first semiconductor layer SEL1.

[0220] For example, the epitaxial substrate SUB1 is removed by a chemical-mechanical planarization (CMP) process or a wet etching process, and the buffer layer is removed by a chemical-mechanical planarization process or a dry etching process.

[0221] For example, the epitaxial substrate SUB1 can be a silicon substrate or a sapphire substrate, the second semiconductor layer SEL2 includes P-type gallium nitride, the light emitting layer LUM includes a multi-quantum well, and the second semiconductor layer SEL2 includes N-type gallium nitride.

[0222] For example, referring to FIG. 13C, 12 light emitting diode wafers Wafer having the second electrode layer 313a are attached to the carrier substrate SUB2 in a manner of 3 rows x 4 columns.

[0223] Referring to FIGS. 13B and 13D, the first semiconductor layer SEL1, the light-emitting layer LUM, the second semiconductor layer SEL2, and the second electrode layer 313a are patterned to obtain a plurality of second electrodes 313, a plurality of second semiconductor portions 3123 on the side of the plurality of second electrodes 313 away from the carrier substrate SUB2, a plurality of light-emitting portions 3123 on the side of the plurality of second semiconductor portions 3123 away from the carrier substrate SUB2, and a plurality of first semiconductor portions 3121 on the side of the plurality of light-emitting portions 3123 away from the carrier substrate SUB2. The second electrode 313, the second semiconductor portion 3123, the light-emitting portion 3123, and the first semiconductor portion 3121 are sequentially stacked on the carrier substrate SUB2, and the side surfaces of the second electrode 313, the second semiconductor portion 3123, the light-emitting portion 3123, and the first semiconductor portion 3121 are smoothly connected, and the included angle between the side surfaces of the second electrode 313, the second semiconductor portion 3123, the light-emitting portion 3123, and the first semiconductor portion 3121 and the plane of the second electrode 313 close to the substrate 100 is an acute angle.

[0224] Referring to FIG. 13E, a first passivation layer PV1 is formed on the side of the first semiconductor portion 3121 away from the carrier substrate SUB2, and the first passivation layer PV1 has a first via V1 that exposes a portion of the first semiconductor portion 3121, and the orthographic projection of the first via V1 on the carrier substrate SUB2 is located within the orthographic projection of the first semiconductor portion 3121 on the carrier substrate SUB2.

[0225] For example, the material of the first passivation layer PV1 includes at least one of silicon oxide, silicon nitride, or titanium oxide, and the thickness of the first passivation layer PV1 is 0.2-1.0 μm.

[0226] Referring to FIG. 13F, a first electrode 311 is formed on the side of the first passivation layer PV1 away from the carrier substrate SUB2, and a first bonding pad PAD1 is formed on the side of the first electrode 311 away from the carrier substrate SUB2. The first electrode 311 is connected to the first semiconductor portion 3121 through the first via V1, and the first bonding pad PAD1 is formed on the side of the first electrode 311 away from the carrier substrate SUB2.

[0227] For example, the first electrode 311 is a laminated film layer of titanium nitride / aluminum / titanium or titanium / aluminum / titanium with a thickness of 50 / 1000 / 100 angstroms, and the first bonding pad PAD1 is a laminated film layer of molybdenum alloy / copper with a thickness of 50 / 1000 / 100 angstroms, and the molybdenum alloy can be a molybdenum-niobium alloy or a molybdenum-niobium-titanium alloy.

[0228] For example, the first electrode 311 and the first bonding pad PAD1 are formed by the same patterning process, the first bonding pad PAD1 is formed by a wet etching process, the first electrode 311 is formed by a dry etching process, and the edge of the first bonding pad PAD1 is recessed by about 2 μm relative to the edge of the first electrode 311.

[0229] Referring to FIG. 13G, a driving circuit layer 200 is formed on the substrate 100, the driving circuit layer 200 includes a third source-drain metal layer SD3, a sixth planarization layer PLN6 located on a side of the third source-drain metal layer SD3 away from the substrate 100, and a sixth passivation layer PV6 located on a side of the sixth planarization layer PLN6 away from the substrate 100, the sixth planarization layer PLN6 and the sixth passivation layer PV6 have a fifth via V5 therein, the third source-drain metal layer SD3 includes a connection terminal 400, and the fifth via V5 exposes at least a portion of the connection terminal 400. A bonding layer BL is further formed on the side of the sixth passivation layer PV6 away from the substrate 100, the bonding layer BL includes a plurality of second bonding pads PAD2, and the second bonding pads PAD2 are electrically connected to the connection terminal 400 through the fifth via V5. A portion of the connection terminal 400 has an extension portion 410, at least a portion of a projection of the extension portion 410 on the substrate 100 does not overlap with a projection of the second bonding pads PAD2 on the substrate 100, and an edge of the extension portion 410 protrudes compared with an edge of the second bonding pads PAD2.

[0230] For example, the second bonding pads PAD2 have a laminated film layer of copper / tin, and a thickness of the second bonding pads PAD2 is 1-5 μm.

[0231] With reference to FIGS. 13F, 13G and 13H, the submount SUB2 with the light emitting device 310 is bonded to the substrate 100 with the driving circuit layer 200 in a vacuum high-temperature bonding manner, and the first bonding pads PAD1 on the light emitting device 310 are bonded to the second bonding pads PAD2 on the driving circuit layer 200. Then, the submount SUB2, the dissociation adhesive layer AL1 and the adhesive layer AL2 are removed, so that the second electrode 313 of the light emitting device 310 is completely exposed.

[0232] For example, the submount SUB2 is removed by a laser dissociation process, and the dissociation adhesive layer AL1 and the adhesive layer AL2 are removed by an etching process.

[0233] With reference to FIGS. 13I and 13J, FIG. 13I schematically shows a cross-sectional view taken along DD’ in FIG. 13J. A packaging layer TFE is formed on a side of the second electrode of the light emitting device 310 away from the substrate 100, and a sixth via V6 is formed through the packaging layer TFE, the sixth passivation layer PV6 and the sixth planarization layer PLN6, and the sixth via V6 exposes the extension portion 410 of the connection terminal 400.

[0234] A first planarization layer PLN1 is formed on a side of the encapsulation layer TFE distal to the substrate 100, the first planarization layer PLN1 includes a plurality of planarization portions 500, the planarization portions 500 cover side surfaces of the light emitting devices 310, the first bonding pads PAD1 and the second bonding pads PAD2, and the planarization portions 500 have first openings K1, the first openings K1 expose at least a portion of the second electrodes of the light emitting devices 310.

[0235] A bridge portion 610 is formed on a side of the first planarization layer PLN1 distal to the substrate 100, one end of the bridge portion 610 is electrically connected to the second electrode of one of the light emitting devices 310 through the first opening K1, and the other end of the bridge portion 610 is electrically connected to the epitaxial portion 410 of the connection terminal 400 electrically connected to another adjacent one of the light emitting devices 310 through the sixth via V6.

[0236] For example, the encapsulation layer TFE includes a first encapsulation layer located on a side of the light emitting devices 310 distal to the substrate 100 and a second encapsulation layer located on a side of the first encapsulation layer distal to the substrate 100. The first encapsulation layer is formed by an atomic layer deposition process, and the second encapsulation layer is formed by a chemical vapor deposition process. The material of the encapsulation layer TFE includes at least one of silicon oxide, silicon nitride and silicon carbonitride, and the thickness of the encapsulation layer TFE is 0.5-2 μm.

[0237] For example, the material of the bridge portion 610 includes indium tin oxide or indium zinc oxide.

[0238] Referring to FIG. 13K and FIG. 13L in combination, FIG. 13K schematically illustrates a cross-sectional view taken along EE’ in FIG. 13L, a light blocking portion BANK is formed between adjacent light emitting devices 310, a projection of the light blocking portion BANK on the substrate 100 is located between projections of two adjacent first openings K1 on the substrate 100. A plane of the light blocking portion BANK distal to the substrate 100 is farther from the substrate 100 than a plane of the light emitting devices 310 distal to the substrate 100.

[0239] For example, the light blocking portion BANK is located between two adjacent planarization portions 500, a plurality of light blocking portions BANK are connected to each other to form a grid-shaped light blocking structure, the grid-shaped light blocking structure has a plurality of third openings K3, and a plurality of light emitting devices 310 are located in the plurality of third openings K3.

[0240] With reference to FIG. 13M and FIG. 13N, FIG. 13M schematically shows a cross-sectional view taken along FF’ in FIG. 13N, the color conversion layer 700 is formed in the third opening K3, the color conversion layer 700 includes the first color conversion part 711, the second color conversion part 712 and the light transmission part 730, the third opening K3 includes a first sub-opening K31, a second sub-opening K32 and a third sub-opening K33, the first color conversion part 711 is located in the first sub-opening K31, the second color conversion part 712 is located in the second sub-opening K32, and the light transmission part 730 is located in the third sub-opening K33.

[0241] The black matrix layer BM is formed on the side of the light blocking part BANK away from the substrate 100, the black matrix layer BM has an opening, and the color film layer CF is formed in the opening of the black matrix layer BM, the color film layer CF includes the first color film part CF1, the second color film part and the third color film part, the first color film part CF1 is located on the side of the first color conversion part 711 away from the substrate 100, the second color film part is located on the side of the second color conversion part away from the substrate 100, and the third color film part is located on the side of the light transmission part away from the substrate 100.

[0242] The organic protective layer OC is formed on the side of the black matrix layer BM and the color film layer CF away from the substrate 100, thereby obtaining the display substrate.

[0243] FIG. 12C schematically shows a flowchart of forming the light emitting device layer in the preparation method of the display substrate according to an embodiment of the present disclosure.

[0244] According to some exemplary embodiments, forming the light emitting device layer on the side of the driving circuit layer away from the substrate includes the following steps S310-S390.

[0245] In step S310, a light emitting diode epitaxial wafer is provided, the light emitting diode epitaxial wafer includes an epitaxial substrate, a buffer layer located on the epitaxial substrate, a first semiconductor layer located on the side of the buffer layer away from the epitaxial substrate, a light emitting layer located on the side of the first semiconductor layer away from the epitaxial substrate, a second semiconductor layer located on the side of the light emitting layer away from the epitaxial substrate, a second electrode layer formed on the side of the second semiconductor layer away from the epitaxial substrate, and a bridge layer formed on the side of the second electrode layer away from the epitaxial substrate.

[0246] In step S320, a carrier substrate is provided, a glue layer is formed on the carrier substrate, and at least one light emitting diode epitaxial wafer formed with the second electrode layer and the bridge layer is attached to the carrier substrate.

[0247] In step S330, the epitaxial substrate and the buffer layer are removed.

[0248] In step S340, the first semiconductor layer, the light emitting layer, the second semiconductor layer and the second electrode layer are patterned to form a plurality of second electrodes, a plurality of second semiconductor portions located on the side of the plurality of second electrodes away from the carrier substrate, a plurality of light emitting portions located on the side of the plurality of second semiconductor portions away from the carrier substrate, a plurality of first semiconductor portions located on the side of the plurality of light emitting portions away from the carrier substrate, and the bridge layer is patterned to form a plurality of second bridge portions arranged at intervals.

[0249] In step S350, a second passivation layer is formed on the side of the first semiconductor portion away from the carrier substrate, the second passivation layer has a first via and a second via, the first via exposes at least a portion of the first semiconductor portion, and the second via exposes at least a portion of the second bridge portion.

[0250] In step S360, a first electrode and a first bridge portion are formed on the side of the second passivation layer away from the carrier substrate, the first electrode is connected to the first semiconductor portion through the first via, and the first bridge portion is electrically connected to the second bridge portion through the second via.

[0251] In step S370, a first bonding pad is formed on the side of the first electrode away from the carrier substrate.

[0252] In step S380, a plurality of second bonding pads are formed on the side of the driving circuit layer away from the substrate substrate.

[0253] In step S390, the first bonding pad on the carrier substrate is bonded to the second bonding pad on the substrate substrate. FIGS. 14A-14Q schematically show a forming process of a display substrate according to some embodiments of the present disclosure.

[0254] Referring to FIG. 14A, a light emitting diode epitaxial wafer is provided, which includes an epitaxial substrate SUB1, a buffer layer BUF located on the epitaxial substrate SUB1, a first semiconductor layer SEL1 located on the side of the buffer layer BUF away from the epitaxial substrate SUB1, a light emitting layer LUM located on the side of the first semiconductor layer SEL1 away from the epitaxial substrate SUB1, a second semiconductor layer SEL2 located on the side of the light emitting layer LUM away from the epitaxial substrate SUB1, a second electrode layer 313a formed on the side of the second semiconductor layer SEL2 away from the epitaxial substrate SUB1, and a bridge layer 600 formed on the side of the second electrode layer 313a away from the epitaxial substrate SUB1.

[0255] Referring to FIG. 14B, a middle substrate SUB2 is provided, a glue layer is formed on the middle substrate SUB2, the glue layer includes a separation glue layer AL1 formed on the middle substrate SUB2 and a sticky glue layer AL2 formed on a side of the separation glue layer AL1 away from the middle substrate SUB2, and at least one light emitting diode epitaxial wafer formed with a second electrode layer 313a and a bridge layer 600 is attached to the middle substrate SUB2, wherein one side of the bridge layer 600 is attached to the sticky glue layer AL2 of the middle substrate SUB2.

[0256] For example, referring to FIG. 14C, 12 light emitting diode epitaxial wafers Wafer are attached to the middle substrate SUB2 in a manner of 3 rows x 4 columns.

[0257] For example, the thickness of the sticky glue layer AL2 is 2-5 μm, and the thickness of the separation glue layer AL1 is 1-2 μm.

[0258] Referring to FIG. 14D, the epitaxial substrate SUB1 and the buffer layer are removed so that the first semiconductor layer SEL1 is completely exposed.

[0259] For example, the epitaxial substrate SUB1 is first thinned by a mechanical grinding process so that the thickness of the epitaxial substrate SUB1 is reduced from 0.6 μm to 0.05-0.1 μm, and then the remaining epitaxial substrate SUB1 is thinned by a wet etching process until the epitaxial substrate SUB1 is completely removed. After the epitaxial substrate SUB1 is removed, the buffer layer is removed by a dry etching process so that the first semiconductor layer SEL1 is completely exposed.

[0260] Referring to FIG. 14E and FIG. 14F, wherein FIG. 14E schematically shows a cross-sectional view taken along GG' in FIG. 14F, the first semiconductor layer SEL1, the light emitting layer LUM, the second semiconductor layer SEL2 and the second electrode layer 313a are patterned to obtain a plurality of second electrodes 313, a plurality of second semiconductor portions 3123 located on a side of the plurality of second electrodes 313 away from the middle substrate SUB2, a plurality of light emitting portions 3123 located on a side of the plurality of second semiconductor portions 3123 away from the middle substrate SUB2, and a plurality of first semiconductor portions 3121 located on a side of the plurality of light emitting portions 3123 away from the middle substrate SUB2. The second electrode 313, the second semiconductor portion 3123, the light emitting portion 3123 and the first semiconductor portion 3121 connected in sequence constitute a light emitting device intermediate structure 310M.

[0261] For example, the orthographic projection of the light emitting device intermediate structure 310M on the middle substrate SUB2 is rectangular, circular or elliptical. The spacing between adjacent light emitting device intermediate structures 310M is 2-20 μm.

[0262] For example, when etching the first semiconductor layer SEL1, the light-emitting layer LUM, the second semiconductor layer SEL2 and the second electrode layer 313a, a certain etching loss may be caused to the underlying bridge layer 600. Therefore, the thickness of the bridge layer 600 can be set to be slightly thicker, and the thickness of the bridge layer 600 can be 2000-9000 angstroms.

[0263] With reference to FIGS. 14E, 14G and 14H, FIG. 14G schematically shows a cross-sectional view taken along HH' in FIG. 14H, the bridge layer 600 is patterned to form a plurality of spaced-apart second bridge portions 612, the orthographic projection of the second bridge portions 612 on the support substrate SUB2 covers the orthographic projection of the second electrode 313 on the support substrate SUB2, and the second bridge portions 612 protrude towards the adjacent other second bridge portions 612 compared to the second electrode 313.

[0264] With reference to FIGS. 14I and 14J, FIG. 14I schematically shows a cross-sectional view taken along II' in FIG. 14J, the second passivation layer PV2 is formed on the side of the first semiconductor portion 3121 away from the support substrate SUB2, and the second passivation layer PV2 has a first via V1 and a second via V2, the first via V1 exposes at least a portion of the first semiconductor portion 3121, and the second via V2 exposes at least a portion of the second bridge portion 612.

[0265] For example, the step of forming the second passivation layer PV2 can include forming a first silicon oxide film by an atomic layer deposition process, forming a second silicon oxide film by a chemical vapor deposition process, and finally patterning the deposited silicon oxide film to form the first via V1 and the second via V2.

[0266] For example, the thickness of the first silicon oxide film is 500 angstroms, and the thickness of the first silicon oxide film is 0.2-0.3 μm.

[0267] With reference to FIGS. 14K and 14L, FIG. 14K schematically shows a cross-sectional view taken along JJ' in FIG. 14L, the first electrode 311 and the first bridge portion 611 are formed on the side of the second passivation layer PV2 away from the support substrate SUB2, the first electrode 311 and the first bridge portion 611 are formed by the same film forming process and patterning process, and the first electrode 311 and the first bridge portion 611 are connected as an integral structure.

[0268] The first electrode 311 is connected to the first semiconductor portion 3121 through the first via V1, and the first electrode 311, the first semiconductor portion 3121, the light-emitting portion 3123, the second semiconductor portion 3123 and the second electrode 313 constitute the light-emitting device 310.

[0269] The first bridge portion 611 is electrically connected with the second bridge portion 612 through the second via V2, so that in the two adjacent light emitting devices 310, the first electrode 311 of one light emitting device 310 is electrically connected with the second electrode 313 of the other light emitting device 310 through the first bridge portion 611 and the second bridge portion 612.

[0270] Referring to FIG. 14M, a third passivation layer PV3 is formed on the side of the first electrode 311 and the first bridge portion 611 away from the middle substrate SUB2, and the third passivation layer PV3 has a plurality of third vias V3 exposing at least part of the first electrode 311.

[0271] For example, the material of the third passivation layer PV3 includes silicon nitride.

[0272] Referring to FIG. 14N and FIG. 14O in combination, FIG. 14N schematically shows a cross-sectional view taken along KK' in FIG. 14O, and a first bonding pad PAD1 is formed in the third via V3 and is electrically connected with the first electrode 311 through the third via V3.

[0273] For example, the step of forming the first bonding pad PAD1 can include sequentially depositing a molybdenum alloy film and a copper film by a physical vapor deposition process, patterning the molybdenum alloy film and the copper film to only retain the part in the third via V3, and finally growing a tin layer on the surface of the copper layer by an electroless plating process, i.e., the first bonding pad PAD1 has a stack structure of molybdenum alloy / copper / tin.

[0274] For example, the thickness of the molybdenum alloy layer is 200-1000 angstroms, the thickness of the copper layer is 10000-50000 angstroms, and the thickness of the tin layer is 0.5-3 micrometers.

[0275] Referring to FIG. 14P, a driving circuit layer 200 is formed on the substrate substrate 100, and a plurality of second bonding pads PAD2 are formed on the side of the driving circuit layer 200 away from the substrate substrate 100. The middle substrate SUB2 having the light emitting device 310 is vacuum high-temperature bonded with the substrate substrate 100 having the driving circuit layer 200 in a manner that the first bonding pad PAD1 on the light emitting device 310 is bonded with the second bonding pad PAD2 on the driving circuit layer 200.

[0276] For example, the material of the second bonding pad PAD2 includes copper, and the thickness of the second bonding pad PAD2 is 1-5 micrometers.

[0277] Referring to FIG. 14Q, the middle substrate SUB2, the adhesive layer AL1 and the viscous adhesive layer AL2 are removed, so that the second bridge portion 612 is completely exposed.

[0278] Then, a color conversion layer, a color film layer and a protective cover plate are formed on the second bridge portion 612 away from the substrate substrate 100, and a display substrate is obtained.

[0279] In the preparation method provided in the embodiments of the present disclosure, the series connection of the light emitting devices is realized on the carrier substrate to obtain a light emitting unit, and then the light emitting unit is transferred to the driving circuit layer, so that the connection via of the light emitting device and the driving circuit layer only includes the connection via of the second bonding pad and the driving circuit layer, thereby facilitating the realization of higher display resolution.

[0280] FIGS. 15A-15D schematically show process diagrams of forming a display substrate according to some embodiments of the present disclosure.

[0281] With reference to FIGS. 14M, 15A and 15B, FIG. 15A schematically shows a cross-sectional view taken along LL' in FIG. 15B, a reflective layer REL is formed on the third passivation layer PV3 away from the carrier substrate SUB2, the reflective layer REL includes a plurality of reflective portions REF arranged at intervals, and the plurality of reflective portions REF are electrically connected to the plurality of first electrodes 311 through a plurality of third vias V3.

[0282] With reference to FIGS. 15C and 15D, FIG. 15C schematically shows a cross-sectional view taken along MM' in FIG. 15D, an insulating protective layer PL is formed on the reflective layer REL away from the carrier substrate SUB2, the insulating protective layer PL has a plurality of seventh vias V7, the seventh vias V7 expose a portion of the reflective portions REF, a first bonding pad PAD1 is formed in the seventh via V7, and the first bonding pad PAD1 is electrically connected to the reflective portion REF through the seventh via V7.

[0283] Subsequent preparation steps for forming the display substrate can refer to the foregoing embodiments, which will not be described here.

[0284] FIGS. 16A-16B schematically show process diagrams of forming a display substrate according to some embodiments of the present disclosure.

[0285] With reference to FIGS. 14M and 16A, a third planarization layer PLN3 is formed on the third passivation layer PV3 away from the carrier substrate SUB2, the third planarization layer PLN3 has a fourth via V4, and the fourth via V4 of the third planarization layer PLN3 is in communication with the third via V3 of the third passivation layer PV3 to expose at least a portion of the first electrode 311.

[0286] Referring to FIG. 16B, a first bonding pad PAD1 is formed in the fourth via V4 and the third via V3, and the first bonding pad PAD1 is electrically connected to the first electrode 311 through the fourth via V4 and the third via V3.

[0287] Subsequent manufacturing steps for forming the display substrate can refer to the foregoing embodiments, which will not be repeated here.

[0288] FIGS. 17A-17E schematically show a process diagram of forming a display substrate according to some embodiments of the present disclosure.

[0289] With reference to FIG. 14E and FIG. 17A, the bridge layer 600 and the adhesive layer AL2 are patterned in one patterning process to form a plurality of second bridge portions 612 and a plurality of adhesive portions AL21.

[0290] Referring to FIG. 17B, a second passivation layer PV2 is formed on a side of the first semiconductor portion 3121 away from the carrier substrate SUB2, the second passivation layer PV2 has a first via V1 and a second via V2, the first via V1 exposes at least a portion of the first semiconductor portion 3121, and the second via V2 exposes at least a portion of the second bridge portion 612. Since the adhesive layer is patterned into a plurality of adhesive portions AL21, the second passivation layer PV2 fills the space between the adhesive portions AL21.

[0291] Referring to FIG. 17C, a first electrode 311 and a first bridge portion 611 are formed on a side of the second passivation layer PV2 away from the carrier substrate SUB2, the first electrode 311 and the first bridge portion 611 are formed by the same film forming process and patterning process, and the first electrode 311 and the first bridge portion 611 are connected as an integral structure.

[0292] A third passivation layer PV3 is formed on a side of the first electrode 311 and the first bridge portion 611 away from the carrier substrate SUB2, the third passivation layer PV3 has a plurality of third vias V3, and the third vias V3 expose at least a portion of the first electrode 311.

[0293] A first bonding pad PAD1 is formed in the third via V3, and the first bonding pad PAD1 is electrically connected to the first electrode 311 through the third via V3.

[0294] Referring to FIG. 17D, a driving circuit layer 200 is formed on the substrate substrate 100, and a plurality of second bonding pads PAD2 are formed on a side of the driving circuit layer 200 away from the substrate substrate 100. The carrier substrate SUB2 having the light emitting device 310 and the substrate substrate 100 having the driving circuit layer 200 are bonded together by vacuum high-temperature bonding, and the first bonding pad PAD1 on the light emitting device 310 and the second bonding pad PAD2 on the driving circuit layer 200 are bonded together.

[0295] With reference to FIGS. 17D and 17E, the middle substrate SUB2, the adhesive layer AL1 and the adhesive portion AL21 are removed, so that the second bridge portion 612 is completely exposed. The second passivation layer PV2 is planarized, so that the plane of the second passivation layer PV2 is substantially flush with the plane of the substrate 100 and the plane of the second bridge portion 612 is substantially flush with the plane of the substrate 100.

[0296] In the preparation method provided by the embodiments of the present disclosure, the adhesive layer AL2 is patterned into a plurality of spaced adhesive portions AL21 at the same time as the plurality of second bridge portions 612 are patterned, so that the risk of residual adhesive layer can be greatly reduced when the middle substrate SUB2, the adhesive layer AL1 and the adhesive portion AL21 are finally removed.

[0297] At least some embodiments of the present disclosure also provide a display device including the display substrate as described above. The display device can include any device or product having a display function. For example, the display device can be a smart phone, a mobile phone, an electronic book reader, a desktop PC (personal computer), a laptop PC, a netbook PC, a PDA (personal digital assistant), a PMP (portable multimedia player), a digital audio player, a mobile medical device, a camera, a wearable device (e.g., a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, electronic accessories, electronic tattoos, or a smart watch), a television, etc.

[0298] It should be understood that the display panel and the display device according to the embodiments of the present disclosure have all the features and advantages of the display substrate described above, and specific reference can be made to the description above, which will not be repeated here. Although some embodiments of the general inventive concept of the present disclosure have been shown and described, those of ordinary skill in the art will understand that changes can be made in these embodiments without departing from the principles and spirit of the general inventive concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, The display substrate includes: Substrate; A driving circuit layer is located on the substrate; and A light-emitting device layer is located on the side of the driving circuit layer away from the substrate. The light-emitting device layer includes a plurality of light-emitting devices. Each light-emitting device includes a first electrode, a light-emitting functional part located on the side of the first electrode away from the substrate, and a second electrode located on the side of the light-emitting functional part away from the substrate. The light-emitting device layer includes at least one light-emitting unit, and the light-emitting unit includes at least two light-emitting devices connected in series. The light-emitting device is configured to emit light from the second electrode side, the substrate has a first surface facing the light-emitting device layer, the light-emitting functional part includes a first light-emitting surface close to the first surface and a second light-emitting surface away from the first surface, the orthographic projection of the first light-emitting surface on the substrate is located at the orthographic projection of the second light-emitting surface on the substrate, and the area of ​​the first light-emitting surface is smaller than the area of ​​the second light-emitting surface.

2. The display substrate according to claim 1, wherein, The shape of the cross section of the light-emitting functional part perpendicular to the first surface is an inverted trapezoid.

3. The display substrate according to claim 2, wherein, The light-emitting functional part has a first side surface that intersects with the first surface of the substrate, and the angle between the first side surface of the light-emitting functional part and the first surface of the substrate is 50°-70°.

4. The display substrate according to any one of claims 1-3, wherein, A first bonding pad is provided on the side of the first electrode near the driving circuit layer, and a second bonding pad is provided on the side of the driving circuit layer near the first electrode. The first bonding pad and the second bonding pad are electrically connected. The light-emitting device is electrically connected to the driving circuit layer through the first bonding pad and the second bonding pad. The orthographic projection of the first bonding pad on the substrate is located within the orthographic projection of the second bonding pad on the substrate.

5. The display substrate according to any one of claims 1-4, wherein, The light-emitting unit further includes at least one bridging portion, wherein in two adjacent and electrically connected light-emitting devices, the first electrode of one light-emitting device is electrically connected to the second electrode of the other light-emitting device through the bridging portion.

6. The display substrate according to claim 5, wherein, The display substrate further includes a first passivation layer, which is located between the first electrode and the light-emitting functional part. The first passivation layer extends from a first side of the light-emitting functional part to the plane of the light-emitting functional part facing the substrate. The first passivation layer has a first via, which exposes a portion of the plane of the light-emitting functional part facing the substrate. The first electrode is connected to the light-emitting functional part through the first via. The orthographic projection of the first electrode on the substrate coincides with the orthographic projection of the first passivation layer on the substrate. The side of the first electrode facing the substrate has a first groove. The first bonding pad is located within the first groove of the first electrode.

7. The display substrate according to claim 6, wherein, The display substrate further includes a reflective portion that covers at least a portion of the first side surface of the light-emitting functional portion.

8. The display substrate according to claim 7, wherein, The reflective portion is located on the side of the first passivation layer away from the light-emitting functional portion, and the reflective portion and the first electrode are located on the same layer.

9. The display substrate according to claim 8, wherein, The reflective part and the first electrode are integrated into one structure, and the orthogonal projection of the reflective part and the first electrode on the substrate covers the orthogonal projection of the light-emitting functional part on the substrate.

10. The display substrate according to any one of claims 5-9, wherein, The driving circuit layer further includes a connection terminal located on the side of the second bonding pad near the substrate, and the connection terminal is electrically connected to the first electrode of the light-emitting device through the second bonding pad and the first bonding pad; as well as In two adjacent and electrically connected light-emitting devices, the connection terminal electrically connected to one of the light-emitting devices has an epitaxial portion, at least a portion of the orthographic projection of the epitaxial portion on the substrate does not overlap with the orthographic projection of the second bonding pad on the substrate, and the portion of the epitaxial portion protruding relative to the second bonding pad is electrically connected to the second electrode of the other light-emitting device through the bridging portion.

11. The display substrate according to claim 10, wherein, It also includes a first planarization layer located on the side of the light-emitting device layer away from the substrate. The first planarization layer includes a plurality of planarization portions, which cover the sides of the light-emitting device, the first bonding pad, and the second bonding pad. The planarization portions have a first opening that exposes at least a portion of the second electrode of the light-emitting device. as well as The bridging portion is located on the side of the first planarization layer away from the substrate. One end of the bridging portion is electrically connected to the second electrode of one of the light-emitting devices through the first opening, and the other end of the bridging portion extends along the surface of the planarization layer and is electrically connected to the first electrode of an adjacent light-emitting device through the connection terminal.

12. The display substrate according to claim 11, wherein, The display substrate further includes a light-blocking portion, the orthogonal projection of which is located between the orthogonal projections of two adjacent first openings on the substrate. as well as The plane of the light-blocking portion that is farther away from the substrate is farther away from the substrate than the plane of the light-emitting device that is farther away from the substrate. The light-emitting device is configured to emit a third color light, and the light-blocking portion is configured to absorb or reflect the third color light.

13. The display substrate according to claim 12, wherein, The light-blocking portion is located between two adjacent planarization portions, and the light-blocking portion is located on the side of the bridging portion away from the substrate; and The plane of the light-blocking portion near the substrate is closer to the substrate than the plane of the light-emitting device near the substrate.

14. The display substrate according to claim 13, wherein, The display substrate further includes a color conversion section, which is located between two adjacent light-blocking sections and covers the light-emitting device. The light-blocking portion is spaced apart from the adjacent planarization portion, and a portion of the color conversion portion is disposed around the side of the light-emitting device; and The color conversion unit includes a first color conversion unit and a second color conversion unit. The first color conversion unit is configured to convert a third color light into a first color light, and the second color conversion unit is configured to convert a third color light into a second color light.

15. The display substrate according to claim 12, wherein, The display substrate further includes a second planarization layer located on the side of the first planarization layer away from the substrate, and the light-blocking portion is located on the side of the second planarization layer away from the substrate. The plane of the light-blocking portion near the substrate is further away from the substrate than the plane of the light-emitting device near the substrate.

16. The display substrate according to claim 5, wherein, The display substrate further includes a second passivation layer, which is located between the first electrode and the light-emitting functional part. The second passivation layer covers at least a first side of the light-emitting functional part. The second passivation layer has a first via, which exposes a portion of the plane of the light-emitting functional part facing the substrate. The first electrode is connected to the light-emitting functional part through the first via. The bridging portion includes a first bridging portion and a second bridging portion. The first bridging portion is located on the side of the second passivation layer close to the substrate and is electrically connected to the adjacent first electrode. The second bridging portion is located on the side of the second passivation layer away from the substrate and is electrically connected to the adjacent second electrode. The second passivation layer further comprises a second via, through which the first bridging portion and the second bridging portion are electrically connected; and In two adjacent and electrically connected light-emitting devices, the first electrode of one light-emitting device is electrically connected to the second electrode of the other light-emitting device through the first bridging portion and the second bridging portion.

17. The display substrate according to claim 16, wherein, The first bridging portion and the first electrode are located on the same layer, and the first bridging portion and the adjacent first electrode are connected as an integral structure.

18. The display substrate according to claim 16 or 17, wherein, The material of the second bridging portion includes a transparent conductive material, and the orthographic projection of the second bridging portion on the substrate covers the orthographic projection of the second electrode on the substrate.

19. The display substrate according to claim 16 or 17, wherein, The material of the second bridging portion includes a metallic conductive material. The orthographic projection of the second bridging portion on the substrate overlaps with the orthographic projection of the second electrode on the substrate, and the orthographic projection of the second bridging portion on the substrate does not overlap with the orthographic projection of the light-emitting functional portion on the substrate.

20. The display substrate according to any one of claims 16-19, wherein, The display substrate further includes a reflective layer located between the light-emitting device layer and the driving circuit layer, the reflective layer covering at least a portion of the side surface of the light-emitting device.

21. The display substrate according to claim 20, wherein, The display substrate further includes a third passivation layer located between the reflective layer and the first electrode, the third passivation layer including a plurality of third vias; The reflective layer includes a plurality of spaced-apart reflective portions, which are electrically connected to a plurality of first electrodes via the plurality of third vias; and The first bonding pad is located on the side of the reflective layer closer to the substrate, and the first bonding pad is electrically connected to the first electrode through the reflective portion.

22. The display substrate according to any one of claims 16-21, wherein, The display substrate further includes a third planarization layer located between the light-emitting device layer and the driving circuit layer, the third planarization layer filling at least a portion of the spacing region between two adjacent light-emitting devices.

23. The display substrate according to claim 22, wherein, The surface of the third planarization layer closest to the substrate is closer to the substrate than the surface of the light-emitting device closest to the substrate. as well as The third planarization layer has a fourth via that exposes at least a portion of the first electrode, and the first bonding pad is electrically connected to the first electrode through the fourth via.

24. The display substrate according to claim 22 or 23, wherein, The light-emitting device is configured to emit a third color light, and the third planarization layer is configured to absorb or reflect the third color light.

25. A method for preparing a display substrate, wherein, The preparation method includes the following steps: Provide a substrate; A driving circuit layer is formed on the substrate. A light-emitting device layer is formed on the side of the driving circuit layer away from the substrate, and the light-emitting device layer covers... The system includes multiple light-emitting devices, each light-emitting device comprising a first electrode, a light-emitting functional portion located on the side of the first electrode away from the substrate, and a second electrode located on the side of the light-emitting functional portion away from the substrate. The light-emitting device layer includes at least one light-emitting unit, and each light-emitting unit includes at least two light-emitting devices connected in series. The light-emitting device is configured to emit light from the second electrode side, the substrate has a first surface facing the light-emitting device layer, and the shape of the cross section of the light-emitting functional part perpendicular to the first surface is an inverted trapezoid.

26. The method for preparing a display substrate according to claim 25, wherein, Forming a light-emitting device layer on the side of the driving circuit layer away from the substrate includes: A light-emitting diode epitaxial wafer is provided, the light-emitting diode epitaxial wafer comprising an epitaxial substrate, a buffer layer on the epitaxial substrate, a first semiconductor layer on the side of the buffer layer away from the epitaxial substrate, a light-emitting layer on the side of the first semiconductor layer away from the epitaxial substrate, a second semiconductor layer on the side of the light-emitting layer away from the epitaxial substrate, and a second electrode layer formed on the side of the second semiconductor layer away from the epitaxial substrate; A mid-mount substrate is provided, an adhesive layer is formed on the mid-mount substrate, and at least one light-emitting diode epitaxial wafer having a second electrode layer and a bridging layer formed thereon is attached to the mid-mount substrate; Remove the epitaxial substrate and the buffer layer; The first semiconductor layer, the light-emitting layer, the second semiconductor layer, and the second electrode layer are patterned to form a plurality of second electrodes, a plurality of second semiconductor portions located on the side of the plurality of second electrodes away from the intermediate substrate, a plurality of light-emitting portions located on the side of the plurality of second semiconductor portions away from the intermediate substrate, and a plurality of first semiconductor portions located on the side of the plurality of light-emitting portions away from the intermediate substrate. A first electrode is formed on the side of the first semiconductor portion away from the intermediate substrate, and a first bonding pad is formed on the side of the first electrode away from the intermediate substrate. A plurality of second bonding pads are formed on the side of the driving circuit layer away from the substrate. The driving circuit layer includes a connection terminal, which is electrically connected to the second bonding pads. A portion of the connection terminal has an epitaxial portion. At least a portion of the orthographic projection of the epitaxial portion on the substrate does not overlap with the orthographic projection of the second bonding pad on the substrate. The driving circuit layer includes a sixth via, which exposes the epitaxial portion of the connection terminal. The first bonding pad on the intermediate substrate is bonded to the second bonding pad on the substrate. On the tray, remove the intermediate substrate and the adhesive layer; and A bridging portion is formed on the side of the second electrode away from the substrate. One end of the bridging portion is electrically connected to the second electrode of one of the light-emitting devices, and the other end of the bridging portion is electrically connected through the sixth via to the epitaxial portion of the connection terminal that is electrically connected to another adjacent light-emitting device.

27. The method for preparing a display substrate according to claim 25, wherein, Forming a light-emitting device layer on the side of the driving circuit layer away from the substrate includes: A light-emitting diode epitaxial wafer is provided, the light-emitting diode epitaxial wafer comprising an epitaxial substrate, a buffer layer on the epitaxial substrate, a first semiconductor layer on the side of the buffer layer away from the epitaxial substrate, a light-emitting layer on the side of the first semiconductor layer away from the epitaxial substrate, a second semiconductor layer on the side of the light-emitting layer away from the epitaxial substrate, a second electrode layer formed on the side of the second semiconductor layer away from the epitaxial substrate, and a bridging layer formed on the side of the second electrode layer away from the epitaxial substrate; A mid-mount substrate is provided, an adhesive layer is formed on the mid-mount substrate, and at least one light-emitting diode epitaxial wafer having a second electrode layer and a bridging layer formed thereon is attached to the mid-mount substrate; Remove the epitaxial substrate and the buffer layer; The first semiconductor layer, the light-emitting layer, the second semiconductor layer, and the second electrode layer are patterned to form a plurality of second electrodes, a plurality of second semiconductor portions located on the side of the plurality of second electrodes away from the intermediate substrate, a plurality of light-emitting portions located on the side of the plurality of second semiconductor portions away from the intermediate substrate, and a plurality of first semiconductor portions located on the side of the plurality of light-emitting portions away from the intermediate substrate. The bridging layer is patterned to form multiple spaced second bridging portions; A second passivation layer is formed on the side of the first semiconductor portion away from the intermediate substrate. The second passivation layer has a first via and a second via. The first via exposes at least a portion of the first semiconductor portion, and the second via exposes at least a portion of the second bridging portion. A first electrode and a first bridging portion are formed on the side of the second passivation layer away from the intermediate substrate. The first electrode is connected to the first semiconductor portion through the first via, and the first bridging portion is electrically connected to the second bridging portion through the second via. A first bonding pad is formed on the side of the first electrode away from the intermediate substrate; A plurality of second bonding pads are formed on the side of the driving circuit layer away from the substrate; and The first bonding pad on the intermediate substrate is bonded to the second bonding pad on the substrate.

28. A display device, wherein, The display device includes a display substrate according to any one of claims 1-24.

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