Ultra-low-power noise buffer and electronic device

Abstract

Provided in the embodiments of the present invention are an ultra-low-power noise buffer and an electronic device. The ultra-low-power noise buffer comprises: a source current driving circuit and a sink current driving circuit. The sink current driving circuit is electrically connected to the source current driving circuit, and the sink current driving circuit comprises a first transistor, a second transistor and a first current source, wherein the first transistor is electrically connected to the first current source, the first transistor is electrically connected to the second transistor, and the second transistor is electrically connected to the first current source. The source current driving circuit comprises a second current source, a third transistor, an operational amplifier and a voltage source, wherein the second current source is electrically connected to the first transistor and the third transistor, the third transistor is electrically connected to the first transistor and the operational amplifier, and the operational amplifier is electrically connected to the voltage source, the first transistor, the second transistor and the first current source. Thus, the chip area is reduced, the power consumption, noise induction, output resistance and total harmonic distortion (THD) are reduced, and the power supply rejection ratio (PSRR) is improved.

Description

An ultra-low power consumption noise buffer and electronic device TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, and in particular to an ultra-low power consumption noise buffer and electronic device. BACKGROUND

[0002] An operational amplifier is a circuit unit with a very high amplification factor, which can usually be combined with a feedback network to form a functional module. The operational amplifier is an amplifier with special coupling circuit and feedback. For example, the operational amplifier includes a two-stage amplifier, which has complex circuit, more devices, large power, large noise and large area.

[0003] A source follower is a circuit in which a field effect transistor is used for impedance conversion and voltage following. A conventional source follower has the characteristics of low noise, small size and no driving capability. TECHNICAL PROBLEM

[0004] Therefore, the present application provides an ultra-low power consumption noise buffer and electronic device to reduce the chip area, reduce the power consumption, noise induction, output resistance and total harmonic distortion (THD), and improve the power supply rejection ratio (PSRR). TECHNICAL SOLUTION

[0005] In one aspect, the present application provides an ultra-low power consumption noise buffer, comprising: a pull current driving circuit and a sink current driving circuit; the sink current driving circuit is electrically connected with the pull current driving circuit;

[0006] The sink current driving circuit comprises a first transistor, a second transistor and a first current source, wherein the first transistor is electrically connected with the first current source, the first transistor is electrically connected with the second transistor, and the second transistor is electrically connected with the first current source;

[0007] The pull current driving circuit comprises a second current source, a third transistor, an operational amplifier and a voltage source, wherein the second current source is electrically connected with the first transistor and the third transistor, the third transistor is electrically connected with the first transistor and the operational amplifier, and the operational amplifier is electrically connected with the voltage source, the first transistor, the second transistor and the first current source.

[0008] Optionally, the gate of the first transistor is electrically connected with an input end, the source and body of the first transistor are electrically connected with the second current source, the drain of the third transistor and an output end, the drain of the first transistor is electrically connected with the positive input end of the operational amplifier, the first end of the first current source and the gate of the second transistor;

[0009] The gate of the second transistor is electrically connected with the first end of the first current source and the non-inverting input terminal of the operational amplifier, the source and body terminal of the second transistor are electrically connected with the second end of the first current source, the negative electrode of the voltage source and the ground or power supply, and the drain of the second transistor is electrically connected with the output terminal, the second end of the second current source, the drain of the third transistor and the source and body terminal of the first transistor.

[0010] Optionally, the source and body terminal of the third transistor are electrically connected with the first end of the second current source and the power supply voltage, the gate of the third transistor is electrically connected with the output terminal of the operational amplifier, and the drain of the third transistor is electrically connected with the second end of the second current source and the output terminal.

[0011] The inverting input terminal of the operational amplifier is electrically connected with the second end of the first current source and the ground or power supply through the voltage source.

[0012] Optionally, the operational amplifier comprises a current source and at least one transistor.

[0013] Optionally, the operational amplifier comprises a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a third current source.

[0014] The third transistor is electrically connected with the seventh transistor, the seventh transistor is electrically connected with the sixth transistor, the sixth transistor is electrically connected with the fifth transistor, the fifth transistor is electrically connected with the fourth transistor, and the third current source is electrically connected with the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor.

[0015] Optionally, when the transistor is a PMOS transistor, the gate of the fourth transistor is electrically connected with the first end of the first current source, the drain of the first transistor and the gate of the second transistor, the source and body terminal of the fourth transistor are electrically connected with the ground or power supply, the second end of the first current source, the source and body terminal of the second transistor, the source and body terminal of the fifth transistor and the source and body terminal of the sixth transistor, and the drain of the fourth transistor is electrically connected with the second end of the third current source, the gate and drain of the fifth transistor and the gate of the sixth transistor.

[0016] The gate and drain of the fifth transistor are electrically connected with the gate of the sixth transistor and the second end of the third current source, and the source and body terminal of the fifth transistor are electrically connected with the ground or power supply, the second end of the first current source, the source and body terminal of the second transistor and the source and body terminal of the sixth transistor.

[0017] Optionally, it further comprises:

[0018] The drain of the sixth transistor is electrically connected with the drain and the gate of the seventh transistor, and the source and the body terminal of the sixth transistor are electrically connected with the ground or the power supply, the second end of the first current source, the source and the body terminal of the second transistor;

[0019] The gate of the seventh transistor is electrically connected with the gate of the third transistor, and the source and the body terminal of the seventh transistor are electrically connected with the power supply voltage, the first end of the third current source, the source and the body terminal of the third transistor, and the first end of the second current source.

[0020] Optionally, when the transistor is an NMOS transistor, the source and the body terminal of the fourth transistor are electrically connected with the first end of the first current source, the power supply voltage, the source and the body terminal of the second transistor, the source and the body terminal of the fifth transistor, and the source and the body terminal of the sixth transistor, the gate of the fourth transistor is electrically connected with the second end of the first current source, the gate of the second transistor, and the drain of the first transistor, and the drain of the fourth transistor is electrically connected with the first end of the third current source, the gate and the drain of the fifth transistor, and the gate of the sixth transistor.

[0021] The source and the body terminal of the fifth transistor are electrically connected with the source and the body terminal of the sixth transistor, the power supply voltage, the first end of the first current source, and the source and the body terminal of the second transistor, and the drain and the gate of the fifth transistor are electrically connected with the first end of the third current source and the gate of the sixth transistor.

[0022] Optionally, the application further comprises:

[0023] The drain of the sixth transistor is electrically connected with the drain and the gate of the seventh transistor, and the source and the body terminal of the sixth transistor are electrically connected with the power supply voltage, the first end of the first current source, and the source and the body terminal of the second transistor.

[0024] The gate and the drain of the seventh transistor are electrically connected with the gate of the third transistor, and the source and the body terminal of the seventh transistor are electrically connected with the ground or the power supply, the second end of the third current source, the source and the body terminal of the third transistor, and the second end of the second current source.

[0025] In another aspect, the embodiment of the application provides an electronic device comprising the above-mentioned ultra-low-power consumption noise buffer. Advantages

[0026] The technical scheme of the super low power consumption noise buffer provided by the embodiment of the present application comprises: a pull current driving circuit and a sink current driving circuit; the sink current driving circuit is electrically connected with the pull current driving circuit; the sink current driving circuit comprises a first transistor, a second transistor and a first current source, wherein the first transistor is electrically connected with the first current source, the first transistor is electrically connected with the second transistor, and the second transistor is electrically connected with the first current source; the pull current driving circuit comprises a second current source, a third transistor, an operational amplifier and a voltage source, wherein the second current source is electrically connected with the first transistor and the third transistor, the third transistor is electrically connected with the first transistor and the operational amplifier, the operational amplifier is electrically connected with the voltage source, the first transistor, the second transistor and the first current source, the chip area is reduced, the power consumption, noise induction, output resistance and total harmonic distortion (THD) are reduced, and the power supply voltage rejection ratio (PSRR) is improved. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical scheme of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0028] Fig. 1 is a circuit diagram of a super low power consumption noise buffer provided in the related art;

[0029] Fig. 2 is a circuit diagram of a super low power consumption noise buffer provided in an embodiment of the present application;

[0030] Fig. 3 is a circuit diagram of another super low power consumption noise buffer provided in an embodiment of the present application;

[0031] Fig. 4 is a circuit diagram of another super low power consumption noise buffer provided in an embodiment of the present application;

[0032] Fig. 5 is a circuit diagram of a conventional low noise amplifier provided in the related art. BEST MODE FOR CARRYING OUT THE INVENTION

[0033] In order to better understand the technical scheme of the present application, the embodiments of the present application will be described in detail below with reference to the drawings.

[0034] It should be clear that the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0035] The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the description of the invention and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0036] It should be understood that the term "and / or" as used herein merely describes associated objects, which can exist in three relationships, for example, A and / or B, which can represent three cases: A exists alone, A and B exist together, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the front and rear associated objects.

[0037] A super low power consumption noise buffer is provided in the related art. FIG. 1 is a circuit diagram of the super low power consumption noise buffer provided in the related art. As shown in FIG. 1, the super low power consumption noise buffer includes a first field effect transistor (MOS tube) MN1, a second field effect transistor MP1, a first current source I1, a second current source I2, an input end VIN for providing an input signal, and an output end VOUT for outputting an electrical signal. The input end VIN is electrically connected to the gate of the first field effect transistor MN1 to output an electrical signal to the first field effect transistor MN1. The drain of the first field effect transistor MN1 is electrically connected to a power supply voltage VDD through the first current source I1, and the source and body of the first field effect transistor MN1 are both electrically connected to the output end VOUT to output an electrical signal. Meanwhile, the source of the first field effect transistor MN1 is grounded through the second current source I2, and the first current source I1 and the second current source I2 provide working currents for the first field effect transistor MN1 and the second field effect transistor MP1. The source and body of the second field effect transistor MP1 are both electrically connected to the power supply voltage VDD, the gate of the second field effect transistor MP1 is electrically connected to the drain of the first field effect transistor MN1, and the drain of the second field effect transistor MP1 is electrically connected to the output end VOUT. The first field effect transistor MN1 is an N-type field effect transistor, and the second field effect transistor MP1 is a P-type field effect transistor.

[0038] The power supply noise (Vnoise, VDD) is coupled to the gate voltage Vo1 (Vnoise, Vo1 Vnoise, VDD) of the second field effect transistor MP1 through the coupling effect of the gate-source of the second field effect transistor MP1, and the power supply noise is coupled to the output end VOUT through the first field effect transistor MN1. Wherein, VDD≈R1 / (R1+R2), R1 is the effective impedance of the output end VOUT (excluding the first field effect transistor MN1), and R2 is the equivalent impedance of the signal path from the drain of the first field effect transistor MN1. In the related art, R2=r02, and r02 is the impedance of the first field effect transistor MN1. Therefore, the PSRR of the super low power consumption noise buffer in the related art is low.

[0039] To solve the technical problems in the related art, an embodiment of the present application provides an ultra-low power consumption noise buffer, and FIG. 2 is a circuit diagram of an ultra-low power consumption noise buffer provided by an embodiment of the present application, as shown in FIG. 2, the ultra-low power consumption noise buffer comprises: a pull current driving circuit 1 and a sink current driving circuit 2, the sink current driving circuit 2 is electrically connected with the pull current driving circuit 1.

[0040] The sink current driving circuit 2 comprises a first transistor M0, a second transistor M1 and a first current source J0, wherein the first transistor M0 is electrically connected with the first current source J0, the first transistor M0 is electrically connected with the second transistor M1, and the second transistor M1 is electrically connected with the first current source J0.

[0041] The pull current driving circuit 1 comprises a second current source J1, a third transistor M2, an operational amplifier X0 and a voltage source V0, wherein the second current source J1 is electrically connected with the first transistor M0 and the third transistor M2, the third transistor M2 is electrically connected with the first transistor M0 and the operational amplifier X0, and the operational amplifier X0 is electrically connected with the voltage source V0, the first transistor M0, the second transistor M1 and the first current source J0.

[0042] In an embodiment of the present application, the gate of the first transistor M0 is electrically connected with an input end VIN, the source and body of the first transistor M0 are electrically connected with the drain of the third transistor M2 and an output end VOUT, and the drain of the first transistor M0 is electrically connected with the non-inverting input end of the operational amplifier X0, the first end of the first current source J0 and the gate of the second transistor M1.

[0043] The gate of the second transistor M1 is electrically connected with the first end of the first current source J0 and the non-inverting input end of the operational amplifier X0, the source and body of the second transistor M1 are electrically connected with the second end of the first current source J0, the negative pole of the voltage source V0 and ground or a power supply VSS, and the drain of the second transistor M1 is electrically connected with the output end VOUT, the second end of the second current source J1, the drain of the third transistor M2 and the source and body of the first transistor M0.

[0044] In an embodiment of the present application, the source and body of the third transistor M2 are electrically connected with the first end of the second current source J1 and a power supply voltage VDD, the gate of the third transistor M2 is electrically connected with the output end of the operational amplifier X0, and the drain of the third transistor M2 is electrically connected with the second end of the second current source J1 and the output end VOUT.

[0045] The inverting input end of the operational amplifier X0 is electrically connected with the second end of the first current source J0 and ground or the power supply VSS through the voltage source V0.

[0046] In an embodiment of the present application, the operational amplifier X0 comprises a current source and at least one transistor.

[0047] As an alternative, the operational amplifier comprises a fourth transistor M3, a fifth transistor M4, a sixth transistor M5, a seventh transistor M6 and a third current source J2.

[0048] The third transistor M2 is electrically connected with the seventh transistor M6, the seventh transistor M6 is electrically connected with the sixth transistor M5, the sixth transistor M5 is electrically connected with the fifth transistor M4, the fifth transistor M4 is electrically connected with the fourth transistor M3, and the third current source J2 is electrically connected with the third transistor M2, the fourth transistor M3, the fifth transistor M4, the sixth transistor M5 and the seventh transistor M6.

[0049] In an embodiment of the present application, Fig. 3 is a circuit diagram of another ultra-low power consumption noise buffer provided by an embodiment of the present application, as shown in Fig. 3, when the transistors are PMOS transistors, the gate of the fourth transistor M3 is electrically connected with the first end of the first current source J0, the drain of the first transistor M0 and the gate of the second transistor M1, the source and body of the fourth transistor M3 are electrically connected with the ground or the power supply VSS, the second end of the first current source J0, the source and body of the second transistor M1, the source and body of the fifth transistor M4, the source and body of the sixth transistor M5, the drain of the fourth transistor M3 is electrically connected with the second end of the third current source J2, the gate and drain of the fifth transistor M4, the gate of the sixth transistor M5.

[0050] The gate and drain of the fifth transistor M4 are electrically connected with the gate of the sixth transistor M5 and the second end of the third current source J2, the source and body of the fifth transistor M4 are electrically connected with the ground or the power supply VSS, the second end of the first current source J0, the source and body of the second transistor M1, the source and body of the sixth transistor M5.

[0051] The drain and gate of the sixth transistor M5 are electrically connected with the drain and gate of the seventh transistor M6, the source and body of the sixth transistor M5 are electrically connected with the ground or the power supply VSS, the second end of the first current source J0, the source and body of the second transistor M1.

[0052] The gate of the seventh transistor M6 is electrically connected with the gate of the third transistor M2, the source and body of the seventh transistor M6 are electrically connected with the power supply voltage VDD, the first end of the third current source J2, the source and body of the third transistor M2, the first end of the second current source J1.

[0053] In an embodiment of the present application, Fig. 4 is a circuit diagram of another ultra-low power consumption noise buffer provided by an embodiment of the present application, as shown in Fig. 4, when the transistor is an NMOS transistor, the source and body terminal of the fourth transistor M3 are electrically connected with the first end of the first current source J0, the power supply voltage VDD, the source and body terminal of the second transistor M1, the source and body terminal of the fifth transistor M4, and the source and body terminal of the sixth transistor M5, the gate of the fourth transistor M3 is electrically connected with the second end of the first current source J0, the gate of the second transistor M1, and the drain of the first transistor M0, and the drain of the fourth transistor M3 is electrically connected with the first end of the third current source J2, the gate and drain of the fifth transistor M4, and the gate of the sixth transistor M5.

[0054] The source and body terminal of the fifth transistor M4 are electrically connected with the source and body terminal of the sixth transistor M5, the power supply voltage VDD, the first end of the first current source J0, and the source and body terminal of the second transistor M1, and the drain and gate of the fifth transistor M4 are electrically connected with the first end of the third current source J2 and the gate of the sixth transistor M5.

[0055] The drain and gate of the sixth transistor M5 are electrically connected with the drain and gate of the seventh transistor M6, and the source and body terminal of the sixth transistor M5 are electrically connected with the power supply voltage VDD, the first end of the first current source J0, and the source and body terminal of the second transistor M1.

[0056] The gate and drain of the seventh transistor M6 are electrically connected with the gate of the third transistor M2, and the source and body terminal of the seventh transistor M6 are electrically connected with the ground or the power supply VSS, the second end of the third current source J2 and the source and body terminal of the third transistor M2, and the second end of the second current source J1.

[0057] In the technical scheme provided by the embodiment of the present application, the ultra-low power consumption noise buffer comprises a pull current driving circuit and a sink current driving circuit, the sink current driving circuit is electrically connected with the pull current driving circuit, the sink current driving circuit comprises a first transistor, a second transistor, and a first current source, the first transistor is electrically connected with the first current source, the first transistor is electrically connected with the second transistor, and the second transistor is electrically connected with the first current source, the pull current driving circuit comprises a second current source, a third transistor, an operational amplifier, and a voltage source, the second current source is electrically connected with the first transistor and the third transistor, the third transistor is electrically connected with the first transistor and the operational amplifier, the operational amplifier is electrically connected with the voltage source, the first transistor, the second transistor, and the first current source, the chip area is reduced, the power consumption, the noise induction, the output resistance, and the total harmonic distortion (THD) are reduced, and the power supply voltage rejection ratio (PSRR) is improved.

[0058] In the technical scheme provided by the embodiment of the present application, compared with the ultra-low power consumption noise buffer provided in the related art of FIG. 1, the pull current driving circuit 1 and the sink current driving circuit 2 are designed to enhance the driving capability of the pull current and the sink current, thereby reducing the output resistance.

[0059] In the technical scheme provided by the embodiment of the present application, the negative feedback of the pull current and the sink current can be provided at the same time to stabilize the output voltage to provide noise, thereby improving the PSRR.

[0060] In the technical scheme provided by the embodiment of the present application, the pull current driving circuit 1 and the sink current driving circuit 2 are both used to enhance the driving capability of the circuit under different output loads, maintain the first transistor M0 to propagate the input signal to the output with minimum loss and distortion, and thus realize low THD.

[0061] In the technical scheme provided by the embodiment of the present application, FIG. 5 is a circuit diagram of a conventional low noise amplifier provided in the related art, as shown in FIG. 5, compared with the conventional low noise amplifier, the technical scheme provided by the embodiment of the present application only needs one device (the first transistor M0) as a signal path, and the feedback devices of the receiver / source driver are few. Therefore, compared with the conventional low noise amplifier in FIG. 5, the chip area of the ultra-low power consumption noise buffer in the present application is smaller.

[0062] In the technical scheme provided by the embodiment of the present application, since the single device (the first transistor M0) dominates the noise, compared with the conventional low noise amplifier in FIG. 5, the input device (the first transistor M0, the second transistor M1) and the load device (the fifth transistor M4, the sixth transistor M5) in the embodiment of the present application will contribute noise, therefore, the technical scheme provided by the embodiment of the present application has the advantage of lower noise, or needs less power consumption.

[0063] An embodiment of the present application provides an electronic device including the above-mentioned ultra-low power consumption noise buffer. For example, the electronic device can include a microphone, a smart phone, a camera, a headset, etc.

[0064] The above merely provides the preferred embodiments of the present application but not for limiting the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An ultra-low power noise buffer, characterized in that, include: Current-pull drive circuit and current-sink drive circuit; The sinking current driving circuit is electrically connected to the sourcing current driving circuit. The current sinking drive circuit includes a first transistor, a second transistor, and a first current source, wherein the first transistor is electrically connected to the first current source, the first transistor is electrically connected to the second transistor, and the second transistor is electrically connected to the first current source. The current-driving circuit includes a second current source, a third transistor, an operational amplifier, and a voltage source. The second current source is electrically connected to the first transistor and the third transistor. The third transistor is electrically connected to the first transistor and the operational amplifier. The operational amplifier is electrically connected to the voltage source, the first transistor, the second transistor, and the first current source.

2. The ultra-low power noise buffer according to claim 1, characterized in that, The gate of the first transistor is electrically connected to the input terminal, and the source and body of the first transistor are both electrically connected to the second current source, the drain of the third transistor, and the output terminal. The drain of the first transistor is electrically connected to the non-inverting input terminal of the operational amplifier, the first terminal of the first current source, and the gate of the second transistor. The gate of the second transistor is electrically connected to the first terminal of the first current source and the non-inverting input terminal of the operational amplifier. The source and body of the second transistor are both electrically connected to the second terminal of the first current source, the negative terminal of the voltage source, and ground or power supply. The drain of the second transistor is electrically connected to the output terminal, the second terminal of the second current source, the drain of the third transistor, and the source and body of the first transistor.

3. The ultra-low power noise buffer according to claim 2, characterized in that, The source and body of the third transistor are both electrically connected to the first terminal of the second current source and the power supply voltage. The gate of the third transistor is electrically connected to the output terminal of the operational amplifier. The drain of the third transistor is electrically connected to the second terminal and the output terminal of the second current source. The inverting input terminal of the operational amplifier is electrically connected to the second terminal of the first current source and ground or power supply through the voltage source.

4. The ultra-low power noise buffer according to claim 1, characterized in that, The operational amplifier includes a current source and at least one transistor.

5. The ultra-low power noise buffer according to claim 4, characterized in that, The operational amplifier includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a third current source; The third transistor is electrically connected to the seventh transistor, the seventh transistor is electrically connected to the sixth transistor, the sixth transistor is electrically connected to the fifth transistor, the fifth transistor is electrically connected to the fourth transistor, and the third current source is electrically connected to the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor.

6. The ultra-low power noise buffer according to claim 5, characterized in that, When the transistor is a PMOS transistor, the gate of the fourth transistor is electrically connected to the first terminal of the first current source, the drain of the first transistor, and the gate of the second transistor. The source and body of the fourth transistor are both electrically connected to ground or power supply, the second terminal of the first current source, the source and body of the second transistor, the source and body of the fifth transistor, and the source and body of the sixth transistor. The drain of the fourth transistor is electrically connected to the second terminal of the third current source, the gate and drain of the fifth transistor, and the gate of the sixth transistor. The gate and drain of the fifth transistor are both electrically connected to the gate of the sixth transistor and the second terminal of the third current source. The source and body of the fifth transistor are both electrically connected to ground or power supply, the second terminal of the first current source, the source and body of the second transistor, and the source and body of the sixth transistor.

7. The ultra-low power noise buffer according to claim 6, characterized in that, Also includes: The drain of the sixth transistor is electrically connected to the drain and gate of the seventh transistor, and the source and body of the sixth transistor are both electrically connected to ground or power supply, the second terminal of the first current source, and the source and body of the second transistor. The gate of the seventh transistor is electrically connected to the gate of the third transistor, and the source and body of the seventh transistor are both electrically connected to the power supply voltage, the first terminal of the third current source, the source and body of the third transistor, and the first terminal of the second current source.

8. The ultra-low power noise buffer according to claim 5, characterized in that, When the transistor is an NMOS transistor, the source and body of the fourth transistor are electrically connected to the first terminal of the first current source, the power supply voltage, the source and body of the second transistor, the source and body of the fifth transistor, and the source and body of the sixth transistor. The gate of the fourth transistor is electrically connected to the second terminal of the first current source, the gate of the second transistor, and the drain of the first transistor. The drain of the fourth transistor is electrically connected to the first terminal of the third current source, the gate and drain of the fifth transistor, and the gate of the sixth transistor. The source and body of the fifth transistor are electrically connected to the source and body of the sixth transistor, the power supply voltage, the first terminal of the first current source, and the source and body of the second transistor. The drain and gate of the fifth transistor are electrically connected to the first terminal of the third current source and the gate of the sixth transistor.

9. The ultra-low power noise buffer according to claim 8, characterized in that, Also includes: The drain of the sixth transistor is electrically connected to the drain and gate of the seventh transistor, and the source and body of the sixth transistor are both electrically connected to the power supply voltage, the first terminal of the first current source, and the source and body of the second transistor. The gate and drain of the seventh transistor are both electrically connected to the gate of the third transistor, and the source and body of the seventh transistor are both electrically connected to the ground or power supply, the second terminal of the third current source, the source and body of the third transistor, and the second terminal of the second current source.

10. An electronic device, characterized in that, Including the ultra-low power noise buffer as described in any one of claims 1 to 9.

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