Delay measurement circuit and memory

Abstract

Embodiments of the present disclosure provide a delay measurement circuit and a memory. The delay measurement circuit comprises: a loop flag generation circuit, electrically connected to a loop of a delay-locked loop, and used for generating a loop flag signal when performing loop delay measurement on the delay-locked loop and inputting the loop flag signal to the loop of the delay-locked loop, and after the loop flag signal circulates in the loop of the delay-locked loop for M times, generating a measurement end signal and generating a target pulse signal, the effective pulse width of the target pulse signal being equal to M times a loop delay; and a counting circuit, electrically connected to the loop flag generation circuit, and used for receiving a divided clock signal, using the divided clock signal to time the effective pulse width of the target pulse signal to obtain a timing result, and performing preset processing on the timing result to obtain a loop delay measurement result of the delay-locked loop. The embodiments of the present disclosure are at least conducive to increasing the margin value of the delay measurement circuit and improving the accuracy of loop delay measurement.

Description

Delay measurement circuit and memory

[0001] The present application claims priority from the Chinese patent application No. 202410826730.0 filed on June 24, 2024, and entitled "Delay measurement circuit and memory", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a delay measurement circuit and a memory. BACKGROUND

[0003] In a memory system, data is usually transmitted in a certain timing. The normal operation of the memory relies on the internal command and clock being able to have accurate timing. For example, when the memory receives a read command, it needs to output data from the data port after a desired delay time. When the memory receives a write command, it also needs to receive data from the data port after a desired delay time. This requires the memory to be able to accurately measure and calculate the path delay of the command signal and the clock signal, so as to achieve accurate control of the timing. However, as the operating frequency of the memory increases, it may bring challenges to the measurement of the path delay.

[0004] SUMMARY

[0005] Embodiments of the present disclosure provide a delay measurement circuit and a memory, which at least have the advantages of increasing the margin value of the delay measurement circuit and improving the accuracy of the loop delay measurement.

[0006] In a first aspect, embodiments of the present disclosure provide a delay measurement circuit applied to a delay-locked loop, comprising:

[0007] a loop flag generation circuit, electrically connected with the loop of the delay-locked loop, configured to generate a loop flag signal and input the loop flag signal to the loop of the delay-locked loop when performing loop delay measurement on the delay-locked loop, and generate a measurement end signal and a target pulse signal after the loop flag signal circulates in the loop of the delay-locked loop for M times, wherein the effective pulse width of the target pulse signal is equal to M times of the loop delay, and M is an even number greater than 1.

[0008] a counting circuit, electrically connected with the loop flag generation circuit, configured to receive a divided clock signal, use the divided clock signal to time the effective pulse width of the target pulse signal to obtain a timing result, and perform a preset processing on the timing result to obtain a loop delay measurement result of the delay-locked loop.

[0009] In some embodiments, the delay measurement circuit further comprises:

[0010] The control circuit is configured to generate a first level of measurement control signal when performing loop delay measurement on the delay-locked loop, and generate a second level of measurement control signal at other time.

[0011] In some embodiments, the delay measurement circuit further comprises:

[0012] The selection circuit is electrically connected to the loop of the delay-locked loop, and is configured to select inputting the loop flag signal to the loop of the delay-locked loop when performing loop delay measurement on the delay-locked loop, and inputting a reference clock signal to the loop of the delay-locked loop at other time.

[0013] In some embodiments, the loop flag generation circuit comprises:

[0014] The initial flag generation circuit is configured to generate an initial loop flag signal after waiting for a preset period in response to the measurement control signal changing from the second level to the first level; when the working frequency of the delay-locked loop is greater than a preset frequency, the preset period is a first value, when the working frequency of the delay-locked loop is less than or equal to the preset frequency, the preset period is a second value, and the first value is greater than the second value.

[0015] The logic processing circuit is electrically connected to the loop of the delay-locked loop, and is configured to receive a signal from the feedback end of the loop and perform inverting processing on the signal, and perform AND logic processing on the inverting processed signal and the initial loop flag signal to generate the loop flag signal.

[0016] In some embodiments, the loop flag generation circuit further comprises:

[0017] The target pulse generation circuit is configured to count the change edges of the loop flag signal, start generating an effective pulse of the target pulse signal in response to a first change edge of the loop flag signal, and end the effective pulse of the target pulse signal in response to an M+1th change edge of the loop flag signal; and generate the measurement end signal in response to the end of the effective pulse of the target pulse signal.

[0018] In some embodiments, the initial flag generation circuit comprises:

[0019] The first selector is configured to receive a frequency characteristic signal, a first divided clock signal and a second divided clock signal, select the first divided clock signal as a timing clock signal when the frequency characteristic signal indicates that the operating frequency of the delay-locked loop is greater than a preset frequency, and select the second divided clock signal as the timing clock signal when the frequency characteristic signal indicates that the operating frequency of the delay-locked loop is less than or equal to the preset frequency; the frequency of the second divided clock signal is higher than the frequency of the first divided clock signal.

[0020] A first trigger is configured to receive the timing clock signal at the clock end of each of the first triggers, receive the measurement control signal at the data end of the first trigger, connect the data end of each of the first triggers after the first trigger to the output end of the first trigger of the previous stage, and output the initial loop flag signal at the output end of the last first trigger, where A is an integer greater than 1.

[0021] In some embodiments, the delay measurement circuit further comprises:

[0022] A frequency divider is configured to receive a reference clock signal, perform frequency division processing on the reference clock signal, and generate a plurality of divided clock signals, the plurality of divided clock signals at least including the first divided clock signal and the second divided clock signal.

[0023] In some embodiments, the frequency divider comprises:

[0024] A second trigger is configured to receive the reference clock signal at the clock end, and connect the data end to the inverted output end;

[0025] A third trigger is configured to connect the clock end to the output end of the second trigger, connect the data end to the inverted output end, and output the second divided clock signal at the output end, the clock period of the second divided clock signal being 4 times the clock period of the reference clock signal.

[0026] A fourth trigger is configured to connect the clock end to the output end of the third trigger, connect the data end to the inverted output end, and output the first divided clock signal at the output end, the clock period of the first divided clock signal being 8 times the clock period of the reference clock signal.

[0027] In some embodiments, the target pulse generation circuit comprises:

[0028] A fifth trigger is configured to receive the loop flag signal at the clock end, and connect the data end to the inverted output end;

[0029] a sixth flip-flop, a clock terminal of which is connected with an output terminal of the fifth flip-flop, a data terminal of which is connected with an inverted output terminal of the sixth flip-flop, and an output terminal of which outputs the target pulse signal;

[0030] a seventh flip-flop, a clock terminal of which receives an inverted signal of the target pulse signal, a data terminal of which receives a power signal, and an output terminal of which outputs the measurement end signal;

[0031] wherein the M is equal to 4.

[0032] In some embodiments, the control circuit receives a lock flag signal and the measurement end signal, generates a measurement control signal of a first level in response to the lock flag signal, and generates a measurement control signal of a second level in response to the measurement end signal; wherein the lock flag signal represents that the delay-locked loop has completed phase locking.

[0033] In some embodiments, the control circuit comprises:

[0034] an eighth flip-flop, a clock terminal of which receives a reference clock signal, a data terminal of which receives the lock flag signal, an output terminal of which outputs the measurement control signal, and a reset terminal of which receives the measurement end signal.

[0035] In some embodiments, the counting circuit comprises:

[0036] a delay adjustment circuit configured to receive the divided clock signal, delay the divided clock signal by a first adjustment time length, and generate an adjusted divided clock signal; the first adjustment time length is used to match a physical delay required by the loop flag generation circuit to generate the target pulse signal.

[0037] a gating circuit configured to receive the adjusted divided clock signal and the target pulse signal, perform gating processing on the adjusted divided clock signal by using the target pulse signal, and generate a counting clock signal.

[0038] a binary counter configured to count clock pulses of the counting clock signal, and generate a binary timing result.

[0039] In some embodiments, the preset processing comprises: performing shift processing on the binary timing result according to a frequency of the divided clock signal and a value of the M, to obtain the loop delay measurement result.

[0040] In some embodiments, a difference between a time for the loop flag signal to circulate once in a loop of the delay-locked loop and a time for the reference clock signal to circulate once in the loop of the delay-locked loop is less than a first preset value.

[0041] In a second aspect, the present disclosure provides a memory comprising at least the delay measurement circuit according to the first aspect.

[0042] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages.

[0043] The delay measurement circuit is applied to a delay-locked loop and comprises a loop mark generation circuit electrically connected to a loop of the delay-locked loop and configured to generate a loop mark signal and input the loop mark signal to the loop of the delay-locked loop when performing loop delay measurement on the delay-locked loop, generate a measurement end signal and a target pulse signal after the loop mark signal circulates in the loop of the delay-locked loop for M times, and the effective pulse width of the target pulse signal is equal to M times of the loop delay; wherein M is an even number greater than 1; a counting circuit electrically connected to the loop mark generation circuit and configured to receive a divided clock signal, count the effective pulse width of the target pulse signal by using the divided clock signal to obtain a counting result, and perform preset processing on the counting result to obtain a loop delay measurement result of the delay-locked loop. According to the scheme, the loop mark signal is input to the loop of the delay-locked loop in a manner of circulating for M times to obtain M times of the loop delay value, which is embodied by the effective pulse width of the target pulse signal, and the M times of the loop delay value is counted by using the divided clock signal. In this way, the loop measurement circuit has a larger measurement margin value, avoids loop delay measurement errors caused by insufficient margin value under a high clock frequency, and improves the accuracy of loop delay measurement. BRIEF DESCRIPTION OF DRAWINGS

[0044] One or more embodiments are illustrated by way of example in the drawings, which are for illustrative purposes only and are not meant to limit the embodiments, and elements having the same reference numerals in the drawings represent like elements unless otherwise specified. The drawings in the accompanying drawings do not constitute a proportional limit; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the drawings needed in the embodiments will be briefly introduced below, and obviously, other drawings can be obtained according to these drawings without creative labor for those skilled in the art.

[0045] FIG. 1 is a structural schematic diagram of a delay-locked loop DLL;

[0046] FIG. 2 is a structural schematic diagram of a delay measurement circuit;

[0047] FIG. 3a is a signal waveform diagram of a delay measurement circuit in a case;

[0048] FIG. 3b is a signal waveform diagram of a delay measurement circuit in another case;

[0049] FIG. 4 is a structural schematic diagram of a delay measurement circuit according to an embodiment of the present disclosure;

[0050] FIG. 5 is a structural schematic diagram of a delay measurement circuit according to an embodiment of the present disclosure;

[0051] FIG. 6 is a structural schematic diagram of a control circuit according to an embodiment of the present disclosure;

[0052] FIG. 7 is a partial structural schematic diagram of a delay measurement circuit according to an embodiment of the present disclosure;

[0053] FIG. 8 is a structural schematic diagram of a frequency divider according to an embodiment of the present disclosure;

[0054] FIG. 9 is a structural schematic diagram of a counting circuit according to an embodiment of the present disclosure;

[0055] FIG. 10 is a signal waveform diagram of a delay measurement circuit according to an embodiment of the present disclosure;

[0056] FIG. 11 is a structural schematic diagram of a memory according to an embodiment of the present disclosure; DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, it should be noted that, for the convenience of description, only the parts related to the application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure. In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first", "second", "third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that "first", "second", "third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0058] Dynamic Random Access Memory (DRAM)

[0059] Synchronous Dynamic Random Access Memory (SDRAM)

[0060] Double Data Rate SDRAM (DDR)

[0061] Low Power DDR (LPDDR)

[0062] DDR standard of the nth generation (DDRn Specification, DDRn), such as DDR3, DDR4, DDR5, DDR6

[0063] LPDDR standard of the nth generation (LPDDRn Specification, LPDDRn), such as LPDDR3, LPDDR4, LPDDR5, LPDDR6

[0064] Delay Locked Loop (DLL)

[0065] Loop Measure (LM)

[0066] Latency

[0067] In a memory system, data is usually transmitted with certain timing. The normal operation of a memory relies on the internal command and clock to have accurate timing. For example, when a memory receives a read command, it needs to output data from the data port after a desired latency. When a memory receives a write command, it also needs to receive data from the data port after a desired latency. This requires the memory to accurately measure and calculate the path delay of the command signal and clock signal inside the memory, so as to accurately control the timing.

[0068] The above-mentioned desired latency, also known as "latency", is an important parameter defined in the DRAM design specification. The parameter is configured by the DRAM controller and stored in the register of the DRAM, which specifies that after receiving a read or write command from the DRAM, the data (DQ) and data strobe signal (DQS) need to be sent or received after a fixed time interval of an integer multiple of clock cycles. For example, setting the read latency (RL) to 28 means that after the DRAM receives a read command, the data (DQ) and data strobe signal (DQS) need to be sent after 28 clock cycles. Configured by the DRAM controller, RL can have many settings. In this disclosure, one clock cycle, denoted as tck, is the clock cycle of the external clock signal CK_t received by the DRAM. The purpose of setting the latency is to meet the timing constraints when the master communicates with the slave and to give the DRAM time to prepare data. During the communication between the DRAM and the host, latency errors can cause communication failure or data loss.

[0069] In order to establish timing constraints, the DRAM design specification requires that the latency must be an integer multiple of the clock cycle (N*tck, N is a positive integer), but in actual circuits, due to changes in process, voltage, and temperature, the actual circuit delay is full of uncertain factors, and will be disturbed by external noise. The designer must convert the actual circuit delay into an integer multiple of the clock cycle, and this operation is achieved by a delay-locked loop.

[0070] In the field of DRAM design, the generation of latency mainly includes the actual circuit delay and the shift register delay. Due to changes in environment, process, and voltage, it is difficult to set the initial value of the actual circuit delay as an integer multiple of the clock cycle. Due to the requirements of the design specification, the actual circuit delay must be converted into an integer multiple of the clock cycle, and this operation is usually completed by a delay-locked loop (DLL).

[0071] Referring to FIG. 1, a structure of a delay-locked loop is shown. An external clock signal CK_t is input from a clock port CLK, and the delay of the input path is represented by TD1. Then a reference clock signal REFCLK is generated through a clock divider (CLK DIV), and subsequently output from a data strobe signal output port DQS through a coarse delay line (CDL), a fine delay line (FDL), a clock distribution network (TSAC), and an output driver (DRV). The delays of the three parts of CLK DIV, CDL, and FDL can be represented by TD_DLY. The delays of TSAC and DRV are represented by output delays, which can be represented by TD2. The DLL loop includes the coarse delay line CDL and the fine delay line FDL, and a clock divider replica (CLK DIV REP) for simulating the delay of the clock divider. The DLL loop also includes a replica for simulating the delays of the input path, the clock distribution network TSAC, and the output driver DRV. The delay of the replica is represented by TD_REP, and ideally, TD_REP = TD1 + TD2. The reference clock signal REFCLK enters the DLL loop, and after one cycle, a feedback clock signal FBCLK is output from the output of the replica. A phase detector (PD) compares the phases of the reference clock signal REFCLK and the feedback clock signal FBCLK, and then controls the delays of CDL and FDL through a delay control module (DLY CTRL) so that the phase difference between the reference clock signal REFCLK and the feedback clock signal FBCLK is approximately 0, and the DLL reaches a locked state. Ideally, when the DLL is locked, the rising edges of the reference clock signal REFCLK and the feedback clock signal FBCLK are aligned, and the phase difference between them is equal to 0. However, in actual situations, as long as the phase difference between REFCLK and FBCLK is approximately 0 within an error tolerance range, the DLL is considered to be in a locked state. The delay of the DLL loop is equal to the sum of the delays of the clock divider replica CLK DIV REP, CDL, FDL, and the replica, that is, TD_DLY + TD_REP. When the DLL is locked, the delay of the DLL loop is an integer multiple of the clock period (N*tck), that is, TD_DLY + TD_REP is an integer multiple of the clock period (N*tck). The path delay of the actual circuit is the delay from the input of the CLK port to the output of the DQS port, which is equal to TD1 + TD_DLY + TD2.When the design is such that TD_REP = TD1 + TD2, the path delay of the actual circuit is equal to TD_DLY + TD_REP, i.e. equal to the DLL loop delay. So when the DLL is locked, the path delay of the actual circuit is also an integer multiple of the clock period (N*tck).

[0072] It should be understood that the definitions of phase difference in the present disclosure allow certain errors. The related definitions about phase values, signal edge alignment or signal waveforms are all within the range of error allowance.

[0073] In order to perform data preparation and other operations for DRAM, the latency must be greater than the path delay of the actual circuit, and the remaining delay can be achieved by a clock frequency-based shift register. The latency, the path delay of the actual circuit, and the delay of the shift register are all in units of clock periods. The clock frequency-based shift register has a delay of 1*tck per stage, and the number of stages of the shift register can be obtained by (Latency-N). The value of N is measured by a loop measure (LM) module in the DLL.

[0074] The prerequisite for the DLL to perform loop delay measurement is that the DLL is locked, so as to ensure that the loop delay of the DLL is an integer multiple of the clock period. After the DLL is locked, a lock flag signal (LOCKFLAG) is sent to indicate that the loop delay measurement is started. Referring to FIG. 2, a structure of a delay measurement circuit is shown. The loop delay measurement module includes a freeze signal generation module Freeze, a measurement module Measure, and a decoding module Decoder. The freeze signal generation module generates a freeze signal FREEZE after sampling the lock flag signal LOCKFLAG, which blocks the reference clock signal REFCLK from entering the DLL loop, while the clock that has entered the DLL loop before this time will still be output at FBCLK. The measurement module Measure uses cascaded D flip-flops for counting, and FBCLK is used as the clock input of the cascaded D flip-flops to sample the FREEZE signal to obtain a thermometer code result LM_TM. The result is converted to binary code by the decoding module to obtain the value of N, denoted as LM_BI. The value of N is sent to the operation module in the DRAM to calculate (Latency-N) to obtain the number of stages required by the shift register.

[0075] Referring to FIG. 3a, it shows the signal waveform diagram corresponding to the delay measurement circuit in FIG. 2. In FIG. 3a, it first shows the state of the reference clock signal REFCLK and the feedback clock signal FBCLK before the DLL is locked, at this time, there is a phase difference between the rising edges of the two, which is represented as Tdelta_ref2fb, i.e. Tdelta_ref2fb>0. When the DLL is locked, the phase difference between the two is 0, and the rising edges are aligned. After the DLL is locked, the lock flag signal LOCKFLAG becomes high, and after being sampled by the 6th rising edge of REFCLK, the FREEZE signal becomes low, which is realized in the freeze signal generation module Freeze in FIG. 2. From the rising edge of REFCLK being sampled to the generation of the low-level FREEZE signal, the time is recorded as Tsyn_freeze_gen. The reference clock signal REFCLK is inverted to obtain the REFCLKB signal, and the REFCLKB signal and the FREEZE signal are subjected to NAND logic operation to generate the loop input signal LOOPCLK_IN. The low-level FREEZE signal blocks REFCLK from entering the DLL loop, but the clock pulses 0-6 that have entered the loop before this time can still reach the output end of the feedback clock signal FBCLK. Taking FBCLK as the clock, the FREEZE signal is sampled through cascaded D flip-flops, and if the FREEZE signal is low, the sampling result is 1. As shown in FIG. 3, the rising edges of clock pulses 1-6 of the FBCLK signal sample the low-level FREEZE signal to obtain LM_TM<6:0> = 0111111. The thermometer code is converted into a binary code value of 6, indicating that the clock pulse entering the DLL loop is output from the loop after 6 periods, i.e. the DLL loop delay is equal to 6 times the period of FBCLK, which is also equal to 6 times the period of REFCLK. Since REFCLK is generated by a frequency divider to divide by 2, the clock period of REFCLK is 2tck, so 6 times the period of REFCLK is actually equal to 12*tck, i.e. the DLL loop delay is equal to 12*tck, and the value of N is equal to 12.

[0076] For the delay measurement circuit shown in Fig. 2, the delay between the rising edge of the REFCLK sampling the FREEZE signal and the falling edge of the FREEZE signal after sampling is the margin value of the delay measurement circuit. It is found through research that the margin value needs to be less than 1 tck to ensure the correctness of the loop delay measurement. It is found through research that there are two places in this circuit that consume the margin value. The first place is the absolute delay of the REFCLK sampling to generate the FREEZE signal, that is, Tsyn_freeze_gen. The second place is the phase difference between the REFCLK and the FBCLK after the DLL is locked, that is, Tdelta_ref2fb. Therefore, to ensure the accuracy of the delay measurement circuit, the following margin value condition needs to be met: Tsyn_freeze_gen + Tdelta_ref2fb < 1 tck.

[0077] Fig. 3b shows a case where the loop delay measurement is incorrect due to Tsyn_freeze_gen being too large and exceeding the 1 tck margin value. Because Tsyn_freeze_gen > 1 tck, after the 6th rising edge of the REFCLK samples the LOOPFLAG signal, more than 1 tck time is needed to generate the falling edge of the FREEZE, so the 6th falling edge of the REFCLK, that is, the 6th rising edge of the REFCLKB enters the loop to generate the 6th falling edge of the LOOPCLK_IN. Also at the moment when the FREEZE becomes 0, the LOOPCLK_IN generates the 7th rising edge, which also enters the loop. Therefore, the FBCLK output by the loop has 7 rising edges 1-7, which sample the FREEZE signal at the low level to obtain LM_TM<6:0> = 1111111. The value of the binary code converted from the thermometer code is 7. Finally, the N value converted is equal to 14, causing the error of the loop delay measurement.

[0078] In addition, when the phase difference Tdelta_ref2fb between the REFCLK and the FBCLK after the DLL is locked is greater than 0, it also occupies the margin value of the loop measurement. For example, when the DRAM performs the self-refresh operation, the power consumption is large, which generates power supply noise to affect the DLL circuit, so that the phase difference Tdelta_ref2fb between the reference clock signal and the feedback clock signal is greater than 0. If the loop delay measurement is performed at this time, the margin value will be more limited, and the risk of failure will be greater. For another example, when the DLL uses the fast lock function (Fast Lock) and performs the loop delay measurement, because the fast lock function has a certain error in aligning the reference clock signal and the feedback clock signal, the error also causes Tdelta_ref2fb to be greater than 0, which causes the margin value of the loop measurement to be limited, thereby causing the failure.

[0079] In summary, as the memory operating frequency increases, the margin value of 1tck in the loop measurement scheme is constantly decreasing, and in practical applications, Tsyn_freeze_gen+Tdelta_ref2fb<1tCK must be met, but due to the influence of factors such as manufacturing process, temperature, and voltage variation, it is often difficult to achieve, and a loop measurement scheme with a larger margin value is urgently needed to meet the needs of high-speed memory.

[0080] Therefore, the embodiment of the present disclosure provides a delay measurement circuit applied to a delay-locked loop, comprising: a loop flag generation circuit, which is electrically connected with a loop of the delay-locked loop, and is configured to generate a loop flag signal when performing loop delay measurement on the delay-locked loop, and input the loop flag signal to the loop of the delay-locked loop; generate a measurement end signal after the loop flag signal circulates M times in the loop of the delay-locked loop, and generate a target pulse signal, the effective pulse width of the target pulse signal being equal to M times of the loop delay; wherein M is an even number greater than 1; a counting circuit, which is electrically connected with the loop flag generation circuit, and is configured to receive a divided clock signal, use the divided clock signal to time the effective pulse width of the target pulse signal to obtain a timing result, and perform a preset processing on the timing result to obtain a loop delay measurement result of the delay-locked loop. The scheme inputs the loop flag signal to the loop of the delay-locked loop in a circulating M-turn manner to obtain M times of the loop delay value, which is embodied by the effective pulse width of the target pulse signal, and the M times of the loop delay value is timed by the divided clock signal. In this way, the loop measurement circuit has a larger measurement margin value, avoids loop delay measurement errors caused by insufficient margin value under high clock frequency, and improves the accuracy of loop delay measurement.

[0081] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0082] In an embodiment of the present disclosure, referring to FIG. 4, a structural schematic diagram of a delay measurement circuit 10 provided by the embodiment of the present disclosure is shown. As shown in FIG. 4, the delay measurement circuit 10 comprises:

[0083] The loop flag generation circuit 11 is electrically connected with the loop 21 of the delay-locked loop 20, and is configured to generate a loop flag signal when performing loop delay measurement on the delay-locked loop 20, and input the loop flag signal to the loop 21 of the delay-locked loop; generate a measurement end signal after the loop flag signal circulates M times in the loop 21 of the delay-locked loop, and generate a target pulse signal, the effective pulse width of the target pulse signal being equal to M times of the loop delay; wherein M is an even number greater than 1;

[0084] The counting circuit 12 is electrically connected with the loop mark generating circuit 11, configured to receive the divided clock signal, use the divided clock signal to time the effective pulse width of the target pulse signal, and obtain a timing result; and perform preset processing on the timing result to obtain a loop 21 delay measurement result of the delay-locked loop.

[0085] It should be noted that the delay measurement circuit 10 of the embodiments of the present disclosure can be applied to any electronic device containing a delay-locked loop, such as a memory, a controller, a processor, etc.

[0086] The loop mark generating circuit 11 inputs a loop mark signal into the loop 21 of the delay-locked loop, and the loop mark signal can obtain a loop delay value of M times after circulating M times in the loop 21 of the delay-locked loop. The loop mark generating circuit 11 generates a target pulse signal, and the effective pulse width of the target pulse signal embodies the loop delay value of M times. Since M is an even number greater than 1, the loop delay value of M times is also an even number, and the counting circuit 12 can obtain more margin values by measuring the even number through the divided clock signal. In this way, by using the divided clock signal to measure a wider pulse, the loop measurement circuit has a larger measurement margin value, avoids the loop delay measurement error caused by insufficient margin value under a high clock frequency, and improves the accuracy of the loop delay measurement.

[0087] In some embodiments, the preset processing includes processing the timing result according to the frequency of the divided clock signal and the value of M to obtain the loop delay measurement result. For example, if M is equal to 4, that is, the loop mark signal circulates 4 times in the loop 21 of the delay-locked loop, and the effective pulse width of the target pulse signal is equal to 4 times of the loop delay. The loop delay is represented by N*tck, and the effective pulse width of the target pulse signal is 4N*tck. If the effective pulse width is timed using an eight-divided clock signal, the timing result is (4N*tck) / (8*tck)=N / 2. At this time, the preset processing is to multiply the timing result by 2 to obtain the real loop delay measurement result N. The designer can set the preset processing according to the preselected M value and the frequency of the divided clock signal. Since M is an even number, the loop delay value of M times is also an even number, and more margin values can be obtained by using the divided clock signal.

[0088] In some embodiments, as shown in FIG. 5, the delay measurement circuit 10 further includes:

[0089] The control circuit 13 is configured to generate a measurement control signal of a first level when performing the loop delay measurement on the delay-locked loop 20, and generate a measurement control signal of a second level at other times. The measurement control signal can be used to indicate whether to start the loop delay measurement.

[0090] In some embodiments, the control circuit 13 receives a lock flag signal and a measurement end signal, generates the measurement control signal at the first level in response to the lock flag signal, and generates the measurement control signal at the second level in response to the measurement end signal; wherein the lock flag signal indicates that the delay-locked loop has completed phase locking. The prerequisite for the delay-locked loop to perform the loop delay measurement is that the delay-locked loop has completed locking, so as to ensure that the loop delay of the delay-locked loop is an integer multiple of the clock period. Therefore, the control circuit 13 can only generate the measurement control signal at the first level to instruct to start the loop delay measurement when the lock flag signal indicates that the delay-locked loop has completed locking. And the control circuit 13 generates the measurement control signal at the second level when the measurement end signal indicates that the loop delay measurement has been completed.

[0091] In some embodiments, as shown in FIG. 6, the control circuit includes:

[0092] The eighth flip-flop 131 receives the reference clock signal REFCLK at the clock terminal, receives the lock flag signal LOCKFLAG at the data terminal, outputs the measurement control signal FREEZE at the output terminal, and receives the measurement end signal LM_FINISH at the reset terminal. The measurement control signal FREEZE is generated by sampling the LOCKFLAG with the REFCLK, which is beneficial to the timing accuracy of subsequent processing. The eighth flip-flop 131 can be a D flip-flop.

[0093] In some embodiments, as shown in FIG. 5, the delay measurement circuit 10 further includes:

[0094] The selection circuit 14 is electrically connected to the loop 21 of the delay-locked loop 20, and is configured to select to input the loop flag signal to the loop 21 of the delay-locked loop 20 when the loop delay of the delay-locked loop 20 is measured, and select to input the reference clock signal to the loop 21 of the delay-locked loop 20 at other times.

[0095] In some embodiments, as shown in FIG. 7, the selection circuit 14 can include a multiplexer 141. The multiplexer 141 receives the reference clock signal REFCLK at the first terminal, receives the loop flag signal loop_flag at the second terminal, and receives the measurement control signal FREEZE at the control terminal. When the measurement control signal FREEZE is at the first level, the multiplexer 141 selects to output the loop flag signal loop_flag as the loop input signal Loop_IN. When the measurement control signal FREEZE is at the second level, the multiplexer 141 selects to output the reference clock signal REFCLK as the loop input signal Loop_IN.

[0096] In some embodiments, as shown in FIG. 7, the loop flag generation circuit 11 includes:

[0097] The initial flag generation circuit 111 is configured to generate an initial loop flag signal 1st flag in response to the measurement control signal FREEZE changing from the second level to the first level after waiting for a preset period; when the working frequency of the delay-locked loop 20 is greater than a preset frequency, the preset period is a first value, when the working frequency of the delay-locked loop is less than or equal to the preset frequency, the preset period is a second value, and the first value is greater than the second value.

[0098] The logic processing circuit 112 is electrically connected to the loop 21 of the delay-locked loop and is configured to receive a signal FBCLK from the feedback end of the loop 21 and perform inverting processing on the FBCLK, and perform AND logic processing on the inverting-processed signal and the initial loop flag signal 1st flag to generate a loop flag signal loop_flag.

[0099] It can be understood that the initial flag generation circuit 111 generates the initial loop flag signal 1st flag after waiting for a period of time after the FREEZE signal indicates that the loop delay measurement is started, so as to empty the clock pulses that have entered the loop before the measurement starts, ensure that the subsequent target pulse signal is not affected by the clock pulses that have entered the loop before the measurement starts, and finally ensure the accuracy of the delay measurement. When the working frequency of the DLL is high, the value of 1tck is small, and a large number of clock cycles need to be waited for to empty the clock pulses that have entered the loop before the measurement starts. When the working frequency of the DLL is low, the value of 1tck is large, and a small number of clock cycles need to be waited for to complete the emptying operation. In this way, it can be ensured that a long waiting time will not be consumed at low frequencies, so as to cause the overall working time of the DLL to exceed the timeout. For example, when the working frequency of the DLL is greater than a preset frequency, 32*tck can be waited for to empty the loop, and when the working frequency of the DLL is less than or equal to the preset frequency, 16*tck can be waited for to empty the loop.

[0100] The logic processing circuit 112 sends the initial loop flag signal 1st flag, i.e., the first flag bit, into the DLL loop, and when the first flag bit is output from the feedback end FBCLK, the first flag bit is inverted once, and it is considered that the first flag bit is delayed by N*tck, i.e., one loop delay. The inverted flag bit is sent into the DLL loop again for the next loop delay. When the flag bit reaches the feedback end of the DLL loop for the Mth time, i.e., after experiencing M loop delays, the flag bit is no longer sent into the DLL loop, and the delay experienced by the flag bit is M*N*tck.

[0101] In some embodiments, as shown in FIG. 7, the loop flag generation circuit 11 further includes:

[0102] The target pulse generation circuit 113 is configured to count the change edges of the loop flag signal loop_flag, start generating the active pulse of the target pulse signal 4N_PULSE in response to the first change edge of the loop flag signal loop_flag, end the active pulse of the target pulse signal 4N_PULSE in response to the M+1th change edge of the loop flag signal loop_flag, and generate the measurement end signal LM_FINISH in response to the end of the active pulse of the target pulse signal 4N_PULSE.

[0103] It can be understood that the first change edge of the loop flag signal loop_flag is the time when the loop flag starts to enter the loop. The M+1th change edge of the loop flag signal loop_flag is the time when the loop flag signal loop_flag is output from the feedback end after the loop flag signal loop_flag circulates M times in the loop. Then the time difference between the first change edge and the M+1th change edge of the loop flag signal loop_flag is M times of the loop delay, i.e. M*N*tck. Therefore, the active pulse width of the target pulse signal 4N_PULSE generated in response to the first change edge and the M+1th change edge of the loop flag signal loop_flag is also equal to M*N*tck. When the active pulse of the target pulse signal 4N_PULSE ends, the measurement end signal LM_FINISH is generated, indicating that the loop delay measurement ends, and timely ending the measurement can avoid wasting the measurement time and power consumption.

[0104] In some embodiments, as shown in FIG. 7, the initial flag generation circuit 111 includes:

[0105] The first selector 1111 is configured to receive the frequency characteristic signal TCCDL_HF, the first divided clock signal DIV8_CK and the second divided clock signal DIV4_CK, select the first divided clock signal DIV8_CK and output the timing clock signal DIVCLK when the frequency characteristic signal TCCDL_HF indicates that the working frequency of the delay-locked loop 20 is greater than the preset frequency, and select the second divided clock signal DIV4_CK and output the timing clock signal DIVCLK when the frequency characteristic signal TCCDL_HF indicates that the working frequency of the delay-locked loop 20 is less than or equal to the preset frequency; the frequency of the second divided clock signal DIV4_CK is higher than the frequency of the first divided clock signal DIV8_CK;

[0106] A first flip-flops in cascade 1112, configured as that the clock end of each first flip-flop receives the timing clock signal DIVCLK, the data end of the first first flip-flop receives the measurement control signal FREEZE, the data end of each first flip-flop after the first first flip-flop is connected with the output end of the first flip-flop in the last stage, and the output end of the last first flip-flop outputs the initial loop flag signal 1st flag, wherein A is an integer greater than 1.

[0107] It can be understood that the data terminal of the first stage of the first flip-flop receives the measurement control signal FREEZE, and the output terminal of the last stage of the first flip-flop outputs the initial loop flag signal 1st flag, so that the initial loop flag signal 1st flag is generated after a period of time after the FREEZE signal represents that the loop delay measurement is started, and the clock pulses that have entered the loop before the measurement is started are emptied. In FIG. 7, three cascaded first flip-flops are shown when A is equal to 3, so that the initial loop flag signal 1st flag is output from the third stage of the first flip-flop after the first stage of the first flip-flop samples the FREEZE signal changing from the second level to the first level, and a period of time of two clock signals DIVCLK is waited. Based on the first selector 1111, the clock signal DIVCLK can be selected from two frequency-divided clock signals with different frequencies. When the working frequency of the DLL is high, the value of 1tck is small, and a large number of clock periods need to be waited before the clock pulses that have entered the loop before the measurement is started are emptied, so the first frequency-divided clock signal DIV8_CK with a lower frequency and a longer clock period is selected as the clock signal DIVCLK. When the working frequency of the DLL is low, the value of 1tck is large, and a small number of clock periods need to be waited before the clock pulses that have entered the loop before the measurement is started are emptied, so the second frequency-divided clock signal DIV4_CK with a higher frequency and a shorter clock period is selected as the clock signal DIVCLK. Taking the case where A is equal to 3, the first frequency-divided clock signal DIV8_CK is obtained by dividing the REFCLK by 8, and the second frequency-divided clock signal DIV4_CK is obtained by dividing the REFCLK by 4 as an example. Since the REFCLK is generated by dividing the REFCLK by 2, the clock period of the REFCLK is 2tck, so the period of the first frequency-divided clock signal DIV8_CK is 16tck, and the period of the second frequency-divided clock signal DIV4_CK is 8tck. When the working frequency of the DLL is high, the period of the clock signal DIVCLK is 16tck, so the initial loop flag signal 1st flag is output from the third stage of the first flip-flop after 32tck is waited. When the working frequency of the DLL is low, the period of the clock signal DIVCLK is 8tck, so the initial loop flag signal 1st flag is output from the third stage of the first flip-flop after 16tck is waited. The frequency representation signal TCCDL_HF is used to represent the working frequency of the memory, that is, the working frequency of the DLL. The signal can be obtained by judging the CAS to CAS Delay (CCDL) set in the memory. Generally, the higher the working frequency of the memory, the larger the value of the CCDL, so the working frequency of the memory can be obtained by the value of the CCDL, and then the frequency representation signal is generated. The first flip-flop 1112 can be a D flip-flop.In practical applications, the designer can flexibly select the value of A, the frequencies of the first divided clock signal and the second divided clock signal according to the needs, as long as the purpose of emptying the loop and not wasting test time can be achieved.

[0108] In some embodiments, as shown in FIG. 5, the delay measurement circuit 10 further comprises:

[0109] The frequency divider 15 is configured to receive the reference clock signal REFCLK, perform frequency division processing on the reference clock signal REFCLK, and generate a plurality of divided clock signals, including at least the first divided clock signal DIV8_CK and the second divided clock signal DIV4_CK.

[0110] In some embodiments, as shown in FIG. 8, the frequency divider 15 comprises:

[0111] The second flip-flop 151 has its clock terminal receiving the reference clock signal REFCLK, and has its data terminal connected to its inverted output terminal;

[0112] The third flip-flop 152 has its clock terminal connected to the output terminal of the second flip-flop 151, has its data terminal connected to its inverted output terminal, and has its output terminal outputting the second divided clock signal DIV4_CK, the clock period of the second divided clock signal DIV4_CK being 4 times that of the reference clock signal REFCLK;

[0113] The fourth flip-flop 153 has its clock terminal connected to the output terminal of the third flip-flop 152, has its data terminal connected to its inverted output terminal, and has its output terminal outputting the first divided clock signal DIV8_CK, the clock period of the first divided clock signal DIV8_CK being 8 times that of the reference clock signal REFCLK.

[0114] In this way, the divided clock signals required by the initial flag generation circuit 111 and the counting circuit 12 can be generated. In practical applications, the designer can also add flip-flops according to the needs to obtain more divided clock signals. The second flip-flop, the third flip-flop and the fourth flip-flop can be selected to be D flip-flops.

[0115] In some embodiments, as shown in FIG. 7, the target pulse generation circuit 113 comprises:

[0116] The fifth flip-flop 1131 has its clock terminal receiving the loop flag signal loop_flag, and has its data terminal connected to its inverted output terminal;

[0117] The sixth flip-flop 1132 has its clock terminal connected to the output terminal of the fifth flip-flop 1131, has its data terminal connected to its inverted output terminal, and has its output terminal outputting the target pulse signal 4N_PULSE;

[0118] The seventh flip-flop 1133 receives the inverted signal of the target pulse signal 4N_PULSE at its clock terminal, receives the power supply signal VDD at its data terminal, and outputs the measurement end signal LM_FINISH at its output terminal;

[0119] In the example of FIG. 7, M equals 4, and the loop flag signal loop_flag loops 4 times in the loop. When the initial loop flag signal 1st flag is generated, i.e., the first flag bit is generated, the loop flag signal loop_flag has a first rising edge, and the fifth flip-flop 1131 and the sixth flip-flop 1132 both output high level, so that the target pulse signal 4N_PULSE outputs high level. The first flag bit is sent into the DLL loop, and after being delayed by the DLL loop, the first flag bit is fed back to the loop flag generation circuit 11 from the feedback terminal FBCLK, and the second flag bit 2nd flag is obtained by inverting the first flag bit, and the second flag bit 2nd flag is sent into the DLL loop again. At this time, the clock terminal of the fifth flip-flop 1131 receives the falling edge of the loop flag signal loop_flag, so that the output of the fifth flip-flop 1131 and the sixth flip-flop 1132 does not change. When the second flag bit 2nd flag is output from the feedback terminal of the DLL loop, the third flag bit 3rd flag is obtained by inverting the second flag bit 2nd flag, and at this time, the clock terminal of the fifth flip-flop 1131 receives the rising edge of the loop flag signal loop_flag, so that the fifth flip-flop 1131 outputs low level, and the output of the sixth flip-flop 1132 remains unchanged. In this way, when the fourth flag bit 4th flag is output from the feedback terminal of the DLL loop, the output of the sixth flip-flop 1132 becomes low level, i.e., the target pulse signal 4N_PULSE output becomes low level. Therefore, the effective pulse width of the target pulse signal 4N_PULSE is equal to 4 times the DLL loop delay. Through this method, the M times loop delay value is embodied in the effective pulse width of the target pulse signal. When the target pulse signal 4N_PULSE output becomes low level, its inverted signal becomes high level, and the measurement end signal LM_FINISH is generated by the seventh flip-flop 1133 by sampling the power supply signal VDD at the rising edge of the inverted signal, indicating that the loop delay measurement operation can be ended at this time. The measurement end signal LM_FINISH resets the measurement control signal FREEZE, so that the FREEZE becomes the second level, and the loop flag signal loop_flag is no longer selected to enter the DLL loop, but the reference clock signal REFCLK is selected to enter the DLL loop.

[0120] In some embodiments, as shown in FIG. 9, the counting circuit 12 includes:

[0121] The delay adjustment circuit 121 is configured to receive the divided clock signal, delay the divided clock signal by a first adjustment time length to generate an adjusted divided clock signal LM_CKIN. The first adjustment time length is used to match the physical delay required for the loop flag generation circuit 11 to generate the target pulse signal 4N_PULSE. Because from the time when the measurement control signal FREEZE changes from the second level to the first level to the rising edge of the target pulse signal 4N_PULSE, there are physical delays of circuit elements such as logic processing circuits, flip-flops and other circuits in addition to the preset waiting period, which is an absolute delay value not in units of clock periods. Because the clock for generating the target pulse signal 4N_PULSE and the divided clock signal are both derived from the same clock source REFCLK, the divided clock signal is delayed by the first adjustment time length to match the physical delay, so as to ensure the timing accuracy of the target pulse signal 4N_PULSE.

[0122] The gating circuit 122 is configured to receive the adjusted divided clock signal LM_CKIN and the target pulse signal 4N_PULSE, and perform gating processing on the adjusted divided clock signal LM_CKIN by using the target pulse signal 4N_PULSE to generate a counting clock signal LM_CKOUT. The gating circuit 122 can be implemented by a logic circuit, as long as it can output a valid counting clock signal LM_CKOUT within the effective pulse width of the target pulse signal 4N_PULSE, and the circuit structure is not limited here.

[0123] The binary counter 123 is configured to count the clock pulses of the counting clock signal LM_CKOUT to generate a binary timing result. The 4-bit binary counter shown in FIG. 9 is composed of four D flip-flops 1231, 1232, 1233 and 1234, and four inverters 1235, 1236, 1237 and 1238, and the specific connection mode is shown in FIG. 9, which will not be repeated here. The binary counter counts the clock pulses of the counting clock signal LM_CKOUT to generate a binary timing result LM_BI<3:0>. The binary timing result can be directly obtained without the need for conversion by a decoding module, which saves the layout area and also saves the circuit power consumption.

[0124] In some embodiments, the preset processing includes shifting the timing result of the binary to obtain the loop delay measurement result according to the frequency of the divided clock signal and the value of M. For example, if M equals 4, i.e. the loop flag signal loops 4 times in the loop 21 of the delay-locked loop, the effective pulse width of the target pulse signal equals 4 times of the loop delay. If the effective pulse width is timed by the divided clock signal, the timing result is (4N*tck) / (8*tck)=N / 2. At this time, the preset processing is to multiply the timing result by 2, i.e. to shift the binary timing result to the left by 1 bit to obtain the real loop delay measurement result N. The designer can set the preset processing according to the pre-selected value of M and the frequency of the divided clock signal.

[0125] In some embodiments, the time difference between the time when the loop flag signal loop_flag loops once in the loop 21 of the delay-locked loop and the time when the reference clock signal REFCLK loops once in the loop 21 of the delay-locked loop is less than a first preset value. Because the loop flag signal loop_flag entering the DLL loop needs additional logic gate circuits, such as the logic processing circuit 112 and the selection circuit 14, which will cause additional delay, it is necessary to match the delay of REFCLK and loop_flag in the DLL loop, i.e. the absolute value of the delay difference between them is less than the first preset value, so as not to affect the result of the loop delay measurement.

[0126] Referring to FIG. 10, a signal waveform diagram of the delay measurement circuit is shown. In this example, the loop delay of the DLL is 6*tck, and N=6. M is 4, i.e. the loop flag signal loops 4 times in the loop 21 of the delay-locked loop. The external clock signal CK_t and the reference clock signal REFCLK are shown first. The clock period of CK_t is tck, and the clock period of REFCLK is 2*tck because REFCLK is the result of dividing CK_t by 2. The second divided clock signal DIV4_CK is generated by dividing REFCLK, and the clock period of DIV4_CK is 8*tck. In this example, the working frequency of the DLL is less than or equal to the preset frequency, and A=3. Therefore, the second divided clock signal DIV4_CK is used to sample the measurement control signal FREEZE. In response to the measurement control signal FREEZE changing from the second level to the first level, the initial loop flag signal 1st flag is generated after a waiting period of 16*tck. In this example, the first level is high, and the second level is low. In response to the initial loop flag signal changing to high, the first rising edge of the loop flag signal loop_flag is generated, i.e. the first flag bit. The first flag bit is input into the DLL loop, and after the loop delay, the first flag bit is fed back to the loop flag generation circuit 11 from the feedback end FBCLK. After being inverted, the second flag bit 2nd flag is obtained, i.e. the first falling edge of the loop flag signal loop_flag. The second flag bit is input into the DLL loop again, and the process is repeated 4 times. Loop_IN is the output of the selection circuit, and during the loop measurement, Loop_IN is the loop test signal loop_flag. According to the working principle of the target pulse generation circuit 113 described above, in response to the first changing edge of the loop flag signal loop_flag, i.e. the first flag bit 1st flag, the target pulse signal 4N_PULSE changes from low to high. In response to the fourth changing edge of FBCLK after the generation of the first flag bit, i.e. the fifth changing edge of loop_flag, the target pulse signal 4N_PULSE changes from high to low, and the effective pulse ends. The width of the effective pulse is 4*N*tck. The delay adjustment circuit 121 receives the second divided clock signal DIV4_CK as the divided clock signal used subsequently. The second divided clock signal DIV4_CK is delayed by a first adjustment time Tgen_mch to generate the adjusted divided clock signal LM_CKIN. As described above, from the measurement control signal FREEZE changing from low to high to the rising edge of the target pulse signal 4N_PULSE, there is a physical delay of the circuit elements in addition to the waiting period of 16*tck. The physical delay is represented as T4gen. Ideally, Tgen_mch is used to match T4gen, and the best case is that Tgen_mch is equal to T4gen.But in practice, as long as T4gen-Tgen_mch<4*tck, it can be guaranteed that the subsequent counting will not be wrong. So the margin value here is 4tck, which is 4 times larger than the previous scheme. After the gating circuit 122, only when the target pulse signal 4N_PULSE is high, the counting clock signal LM_CKOUT is output. The number of cycles of LM_CKOUT is counted to get LM_BI<3:0>=0011. According to the previous analysis, the left shift of this binary timing result by 1 bit can get the real loop delay measurement result as 6. The time for the loop flag signal loop_flag to circulate once in the loop 21 of the delay-locked loop is Tloopflag2fb, and the time for the reference clock signal REFCLK to circulate once in the loop 21 of the delay-locked loop is Tref2fb. It needs to satisfy |Tloopflag2fb-Tref2fb|<1*tck, so as to guarantee that the final delay measurement result will not be wrong. So the first preset value here should be 1 clock cycle. Here, the same logic gate count can be set when REFCLK and loop_flag enter the DLL loop to achieve this.

[0127] In summary, the delay measurement circuit provided by the embodiments of the present disclosure has a larger measurement margin value, avoids the loop delay measurement error due to insufficient margin value at high clock frequency, and improves the accuracy of loop delay measurement.

[0128] In another embodiment of the present disclosure, referring to FIG. 11, a schematic diagram of a component structure of a memory 30 provided by the embodiments of the present disclosure is shown. As shown in FIG. 11, the memory 30 at least includes the aforementioned delay measurement circuit 10.

[0129] In some embodiments, the memory at least meets one of the following specifications: DDR3, DDR4, DDR5, DDR6, LPDDR3, LPDDR4, LPDDR5, LPDDR6.

[0130] The delay measurement circuit of the memory obtains the M times loop delay value in a loop M way by inputting the loop mark signal into the loop of the delay-locked loop, and the M times loop delay value is embodied by the effective pulse width of the target pulse signal, and the M times loop delay value is timed by the frequency division clock signal. In this way, the loop measurement circuit has a larger measurement margin value, avoids the loop delay measurement error caused by insufficient margin value under high clock frequency, and improves the accuracy of loop delay measurement. Therefore, the required latency of memory data communication can be accurately realized, and the failure of data transmission is avoided.

[0131] The above merely describes preferred embodiments of the present disclosure, but does not limit the protection scope of the present disclosure. It should be noted that in the present disclosure, the terms "comprise", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of another identical element in the process, method, article or device including the element. The above sequence number of the embodiments of the present disclosure is only for description, and does not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method or device embodiments. The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A delay measurement circuit (10), characterized by, Applied to a delay-locked loop (20), comprising: a loop mark generating circuit (11) electrically connected with a loop of the delay-locked loop, configured to generate a loop mark signal and input the loop mark signal into the loop of the delay-locked loop when measuring a loop delay of the delay-locked loop, generate a measurement end signal after the loop mark signal circulates in the loop of the delay-locked loop for M times, and generate a target pulse signal, wherein an effective pulse width of the target pulse signal is equal to M times of the loop delay, and M is an even number greater than 1; a counting circuit (12) electrically connected with the loop mark generating circuit, configured to receive a divided clock signal, count the effective pulse width of the target pulse signal by using the divided clock signal to obtain a counting result, and perform preset processing on the counting result to obtain a loop delay measurement result of the delay-locked loop.

2. The delay measurement circuit (10) according to claim 1, characterized in that Further comprising: a control circuit (13) configured to generate a measurement control signal of a first level when measuring the loop delay of the delay-locked loop, and generate a measurement control signal of a second level at other times.

3. The delay measurement circuit (10) according to claim 1, characterized in that Further comprising: a selection circuit (14) electrically connected with the loop of the delay-locked loop, configured to select the loop mark signal to be input into the loop of the delay-locked loop when measuring the loop delay of the delay-locked loop; and input a reference clock signal into the loop of the delay-locked loop at other times.

4. The delay measurement circuit (10) according to claim 2, characterized in that The loop mark generating circuit comprises: an initial mark generating circuit (111) configured to generate an initial loop mark signal after waiting for a preset period in response to the measurement control signal changing from the second level to the first level, wherein the preset period is a first value when an operating frequency of the delay-locked loop is greater than a preset frequency, and the preset period is a second value when the operating frequency of the delay-locked loop is less than or equal to the preset frequency, and the first value is greater than the second value; a logic processing circuit (112) electrically connected with the loop of the delay-locked loop, configured to receive a signal from a feedback end of the loop and perform inverting processing on the signal, and perform AND logic processing on the inverting processed signal and the initial loop mark signal to generate the loop mark signal.

5. The delay measurement circuit (10) according to claim 4, characterized by The loop mark generating circuit further comprises: a target pulse generating circuit (113) configured to count variation edges of the loop mark signal, start generating an effective pulse of the target pulse signal in response to a first variation edge of the loop mark signal, end the effective pulse of the target pulse signal in response to an M+1th variation edge of the loop mark signal, and generate the measurement end signal in response to the end of the effective pulse of the target pulse signal.

6. The delay measurement circuit (10) according to claim 4, characterized by The initial mark generating circuit comprises: The first selector (1111) is configured to receive a frequency characteristic signal, a first frequency division clock signal and a second frequency division clock signal, select the first frequency division clock signal as a timing clock signal when the frequency characteristic signal indicates that the operating frequency of the delay-locked loop is greater than a preset frequency, select the second frequency division clock signal as the timing clock signal when the frequency characteristic signal indicates that the operating frequency of the delay-locked loop is less than or equal to the preset frequency, and the frequency of the second frequency division clock signal is higher than the frequency of the first frequency division clock signal; A first flip-flop (1112) is configured to receive the timing clock signal at the clock end of each first flip-flop, receive the measurement control signal at the data end of the first flip-flop, connect the data end of each first flip-flop after the first flip-flop with the output end of the first flip-flop of the previous stage, and output the initial loop flag signal at the output end of the last first flip-flop, wherein A is an integer greater than 1.

7. The delay measurement circuit (10) according to claim 6, characterized by Further comprising: A frequency divider (15) is configured to receive a reference clock signal, perform frequency division processing on the reference clock signal, and generate a plurality of frequency division clock signals, wherein the plurality of frequency division clock signals at least include the first frequency division clock signal and the second frequency division clock signal.

8. The delay measurement circuit (10) according to claim 7, characterized by The frequency divider includes: A second flip-flop (151) is configured to receive the reference clock signal at the clock end, and connect the data end with the inverted output end; A third flip-flop (152) is configured to connect the clock end with the output end of the second flip-flop, connect the data end with the inverted output end, and output the second frequency division clock signal at the output end, wherein the clock period of the second frequency division clock signal is 4 times the clock period of the reference clock signal; A fourth flip-flop (153) is configured to connect the clock end with the output end of the third flip-flop, connect the data end with the inverted output end, and output the first frequency division clock signal at the output end, wherein the clock period of the first frequency division clock signal is 8 times the clock period of the reference clock signal.

9. The delay measurement circuit (10) according to claim 5, characterized by The target pulse generation circuit includes: A fifth flip-flop (1131) is configured to receive the loop flag signal at the clock end, and connect the data end with the inverted output end; A sixth flip-flop (1132) is configured to connect the clock end with the output end of the fifth flip-flop, connect the data end with the inverted output end, and output the target pulse signal at the output end; A seventh flip-flop (1133) is configured to receive the inverted signal of the target pulse signal at the clock end, receive the power signal at the data end, and output the measurement end signal at the output end; Wherein, the M is equal to 4.

10. The delay measurement circuit (10) according to claim 2, characterized in that The control circuit receives a lock flag signal and the measurement end signal, generates a first level of measurement control signal in response to the lock flag signal, and generates a second level of measurement control signal in response to the measurement end signal; wherein the lock flag signal indicates that the delay-locked loop has completed phase locking.

11. The delay measurement circuit (10) according to claim 10, characterized by The control circuit includes: An eighth flip-flop (131) has a clock terminal receiving a reference clock signal, a data terminal receiving the lock flag signal, an output terminal outputting the measurement control signal, and a reset terminal receiving the measurement end signal.

12. The delay measurement circuit (10) according to claim 1, characterized by The counting circuit comprises: A delay adjustment circuit (121) configured to receive the divided clock signal, delay the divided clock signal by a first adjustment time length, and generate an adjusted divided clock signal; the first adjustment time length is used to match a physical delay required by the loop flag generation circuit to generate the target pulse signal; A gating circuit (122) configured to receive the adjusted divided clock signal and the target pulse signal, perform gating processing on the adjusted divided clock signal by using the target pulse signal, and generate a counting clock signal; A binary counter (123) configured to count clock pulses of the counting clock signal, and generate a binary timing result.

13. The delay measurement circuit (10) according to claim 12, characterized by The preset processing comprises: performing shift processing on the binary timing result according to a frequency of the divided clock signal and a value of the M, to obtain the loop delay measurement result.

14. The delay measurement circuit (10) according to claim 3, characterized by A difference between a time for the loop flag signal to circulate once in a loop of the delay-locked loop and a time for the reference clock signal to circulate once in the loop of the delay-locked loop is less than a first preset value.

15. A memory (30) characterized by: An electronic device comprising the delay measurement circuit (10) according to any one of claims 1-14.

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