Data storage apparatus, data storage system and data organization method used

Abstract

Disclosed in the present application are a data storage apparatus, a data storage system, and a data organization method used. The data storage apparatus comprises a memory controller, wherein the memory controller establishes a communication connection with a host system, and the memory controller is configured to: acquire parameter information of target data on the basis of a first instruction generated by the host system, wherein the parameter information comprises an original logical address, a target logical address and a data size of the target data; acquire the target data on the basis of the original logical address, and store the target data in a target physical address corresponding to the target logical address; and generate a second instruction and send same to the host system, so as to indicate that the execution of the first instruction is completed. In this way, the number of I / O operations performed by a data storage system during the execution of a data organization operation is reduced, and the memory controller independently completes the data organization operation, thereby improving the efficiency of data organization.

Description

Data storage device, data storage system and data arrangement method used TECHNICAL FIELD

[0001] The present application relates to a data management technology, in particular to a data storage device configured with a non-volatile memory, a data storage system and a data arrangement method used. BACKGROUND

[0002] Non-volatile memory refers to computer storage that does not lose stored data when the current is cut off, has the advantages of data non-volatility, power saving, small size and no mechanical structure, and is widely used in various electronic devices.

[0003] At present, when performing file system management (such as data arrangement operation) on a storage device, data reading, data writing back, LBA (Logic Block Address) modification and other operations need to be realized through a host system, which will occupy a lot of I / O time, so that the host system cannot interact with the device during this period.

[0004] Therefore, there is an urgent need for a data storage system, a memory controller and a data arrangement method used to solve the above problems. SUMMARY

[0005] The purpose of the present application is to solve the above problems by reducing the I / O times of the data storage system when performing data arrangement operation, and by the memory controller to complete the data arrangement operation, thereby improving the efficiency of data arrangement.

[0006] One or more embodiments of the present application provide a data storage device communicatively connected to a host system. The data storage device comprises: a rewritable non-volatile memory module comprising a plurality of memory dies, wherein each of the memory dies has a plurality of physical blocks, each of the physical blocks has a plurality of physical pages, and the plurality of physical pages correspond to a plurality of physical addresses, respectively; and a memory controller electrically connected to the rewritable non-volatile memory module, wherein the memory controller receives a first instruction from the host system to obtain parameter information of target data, wherein the first instruction is generated by the host system, and the parameter information comprises original logical address, target logical address and data size of the target data; the memory controller acquires the target data according to the original logical address and stores the target data into a target physical address corresponding to the target logical address; and the memory controller generates a second instruction and sends the second instruction to the host system, wherein the second instruction is used to indicate that the data storage device has completed the first instruction.

[0007] In one or more embodiments of the present application, the memory controller obtains a target physical address corresponding to the target logical address via a logical-to-physical address table according to the target logical address; and reads the target data from the target physical address of the rewritable non-volatile memory module.

[0008] In one or more embodiments of the present application, the target read instruction and the target write instruction are wrapped into a general flash memory instruction to generate the first instruction.

[0009] In one or more embodiments of the present application, the first instruction further comprises a logical address replacement flag, the logical replacement flag is used to indicate whether to perform an address replacement operation, the address replacement operation is used to represent replacing the original logical address in the logical-to-physical address table with the target logical address, wherein before performing the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address, the memory controller determines whether to perform the address replacement operation according to the logical address replacement flag.

[0010] In one or more embodiments of the present application, the logical address replacement flag comprises a first value and a second value, and the determining whether to perform the address replacement operation according to the logical address replacement flag comprises: if the logical address replacement flag is the first value, the memory controller does not perform the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address, and performs the address replacement operation; and if the logical address replacement flag is the second value, the memory controller performs the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address, and does not perform the address replacement operation.

[0011] In one or more embodiments of the present application, the operation of replacing the original logical address in the logical-to-physical address table with the target logical address comprises: the memory controller obtains the target physical address corresponding to the target logical address via the logical-to-physical address table according to the target logical address; and the memory controller modifies the logical-to-physical address table to replace the original logical address mapped by the target physical address with the target logical address.

[0012] In one or more embodiments of the present application, wherein the storage device further comprises a buffer memory, and wherein the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address comprises: the memory controller obtaining the original physical address corresponding to the original logical address via the logical-to-physical address table according to the original logical address; the memory controller reading the target data from the original physical address into the buffer memory; the memory controller writing the target data in the buffer memory into the target physical address of the rewritable non-volatile memory module; and the memory controller updating the logical-to-physical address table according to the target logical address and the target physical address.

[0013] In one or more embodiments of the present application, wherein the first instruction further comprises a group tag, and wherein the memory controller determines that the target data belongs to one of a plurality of data of a target data group, a total number of the plurality of data, and a target order of the target data in the target data group according to the group tag; the memory controller allocates a plurality of continuous physical addresses corresponding to the plurality of data for storing the plurality of data according to the target data group and the total number of the plurality of data, wherein a total number of the plurality of physical addresses is equal to the total number of the plurality of data, and the plurality of data of the target data group can be read from the plurality of physical addresses via a sequential read operation; and the memory controller selects the target physical address from the plurality of physical addresses for storing the target data according to the target order.

[0014] In one or more embodiments of the present application, wherein the first instruction further comprises a verification key corresponding to the target data, and wherein the memory controller determines whether the first instruction is legal according to the verification key before performing the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address, wherein if the first instruction is determined to be legal, the memory controller performs the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address; and if the first instruction is determined to be illegal, the memory controller does not perform the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address, and sends an error message corresponding to the first instruction to the host system.

[0015] One or more embodiments of the present application provide a data storage system, comprising: a data storage device configured with a rewritable non-volatile memory module including a plurality of memory dies, wherein each of the memory dies has a plurality of physical blocks, and each of the physical blocks has a plurality of physical pages corresponding to a plurality of physical addresses, respectively; and a host system communicatively connected to the data storage device. The data storage device receives a first instruction from the host system to obtain parameter information of target data, wherein the first instruction is generated by the host system, and the parameter information includes an original logical address, a target logical address and a data size of the target data. The data storage device obtains the target data according to the original logical address and stores the target data into a target physical address corresponding to the target logical address. The data storage device generates a second instruction and sends the second instruction to the host system, wherein the second instruction is used to indicate the data storage device to complete the first instruction.

[0016] One or more embodiments of the present application provide a data arrangement method, comprising: receiving a first instruction from a host system to obtain parameter information of target data, wherein the first instruction is generated by the host system, and the parameter information includes an original logical address, a target logical address and a data size of the target data; obtaining the target data according to the original logical address and storing the target data into a target physical address corresponding to the target logical address; and generating a second instruction and sending the second instruction to the host system, wherein the second instruction is used to indicate a data storage device to complete the first instruction.

[0017] Based on the above, the data storage device, the data storage system and the data arrangement method provided by the embodiments of the present application can process the data address arrangement operation of the target data corresponding to the first instruction at the storage device end according to the first instruction after receiving the first instruction issued by the host system, and respond to the host system that the first instruction has been completed after completing the data address arrangement operation, so as to reduce the problem of too high I / O frequency of the target data accessed between the host system and the storage device caused by the data arrangement operation in the prior art, and greatly avoid the busy state of I / O occupied caused by the host system needing to access / process the address migration of the target data, thereby effectively improving the data arrangement efficiency and work efficiency of the data storage system and the memory controller. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.

[0019] Fig. 1 is a block diagram of a data storage system according to an embodiment of the present application;

[0020] Fig. 2 is a flowchart of a data arrangement method according to an embodiment of the present application;

[0021] Fig. 3 is a schematic diagram of the operation of a data storage system according to an embodiment of the present application;

[0022] Fig. 4 is a schematic diagram of arrangement target data of a data storage system according to an embodiment of the present application;

[0023] Fig. 5 is a schematic diagram of arrangement target data of a data storage system according to another embodiment of the present application;

[0024] Fig. 6 is a schematic diagram of generating a first instruction according to an embodiment of the present application;

[0025] Fig. 7 is a schematic diagram of replacing a logical address of target data by a logical-to-physical address table according to an embodiment of the present application;

[0026] Fig. 8 is a schematic diagram of replacing a logical address of target data by a physical-to-logical address table according to an embodiment of the present application.

[0027] BRIEF DESCRIPTION OF DRAWINGS 10: host system 20: storage device 211: first processor 110: second processor 120: host memory 130: data transfer interface circuit 210: memory controller 212: data management circuit 213: memory interface control circuit 214: buffer memory 220: re-writable non-volatile memory module 230: connection interface circuit S210, S220, S230, S240, S250: flow steps of a data arrangement method A41-A46, A51, A61-A63, A71, A72, A81: arrow DCI, DCI1, DCI2, DCI3: first instruction TB71, TB72: logical-to-physical address table TB81, TB82: physical-to-logical address table DETAILED DESCRIPTION

[0028] Reference will now be made in detail embodiments of the application examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0029] Figure 1 is a block diagram of a data storage system according to an embodiment of the present application. Referring to Figure 1, the data storage system includes a host system 10 and a storage device 20. The host system 10 is, for example, a personal computer, a notebook computer, a server. The host system 10 includes a processor 110 (also referred to as a second processor) and a host memory 120, a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled to (also referred to as electrically connected to) the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120 and the data transfer interface circuit 130 are coupled to each other by a system bus. In this embodiment, the processor 110, the host memory 120 and the data transfer interface circuit 130 can be disposed on a host board of the host system 10.

[0030] The storage device 20 (also referred to as a data storage device) includes a storage controller 210, a rewritable non-volatile memory module 220 and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also referred to as a first processor), a data management circuit 212 and a memory interface control circuit 213.

[0031] In this embodiment, the host system 10 is coupled to the storage device 20 by the data transfer interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transfer interface circuit 130.

[0032] In the present embodiment, the number of data transfer interface circuits 130 can be one or more. Through the data transfer interface circuits 130, the host board can be coupled to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a Near Field Communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy memory storage device (e.g., iBeacon), or the like memory storage device based on various wireless communication technologies. In addition, the host board can also be coupled to various I / O devices such as a Global Positioning System (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, and the like via a system bus.

[0033] In the present embodiment, the data transfer interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In addition, data transfer between the data transfer interface circuit 130 and the connection interface circuit 230 is performed using the Non-Volatile Memory express (NVMe) communication protocol.

[0034] In addition, in another embodiment, the connection interface circuit 230 can be packaged in a chip with the memory controller 210, or the connection interface circuit 230 can be disposed outside a chip containing the memory controller 210.

[0035] In the present embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in the present embodiment, the host memory 120 can be a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), or the like. However, it must be understood that the present application is not limited thereto, and the host memory 120 can also be other suitable memory.

[0036] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in a hardware type or a firmware type and perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 220 according to instructions of the host system 10.

[0037] In more detail, the processor 211 in the memory controller 210 is a hardware with computing capability, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with a plurality of control instructions / program codes, and when the storage device 20 is operated, the control instructions / program codes are executed to perform operations such as writing, reading and erasing data. In addition, in the present embodiment, the control instructions / program codes can also be executed to perform data reading operations to implement the data reading method provided by the present application. The control instructions / program codes corresponding to the data reading method can also be implemented as a circuit unit in hardware form to implement the data reading method provided by the present application.

[0038] It is worth mentioning that, in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a micro-processor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar circuit components, and the present application is not limited thereto.

[0039] In the present embodiment, as described above, the memory controller 210 further includes the data management circuit 212 and the memory interface control circuit 213. It should be noted that the operations performed by the components of the memory controller 210 can also be considered as operations performed by the memory controller 210.

[0040] The data management circuit 212 is coupled to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is configured to accept instructions from the processor 211 to perform data transfer. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 and the read data is written into the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., a write operation is performed according to a write instruction from the host system 10). For another example, data is read from one or more physical units of the rewritable non-volatile memory module 220 (the data can be read from one or more memory cells of the one or more physical units) via the memory interface control circuit 213 and the read data is written into the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 can be integrated into the processor 211.

[0041] The memory interface control circuit 213 is configured to accept instructions from the processor 211 to perform write (also referred to as programming), read or erase operations on the rewritable non-volatile memory module 220 in cooperation with the data management circuit 212.

[0042] In addition, data to be written into the rewritable non-volatile memory module 220 is converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 sends corresponding instruction sequences to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform corresponding operations. For example, the instruction sequences can include write instruction sequences to instruct writing of data, read instruction sequences to instruct reading of data, erase instruction sequences to instruct erasing of data, and corresponding instruction sequences to instruct various memory operations. The instruction sequences can include one or more signals or data on a bus. The signals or data can include instruction codes or program codes. For example, in a read instruction sequence, identification codes of the read, memory addresses, physical addresses, etc. are included.

[0043] In addition, the memory controller 210 establishes a logical to physical address table and a physical to logical address table to record the address mapping relationship between the logical units (e.g., logical blocks, logical pages, or logical columns) and the physical units (e.g., physical erase units / physical blocks, physical pages, physical columns) configured to the rewritable non-volatile memory module 220. In other words, the memory controller 210 can look up the physical unit mapped by a logical unit (e.g., look up the physical page mapped by a logical page; look up the physical address mapped by a logical address) through the logical to physical address table (also referred to as a mapping table), and the memory controller 210 can look up the logical unit mapped by a physical unit (e.g., look up the logical page mapped by a physical page; look up the logical address mapped by a physical address) through the physical to logical address table. However, the above technical concept about the mapping between the logical address and the physical address is a common technical means for those skilled in the art and is not the technical solution to be described in the present application, and thus will not be described herein.

[0044] In an embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is coupled to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data used to manage the storage device 20, so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 216.

[0045] The rewritable non-volatile memory module 220 is coupled to the memory controller 210 (the memory interface control circuit 213) and is used to store the data written by the host system 10.

[0046] In the present embodiment, the rewritable non-volatile memory module 220 has a plurality of word lines, wherein each of the plurality of word lines is coupled to a plurality of storage units, also referred to as columns (also referred to as physical columns). The plurality of columns on the same word line forms a physical program unit (also referred to as a physical page). Each physical page corresponds to a physical address, which is used to record the location of the data stored in the physical page. In addition, a plurality of physical pages can form a physical block (also referred to as a physical erase unit). Each of the plurality of memory dies of the rewritable non-volatile memory module 220 has a plurality of physical blocks. It should be noted that the present application is not limited to the size of each physical page and logical page.

[0047] FIG. 2 is a flow chart of a data arrangement method according to an embodiment of the present application. FIG. 3 is a schematic diagram of the operation of a data storage system according to an embodiment of the present application.

[0048] Specifically, referring to FIG. 2 and FIG. 3, the data arrangement method according to the present application comprises the following steps:

[0049] S210, the memory controller 210 receives a first instruction from the host system 10 to obtain parameter information of target data.

[0050] The first instruction is generated by the host system 10, and the parameter information comprises the original logical address, target logical address and data size of the target data.

[0051] For example, as described in FIG. 1, the host system 10 is coupled to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operation.

[0052] Specifically, after the host system 10 obtains the target data, the original logical address, target logical address and data size corresponding to the target data, a first instruction corresponding to the target data is generated to instruct the memory controller 210 to complete the data arrangement operation. Further, the first instruction is sent to the memory controller 210.

[0053] In an embodiment, the data arrangement operation is, for example, a disk arrangement operation or a file archive arrangement operation performed by the operating system (OS) of the host system 10. The disk arrangement operation is used to change the data that should be stored sequentially from a fragmented storage state to a sequential storage state. The file archive arrangement operation is used to copy or move multiple pieces of data belonging to the same directory or file archive to other locations on the disk.

[0054] That is, the disk arrangement operation or the file archive arrangement operation changes the multiple pieces of data with read-write correlation stored in multiple non-sequential logical units to multiple sequential logical units.

[0055] S220, the memory controller 210 obtains the target data according to the original logical address and stores the target data in the target physical address corresponding to the target logical address.

[0056] For example, the memory controller 210 completes the data arrangement operation according to the received first instruction.

[0057] S230, the memory controller 210 generates a second instruction and sends the second instruction to the host system 10.

[0058] The second instruction is used to indicate the data storage device 20 to execute the first instruction.

[0059] Thus, by the storage device 20 proposed in the embodiments of the present application, the memory controller 210 performs the data arrangement operation according to the received first instruction, and sends the second instruction to the host system 10 to indicate that the current data arrangement operation is completed after the memory controller 210 executes the first instruction. Thus, the number of I / Os of the data storage system in performing the data arrangement operation can be reduced, and the data arrangement efficiency is improved. It should be noted that in an embodiment, the memory controller 210 can give corresponding response information to the status query instruction from the host system 10 to indicate that the storage device 20 executes the first instruction.

[0060] FIG. 6 is a schematic diagram of generating a first instruction according to an embodiment of the present application.

[0061] For example, referring to FIG. 6, in this example, the host system 10 (e.g., the second processor 110) identifies three pieces of target data TD1, TD2, TD3 to be arranged due to performing the data arrangement operation, which are respectively stored in logical addresses "LBA101", "LBA103", "LBA107" (also referred to as original logical addresses). In addition, it is assumed that the host system 10 also determines that the three pieces of target data TD1-TD3 should be stored to sequentially other three logical addresses "LBA201", "LBA202", "LBA203" (also referred to as target logical addresses) according to the data arrangement operation. In addition, the host system 10 also identifies the data size of each of the three pieces of target data TD1-TD3 (for the convenience of description, it is assumed that the data size of each of the three pieces of target data TD1-TD3 is one program unit).

[0062] In an embodiment, the host system 10 further sets that the three pieces of target data TD1-TD3 belong to the same target data group DG1.

[0063] In the example of FIG. 6, as shown by an arrow A61, the host system 10 generates a target read instruction according to the original logical address "LBA101" and the data size of the target data TD1, generates a target write instruction according to the target logical address "LBA201" and the data size of the target data TD1, and generates a first instruction DCI1 according to the target read instruction and the target write instruction.

[0064] In an embodiment, the host system 10 packages the target read instruction and the target write instruction into a universal flash storage (UFS) instruction to generate the first instruction.

[0065] Similarly, as shown by arrow A62, the host system 10 generates the first instruction DCI2 according to the original logical address "LBA103", the target logical address "LBA202" and the data size of the target data TD2; as shown by arrow A63, the host system 10 generates the first instruction DCI3 according to the original logical address "LBA107", the target logical address "LBA203" and the data size of the target data TD3.

[0066] After the first instructions DCI1-DCI3 are generated, the host system 10 sends (issues) the first instructions DCI1-DCI3 to the storage device 20, so that the storage device 20 performs corresponding arrangement on the stored target data according to the first instructions DCI1-DCI3.

[0067] In this way, by the method of the embodiment of the present application, the target read instruction and the target write instruction are packaged into the UFS instruction to generate the first instruction, and then the memory controller 210 can be directly instructed by the first instruction to read the data and modify the logical address by itself, so as to finally save the I / O resource and improve the efficiency of the system file arrangement.

[0068] It is worth mentioning that, in an embodiment, the generated first instruction can further include a group marker. The group marker is used to record which target data group the corresponding target data belongs to, and is also used to record the order (also referred to as target order) of the corresponding target data in the target data group.

[0069] That is, after receiving the first instruction containing the group marker, the memory controller 210 can determine, according to the group marker, that the target data belongs to the target data group and the target order of the target data in the target data group. In addition, the memory controller 210 further specifies the target physical address according to the target data group and the target order, so that the plurality of target data of the same target data group can be stored in the sequential plurality of physical addresses, thereby facilitating the subsequent sequential reading operation on these data.

[0070] In this way, by the method proposed in the embodiment, the plurality of target physical addresses used to store the plurality of target data belonging to the target data group are continuous, so that the plurality of target data of the target data group can be continuously read from the plurality of target physical addresses through the sequential reading operation.

[0071] After receiving the first instruction, the memory controller 210 parses the received first instruction to obtain the original logical address, the target logical address and the data size corresponding to the target data. Then, the memory controller 210 moves the target data stored in the rewritable non-volatile memory module 220 from the original physical address corresponding to the original logical address to the target physical address corresponding to the target logical address. Finally, after the target data is stored to the target physical address, the memory controller 210 generates a second instruction to respond that the host system 10 has completed the first instruction.

[0072] By the method proposed in the embodiment, the memory controller 210 obtains the parameter information required by the data consolidation operation based on the received first instruction, and further completes the first instruction based on the parameter information, and finally generates a second instruction to respond that the current data consolidation operation of the host system 10 is completed. In this way, the I / O resources can be saved, the transmission time of the target data from the memory controller 210 to the host system 10 can be saved, and the efficiency of the system file consolidation can be improved.

[0073] Step S220 can be implemented in various ways, and the following is an example.

[0074] In an embodiment, the memory controller 210 uses the buffer memory 214 to temporarily store the target data read from the original physical address, and then writes the target data to the target physical address and updates to the target logical address.

[0075] FIG. 4 is a schematic diagram of consolidating target data of a data storage system according to an embodiment of the present application. Referring to FIG. 4, in the embodiment, the host system 10 transmits a first instruction DCI to the storage device 20 as shown by arrow A41. Then, the storage device 20 (e.g., the memory controller 210) parses the received first instruction DCI to obtain the original logical address, the target logical address and the data size corresponding to the target data.

[0076] Then, the memory controller 210 obtains the original physical address corresponding to the target data by querying the logical-to-physical address table according to the original logical address as shown by arrow A42. Then, the memory controller 210 reads the target data from the original physical address to the buffer memory 214 as shown by arrow A43. Then, the memory controller 210 writes the target data in the buffer memory 214 to the target physical address as shown by arrow A44. The memory controller 210 can determine the specific value of the target physical address by itself.

[0077] After the target data is written to the target physical address, the memory controller 210 updates the logical-to-physical address table to map the target logical address corresponding to the target data to the target physical address, as indicated by arrow A45. In one embodiment, the memory controller 210 also updates the physical-to-logical address table accordingly.

[0078] Finally, after the logical-to-physical address table is updated, the memory controller 210 responds to the host system 10 (e.g., sends a corresponding response signal (second command)) that the first command DCI has been executed, as indicated by arrow A46.

[0079] In another embodiment, the memory controller 210 modifies the logical-to-physical address table or the physical-to-logical address table directly to achieve the relocation of the data at the logical address (from the original logical address to the target logical address).

[0080] Fig. 5 is a diagram illustrating the relocation of target data in a data storage system according to another embodiment of the present application. Referring to Fig. 5, in this embodiment, the host system 10 sends a first command DCI to the storage device 20, as indicated by arrow A41. The storage device 20 (e.g., the memory controller 210) then parses the received first command DCI to obtain the original logical address, the target logical address and the data size corresponding to the target data. Next, the memory controller 210 obtains the original physical address corresponding to the target data by querying the logical-to-physical address table according to the original logical address, as indicated by arrow A42.

[0081] Next, the memory controller 210 modifies the logical-to-physical address table directly by writing the value of the original physical address to the physical address field mapped by the target logical address so as to map the target logical address to the original physical address, as indicated by arrow A51. In addition, the memory controller 210 deletes the value of the original physical address in the physical address field mapped by the original logical address.

[0082] Finally, after the logical-to-physical address table is updated, the memory controller 210 responds to the host system 10 (e.g., sends a corresponding response signal (second command)) that the first command DCI has been executed, as indicated by arrow A46.

[0083] It is worth mentioning that, by the above-mentioned manner, the logical address of the target data can be quickly modified from the original logical address to the target logical address without substantially relocating the target data, thereby avoiding the I / O occupation problem caused by handling the data relocation operation. In addition, since the modified logical address is based on the first command, the efficiency of the host system 10 when accessing the corresponding data will also be increased.

[0084] In one embodiment, the memory controller 210 can be instructed by a specific flag to determine whether to directly update the logical-to-physical address table or the physical-to-logical address table (without changing the physical address of the target data). This specific flag can also be referred to as a logical address replacement flag.

[0085] In one embodiment, the host system 10 can set the logical address replacement flag during the generation of the first instruction to determine which approach to use to implement the first instruction.

[0086] In more detail, if the logical address replacement flag is a first value (e.g., 1), the memory controller does not perform an operation to move the target data stored in the rewritable non-volatile memory module 220 from the original physical address corresponding to the original logical address to the target physical address corresponding to the target logical address; and

[0087] The memory controller 210 directly replaces the original logical address mapped by the original physical address corresponding to the target data in the logical-to-physical address table with the target logical address, and responds to the host system 10 that the first instruction has been completed.

[0088] FIG. 7 is a diagram illustrating the replacement of the logical address of the target data by the logical-to-physical address table, according to an embodiment of the present application. Referring to FIG. 7, a first instruction DCI1 is assumed to be parsed by the memory controller 210 to identify an original logical address "LBA101" and a target logical address "LBA201". In addition, it is further assumed that the first instruction DCI1 has a logical address replacement flag of a first value. Upon determining the logical address replacement flag, the memory controller 210 updates the logical-to-physical address table TB71 to the logical-to-physical address table TB72, as shown by arrow A71, in which the value "PBA123" of the original physical address corresponding to the original logical address "LBA101" is directly moved to the field of the physical address mapped by the target logical address "LBA201" (as shown by arrow A72). It should be noted that in this embodiment, the target data itself is not moved.

[0089] In one embodiment, the memory controller 210 further correspondingly modifies the physical-to-logical address table.

[0090] Figure 8 is a diagram illustrating updating a physical-to-logical address table to replace a logical address of target data according to an embodiment of the present application. Referring to Figure 8, continuing the example of Figure 7, assume that the memory controller 210 parses the first instruction DCI1 and identifies the original logical address "LBA101" and the target logical address "LBA201". Further, assume that the first instruction DCI1 has a logical address replacement flag of a first value. Upon detecting the logical address replacement flag, the memory controller 210 updates the physical-to-logical address table TB81 to TB82 as shown by arrow A71, where the value "LBA101" corresponding to the original logical address mapped by the original physical address "PBA123" is directly modified to the value "LBA201" corresponding to the target logical address, so that the original physical address of the target data is mapped to the target logical address. Note that in this embodiment, the target data itself is not moved.

[0091] On the other hand, if the logical address replacement flag is not the first value (e.g., a second value), the memory controller 210 does not implement the first instruction using the methods described in Figures 7 and 8.

[0092] In more detail, in one embodiment, if the logical address replacement flag is the second value (e.g., 0), in implementing the operation of moving the target data stored in the re- writable non-volatile memory module 220 from the original physical address corresponding to the original logical address to the target physical address corresponding to the target logical address, the memory controller 210 obtains the original physical address corresponding to the original logical address of the target data from the physical-to-logical address table; the memory controller 210 reads the target data from the original physical address to the buffer memory 214; the memory controller 210 writes the target data in the buffer memory 214 to the target physical address of the re- writable non-volatile memory module 220; and the memory controller 210 updates the physical-to-logical address table according to the target logical address and the target physical address (i.e., sets the physical address mapped by the target logical address in the physical-to-logical address table to the target physical address).

[0093] That is, if the logical address replacement flag is the second value, the memory controller 210 implements the first instruction using the method described in Figure 4.

[0094] Thus, by the grouping marking and the logical address replacement marking of the second value proposed by the embodiment of the present application, the memory controller 210 can set the target physical addresses of the plurality of target data belonging to the same target data group to be in a continuous relationship, so as to substantially enable the plurality of target data belonging to the same target data group to be read by a sequential read operation after being moved to the continuous physical addresses, and to accelerate the read efficiency of the plurality of target data belonging to the same target data group.

[0095] In an embodiment, the host system 10 and the storage device 20 can further perform an authentication procedure to filter out illegal first instructions, so as to ensure the security of data storage.

[0096] In more detail, the produced first instruction further comprises a verification key corresponding to the target data, wherein before performing the operation of moving the target data stored in the rewritable non-volatile memory module 220 from the original physical address corresponding to the original logical address to the target physical address corresponding to the target logical address, the memory controller 210 determines whether the first instruction is legal according to the verification key.

[0097] If the first instruction is determined to be legal, the memory controller 210 performs the operation of moving the target data stored in the rewritable non-volatile memory module 220 from the original physical address corresponding to the original logical address to the target physical address corresponding to the target logical address; and if the first instruction is determined to be illegal, the memory controller 210 does not perform the operation of moving the target data stored in the rewritable non-volatile memory module 220 from the original physical address corresponding to the original logical address to the target physical address corresponding to the target logical address, and sends an error notification corresponding to the first instruction to the host system 10.

[0098] In other words, according to the legal verification key agreed between the legal host system 10 and the storage device 20, the storage device 20 can effectively verify whether the currently received first instruction is from the legal host system 10. For example, if the verification key in the first instruction is not the legal verification key, the storage device 20 can determine that the currently received first instruction is illegal, so as to avoid the logical address or / and the physical address of the target data from being changed due to the illegal first instruction.

[0099] Based on the above, the data storage device, the data storage system and the data arrangement method provided by the embodiments of the present application can, after receiving the first instruction issued by the host system, process the data address arrangement operation of the target data corresponding to the first instruction at the storage device end according to the first instruction, and respond to the host system that the first instruction has been completed after completing the data address arrangement operation, so as to reduce the problem of too high I / O frequency of the target data between the host system and the storage device caused by the data arrangement operation in the prior art, and greatly avoid the busy state of I / O occupation caused by the host system needing to access / process the address migration of the target data, thereby effectively improving the data arrangement efficiency and working efficiency of the data storage system and the memory controller.

[0100] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data storage device, communicatively connected to a host system, characterized by, Comprising: a rewritable non-volatile memory module, comprising a plurality of memory dies, wherein each of the memory dies has a plurality of physical blocks, each of the physical blocks has a plurality of physical pages, and the plurality of physical pages respectively correspond to a plurality of physical addresses; and a memory controller electrically connected to the rewritable non-volatile memory module, wherein the memory controller receives a first instruction from the host system to obtain parameter information of target data, wherein the first instruction is generated by the host system, the parameter information comprises original logical addresses of the target data, target logical addresses, and a data size; the memory controller obtains the target data according to the original logical addresses and stores the target data into target physical addresses corresponding to the target logical addresses; and the memory controller generates a second instruction and sends the second instruction to the host system, wherein the second instruction is used to instruct the data storage device to execute the first instruction.

2. The data storage device of claim 1, wherein, wherein the memory controller obtains original physical addresses corresponding to the original logical addresses via a logical-to-physical address table according to the original logical addresses; and reads the target data from the original physical addresses of the rewritable non-volatile memory module.

3. The data storage device of claim 1, wherein, wherein the target read instruction and the target write instruction are packaged into a general flash storage instruction to generate the first instruction.

4. The data storage device of claim 1, wherein, wherein the first instruction further comprises a logical address replacement flag, the logical address replacement flag is used to indicate whether to perform an address replacement operation, the address replacement operation is used to represent replacing the original logical addresses in the logical-to-physical address table with the target logical addresses, wherein before performing the operation of obtaining the target data according to the original logical addresses and storing the target data into the target physical addresses corresponding to the target logical addresses, the memory controller determines whether to perform the address replacement operation according to the logical address replacement flag.

5. The data storage device of claim 4, wherein, the logical address replacement flag comprises a first value and a second value, and the determination of whether to perform the address replacement operation according to the logical address replacement flag comprises: if the logical address replacement flag is the first value, the memory controller does not perform the operation of obtaining the target data according to the original logical addresses and storing the target data into the target physical addresses corresponding to the target logical addresses, and performs the address replacement operation; and if the logical address replacement flag is the second value, the memory controller performs the operation of obtaining the target data according to the original logical addresses and storing the target data into the target physical addresses corresponding to the target logical addresses, and does not perform the address replacement operation.

6. The data storage device of claim 4, wherein, the operation of replacing the original logical addresses in the logical-to-physical address table with the target logical addresses comprises: the memory controller obtains original physical addresses corresponding to the original logical addresses via the logical-to-physical address table according to the original logical addresses; and The memory controller modifies the logical-to-physical address table to replace the original logical address mapped by the original physical address with the target logical address.

7. The data storage device of claim 4, wherein, wherein the storage device further comprises a buffer memory, and wherein the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address comprises: The memory controller obtains, according to the original logical address, an original physical address corresponding to the original logical address via the logical-to-physical address table; The memory controller reads the target data from the original physical address to the buffer memory; The memory controller writes the target data in the buffer memory to the target physical address of the re-writable non-volatile memory module; and The memory controller updates the logical-to-physical address table according to the target logical address and the target physical address.

8. The data storage device of claim 7, wherein, wherein the first instruction further comprises a group tag, and wherein The memory controller determines, according to the group tag, that the target data belongs to one of a plurality of data of a target data group, a total number of the plurality of data, and a target order of the target data in the target data group; The memory controller allocates, according to the target data group and the total number of the plurality of data, a plurality of continuous physical addresses corresponding to the plurality of data for storing the plurality of data, wherein a total number of the plurality of physical addresses is equal to the total number of the plurality of data, and the plurality of data of the target data group can be read from the plurality of physical addresses via a sequential read operation; and The memory controller selects, according to the target order, the target physical address from the plurality of physical addresses for storing the target data.

9. The data storage device of claim 1, wherein, wherein the first instruction further comprises a verification key corresponding to the target data, and wherein before performing the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address, The memory controller determines, according to the verification key, whether the first instruction is legal, wherein if the first instruction is determined to be legal, the memory controller performs the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address; and if the first instruction is determined to be illegal, the memory controller does not perform the operation of obtaining the target data according to the original logical address and storing the target data into the target physical address corresponding to the target logical address, and sends an error notification corresponding to the first instruction to the host system.

10. A data storage system, characterized by comprise: a data storage device configured with a re-writable non-volatile memory module comprising a plurality of memory dies, wherein each of the memory dies has a plurality of physical blocks, and each of the physical blocks has a plurality of physical pages corresponding to a plurality of physical addresses, respectively; and a host system communicatively connected to the data storage device, wherein the host system sends a first instruction to the data storage device, wherein the first instruction comprises a target logical address and a target physical address corresponding to the target logical address, and wherein the target logical address is different from an original logical address corresponding to an original physical address of the data storage device. The data storage device receives a first instruction from the host system to acquire parameter information of target data, wherein the first instruction is generated by the host system, and the parameter information comprises original logical address, target logical address and data size of the target data; The data storage device acquires the target data according to the original logical address and stores the target data into a target physical address corresponding to the target logical address; And The data storage device generates a second instruction and sends the second instruction to the host system, wherein the second instruction is used to indicate the data storage device to execute the first instruction.

11. A data organization method, characterized by, Comprise: Receiving a first instruction from a host system to acquire parameter information of target data, wherein the first instruction is generated by the host system, and the parameter information comprises original logical address, target logical address and data size of the target data; Acquiring the target data according to the original logical address and storing the target data into a target physical address corresponding to the target logical address; and Generating a second instruction and sending the second instruction to the host system, wherein the second instruction is used to indicate the data storage device to execute the first instruction.

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