Hot-plug control method and apparatus for server bus device, and electronic device

Abstract

Provided in the embodiments of the present application are a hot-plug control method and apparatus for a server bus device, and an electronic device. The method comprises: detecting a startup operation triggered on a bus device; when it is detected that the startup operation has been triggered on the bus device, controlling the bus device to enter a target startup stage among startup stages comprised in a device startup process, wherein the target startup stage is a beginning stage of a protocol execution process of the bus device having a second protocol, and the second protocol is different from a first protocol; and upon expiration of a configured first preset duration, controlling the bus device to execute other startup stages in the device startup process other than the target startup stage. By means of the present application, the problem of a lower success rate of starting up a bus device is solved, thus achieving the effect of improving the success rate of starting up the bus device.

Description

Server bus device hot plug control method and device and electronic device

[0001] Cross-reference to Related Applications

[0002] The present application claims priority from a Chinese patent application No. 2024108625014 filed on June 28, 2024, and entitled "Server bus device hot plug control method and device and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Embodiments of the present application relate to the field of bus devices, in particular, to a server bus device hot plug control method, device and electronic device. BACKGROUND

[0004] Peripheral devices of a server can be flexibly configured to implement different functions, for example, OCP (Open Compute Project) cards in a bus device. Hot plug of the OCP cards needs to be implemented by using a notification type hot plug. The OCP cards are inserted into a running server system, and in the related art, a CPLD (Complex Programmable Logic Device) needs to power on and release reset of the OCP cards according to a second protocol (for example, OCP3.0 protocol), and after an OS (Operating System) and the OCP cards complete establishment of a data link (for example, PCIE connection) conforming to a first protocol (for example, PCIE (peripheral component interconnect express) protocol), the OCP card hot plug is completed.

[0005] In this process, the requirements for the time between power-on and reset release of the bus device (for example, OCP card) in the second protocol (for example, OCP3.0 protocol) and the first protocol (for example, PCIE protocol) are in conflict. The second protocol (for example, OCP3.0 protocol) requires that the time from power-on of the OCP card to release of the reset is greater than 1S, while the first protocol (for example, PCIE protocol) requires that the time from power-on of the PCIE device to establishment of the connection (release of the reset) is less than 1S. This can cause power-on failure of the bus device. SUMMARY

[0006] Embodiments of the present application provide a server bus device hot plug control method, device and electronic device to at least solve the problem of low success rate of starting of the bus device in the related art.

[0007] According to an embodiment of the present application, a server bus device hot plug control method is provided, the server comprises a processor and a controller, the controller is connected with the processor, the processor is configured to interact with a bus device connected with the server through a data link conforming to a first protocol, the method is applied to the controller, and the method comprises the following steps.

[0008] In an exemplary embodiment, the server further comprises a start trigger component, the start trigger component is connected with the controller, and the detection of the triggered start operation on the bus device comprises the following steps: detecting whether the start trigger component is executed with a trigger operation; and in the case that the start trigger component is detected with the trigger operation, determining that the triggered start operation on the bus device is detected.

[0009] In an exemplary embodiment, the controller further comprises a register, the register is configured to store information about whether the start trigger component is executed with the trigger operation, and after the bus device is controlled to enter the target start stage in the start stages included in the device start process, the method further comprises the following steps: extracting target information of the start trigger component, wherein the target information is used to indicate that the start trigger component is executed with the trigger operation; and storing the target information into the register.

[0010] In an exemplary embodiment, the bus device is connected to a device interface on the server, and after the first preset time interval, the control of the bus device to execute the other start stages except the target start stage in the device start process comprises the following steps: in the case that the device start process comprises N start stages, after the first preset time interval, the control of the bus device to execute N-1 start stages except the target start stage in the N start stages is performed by executing the following steps, wherein N is a positive integer greater than or equal to 2:

[0011] extracting M preset time intervals between the N start stages, M is a positive integer; determining a preset time interval between the target start stage and a first start stage in the N-1 start stages and preset time intervals between adjacent start stages in the N-1 start stages according to the M preset time intervals, to obtain a reference preset time interval; and controlling the bus device to execute the N-1 start stages except the target start stage in the N start stages according to the reference preset time interval.

[0012] In an exemplary embodiment, the reference preset time length is determined according to M preset time lengths, a preset time length between the target starting stage and a first starting stage of the N-1 starting stages, and a preset time length between adjacent starting stages of the N-1 starting stages, comprising: determining an ith preset time length between starting execution of an ith starting stage of the N-1 starting stages and starting execution of an ith+1 starting stage by executing the following steps M preset time lengths, wherein i is a positive integer less than or equal to N-1, and the reference preset time length comprises the ith preset time length: extracting the ith preset time length from the preset time lengths except a first preset time length of the M preset time lengths; or extracting an ith2-1 preset time length and an ith1-1 preset time length from the preset time lengths except the first preset time length of the M preset time lengths, wherein the ith1-1 preset time length is a preset time length between starting execution of an ith-1 starting stage of the N-1 starting stages and starting execution of the ith starting stage, the ith2-1 preset time length is a preset time length between the ith-1 starting stage and the ith+1 starting stage of the N-1 starting stages, and the ith preset time length is determined according to the ith2-1 preset time length and the ith1-1 preset time length, wherein i1 is equal to i2 is equal to i.

[0013] In an exemplary embodiment, the ith preset time length is determined according to the ith2-1 preset time length and the ith1-1 preset time length, comprising: determining the ith preset time length as a value obtained by subtracting the ith1-1 preset time length from the ith2-1 preset time length.

[0014] In an exemplary embodiment, the bus device is controlled to execute N-1 starting stages except the target starting stage of the N starting stages according to the reference preset time length, comprising: in a case that the bus device starts to execute the target starting stage, controlling the bus device to start to execute a first starting stage after a first preset time length of the N-1 preset time lengths, wherein the reference preset time length comprises the N-1 preset time lengths; and in a case that the bus device starts to execute the first starting stage, controlling the bus device to execute corresponding starting stages of the N-1 starting stages except the first starting stage according to N-2 preset time lengths, wherein the N-2 preset time lengths are preset time lengths except a preset time length between the target starting stage and the first starting stage of the reference preset time length.

[0015] In an exemplary embodiment, the server further comprises a start trigger component, the start trigger component is connected with the controller, the controller further comprises a register, the register stores target information indicating that the start trigger component is triggered, in the case that the control bus device starts to execute the target start stage, the first preset time length in the N-1 preset time lengths elapses, the control bus device starts to execute the first start stage, comprising: in the case that the control bus device starts to execute the target start stage and the first start stage comprises an information reading stage, the first preset time length elapses, a target reading instruction is generated and sent to the processor, wherein the target reading instruction is used to instruct the processor to read the information stored in the register, and the processor is configured to read the information stored in the register in response to the received target reading instruction.

[0016] In an exemplary embodiment, the control bus device executes the corresponding start stage in the N-1 start stages except the first start stage according to the N-2 preset time lengths, comprising: the control bus device executes the s-th start stage in the N-1 start stages except the first start stage according to the s-1-th preset time length in the N-2 preset time lengths and executes the s+1-th start stage in the N-1 start stages except the first start stage according to the s-th preset time length in the N-2 preset time lengths by executing the following steps, wherein the s-1-th preset time length is a preset time length between the start of the s-1-th start stage and the start of the s-th start stage, the s-th preset time length is a preset time length between the start of the s-th start stage and the start of the s+1-th start stage, and s is a positive integer less than or equal to N-2 and greater than 1; in the case that the control bus device starts to execute the s-1-th start stage, the s-1-th preset time length elapses, and the control bus device starts to execute the s-th start stage; in the case that the control bus device starts to execute the s-th start stage, the s-th preset time length elapses, and the control bus device starts to execute the s+1-th start stage.

[0017] In an exemplary embodiment, the controller further comprises a register, the register stores target information indicating that the start trigger component is triggered, in the case that the control bus device starts to execute the s-1-th start stage, the s-1-th preset time length elapses, and the control bus device starts to execute the s-th start stage, comprising: in the case that the s-1-th start stage comprises an information reading stage, the s-th start stage comprises a signal receiving stage, and the control bus device starts to execute the s-1-th start stage, the s-1-th preset time length elapses, and a target signal sent by the processor is received, wherein the processor is configured to generate and send the target signal to the controller in the case that the target information is read from the register.

[0018] In an exemplary embodiment, in a case where the control bus device starts to execute the s-th start stage, the control bus device starts to execute the (s+1)-th start stage after the interval of the s-th preset time length, including: in a case where the s-th start stage includes a signal receiving stage and the (s+1)-th start stage includes a reset removing stage, in a case where the control bus device starts to execute the signal receiving stage, the control bus device executes the reset removing operation after the interval of the s-th preset time length.

[0019] In an exemplary embodiment, after the control bus device starts to execute the (s+1)-th start stage, the method further includes: in a case where the control bus device starts to execute the (s+1)-th start stage and the (s+2)-th start stage includes a data link establishing stage, generating and sending a data link establishing instruction to the processor after the interval of the (s+1)-th preset time length in the N-2 preset time lengths, wherein the data link establishing instruction is used to instruct the processor to establish a target data link between the processor and the bus device in compliance with the first protocol; receiving a data link establishing result returned by the processor, wherein the processor is configured to establish the target data link between the processor and the bus device in compliance with the first protocol in response to the received data link establishing instruction.

[0020] In an exemplary embodiment, the server is deployed with a device interface, the device interface is connected with the bus device, and the server is deployed with a storage space, before detecting the start operation triggered on the bus device, the method further includes: configuring the preset time length interval between the start stages included in the device start process of the bus device of the device interface according to the protocol execution process and the establishment process of the data link; and recording the device interface and the preset time length interval between the start stages included in the device start process of the bus device of the device interface having a corresponding relationship in the storage space.

[0021] In an exemplary embodiment, the preset time intervals between the start-up stages included in the device start-up procedure of the bus device of the device interface are configured according to the protocol execution procedure and the data link establishment procedure, including: in the case that the device start-up procedure of the bus device of the device interface includes N start-up stages and the preset time intervals between the N start-up stages include M preset time intervals, wherein N is a positive integer greater than or equal to 2 and M is a positive integer, the M preset time intervals are configured according to the protocol execution time and the establishment time by performing the following steps: selecting a tth preset time interval from the M preset time intervals, and configuring the tth preset time interval, wherein the tth preset time interval is a time interval between a start of a first reference start-up stage of the N start-up stages and a start of a second reference start-up stage of the N start-up stages, the first reference start-up stage and the second reference start-up stage are included in both the protocol execution procedure and the data link establishment procedure, and t is a positive integer less than or equal to N; and configuring the preset time intervals other than the tth preset time interval from the M preset time intervals according to the tth preset time interval.

[0022] In an exemplary embodiment, the preset time intervals other than the tth preset time interval from the M preset time intervals are configured according to the tth preset time interval, including: the K preset time intervals from the M preset time intervals are configured by performing the following steps, wherein the K preset time intervals are preset time intervals used for determining the protocol execution time, and K is a positive integer less than or equal to M: a first difference preset time interval is obtained by subtracting the tth preset time interval from a second preset time interval; and each of the K preset time intervals is configured according to the first difference preset time interval, wherein a sum of the K preset time intervals is equal to the first difference preset time interval.

[0023] In an exemplary embodiment, each of the K preset time intervals is configured according to the first difference preset time interval, wherein a sum of the K preset time intervals is equal to the first difference preset time interval, including: each of the K preset time intervals is configured according to Q first difference preset time intervals by performing the following steps, wherein a qth first difference preset time interval from the Q first difference preset time intervals is obtained by subtracting a qth configured tth preset time interval from the second preset time interval Q times, Q is a positive integer greater than or equal to 2, and q is a positive integer less than or equal to Q: an average difference preset time interval is obtained by performing an average operation on the Q first difference preset time intervals; and each of the K preset time intervals is configured according to the average difference preset time interval, wherein a sum of the K preset time intervals is equal to the average difference preset time interval.

[0024] In an exemplary embodiment, configuring the preset time lengths other than the tth preset time length according to the tth preset time length comprises: configuring P preset time lengths in the preset time lengths other than the tth preset time length by performing the following steps, wherein the M preset time lengths comprise the tth preset time length, the P preset time lengths and the K preset time lengths, and P is a positive integer less than or equal to M, and the P preset time lengths are preset time lengths used for determining the setup time: subtracting the tth preset time length from the second preset time length to obtain a second difference preset time length; and configuring each preset time length in the P preset time lengths according to the second difference preset time length.

[0025] In an exemplary embodiment, before configuring the preset time lengths other than the tth preset time length according to the tth preset time length, the method further comprises: detecting a time length difference between the protocol execution time and the setup time; performing a sum operation on a target product and the time length difference to obtain a sum value time length, wherein the target product is a value obtained by performing a product operation on the time length difference and a target ratio; and configuring the second preset time length as the sum value time length.

[0026] According to another embodiment of the present application, a server PCle device hot insertion control method is provided, comprising: a processor, a programmable logic controller connected with the processor, configured to: detect a hot insertion trigger signal of a PCle device; control the PCle device to be powered on after receiving the hot insertion trigger signal of the PCle device, and start a first preset time delay; start a driver loading of the PCle device according to the read hot insertion trigger signal after the first preset time delay is completed; and send a power enable signal to the programmable logic controller after the driver loading of the PCle device is completed, and the programmable logic controller establishes a high-speed connection between the PCle device and the processor according to the power enable signal to realize the hot insertion of the PCle device.

[0027] According to another embodiment of the present application, a server bus device hot insertion control device is provided, the device comprising: a server comprising a processor and a controller, the controller being connected with the processor, and the processor being configured to interact with a bus device connected with the server through a data link conforming to a first protocol, the device being applied to the controller, and the device comprising: a first detection module configured to detect a start operation triggered on the bus device; a first control module configured to control the bus device to enter a target start stage in start stages included in a device start process in a case where it is detected that the bus device is triggered to start; wherein the target start stage is a start stage of a protocol execution process of the bus device conforming to a second protocol, and the second protocol is different from the first protocol; and a second control module configured to control the bus device to execute other start stages in the device start process except the target start stage after a first preset time length configured at intervals.

[0028] According to a further embodiment of the present application, a non-transitory computer readable storage medium is also provided, which stores a computer program, wherein the computer program is configured to perform the steps of any of the method embodiments described above when executed.

[0029] According to a further embodiment of the present application, an electronic device is also provided, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the computer program to perform the steps of any of the method embodiments described above.

[0030] According to a further embodiment of the present application, a computer program product is also provided, which comprises a computer program, wherein the computer program is executed by a processor to implement the steps of any of the method embodiments described above.

[0031] Through the present application, in the case that it is detected that the bus device is triggered to start an operation, the bus device is directly controlled to enter a start stage in a start-up stage, the timing of the protocol execution process is started, and then the bus device is controlled to execute other start-up stages in the start-up stage except the start stage according to the preset time length of the interval between the start-up stages included in the device start-up process of the configured bus device. In this way, the time of the protocol execution process is lengthened, the establishment time of the data link is shortened, the protocol execution time meets the second protocol supported by the bus device, and at the same time, the establishment time of the data link meets the first protocol, so that the start-up failure of the bus device caused by the conflict between the execution time of the start-up stage and the establishment time of the data link is avoided. Therefore, the problem of low success rate of the start-up of the bus device can be solved, and the success rate of the start-up of the bus device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0032] FIG. 1 is a hardware structure block diagram of a server device of a server bus device hot insertion control method according to an embodiment of the present application;

[0033] FIG. 2 is a flow chart of a server bus device hot insertion control method according to an embodiment of the present application;

[0034] FIG. 3 is a schematic diagram of an optional server bus device hot insertion control framework according to an embodiment of the present application;

[0035] FIG. 4 is a schematic diagram of detecting whether a start-up operation is triggered according to an embodiment of the present application;

[0036] FIG. 5 is a schematic diagram of storing information to a register according to an embodiment of the present application;

[0037] FIG. 6 is a schematic diagram of hot insertion of a bus device according to an embodiment of the present application;

[0038] FIG. 7 is a schematic diagram of an optional server bus device hot plug control framework II according to an embodiment of the present application;

[0039] FIG. 8 is a schematic diagram of an optional hot plug of a bus device in the related art according to an embodiment of the present application;

[0040] FIG. 9 is a structural block diagram of a server bus device hot plug control apparatus according to an embodiment of the present application. DETAILED DESCRIPTION

[0041] Hereinafter, the embodiments of the present application will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0042] It should be noted that the terms "first", "second" and the like in the description and claims of the present application and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence.

[0043] The method embodiments provided in the embodiments of the present application can be executed in a server device or similar computing apparatus. Taking an example of running on a server device, FIG. 1 is a hardware structural block diagram of a server device of a server bus device hot plug control method according to an embodiment of the present application. As shown in FIG. 1, the server device can include one or more (only one is shown in FIG. 1) processors 102 (the processor 102 can include but is not limited to a processing device such as a microcontroller unit MCU or a field-programmable gate array FPGA, etc.) and a memory 104 configured to store data, wherein the server device can further include a transmission device 106 configured to have a communication function and an input and output device 108. It can be understood by those skilled in the art that the structure shown in FIG. 1 is only schematic, and does not limit the structure of the server device. For example, the server device can further include more or less components than those shown in FIG. 1, or have a different configuration from that shown in FIG. 1.

[0044] The memory 104 can be configured to store computer programs, such as software programs of application software and modules, such as a computer program corresponding to the server bus device hot plug control method in the embodiments of the present application. The processor 102 can execute various functional applications and data processing, i.e., implement the above method, by running the computer programs stored in the memory 104. The memory 104 can include a high-speed random access memory, and can further include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some examples, the memory 104 can include memories remotely arranged relative to the processor 102, which can be connected to the server device through a network. Examples of the above network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0045] The transmission device 106 is configured to receive or send data via a network. Examples of the above network can include a wireless network provided by a communication provider of the server device. In one example, the transmission device 106 includes a network adapter (NIC), which can be connected to other network devices through a base station so as to be able to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is configured to communicate with the Internet in a wireless manner.

[0046] First, the terms involved in the embodiments of the present application are explained as follows:

[0047] CPLD: Complex Programmable Logic Device, complex programmable logic device.

[0048] OCP: Open Compute Project, open computing platform, OCP card, which refers to a specific network card, which is essentially a PCIE device, one of the main features of which is to support notification hot plug.

[0049] PCIE: peripheral component interconnect express, a high-speed serial computer expansion bus standard.

[0050] CPU: Central Processing Unit, central processor, which is the core device for normal operation of the server.

[0051] OS: Operating System, operating system.

[0052] UFM: User Flash Memory, a piece of Flash (flash memory) area built in CPLD, the data stored in this area will not be lost when the CPLD is powered off.

[0053] In the embodiment, a server bus device hot insertion control method is provided, the server comprises a processor and a controller, the controller is connected with the processor, the processor is configured to interact with a bus device connected with the server through a data link conforming to a first protocol, the method is applied to the controller, and a flowchart of the server bus device hot insertion control method is shown in FIG. 2, as shown in FIG. 2, the flowchart comprises the following steps:

[0054] In the embodiment, a server bus device hot insertion control method is provided, the server comprises a processor and a controller, the controller is connected with the processor, the processor is configured to interact with a bus device connected with the server through a data link conforming to a first protocol, the method is applied to the controller, and a flowchart of the server bus device hot insertion control method is shown in FIG. 2, as shown in FIG. 2, the flowchart comprises the following steps:

[0055] In the embodiment, a server bus device hot insertion control method is provided, the server comprises a processor and a controller, the controller is connected with the processor, the processor is configured to interact with a bus device connected with the server through a data link conforming to a first protocol, the method is applied to the controller, and a flowchart of the server bus device hot insertion control method is shown in FIG. 2, as shown in FIG. 2, the flowchart comprises the following steps:

[0056] In the embodiment, a server bus device hot insertion control method is provided, the server comprises a processor and a controller, the controller is connected with the processor, the processor is configured to interact with a bus device connected with the server through a data link conforming to a first protocol, the method is applied to the controller, and a flowchart of the server bus device hot insertion control method is shown in FIG. 2, as shown in FIG. 2, the flowchart comprises the following steps:

[0057] In the embodiment, a server bus device hot insertion control method is provided, the server comprises a processor and a controller, the controller is connected with the processor, the processor is configured to interact with a bus device connected with the server through a data link conforming to a first protocol, the method is applied to the controller, and a flowchart of the server bus device hot insertion control method is shown in FIG. 2, as shown in FIG. 2, the flowchart comprises the following steps:

[0058] Figure 3 is a schematic diagram of an optional server bus device hot plug control framework 1 according to an embodiment of the present application. As shown in Figure 3, a motherboard is deployed in the server. The server is deployed with a processor (e.g., CPU), a controller (e.g., CPLD), and a bus device (e.g., OCP card), a start trigger component (e.g., Hotplug Button), and device interface 1 to device interface 3. The OCP card can be but is not limited to connected to device interface 2.

[0059] A storage space is also deployed in the server. The controller (e.g., CPLD) is also connected to the processor and the storage space. The storage space stores preset time durations between start stages included in a device start process of a bus device configured for each device interface (e.g., preset time duration 1 between start stages included in a device start process of a bus device configured for device interface 1, preset time duration 2 between start stages included in a device start process of a bus device configured for device interface 2, and preset time duration between start stages included in a device start process of a bus device configured for device interface 3).

[0060] Figure 7 is a schematic diagram of an optional server bus device hot plug control framework 2 according to an embodiment of the present application. Figure 8 is a schematic diagram of an optional bus device hot plug in the related art according to an embodiment of the present application. In combination of Figure 7 and Figure 8, a processor (e.g., CPU (Central Processing Unit)) and a programmable logic controller (e.g., CPLD (Complex Programmable logic device)) and an OCP card are deployed on the server. The OCP card can be but is not limited to communicate with the CPU through a BUS bus.

[0061] In the related art, when an OCP card is inserted into a running server system, the OCP card is not powered on actively. At this time, the Hotplug Button is pressed, the OS reads, through I2C (Inter-Integrated Circuit), that the IO (Input / Output) Expander (or CPLD) receives the Hotplug signal, and controls the Power LED (light-emitting diode) to change from off to flashing through I2C by means of the IO Expander (or CPLD), and controls the Power EN signal to become valid. At the same time, the OS also communicates with the OCP card through the PCIE high-speed link to attempt to establish a connection. After the CPLD detects that the OCP card is in place, the CPLD can, but is not limited to, power on and reset the OCP card according to the Power EN signal in accordance with the OCP3.0 protocol. After the OS and the OCP card complete the PCIE connection establishment, the OS controls the Power LED state to change from flashing to constant brightness, and the OCP card hot insertion is completed.

[0062] In the related art, during the OCP card hot insertion process, an exception log "Failed to check link status" appears under the OS. Secondly, during the OCP card hot insertion process, another alarm light controlled by the OS through I2C will be lit for about 1 second and then turned off. It can be understood that in the related art, the OCP card hot insertion will appear abnormal.

[0063] In the related art, during the OCP card hot insertion process, an exception log "Failed to check link status" appears under the OS. Secondly, during the OCP card hot insertion process, another alarm light controlled by the OS through I2C will be lit for about 1 second and then turned off. It can be understood that in the related art, the OCP card hot insertion will appear abnormal.

[0064] In the technical solution provided in step S202, the processor can but is not limited to be configured to interact with the bus device connected with each device interface through a data link conforming to the first protocol. For example, the first protocol can but is not limited to include the PCIE protocol, and the second protocol can but is not limited to include the OCP protocol, etc. The present application does not limit this.

[0065] Optionally, in the embodiment, the protocol execution time of the second protocol supported by the bus device is greater than the establishment time of the data link, and the storage space stores preset time lengths between start-up stages included in the device start-up process of the bus device configured for each device interface.

[0066] Optionally, in the embodiment, in the case that different bus devices are connected with the same device interface on the server, the preset time lengths between start-up stages included in the device start-up process of the corresponding bus device can but are not limited to be the same.

[0067] Optionally, in the embodiment, the preset time lengths between start-up stages included in the device start-up process of the bus device configured for each device interface and stored in the storage space can but are not limited to include preset time lengths between adjacent start-up stages or preset time lengths between two start-up stages separated by at least one start-up stage.

[0068] Optionally, in the embodiment, the bus device (for example, the OCP card) can but is not limited to support hot swapping (Hot Swap), that is, hot plugging. For example, hot insertion can but is not limited to be configured to indicate that the bus device (for example, the OCP card) is inserted into a running server system. After the power-on of the bus device (for example, the OCP card) is completed and the PCIE high-speed connection (equivalent to the data link) between the processor or the operating system of the server and the bus device (for example, the OCP card) is established, the hot insertion process of the bus device (for example, the OCP card) is completed. Hot extraction can but is not limited to include notifying the driver (driver) to unload the driver first. After the driver unloading is completed, the processor or the operating system of the server terminates the PCIE high-speed connection for communication with the OCP card, the controller (for example, the CPLD) powers off the OCP card, and then the extraction operation can be performed. The hot extraction process of the bus device (for example, the OCP card) is completed.

[0069] In one exemplary embodiment, the server further includes a start-up triggering component connected with the controller, and the start-up triggering component detects the triggered start-up operation on the bus device, including: detecting whether the start-up triggering component is executed with a triggering operation; and in the case that it is detected that the start-up triggering component is executed with the triggering operation, determining that the start-up operation triggered on the bus device is detected.

[0070] Optionally, in the embodiment, the server further comprises a start trigger component, for example, but not limited to, a button deployed on the server, and in a case where it is detected that the start trigger component is not executed with a trigger operation, it is determined that the start operation on the bus device is not detected.

[0071] FIG. 4 is a schematic diagram of detecting whether a start operation is triggered according to an embodiment of the present application, as shown in FIG. 4, the server is deployed with a controller and a start trigger component, in such a case, it can be, but not limited to, detecting whether the start trigger component is executed with a trigger operation; in a case where it is detected that the start trigger component is executed with a trigger operation, it is determined that the start operation on the bus device is detected, in such a case, it can be, but not limited to, controlling the bus device to enter a target start phase.

[0072] In the technical solution provided in the above step S204, the bus device supports the second protocol, and the bus device can use the function supported by the second protocol only in a case where a protocol execution process is completed, it can be understood that the protocol execution process is a process of executing the operation included in the second protocol supported by the bus device. For example, in a case where the second protocol includes the OCP protocol, the protocol execution process can be, but not limited to, including a process of CPLD controlling OCP power on to CPLD controlling OCP reset.

[0073] Optionally, in the embodiment, the protocol execution processes corresponding to different second protocols can be, but not limited to, different, it can be understood that the start phases in the protocol execution processes corresponding to different second protocols can be, but not limited to, different, for example, in a case where the second protocol includes the OCP protocol, the target start phase can be, but not limited to, including a phase of powering on the bus device.

[0074] In an exemplary embodiment, the controller is further deployed with a register, the register is configured to store information of whether the start trigger component is executed with a trigger operation, after the bus device is controlled to enter the target start phase in the start phase included in the device start process, the above method further comprises: extracting target information of the start trigger component, wherein the target information is used to indicate that the start trigger component is executed with a trigger operation; and storing the target information into the register.

[0075] Optionally, in the embodiment, in a case where it is detected that the start trigger component is not executed with a trigger operation, it can be determined that the start operation on the bus device is not detected, in such a case, it can be, but not limited to, extracting reference information of the start trigger component, wherein the reference information is used to indicate that the start trigger component is not executed with a trigger operation; and storing the reference information into the register.

[0076] Fig. 5 is a schematic diagram of an optional method of storing information into a register according to an embodiment of the present application. As shown in Fig. 5, a controller and a start trigger component are deployed in a server, and the controller and the start trigger component are connected. In a case where it is detected that the start trigger component has performed a trigger operation, the controller can but is not limited to store target information indicating that the start trigger component has performed the trigger operation into the register.

[0077] In the technical solution provided in step S206, in a case where the bus device starts to enter a target start phase included in the start phase of the device start process, the bus device can but is not limited to perform other start phases except the target start phase after the first preset time interval.

[0078] In this way, the conflict between the protocol execution time and the data link establishment time is avoided, so that the protocol execution time meets the requirement of the second protocol, and the data link establishment time meets the requirement of the first protocol, and the compatibility of the bus device to the second protocol and the first protocol is improved.

[0079] In an exemplary embodiment, the bus device is connected to a device interface on a server, and after the first preset time interval, the bus device can but is not limited to perform other start phases except a target start phase in the device start process in the following manner: in a case where the device start process includes N start phases, after the first preset time interval, the bus device performs N-1 start phases except the target start phase in the N start phases by performing the following steps, where N is a positive integer greater than or equal to 2: extracting M preset time intervals between the N start phases, where M is a positive integer; determining a preset time interval between the target start phase and a first start phase of the N-1 start phases and preset time intervals between adjacent start phases of the N-1 start phases according to the M preset time intervals, to obtain reference preset time intervals; and controlling the bus device to perform the N-1 start phases except the target start phase in the N start phases according to the reference preset time intervals.

[0080] Optionally, in the embodiment, the preset time interval between two adjacent start phases of the N start phases can but is not limited to be determined in the following manner: the preset time interval between the target start phase and the first start phase of the N-1 start phases is determined according to the M preset time intervals, and preset time intervals between other adjacent start phases except the first start phase of the N-1 start phases are determined according to the M preset time intervals.

[0081] In an exemplary embodiment, the ith preset time length between the start of the ith start-up stage and the start of the ith+1 start-up stage can be determined, but not limited to, by performing the following steps for M preset time lengths, wherein i is a positive integer less than or equal to N-1, and the preset time lengths include the ith preset time length: extracting the ith preset time length from the preset time lengths other than the first preset time length among the M preset time lengths; or extracting the ith2-1 preset time length and the ith1-1 preset time length from the preset time lengths other than the first preset time length among the M preset time lengths, wherein the ith1-1 preset time length is a preset time length between the start of the ith-1 start-up stage and the start of the ith start-up stage among the N-1 start-up stages, the ith2-1 preset time length is a preset time length between the ith-1 start-up stage and the ith+1 start-up stage among the N-1 start-up stages, and the ith preset time length is determined according to the ith2-1 preset time length and the ith1-1 preset time length, wherein i1 equals i2 equals i.

[0082] Optionally, in the embodiment, the ith preset time length can also be determined, but not limited to, by the following method: extracting the j1th preset time length and the j2th preset time length from the M preset time lengths, wherein the j1th preset time length is a preset time length between the jth start-up stage and the ith start-up stage among the N-1 start-up stages, j is a positive integer less than i, the difference between i and j is greater than or equal to 2, the j2th preset time length is a preset time length between the jth start-up stage and the ith+1 start-up stage among the N-1 start-up stages, the ith preset time length is determined according to the jth preset time length and the ith preset time length, and j1 equals j2 equals j.

[0083] In this way, the preset time length is determined according to the preset time lengths between two start-up stages separated by at least one start-up stage, and the flexibility of determining the preset time length of the start-up stage is improved.

[0084] In an exemplary embodiment, the ith preset time length can be determined, but not limited to, according to the ith2-1 preset time length and the ith1-1 preset time length by the following method: the ith preset time length is determined as a preset time length obtained by subtracting the ith1-1 preset time length from the ith2-1 preset time length.

[0085] Optionally, in the embodiment, the ith preset time length can also be determined, but not limited to, by the following method: the ith preset time length is determined as a preset time length obtained by subtracting the j1th preset time length from the j2th preset time length.

[0086] In an exemplary embodiment, the bus device can be controlled to perform N-1 start-up stages other than the target start-up stage in the N start-up stages according to the reference preset time length, but not limited to, by the following method: in the case that the bus device starts to perform the target start-up stage, the bus device starts to perform the first start-up stage after the first preset time length in the N-1 preset time lengths, wherein the reference preset time length comprises the N-1 preset time lengths; in the case that the bus device starts to perform the first start-up stage, the bus device performs the corresponding start-up stage in the N-1 start-up stages other than the first start-up stage according to the N-2 preset time lengths, wherein the N-2 preset time lengths are the preset time lengths in the reference preset time length other than the preset time length between the target start-up stage and the first start-up stage.

[0087] Optionally, in the embodiment, the bus device can be controlled to start to perform the target start-up stage first, and then perform the remaining start-up stages in the start-up process according to the preset time length between adjacent start-up stages in the case that the bus device starts to perform the target start-up stage.

[0088] In an exemplary embodiment, the server further comprises a start-up trigger component, the start-up trigger component is connected with the controller, and the controller further comprises a register, wherein the register stores target information for indicating that the start-up trigger component has performed a trigger operation, and the bus device can be controlled to start to perform the first start-up stage after the first preset time length in the N-1 preset time lengths in the case that the bus device starts to perform the target start-up stage by the following method: in the case that the bus device starts to perform the target start-up stage and the first start-up stage comprises an information reading stage, the target reading instruction is generated and sent to the processor after the first preset time length, wherein the target reading instruction is used to instruct the processor to read the information stored in the register, and the processor is configured to read the information stored in the register in response to the received target reading instruction.

[0089] Optionally, in the embodiment, the processor is connected with the register, and the above method further comprises: the processor reads the information stored in the register in response to the received target reading instruction, analyzes whether the read information is used to indicate that the start-up trigger component has performed a trigger operation, generates the target signal in the case that the read information is used to indicate that the start-up trigger component has performed a trigger operation, and sends the target signal to the controller.

[0090] In an exemplary embodiment, the bus device can be controlled to perform the s-th of the N-1 start-up stages other than the first start-up stage in the N-1 start-up stages according to the s-1-th of the N-2 preset time lengths and the s+1-th of the N-1 start-up stages according to the s-th of the N-2 preset time lengths, but not limited to, by performing the following steps, wherein the s-1-th preset time length is the preset time length between the start of the s-1-th start-up stage and the start of the s-th start-up stage, the s-th preset time length is the preset time length between the start of the s-th start-up stage and the start of the s+1-th start-up stage, and s is a positive integer less than or equal to N-2 and greater than 1: in the case of controlling the bus device to start the s-1-th start-up stage, the s-th start-up stage of the bus device is started after the s-1-th preset time length; in the case of controlling the bus device to start the s-th start-up stage, the s+1-th start-up stage of the bus device is started after the s-th preset time length.

[0091] Optionally, in the embodiment, the preset time length between the start-up stages can be, but not limited to, the time length between the start of the previous start-up stage in the start-up process and the start of the next start-up stage after the previous start-up stage in the start-up process, for example, the preset time length between the start-up stage 1 and the start-up stage 2 can be, but not limited to, used to indicate the time length between the start of the start-up stage 1 and the start of the start-up stage 2.

[0092] In an exemplary embodiment, the controller further has a register in which target information indicating that the trigger operation is performed by the trigger component is stored, and the s-th start-up stage of the bus device can be started after the s-1-th preset time length in the case of controlling the bus device to start the s-1-th start-up stage, but not limited to, by the following method: in the case of the s-1-th start-up stage including an information reading stage, the s-th start-up stage including a signal receiving stage, and the bus device starting the s-1-th start-up stage, the target signal sent by the processor is received after the s-1-th preset time length, wherein the processor is configured to generate and send the target signal to the controller in the case of reading the target information from the register.

[0093] Optionally, in the embodiment, the processor can, but is not limited to, after generating the target signal, sending the target signal to the controller after a certain time interval. In this way, compared with the related art in which the controller controls the bus device to enter the target start stage after receiving the target signal, the operation triggered by the target signal is changed, and the time for controlling the bus device to enter the target start stage is advanced, so that the protocol execution time meets the requirement of the second protocol.

[0094] In one exemplary embodiment, after the bus device starts to execute the s th start stage, the bus device starts to execute the s+1 th start stage after a s th preset time interval, including: in the case that the s th start stage includes a signal receiving stage and the s+1 th start stage includes a reset removing stage, after the bus device starts to execute the signal receiving stage, the bus device performs the reset removing operation after a s th preset time interval.

[0095] Optionally, in the embodiment, after the bus device completes the end stage in the protocol execution process of the second protocol, it can be indicated that the protocol execution process of the second protocol of the bus device is completed. The protocol execution time of the second protocol can, but is not limited to, include the time interval between the time when the bus device enters the target start stage included in the start stage of the device start process and the time when the bus device completes the end stage included in the start stage of the device start process.

[0096] For example, in the case that the target start stage includes a stage of powering on the bus device and the end stage includes a stage of performing a reset removing operation on the bus device, after completing the reset removing operation on the bus device, it can be indicated that the protocol execution process of the second protocol has ended. In this case, the protocol execution time of the second protocol can, but is not limited to, include the time interval between the time when the bus device starts to be powered on and the time when the reset removing operation on the bus device is completed.

[0097] In one exemplary embodiment, after the bus device starts to execute the s+1 th start stage, the above method further includes: in the case that the bus device starts to execute the s+1 th start stage and the s+2 th start stage includes a data link establishing stage, generating and sending a data link establishing instruction to the processor after a s+1 th preset time interval in the N-2 preset time intervals, wherein the data link establishing instruction is used to instruct the processor to establish a target data link between the processor and the bus device in accordance with the first protocol; receiving a data link establishing result returned by the processor, wherein the processor is configured to establish the target data link between the processor and the bus device in accordance with the first protocol in response to the received data link establishing instruction.

[0098] Optionally, in the embodiment, in the case that the data link establishment result is used to indicate that the target data link between the bus device and the processor conforming to the first protocol is established, it can be indicated that the device startup process of the bus device has ended.

[0099] Optionally, in the embodiment, the establishment time of the data link can but not limited to include a time length difference between a time of controlling the bus device to enter a start stage in the establishment stage included in the establishment process of the data link and a time of controlling the bus device to complete the execution of an end stage in the establishment stage included in the establishment process of the data link, for example, in the case that the start stage in the establishment stage included in the establishment process of the data link includes the information reading stage and the end stage in the establishment stage included in the establishment process of the data link includes the data link establishment stage, the establishment time of the data link includes the time length difference between the time of controlling the bus device to start entering the information reading stage and the time of controlling the bus device to complete the execution of the data link establishment stage.

[0100] In one exemplary embodiment, the server is deployed with a device interface, the device interface is connected with the bus device, the server is deployed with a storage space, before detecting the startup operation triggered on the bus device, the method further includes: configuring a preset time length of intervals between startup stages included in the device startup process of the bus device of the device interface according to the protocol execution process and the establishment process of the data link; recording the preset time length of intervals between startup stages included in the device startup process of the bus device of the device interface with the corresponding relationship in the storage space.

[0101] Optionally, in the embodiment, the protocol execution process can but not limited to include a plurality of startup stages, the establishment process of the data link can but not limited to include a plurality of establishment stages, and the preset time length of intervals between startup stages included in the device startup process of the bus device of the device interface can but not limited to be configured according to the plurality of startup stages included in the protocol execution process and the plurality of establishment stages included in the establishment process of the data link.

[0102] In order to better understand the hot plug process of the bus device in the embodiments of the present application, the hot plug process of the bus device in the embodiments of the present application is explained and described below in combination with optional embodiments, which can but not limited to be applicable to the embodiments of the present application.

[0103] Figure 6 is a schematic diagram of an optional hot plug of a bus device according to an embodiment of the present application. As shown in Figure 6, by way of example but not limitation, the bus device can include an OPC card, the first protocol can include a PCIE protocol, and the second protocol can include an OCP3.0 protocol. By way of example but not limitation, the preset time interval between the configured start-up stages can include Tdelay, Tdriver, Treset, and Tlink.

[0104] By modifying the CPLD code, after receiving the Hotplug Button, the OCP card is powered on in advance, and the Hotplug Button information is reported by delaying to notify the OS, so that the entire hot plug process meets the requirements of the OCP3.0 protocol and the PCIE protocol. By way of example but not limitation, the following steps can be included:

[0105] 1) The current IO Expander is simulated by the CPLD, and the CPLD can monitor all signals related to the hot plug of the OCP card.

[0106] 2) After the CPLD identifies that the start trigger component (for example, the Hotplug Button) is pressed, the information (for example, the Button signal) indicating whether the start trigger component is triggered is no longer directly given to the OS, and the target signal (for example, the PWREN signal) issued by the OS is no longer waited for. Instead, the CPLD immediately controls the OCP card to enter the start stage in the protocol execution process (for example, powers on the OCP card), and starts the delay counting.

[0107] 3) After Tdelay (equivalent to the first preset time interval), the CPLD updates the information of the Hotplug Button (equivalent to the information indicating whether the start trigger component is triggered) to the register, and triggers an interrupt to notify the OS to read the information using I2C.

[0108] 4) After the OS reads the Button signal, after Tdriver time, the driver loading is completed, the PWREN is issued to the CPLD, and the Data Link process (equivalent to the process of establishing a data link in accordance with the PCIE protocol) is started.

[0109] 5) After the CPLD parses the PWREN, the counting is started, and after Treset time, the reset of the OCP card is released (equivalent to the de-reset), and then the OS can establish a PCIE connection with the OCP card, and the hot plug process of the OCP card is completed.

[0110] By the embodiment of the present application, the time difference of information interacting with the OCP card and the OS is accurately controlled by modifying the CPLD code while keeping the current system topology unchanged, so that the information interaction of the whole system is in a relatively balanced state, thereby achieving the result that both the requirement of OCP3.0 protocol that is ">1S" and the requirement of PCIE protocol that is "<1S" are met, and the conflict problem of the OCP3.0 protocol and the PCIE protocol for hot plug is solved.

[0111] In an exemplary embodiment, the M preset time lengths can be configured according to the protocol execution time and the establishment time by performing the following steps, wherein N is a positive integer greater than or equal to 2, and M is a positive integer: selecting a tth preset time length from the M preset time lengths, and configuring the tth preset time length, wherein the tth preset time length is a time length between a start of a first reference start-up phase in the N start-up phases and a start of a second reference start-up phase in the N start-up phases, the protocol execution process and the establishment process of the data link both include the first reference start-up phase and the second reference start-up phase, and t is a positive integer less than or equal to N; and configuring the preset time lengths other than the tth preset time length in the M preset time lengths according to the tth preset time length.

[0112] Optionally, in the embodiment, the start-up phases included in the protocol execution process and the start-up phases included in the establishment process of the data link can include at least two same phases, and in the case that W start-up phases are included in the start-up phases included in the protocol execution process and the start-up phases included in the establishment process of the data link, W is a positive integer greater than or equal to 3, the first reference start-up phase and the second reference start-up phase can be randomly selected from the W start-up phases, or the adjacent first reference start-up phase and the second reference start-up phase can be selected from the W start-up phases.

[0113] In an exemplary embodiment, the preset time lengths other than the tth preset time length in the M preset time lengths can be configured according to the tth preset time length by performing the following steps, including: configuring K preset time lengths in the M preset time lengths other than the tth preset time length by performing the following steps, wherein the K preset time lengths are preset time lengths used for determining the protocol execution time, and K is a positive integer less than or equal to M: subtracting the tth preset time length from a second preset time length to obtain a first difference preset time length; and configuring each preset time length in the K preset time lengths according to the first difference preset time length, wherein the sum of the K preset time lengths is equal to the first difference preset time length.

[0114] Optionally, in the embodiment, the sum of each preset time length in the K preset time lengths can be determined as the protocol execution time.

[0115] Optionally, in the embodiment, each of the K preset time lengths can be configured within the first difference preset time length, but is not limited to. For example, in the case that the first difference preset time length is 2s and the K preset time lengths include preset time length 1 and preset time length 2, preset time length 1 can be configured as 0.5s and preset time length 2 can be configured as 1.5s, or preset time length 1 can be configured as 0.9s and preset time length 2 can be configured as 1.1s, but is not limited to.

[0116] In an exemplary embodiment, each of the K preset time lengths can be configured according to the Q first difference preset time lengths, but is not limited to, wherein the qth first difference preset time length of the Q first difference preset time lengths is obtained by subtracting the qth preset time length of the tth preset time length configured for the Qth time from the second preset time length, Q is a positive integer greater than or equal to 2, and q is a positive integer less than or equal to Q. The following steps can be performed to configure each of the K preset time lengths according to the Q first difference preset time lengths: performing an average operation on the Q first difference preset time lengths to obtain an average difference preset time length; and configuring each of the K preset time lengths according to the average difference preset time length, wherein the sum of the K preset time lengths is equal to the average difference preset time length.

[0117] Optionally, in the embodiment, the tth preset time length can be configured for the Qth time, and a time length difference obtained by subtracting the tth preset time length from the second preset time length each time can be obtained, to obtain Q time length differences. An average value operation can be performed on the Q time length differences to obtain an average difference preset time length, but is not limited to.

[0118] Optionally, in the embodiment, each of the K preset time lengths can be randomly configured within the average difference preset time length, but is not limited to. For example, in the case that the average difference preset time length is 3s and the K preset time lengths include preset time length 1 and preset time length 2, preset time length 1 can be configured as 0.6s and preset time length 2 can be configured as 2.4s, or preset time length 1 can be configured as 1.6s and preset time length 2 can be configured as 1.4s, but is not limited to.

[0119] In an exemplary embodiment, P preset time lengths in the M preset time lengths except the tth preset time length can be configured by performing the following steps, wherein the M preset time lengths include the tth preset time length, the P preset time lengths and the K preset time lengths, P is a positive integer less than or equal to M, and the P preset time lengths are preset time lengths used to determine the establishment time. The following steps can be performed to configure the P preset time lengths: subtracting the tth preset time length from the second preset time length to obtain a second difference preset time length; and configuring each of the P preset time lengths according to the second difference preset time length.

[0120] Optionally, in the embodiment, each of the P preset time lengths can be but is not limited to determined as a sum of the preset time lengths, and the second preset time length can be but is not limited to used to indicate the establishment time of the data link.

[0121] Optionally, in the embodiment, each of the P preset time lengths can be but is not limited to randomly configured according to the second difference preset time length. For example, in the case that the second difference preset time length is 5s and the P preset time lengths include a preset time length 1 and a preset time length 2, the preset time length 1 can be but is not limited to configured as 3.5s and the preset time length 2 can be but is not limited to configured as 1.5s, or the preset time length 1 can be but is not limited to configured as 1.9s and the preset time length 2 can be but is not limited to configured as 3.1s.

[0122] In an exemplary embodiment, before the M preset time lengths except the tth preset time length are configured according to the tth preset time length, the method further comprises: detecting a time length difference between the protocol execution time and the establishment time; performing a sum operation on a target product and the time length difference to obtain a sum value time length, wherein the target product is a value obtained by performing a product operation on the time length difference and a target ratio; and configuring the second preset time length as the sum value time length.

[0123] Optionally, in the embodiment, the target ratio can be but is not limited to set according to the user's experience and the general derating specification, or the mean value of the ratio obtained through multiple tests, etc. For example, the target ratio can be but is not limited to 0.2 or 0.3 or 0.25, etc., which is not limited in the present application.

[0124] According to another embodiment of the present application, another server PCle device hot plug control method is provided, comprising: a processor, a programmable logic controller connected with the processor, configured to: detect a hot plug trigger signal of a PCle device; control the PCle device to be powered on after receiving the hot plug trigger signal of the PCle device, and start a first preset time delay; start the drive loading of the PCle device according to the read hot plug trigger signal after the first preset time delay is completed; and send a power enable signal to the programmable logic controller after the drive loading of the PCle device is completed, and the programmable logic controller establishes a high-speed connection between the PCle device and the processor according to the power enable signal to realize the hot plug of the PCle device.

[0125] Optionally, in the embodiment, the power enable signal can be but is not limited to include a Power EN signal.

[0126] In order to better understand the configuration process of the preset time length in the embodiment of the present application, the configuration process of the preset time length in the embodiment of the present application will be explained and described below in combination with the optional embodiments, which can be but are not limited to applicable to the embodiment of the present application.

[0127] Because the drivers of different OSs have different loading capabilities and the rates of establishing connection with PCIE are different due to different manufacturers of OCP cards, the CPLD needs to dynamically adjust the time parameters to meet the requirements of different OSs and different brands of OCP manufacturers for timing. In combination with FIG. 6, Tdelay (equivalent to the first preset time length), Treset are controlled by the CPLD, Tdriver is determined by the OS, but the CPLD can calculate Tdriver by analyzing I2C data, and Tlink is unable to be perceived by the CPLD. According to the OCP3.0 protocol and the PCIE protocol, formulas ① and ② can be obtained:

[0128] Formula ①: Tdelay+Tdriver+Treset>1S;

[0129] Formula ②: Tdriver+Tlink<1S;

[0130] Further, formulas ③ and ④ can be obtained according to the above two formulas:

[0131] Formula ③: Tdelay+Treset(Min)=1S-Tdriver;

[0132] Formula ④: Tlink(Max)=1S-Tdriver;

[0133] According to formulas ③ and ④, in the extreme case, Tdelay+Treset(Min) and Tlink(Max) are equal, which can make the hot plug process of the OCP card meet the requirements of the two protocols at the same time. Considering the user experience of customers, the value of Tdelay+Treset cannot be infinitely increased; according to the general derating specification, the time margin can be set to 20% (equivalent to the target ratio of 20%), that is, formula ⑤: Tdelay+Treset(Min)-Tlink(Max)=0.2S;

[0134] By bringing formula ⑤ into formula ③, formula ⑥: Tdelay+Treset=1.2S-Tdriver can be obtained.

[0135] Since Tdriver is controlled by the OS, with different versions, different manufacturers of OS, different manufacturers of OCP card, Tdriver has a certain discrete, in the CPLD first edition code implementation, can but not limited to Tdriver is configured to 0, at this time Tdelay+Treset default setting is 1.2S, and stored in the UFM of CPLD; After that, every time the machine starts, the CPLD will calculate the value of Tdriver, and then get the value of Tdelay+Treset, after 10 times (equivalent to Q equal to 10), the CPLD calculates the average value of adjacent 10 times Tdelay+Treset (for example, 900ms), and updates to the UFM of CPLD; Through this way of dynamically adjusting the time parameter, the driving loading capacity of different manufacturers of OCP card, different OS and the rate of PCIE connection can be met, and the response speed, stability and protocol compliance of the whole OCP hot insertion process can be guaranteed to be in the optimal state.

[0136] Through the description of the above implementation, those skilled in the art can clearly understand that the method according to the above embodiment can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better implementation. Based on such understanding, the technical solutions of the present application or the parts that contribute to the related art can be embodied in the form of software products, which are stored in a storage medium (such as ROM (Read-Only Memory), RAM (Random Access Memory), magnetic disk, optical disk), including a plurality of instructions for making a terminal device (which can be a mobile phone, computer, server, or network device) execute the method of each embodiment of the present application.

[0137] In the present embodiment, a server bus device hot insertion control device is also provided, which is configured to implement the above embodiments and optional implementation manners, which have been described and will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, hardware, or a combination of software and hardware is also possible and contemplated.

[0138] Fig. 9 is a structural block diagram of a server bus device hot insertion control device according to an embodiment of the present application, as shown in Fig. 9, the server includes a processor and a controller, the controller is connected with the processor, the processor is configured to interact with the bus device connected with the server through a data link conforming to the first protocol, the method is applied to the controller, and the device includes:

[0139] The first detection module 902 is configured to detect that the start operation is triggered on the bus device.

[0140] The first control module 904 is configured to, in response to detecting that the start operation is triggered on the bus device, control the bus device to enter a target start stage in the start stages included in the device start process, where the target start stage is a start stage of the protocol execution process of the bus device with the second protocol, and the second protocol is different from the first protocol.

[0141] The second control module 906 is configured to, after the first preset time interval is configured, control the bus device to execute the start stages other than the target start stage in the device start process.

[0142] With the above device, in response to detecting that the start operation is triggered on the bus device, the bus device is directly controlled to enter the start stage in the start stages, and the timing of the protocol execution process is started. Then, according to the preset time interval between the start stages included in the device start process of the bus device, the bus device is controlled to execute the start stages other than the start stage. In this way, the time of the protocol execution process is lengthened, and the establishment time of the data link is shortened. The protocol execution time meets the second protocol supported by the bus device, and the establishment time of the data link meets the first protocol. The conflict between the execution time of the start stage and the establishment time of the data link is avoided, and the start failure of the bus device is avoided. Therefore, the success rate of the start of the bus device can be improved.

[0143] In an exemplary embodiment, the server further includes a start trigger component, the start trigger component is connected with the controller, and the first detection module includes:

[0144] The detection unit is configured to detect whether the start trigger component is executed with the trigger operation.

[0145] The first determination unit is configured to, in response to detecting that the start trigger component is executed with the trigger operation, determine that the start operation is triggered on the bus device.

[0146] In an exemplary embodiment, the controller further includes a register, the register is configured to store information about whether the start trigger component is executed with the trigger operation, and the device further includes:

[0147] The extraction module is configured to, after controlling the bus device to enter the target start stage in the start stages included in the device start process, extract target information of the start trigger component, where the target information is used to indicate that the start trigger component is executed with the trigger operation.

[0148] The storage module is configured to store the target information into a register.

[0149] In one exemplary embodiment, the bus device is connected to a device interface on the server, the second control module comprises:

[0150] In the case that the device startup process comprises N startup stages, after a first preset time interval is configured, the bus device is controlled to execute N-1 startup stages other than the target startup stage among the N startup stages by performing the following steps, wherein N is a positive integer greater than or equal to 2:

[0151] The extraction unit is configured to extract M preset time intervals between the N startup stages, M being a positive integer;

[0152] The second determination unit is configured to determine, according to the M preset time intervals, a preset time interval between the target startup stage and a first startup stage among the N-1 startup stages and a preset time interval between adjacent startup stages among the N-1 startup stages, to obtain a reference preset time interval;

[0153] The control unit is configured to control the bus device to execute N-1 startup stages other than the target startup stage among the N startup stages according to the reference preset time interval.

[0154] In one exemplary embodiment, the second determination unit is configured to:

[0155] The M preset time intervals are determined by performing the following steps: the i-th preset time interval between the start of the i-th startup stage among the N-1 startup stages and the start of the i+1-th startup stage is determined, wherein i is a positive integer less than or equal to N-1, and the reference preset time interval comprises the i-th preset time interval:

[0156] The i-th preset time interval is extracted from the preset time intervals other than the first preset time interval among the M preset time intervals; or,

[0157] The i2-1-th preset time interval and the i1-1-th preset time interval are extracted from the preset time intervals other than the first preset time interval among the M preset time intervals, wherein the i1-1-th preset time interval is a preset time interval between the start of the i-1-th startup stage among the N-1 startup stages and the start of the i-th startup stage, the i2-1-th preset time interval is a preset time interval between the i-1-th startup stage and the i+1-th startup stage among the N-1 startup stages, the i-th preset time interval is determined according to the i2-1-th preset time interval and the i1-1-th preset time interval, and i1 is equal to i2 and equal to i.

[0158] In one exemplary embodiment, the second determination unit is further configured to:

[0159] The ith preset time length is determined as a value obtained by subtracting the i1-1th preset time length from the i2-1th preset time length.

[0160] In one exemplary embodiment, the control unit is configured to:

[0161] In a case where the control bus device starts to execute the target start phase, the control bus device starts to execute the first start phase after an interval of a first preset time length among the N-1 preset time lengths, wherein the reference preset time lengths include the N-1 preset time lengths.

[0162] In a case where the control bus device starts to execute the first start phase, the control bus device executes a corresponding start phase among the N-1 start phases other than the first start phase according to N-2 preset time lengths, wherein the N-2 preset time lengths are preset time lengths among the reference preset time lengths other than the preset time length between the target start phase and the first start phase.

[0163] In one exemplary embodiment, the server further includes a start trigger component, the start trigger component is connected with the controller, the controller further includes a register, the register stores target information indicating that the start trigger component is triggered, and the control unit is configured to:

[0164] In a case where the control bus device starts to execute the target start phase and the first start phase includes an information reading phase, the control bus device generates and sends a target reading instruction to the processor after an interval of the first preset time length, wherein the target reading instruction is used to instruct the processor to read the information stored in the register, and the processor is configured to read the information stored in the register in response to the received target reading instruction.

[0165] In one exemplary embodiment, the control unit is further configured to:

[0166] By executing the following steps, the control bus device executes an s-th start phase among the N-1 start phases other than the first start phase according to an s-1th preset time length among the N-2 preset time lengths, and executes an s+1th start phase among the N-1 start phases other than the first start phase according to an s-th preset time length among the N-2 preset time lengths, wherein the s-1th preset time length is a preset time length between a start of the s-1th start phase and a start of the s-th start phase, the s-th preset time length is a preset time length between a start of the s-th start phase and a start of the s+1th start phase, and s is a positive integer less than or equal to N-2 and greater than 1.

[0167] In a case where the control bus device starts to execute the s-th start stage, a preset time interval of s-1 is set, and the control bus device starts to execute the s+1-th start stage.

[0168] In a case where the control bus device starts to execute the s-th start stage, a preset time interval of s-1 is set, and the control bus device starts to execute the s+1-th start stage.

[0169] In an exemplary embodiment, the controller further has a register in which target information indicating that the trigger operation is executed by the trigger component is stored, and the control unit is further configured to, in a case where the s-1-th start stage includes the information reading stage, the s-th start stage includes the signal receiving stage, and the control bus device starts to execute the s-1-th start stage, receive the target signal sent by the processor after a preset time interval of s-1, wherein the processor is configured to generate and send the target signal to the controller in a case where the target information is read from the register.

[0170] In an exemplary embodiment, the control unit is further configured to, in a case where the s-th start stage includes the signal receiving stage and the s+1-th start stage includes the reset stage, execute the reset operation on the bus device after a preset time interval of s in a case where the control bus device starts to execute the signal receiving stage.

[0171] In an exemplary embodiment, the apparatus further includes:

[0172] The generating module is configured to, after the control bus device starts to execute the s+1-th start stage, generate and send a data link establishment instruction to the processor after a preset time interval of s+1 in a case where the control bus device starts to execute the s+1-th start stage and the s+2-th start stage includes the data link establishment stage, wherein the data link establishment instruction is used to instruct the processor to establish a target data link between the processor and the bus device in accordance with the first protocol.

[0173] The receiving module is configured to receive a data link establishment result returned by the processor, wherein the processor is configured to establish the target data link between the processor and the bus device in accordance with the first protocol in response to the received data link establishment instruction.

[0174] In an exemplary embodiment, the server has a device interface connected to the bus device, and the server has a storage space, and the apparatus further includes:

[0175] The first configuration module is configured to configure preset time intervals between start-up stages included in a device start-up process of the bus device of the device interface according to a protocol execution process and a data link establishment process before detecting a triggered start-up operation on the bus device.

[0176] The recording module is configured to record the device interface having the corresponding relationship and the preset time intervals between the start-up stages included in the device start-up process of the bus device of the device interface in a storage space.

[0177] In an exemplary embodiment, the first configuration module includes: in a case where the device start-up process of the bus device of the device interface includes N start-up stages and preset time intervals between the N start-up stages include M preset time intervals, N is a positive integer greater than or equal to 2, and M is a positive integer, the M preset time intervals are configured according to a protocol execution time and an establishment time by performing the following steps:

[0178] The screening unit is configured to screen the tth preset time interval from the M preset time intervals and configure the tth preset time interval, the tth preset time interval is a time interval between a start of a first reference start-up stage of the N start-up stages and a start of a second reference start-up stage of the N start-up stages, the protocol execution process and the data link establishment process both include the first reference start-up stage and the second reference start-up stage, and t is a positive integer less than or equal to N.

[0179] The configuration unit is configured to configure preset time intervals other than the tth preset time interval from the M preset time intervals according to the tth preset time interval.

[0180] In an exemplary embodiment, the configuration unit is configured to configure K preset time intervals from the M preset time intervals other than the tth preset time interval by performing the following steps, the K preset time intervals are preset time intervals used for determining a protocol execution time, and K is a positive integer less than or equal to M.

[0181] Subtracting the tth preset time interval from the second preset time interval to obtain a first difference preset time interval;

[0182] Configuring each preset time interval from the K preset time intervals according to the first difference preset time interval, and a sum of the K preset time intervals is equal to the first difference preset time interval.

[0183] In an exemplary embodiment, the configuring unit is further configured to configure each of the K preset time lengths according to the Q first difference preset time lengths by performing the following steps, wherein the qth first difference preset time length of the Q first difference preset time lengths is obtained by subtracting the qth preset time length of the tth preset time length configured for the Qth time from the second preset time length, Q is a positive integer greater than or equal to 2, and q is a positive integer less than or equal to Q:

[0184] performing an average operation on the Q first difference preset time lengths to obtain an average difference preset time length;

[0185] configuring each of the K preset time lengths according to the average difference preset time length, wherein the sum of the K preset time lengths is equal to the average difference preset time length.

[0186] In an exemplary embodiment, the configuring unit is configured to configure P preset time lengths of the preset time lengths except the tth preset time length of the M preset time lengths by performing the following steps, wherein the M preset time lengths include the tth preset time length, the P preset time lengths and the K preset time lengths, P is a positive integer less than or equal to M, and the P preset time lengths are preset time lengths for determining the establishment time:

[0187] subtracting the tth preset time length from the second preset time length to obtain a second difference preset time length;

[0188] configuring each of the P preset time lengths according to the second difference preset time length.

[0189] In an exemplary embodiment, the apparatus further comprises:

[0190] The second detecting module is configured to detect a time length difference between the protocol execution time and the establishment time before configuring the preset time lengths except the tth preset time length of the M preset time lengths according to the tth preset time length.

[0191] The executing module is configured to perform a sum operation on the target product and the time length difference to obtain a sum value time length, wherein the target product is a value obtained by performing a product operation on the time length difference and a target ratio;

[0192] The second configuring module is configured to configure the second preset time length as the sum value time length.

[0193] According to another embodiment of the present application, another server PCle device hot plug control apparatus is provided, comprising a processor, a programmable logic controller connected with the processor, and the apparatus comprises:

[0194] The third detecting module is configured to detect a hot plug trigger signal of the PCle device.

[0195] The third control module is set as a programmable logic controller which, after receiving the hot plug trigger signal of the PCle device, controls power-on of the PCle device and starts a first preset time delay;

[0196] The starting module is set as a processor which, after the first preset time delay is completed, starts loading of a driver of the PCle device according to the read hot plug trigger signal;

[0197] The establishing module is set as a processor which, after the loading of the driver of the PCle device is completed, sends a power enable signal to the programmable logic controller, and the programmable logic controller establishes a high-speed connection between the PCle device and the processor according to the power enable signal, so as to realize hot plug of the PCle device.

[0198] It should be noted that the above modules can be implemented by software or hardware, and for the latter, the following implementation manners can be used, but are not limited thereto: the above modules are located in the same processor; or the above modules are located in different processors in any combination.

[0199] Embodiments of the present application also provide a computer readable storage medium, which stores a computer program, and the computer program is set to execute the steps in any of the above method embodiments when running.

[0200] In an example embodiment, the above computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0201] Embodiments of the present application also provide an electronic device, which includes a memory storing a computer program and a processor set to execute the computer program to perform the steps in any of the above method embodiments.

[0202] In an example embodiment, the above electronic device can further include a transmission device connected to the processor and an input and output device connected to the processor.

[0203] Embodiments of the present application also provide a computer program product, which includes a computer program, and the computer program is executed by a processor to perform the steps in any of the above method embodiments.

[0204] The embodiment of the present application further provides another computer program product, comprising a nonvolatile computer readable storage medium, the nonvolatile computer readable storage medium storing a computer program, the computer program being executed by a processor to implement the steps in any of the method embodiments.

[0205] The embodiment of the present application further provides a computer program, comprising computer instructions stored in a computer readable storage medium; a processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to enable the computer device to perform the steps in any of the method embodiments.

[0206] The examples in the embodiments can refer to the examples described in the above embodiments and exemplary embodiments, and the embodiments will not be described herein again.

[0207] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be realized by general computing devices, which can be concentrated on a single computing device or distributed on a network composed of multiple computing devices, and can be realized by program codes executable by the computing devices, so that they can be stored in storage devices and executed by the computing devices, and in some cases, the steps shown or described can be executed in different orders, or they can be manufactured into individual integrated circuit modules, or multiple modules or steps can be manufactured into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

[0208] The above is only optional embodiments of the present application and is not used to limit the present application. Those skilled in the art can make various modifications and changes to the present application. Any modification, equivalent replacement, improvement, etc. within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for controlling hot plug of a server bus device, the method being applied to a controller of a server, the server comprising a processor and the controller, the processor being configured to interact with a bus device connected to the server via a data link complying with a first protocol, the method comprising: detecting a start operation triggered on the bus device; in a case where the start operation triggered on the bus device is detected, controlling the bus device to enter a target start stage among start stages included in a device start process, wherein the target start stage is a start stage of a protocol execution process of the bus device complying with a second protocol, and the second protocol is different from the first protocol; and after a first preset time interval, controlling the bus device to execute start stages other than the target start stage in the device start process. 2.The method of claim 1, wherein the server further comprises a start trigger component connected to the controller, and the detecting the start operation triggered on the bus device comprises: detecting whether the start trigger component is executed with a trigger operation; and in a case where the start trigger component is detected to be executed with the trigger operation, determining that the start operation triggered on the bus device is detected. 3.The method of claim 1, wherein the controller further comprises a register configured to store information about whether the start trigger component is executed with a trigger operation, and after the controlling the bus device to enter the target start stage among the start stages included in the device start process, the method further comprises: extracting target information of the start trigger component, wherein the target information is used to indicate that the start trigger component is executed with the trigger operation; and storing the target information into the register. 4.The method of claim 1, wherein the bus device is connected to a device interface on the server, and the after the first preset time interval, the controlling the bus device to execute the start stages other than the target start stage in the device start process comprises: in a case where the device start process comprises N start stages, after the first preset time interval, the controlling the bus device to execute N-1 start stages other than the target start stage among N start stages comprises: extracting M preset time intervals between the N start stages, M being a positive integer; determining a preset time interval between the target start stage and a first start stage among the N-1 start stages and preset time intervals between adjacent start stages among the N-1 start stages according to the M preset time intervals, to obtain a reference preset time interval; and controlling the bus device to execute the N-1 start stages other than the target start stage among the N start stages according to the reference preset time interval, wherein N is a positive integer greater than or equal to 2. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 5. The method of claim 4, wherein the determining the reference preset time length according to the M preset time lengths comprises: determining an ith preset time length between starting execution of an ith start-up stage of the N-l start-up stages and starting execution of an ith+l start-up stage of the N-l start-up stages, wherein i is a positive integer less than or equal to N-l, and the reference preset time length comprises the ith preset time length, by performing the following steps on the M preset time lengths: extracting the ith preset time length from preset time lengths other than the first preset time length among the M preset time lengths; or extracting an ith2-l preset time length and an ithl-l preset time length from preset time lengths other than the first preset time length among the M preset time lengths, wherein the ithl-l preset time length is a preset time length between starting execution of an ith-l start-up stage of the N-l start-up stages and starting execution of the ith start-up stage, the ith2-l preset time length is a preset time length between the ith-l start-up stage and the ith+l start-up stage, and the ith preset time length is determined according to the ith2-l preset time length and the ithl-l preset time length, wherein i1 is equal to i2 and i1 is equal to i.

6. The method of claim 5, wherein the determining the ith preset time length according to the ith2-l preset time length and the ithl-l preset time length comprises: determining the ith preset time length as a value obtained by subtracting the ithl-l preset time length from the ith2-l preset time length.

7. The method of claim 4, wherein the controlling the bus device to execute N-l start-up stages of the N start-up stages other than the target start-up stage according to the reference preset time length comprises: controlling the bus device to start execution of a first start-up stage of the N-l start-up stages after a first preset time length of N-l preset time lengths in a case where the bus device is controlled to start execution of the target start-up stage, wherein the reference preset time length comprises the N-l preset time lengths; controlling the bus device to execute corresponding start-up stages of the N-l start-up stages other than the first start-up stage according to N-2 preset time lengths in a case where the bus device is controlled to start execution of the first start-up stage, wherein the N-2 preset time lengths are preset time lengths other than a preset time length between the target start-up stage and the first start-up stage among the reference preset time lengths.

8. The method of claim 7, wherein ​ ​ ​ ​ The server further comprises a start trigger component connected with the controller, and a register is further arranged in the controller, in which target information indicating that the start trigger component is triggered is stored, and in the case that the controller controls the bus device to start to execute the target start stage, the first preset time length in the N-1 preset time lengths is waited, and then the bus device is controlled to start to execute the first start stage, which comprises: In the case that the controller controls the bus device to start to execute the target start stage, and the first start stage comprises an information reading stage, the first preset time length is waited, and a target reading instruction is generated and sent to the processor, wherein the target reading instruction is used to instruct the processor to read the information stored in the register, and the processor is arranged to read the information stored in the register in response to the received target reading instruction.

9. The method of claim 7, wherein, The bus device is controlled to execute the corresponding start stage in the N-1 start stages except the first start stage according to the N-2 preset time lengths, which comprises: The bus device is controlled to execute the s-th start stage in the N-1 start stages except the first start stage according to the s-1-th preset time length in the N-2 preset time lengths, and the s+1-th start stage in the N-1 start stages except the first start stage according to the s-th preset time length in the N-2 preset time lengths by executing the following steps, wherein the s-1-th preset time length is a preset time length between the start of the s-1-th start stage and the start of the s-th start stage, the s-th preset time length is a preset time length between the start of the s-th start stage and the start of the s+1-th start stage, and s is a positive integer less than or equal to N-2 and greater than 1: In the case that the bus device is controlled to start to execute the s-1-th start stage, the s-1-th preset time length is waited, and then the bus device is controlled to start to execute the s-th start stage; In the case that the bus device is controlled to start to execute the s-th start stage, the s-th preset time length is waited, and then the bus device is controlled to start to execute the s+1-th start stage.

10. The method of claim 9, wherein, The controller further comprises a register, and the register stores target information indicating that the trigger operation is performed on the trigger component; and the step of controlling the bus device to start the s-th start-up stage after the s-1-th preset time interval comprises: when the s-1-th start-up stage comprises an information reading stage and the s-th start-up stage comprises a signal receiving stage, receiving the target signal sent by the processor after the s-1-th preset time interval, wherein the processor is configured to generate and send the target signal to the controller when the target information is read from the register.

11. The method of claim 9, wherein, the step of controlling the bus device to start the s+1-th start-up stage after the s-th preset time interval when the s-th start-up stage comprises the signal receiving stage and the s+1-th start-up stage comprises a reset removing stage comprises: when the s+1-th start-up stage comprises the reset removing stage, controlling the bus device to start the signal receiving stage, and then performing the reset removing operation on the bus device after the s-th preset time interval.

12. The method of claim 9, wherein, after the step of controlling the bus device to start the s+1-th start-up stage, the method further comprises: when the s+1-th start-up stage comprises a data link establishing stage, generating and sending a data link establishing instruction to the processor after the s+1-th preset time interval in the N-2 preset time intervals, wherein the data link establishing instruction is used to instruct the processor to establish a target data link between the processor and the bus device in accordance with the first protocol; and receiving a data link establishing result returned by the processor, wherein the processor is configured to establish the target data link between the processor and the bus device in accordance with the first protocol in response to the received data link establishing instruction.

13. The method of claim 1, wherein, the server is provided with a device interface connected to the bus device, and the server is provided with a storage space, and before the step of detecting the triggered start-up operation on the bus device, the method further comprises: configuring preset time intervals between start-up stages included in the device start-up process of the bus device of the device interface according to the protocol execution process and the establishment process of the data link; and recording the preset time intervals between start-up stages included in the device start-up process of the bus device of the device interface and the device interface having a corresponding relationship in the storage space.

14. The method of claim 13, wherein, The preset time length between the start-up stages included in the device start-up process of the bus device of the device interface is configured according to the protocol execution time and the establishment time, including: when the device start-up process of the bus device of the device interface includes N start-up stages, and the preset time length between the N start-up stages includes M preset time lengths, and N is a positive integer greater than or equal to 2, and M is a positive integer, the M preset time lengths are configured according to the protocol execution time and the establishment time by performing the following steps: The tth preset time length is selected from the M preset time lengths, and the tth preset time length is configured, wherein the tth preset time length is a time length between a start of a first reference start-up stage in the N start-up stages and a start of a second reference start-up stage in the N start-up stages, and the first reference start-up stage and the second reference start-up stage are included in the protocol execution process and the data link establishment process, and t is a positive integer less than or equal to N; The preset time lengths other than the tth preset time length in the M preset time lengths are configured according to the tth preset time length.

15. The method of claim 14, wherein The preset time lengths other than the tth preset time length in the M preset time lengths are configured according to the tth preset time length, including: the K preset time lengths in the M preset time lengths other than the tth preset time length are configured by performing the following steps, wherein the K preset time lengths are preset time lengths used to determine the protocol execution time, and K is a positive integer less than or equal to M: A second preset time length is subtracted from the tth preset time length to obtain a first difference preset time length; Each of the K preset time lengths is configured according to the first difference preset time length, wherein a sum of the K preset time lengths is equal to the first difference preset time length.

16. The method of claim 15, wherein Each of the K preset time lengths is configured according to the first difference preset time length, wherein a sum of the K preset time lengths is equal to the first difference preset time length, including: each of the K preset time lengths is configured according to Q first difference preset time lengths by performing the following steps, wherein a qth first difference preset time length in the Q first difference preset time lengths is obtained by subtracting a qth time configured tth preset time length from the second preset time length Q times, Q is a positive integer greater than or equal to 2, and q is a positive integer less than or equal to Q: An average operation is performed on the Q first difference preset time lengths to obtain an average difference preset time length; Each of the K preset time lengths is configured according to the average difference preset time length, wherein a sum of the K preset time lengths is equal to the average difference preset time length.

17. The method of claim 14, wherein The configuring the preset time lengths other than the tth preset time length from the M preset time lengths according to the tth preset time length comprises: configuring P preset time lengths from the preset time lengths other than the tth preset time length from the M preset time lengths by performing the following steps, wherein the M preset time lengths comprise the tth preset time length, the P preset time lengths and K preset time lengths, P is a positive integer less than or equal to M, and the P preset time lengths are preset time lengths for determining the establishment time: Subtracting the tth preset time length from a second preset time length to obtain a second difference preset time length; Configuring each preset time length from the P preset time lengths according to the second difference preset time length.

18. The method of claim 14, wherein, Before the configuring the preset time lengths other than the tth preset time length from the M preset time lengths according to the tth preset time length, the method further comprises: Detecting a time length difference between the protocol execution time and the establishment time; Performing a sum operation on a target product and the time length difference to obtain a sum value time length, wherein the target product is a value obtained by performing a product operation on the time length difference and a target ratio; Configuring a second preset time length as the sum value time length.

19. A method of server PCle device hot plug control, the method comprising: Comprise: A processor, a programmable logic controller is connected with the processor, and is used for: Detecting a hot plug trigger signal of a PCle device; The programmable logic controller controls the PCle device to be powered on after receiving the hot plug trigger signal of the PCle device, and starts a first preset time delay; The processor starts the driver loading of the PCle device according to the read hot plug trigger signal after the first preset time delay is completed; The processor sends a power enable signal to the programmable logic controller after the driver loading of the PCle device is completed, and the programmable logic controller establishes a high-speed connection between the PCle device and the processor according to the power enable signal to realize the hot plug of the PCle device.

20. A server bus device hot plug control apparatus, comprising: A server comprising a processor and a controller, the controller being connected with the processor, the processor being arranged to interact with a bus device connected with the server through a data link conforming to a first protocol, the apparatus being applied to the controller, and the apparatus comprising: A first detection module arranged to detect a start operation triggered on the bus device; A first control module arranged to control the bus device to enter a target start stage in a start stage included in a device start process when it is detected that the start operation is triggered on the bus device, wherein the target start stage is a start stage of a protocol execution process of the bus device conforming to a second protocol, and the second protocol is different from the first protocol; A second control module arranged to control the bus device to execute other start stages in the device start process other than the target start stage after a first preset time length is configured.

21. A non-transitory computer readable storage medium, characterized in that, the non-transitory computer readable storage medium has stored therein a computer program, wherein the computer program, when executed by a processor, implements the steps of the method according to any one of claims 1 to 18, or the steps of the method according to claim 19.

22. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, the processor, when executing the computer program, implements the steps of the method according to any one of claims 1 to 18, or the steps of the method according to claim 19.

23. A computer program product, comprising a computer program, characterized in that, the computer program, when executed by a processor, implements the steps of the method according to any one of claims 1 to 18, or the steps of the method according to claim 19.

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