Two-stage cascaded high-gain amplifier based on adaptive biasing and cascode compensation

Abstract

Disclosed in the present invention is a two-stage cascaded high-gain amplifier based on adaptive biasing and cascode compensation. Said amplifier uses the basic structure of a two-stage cascaded amplifier, where a first stage uses an adaptively biased cascode floating inverting amplifier structure, which significantly improves the gain by means of cross-coupled biasing while obtaining a larger current to increase the bandwidth and slew rate, and eliminates the need for an external biasing circuit and an additional common-mode feedback circuit, and a second stage uses a current-source-biased inverting amplifier structure, which achieves a higher current efficiency by means of current reuse, and obtains a larger output swing. In addition, the present invention uses a cascode compensation circuit to eliminate the need for a nulling resistor required for Miller compensation, and offers overall advantages of high gain and high speed.

Description

Two-stage cascaded high-gain amplifier based on adaptive bias and cascode compensation TECHNICAL FIELD

[0001] The application belongs to the technical field of amplifiers, and particularly relates to a two-stage cascaded high-gain amplifier based on adaptive bias and cascode compensation. BACKGROUND

[0002] Signals generated in nature and recognized by humans belong to analog signals, and today's high-performance signal processing is mostly completed in the digital domain by computers, so the analog-to-digital converter (ADC) for converting analog signals continuous in amplitude and time into digital signals discrete in amplitude and time has been widely applied. As an important part of the signal chain, the precision, speed and power consumption of the analog-to-digital converter have become the determining factors of the precision, speed and power consumption of signal processing; with the rapid development of mobile communication, sensors, biological medicine and the Internet of Things, the demand for accurate and high-quality data information is also increasing, so the demand for high-precision ADCs has also increased significantly.

[0003] Common high-precision ADCs include Delta-Sigma ADC and Pipeline ADC. Delta-Sigma ADC achieves very high signal-to-noise ratio by oversampling and noise shaping technology to suppress quantization noise within the signal bandwidth; Pipeline ADC realizes high precision and high speed by cascading multiple sub-ADCs with lower precision. However, Delta-Sigma ADC has high requirements for the gain, bandwidth, slew rate and linearity of the amplifier in the first integrator, and Pipeline ADC also has similar requirements for the performance of the residual amplifier, and the performance of the amplifier in these two ADCs determines the performance and energy efficiency of the entire ADC.

[0004] With the continuous reduction of the feature size of integrated circuits, it is becoming a hot and difficult point in integrated circuit design to realize high-gain high-performance amplifiers. The traditional cascode structure amplifier can achieve very high gain, but its swing is greatly limited. The two-stage amplifier using Miller compensation can achieve high gain while obtaining good stability, but it usually needs a zeroing resistor and consumes a large power consumption. In recent years, the floating inverting amplifier has realized dynamic operation and does not need an additional common-mode feedback circuit, but its gain is usually very low, which is difficult to meet the demand of high-gain high-performance.

[0005] For example, the document [R.S. Ashwin Kumar, N. Krishnapura, and P. Banerjee, “Analysis and design of a discrete-time delta-sigma modulator using a cascoded floating-inverter-based dynamic amplifier,” IEEE J. Solid-State Circuits, vol. 57, no. 11, pp. 3384-3395, Nov. 2022] proposes a common-source common-gate floating inverter amplifier based on VCM bias, which eliminates the additional bias circuit by using VCM bias technology and improves the gain by using common-source common-gate technology; but as a single-stage amplifier, the gain is still limited, and the common-source common-gate structure limits the output swing that the amplifier can provide. The document [Y. Choi, W. Lee, S. Park, C. Kim, H. Jung and C. Kim, “A 101.6-dB-SNDR Fully Dynamic Zoom ADC Using Miller-Compensated Floating Inverter Amplifiers,” in IEEE Transactions on Circuits and Systems II: Express Briefs, doi: 10.1109 / TCSII.2024.3392909] proposes a two-stage cascaded floating inverter amplifier based on Miller compensation, which improves the gain by using a two-stage cascaded technology and improves the stability of the two-stage cascaded amplifier by using a Miller compensation technology, and has an output swing higher than that of a single-stage common-source common-gate structure; but the two stages of the amplifier use ordinary floating inverter amplifier structures without common-source common-gate, so the gain is only slightly higher than that of the VCM biased amplifier, and the gain is still limited, and the Miller compensation technology requires a large Miller capacitor and an additional zeroing resistor. Therefore, at present, we need a high-gain amplifier with higher gain, higher output swing, simple biasing technology and compensation technology. SUMMARY

[0006] In view of the above, the present application provides a two-stage cascaded high-gain amplifier based on adaptive bias and common-source common-gate compensation, which uses an adaptive bias floating inverter amplifier and a current source biased inverter amplifier in cascade to achieve high gain while avoiding the influence of the common-source common-gate structure on the swing.

[0007] A two-stage cascaded high-gain amplifier based on adaptive bias and cascode compensation is provided. It consists of two cascaded amplifier stages. The first stage amplifier forms an adaptive bias through cross-coupling to improve system gain, and the second stage amplifier achieves high current efficiency through current multiplexing, thereby further improving system gain and output swing.

[0008] Furthermore, the first-stage amplifier employs an adaptively biased cascode floating inverting amplifier circuit, while the second-stage amplifier employs a current-source biased inverting amplifier circuit. The adaptively biased cascode floating inverting amplifier, in traditional V... CM Based on the biased cascode floating inverting amplifier, the bias is changed to a cross-coupled adaptive bias to improve gain and speed, eliminating the need for external bias circuits and additional common-mode feedback circuits, maintaining the advantages of low noise and low power consumption, while obtaining larger current to improve bandwidth and slew rate.

[0009] Furthermore, the adaptive biased cascode floating inverting amplifier circuit includes four PMOS transistors M1, M2, M5, and M6, four NMOS transistors M3, M4, M7, and M8, and a capacitor C. RES And six switches S1 to S6, one end of which is connected to the power supply voltage VDD, and the other end of S1 is connected to one end of S3 and C. RES One end of S5 is connected to the source of M1, and the other end of S3 is connected to the source of M2. The gate of M1 is connected to the gate of M3 and serves as the inverting voltage input of the first-stage amplifier. The gate of M2 is connected to the gate of M4 and serves as the non-inverting voltage input of the first-stage amplifier. The drain of M1 is connected to the source of M5 and the gate of M8. The drain of M2 is connected to the source of M6 and the gate of M7. The gate of M5 is connected to the source of M8 and the drain of M4. The gate of M6 is connected to the source of M7 and the drain of M3. The drain of M5 is connected to the drain of M7 and one end of S5 and serves as the non-inverting voltage output of the first-stage amplifier. The drain of M6 is connected to the drain of M8 and one end of S6 and serves as the inverting voltage output of the first-stage amplifier. The other end of S5 is connected to the other end of S6 and connected to an external common-mode voltage V. CM The source of M3 is connected to the source of M4 and one end of S4, and the other end of S4 is connected to C. RES The other end of S1 is connected to one end of S2, and the other end of S2 is grounded; the control electrodes of switches S1, S2, S5, and S6 are connected to the clock signal. The control electrodes of switches S3 and S4 are connected to a clock signal.

[0010] Further, the current source biased inverting amplifier circuit comprises three PMOS transistors M9, M10, M13, three NMOS transistors M11, M12, M14 and two switches S7-S8, wherein the source of M13 is connected to the power supply voltage VDD, the gate of M13 is connected to the bias voltage V BP , the drain of M13 is connected to the source of M9 and the source of M10, the gate of M9 is connected to the gate of M11 and serves as the non-inverting voltage input terminal of the second stage amplifier, the gate of M10 is connected to the gate of M12 and serves as the inverting voltage input terminal of the second stage amplifier, the drain of M9 is connected to the drain of M11 and one end of S8 and serves as the inverting voltage output terminal of the second stage amplifier, the drain of M10 is connected to the drain of M12 and one end of S7 and serves as the non-inverting voltage output terminal of the second stage amplifier, the other end of S7 is connected to the other end of S8 and is connected to the common mode voltage V CM , the source of M11 is connected to the source of M12 and the drain of M14, the gate of M14 is connected to the common mode feedback voltage V CMFB , and the source of M14 is connected to the ground; the control electrodes of switches S7 and S8 are connected to the clock signal

[0011] Further, the clock signal is used to make the switches closed in the system reset stage, the clock signal is used to make the switches closed in the system amplification stage, and the phases are complementary and have a certain dead time.

[0012] Further, the common mode feedback voltage V CMFB is generated by a common mode feedback circuit comprising two resistors R1-R2 and an amplifier AMP1, wherein one end of R1 is connected to the non-inverting voltage output terminal of the second stage amplifier, one end of R2 is connected to the inverting voltage output terminal of the second stage amplifier, the other end of R1 and the other end of R2 are connected to the non-inverting input terminal of AMP1, the inverting input terminal of AMP1 is connected to the common mode voltage V CM , and the output terminal of AMP1 generates the common mode feedback voltage V CMFB .

[0013] Further, a common-source and common-gate compensation circuit is arranged between the two-stage amplifiers, which is used to provide frequency compensation for the two-stage amplifiers, and includes four capacitors C1-C4, wherein one end of C1 is connected to the drain of M3, one end of C2 is connected to the drain of M1, the other end of C1 is connected to the other end of C2 and connected to the inverting voltage output terminal of the second-stage amplifier, one end of C3 is connected to the drain of M4, one end of C4 is connected to the drain of M2, the other end of C3 is connected to the other end of C4 and connected to the non-inverting voltage output terminal of the second-stage amplifier. The compensation circuit provides frequency compensation for the two-stage amplifiers, so that the amplifier is stable, and the Miller compensation required zeroing resistor can be eliminated while separating the main pole and the secondary pole and ensuring the stability of the system.

[0014] Compared with the prior art, the basic structure of two-stage cascade amplifiers is adopted in the application, the first stage adopts a common-source and common-gate floating inverting amplifier structure with adaptive bias, the gain is significantly improved through cross-coupled bias, and at the same time, a larger current is obtained to improve the bandwidth and the slew rate, and the external bias circuit and the additional common-mode feedback circuit are saved; the second stage adopts a current source biased inverting amplifier structure, higher current efficiency is achieved through current multiplexing, and a larger output swing is obtained. In addition, the Miller compensation required zeroing resistor is saved by using the common-source and common-gate compensation circuit, and the whole has the advantages of high gain and high speed. BRIEF DESCRIPTION OF DRAWINGS

[0015] Fig. 1 is a structural block diagram of the two-stage cascade high-gain amplifier of the application.

[0016] Fig. 2 is a structural schematic diagram of the first-stage common-source and common-gate floating inverting amplifier circuit with adaptive bias.

[0017] Fig. 3 is a structural schematic diagram of the second-stage current source biased inverting amplifier circuit.

[0018] Fig. 4(a) is a structural schematic diagram of the common-mode feedback circuit.

[0019] Fig. 4(b) is a structural schematic diagram of the common-source and common-gate compensation circuit.

[0020] Fig. 5 is a schematic diagram of two-phase non-overlapping clock signals used in the amplifier structure of the application. DETAILED DESCRIPTION

[0021] In order to more specifically describe the application, the technical solutions of the application are described in detail below in combination with the drawings and specific embodiments.

[0022] As shown in Fig. 1, the two-stage cascade high-gain amplifier based on adaptive bias and common-source and common-gate compensation of the application provides high gain by cascading the first-stage amplifier and the second-stage amplifier. The first-stage amplifier adopts a common-source and common-gate floating inverting amplifier circuit with adaptive bias, which is connected to the input terminal of the second-stage amplifier. CMThe bias is changed to cross-coupled adaptive bias to improve gain and speed and save external bias circuit while keeping the advantages of low noise and low power consumption on the basis of the bias of the common-source common-gate floating inverting amplifier; the second-stage amplifier adopts current source biased inverting amplifier to further improve gain and uses common-source common-gate compensation to ensure stability while eliminating the zeroing resistor on the basis of the first-stage amplifier.

[0023] Embodiment

[0024] The two-stage high-gain amplifier in the embodiment is composed of a first-stage adaptive bias floating inverting amplifier circuit, a second-stage current source biased inverting amplifier circuit, a common-source common-gate compensation circuit and a common-mode feedback circuit. As shown in FIG. 2, the first-stage adaptive bias common-source common-gate floating inverting amplifier circuit includes PMOS transistors M1, M2, M5, M6, NMOS transistors M3, M4, M7, M8, capacitor C RES , switches S1, S2, S3, S4, S5 and S6, wherein M2 and M4 are the positive input terminals, M1 and M3 are the negative input terminals, M6 and M8 are the loads of M2 and M4 respectively and are the negative output terminals, M5 and M7 are the loads of M1 and M3 respectively and are the positive output terminals, S1, S2, S5 and S6 are closed in the reset stage of the amplifier, S1 and S2 connect the upper and lower plates of C RES to VDD and GND respectively, S5 and S6 connect the positive and negative output terminals to V CM respectively, S3 and S4 are closed in the amplification stage of the amplifier and connect the upper and lower plates of C RES to V SP and V SN respectively to power the common-source common-gate floating inverting amplifier circuit. The upper plate of C RES is connected to VDD and the source terminals of M1 and M2 via S1 and S3 respectively, the lower plate of C RES is connected to GND and the source terminals of M3 and M4 via S2 and S4 respectively, the gate terminals of M1 and M2 are connected to the negative input terminal V IN and the positive input terminal V IP of the differential input signal respectively, the source terminals of M1 and M2 are connected to the upper plate of C SP via S3 respectively, the drain terminals of M1 and M2 are connected to the source terminals of M5 and M6 respectively, the gate terminals of M5 and M6 are connected to the source terminals of M8 and M7 respectively, and the drain terminals of M5 and M6 are connected to the positive output terminal V RES and the negative output terminal V BN1 of the differential output signal respectively. BN2 OP1 ON1 ​​The gate terminals of M3 and M4 are respectively connected to the negative input terminal V of the differential input signal. IN and positive input terminal V IP The source V of M3 and M4 SN Connected to C via S4 respectively RES The lower electrode plate, the drain terminals V of M3 and M4 BP1 and V BP2 Connect the gate terminals of M7 and M8 to the source terminals of M7 and M8 respectively. Connect the gate terminals of M7 and M8 to the source terminals of M6 and M5 respectively. Connect the drain terminals of M7 and M8 to the positive output terminal V of the differential output signal respectively. OP1 and negative output terminal V ON1 Positive output terminal V OP1 and negative output terminal V ON1 Connected to V via S5 and S6 respectively CM .

[0025] As shown in Figure 3, the second-stage current-source biased inverting amplifier circuit includes PMOS transistors M9, M10, M13, M11, M12, and M14, as well as switches S7 and S8. The gate terminals of M9 and M11 are connected to the positive output terminal V of the differential output signal of the first-stage amplifier. OP1 Simultaneously, as the positive input terminal of the differential input signal of the second-stage amplifier, the drain terminals of M9 and M11 are connected to the negative output terminal V of the differential output signal. ON The gate terminals of M10 and M12 are connected to the negative output terminal V of the differential output signal of the first-stage amplifier. ON1 Simultaneously, as the negative input terminal of the differential input signal of the second-stage amplifier, the drain terminals of M10 and M12 are connected to the positive output terminal V of the differential output signal. OP The source terminals of M9 and M10 are connected to the drain terminal of M13, the source terminals of M11 and M12 are connected to the drain terminal of M14, and the gate terminal of M13 is connected to V. BP The reference current is generated to provide a constant current bias for the second-stage amplifier. The source terminal of M13 is connected to VDD, and the gate terminal of M14 is connected to the output terminal V of amplifier AMP1 in the common-mode feedback circuit. CMFB To provide common-mode feedback for the second-stage amplifier, the source terminal of M14 is connected to GND, V OP and V ON Connected to V via S7 and S8 respectively CM S7 and S8 are closed during the amplifier's reset phase.

[0026] As shown in Figure 4(b), the common-source cascode compensation circuit includes capacitors C1, C2, C3, and C4, wherein the upper plate of C1 is connected to V. BP1 The lower plate of C1 is connected to V. ON The upper plate of C2 is connected to V.BN1 The lower plate of C2 is connected to V ON The upper plate of C3 is connected to V BP2 The lower plate of C3 is connected to V OP The upper plate of C4 is connected to V BN2 The lower plate of C4 is connected to V OP The two-stage amplifier is provided with frequency compensation to stabilize the amplifier without using zeroing resistance while separating the main pole and the secondary pole.

[0027] As shown in Fig. 4(a), the common-mode feedback circuit comprises resistors R1, R2 and a differential input single output amplifier AMP1, wherein the left end of R1 is connected to V OP The right end of R1 is connected to V SENSE and the left end of R2, and the right end of R2 is connected to V ON The positive input end of AMP1 is connected to the voltage V SENSE generated by R1 and R2, and the negative input end of AMP1 is connected to V CM The output end V CMFB of AMP1 is connected to the gate end of M14 to provide the voltage required by the common-mode feedback of the second-stage amplifier.

[0028] The working mode of the two-stage high-gain amplifier of the embodiment is as follows:

[0029] The gate ends of M1 and M3, M2 and M4 are the differential input ends of the first stage, the drain ends of M5, M7, M6 and M8 are the differential output ends of the first stage, M1, M3, M2 and M4 receive the input voltage signal and generate a small signal output current g m *v m through their transconductance g in , which flows through the common-gate load M5, M7, M6 and M8 and is converted into an output voltage at the output end through the output impedance. The common-gate M5, M7, M6 and M8 amplify the output impedance of the common-source input tubes M1 and M3, M2 and M4 by g m *r o times, wherein r o is the small signal output resistance of the transistor.

[0030] As shown in Fig. 5, in the reset stage S1 and S2 are closed, the upper plate and the lower plate of C RES are connected to VDD and GND respectively, and are charged, and at the same time S5, S6, S7 and S8 are closed, and the outputs of the first-stage amplifier and the second-stage amplifier are both connected to V CM for resetting; in the amplification stage S1, S2, S5, S6, S7 and S8 are disconnected, and at the same time S3 and S4 are closed, and C RESThe upper and lower plates of the capacitor are connected to V SP and V SN , respectively, to provide power supply for the first-stage amplifier.

[0031] Unlike the traditional way of biasing the common-gate tubes M5, M7, M6 and M8 by V CM , the embodiment adopts a cross-coupled adaptive biasing way to bias M5, M7, M6 and M8, specifically: the sources of M8 and M6 provide biasing for the gates of M5 and M7, respectively, and the sources of M7 and M5 provide biasing for the gates of M6 and M8, respectively. The biasing voltages V BN1 , V BN2 , V BP1 and V BP2 are self-adaptively adjusted with the working of the amplifier, and have good robustness to the changes of PVT. Meanwhile, the overdrive voltages V OV generated in this way are larger than those in the traditional biasing way, ensuring that all the transistors work in the saturation region, and thus the speed of the amplifier is increased; since the overdrive voltages of M5, M7, M6 and M8 are increased, the amplifier realizes larger drain current and higher slew rate than the traditional biasing way. Since adaptive biasing is adopted, the input signal received by the common-gate tube comes from two parts: one part is the input signal generated by the input tube g m r m5 of the other half of the circuit, and the other part is the signal providing biasing for the gate, which is the source of the common-gate tube of the other half of the circuit, i.e. the drain of the input tube of the other half of the circuit, which amplifies the input signal and inputs it to the gate of the common-gate tube. According to the above analysis and calculation, the gain of the first-stage adaptive biasing floating inverting amplifier is g o5 r m1 + g o1 r m4 + g o4 r m1 + g o1 r m7 + g o7 r m3 + g o3 r m2 + g o2 r m3 + g o3 r BP , which is much larger than that of the floating inverting amplifier adopting the traditional biasing way.

[0032] The second-stage amplifier is composed of M13, M14, M15 and M16, and is connected to V BPThe bias current is provided, the gate end of M9, M11, M10 and M12 constitutes the differential input end of the second stage, the drain end of M9, M11, M10 and M12 constitutes the differential output end of the second stage, M9, M11, M10 and M12 constitute the current multiplexing structure, which greatly improves the current utilization efficiency and has a higher output swing; the gate end of M14 is automatically adjusted and maintained by the output of AMP1 in the common-mode feedback circuit, and the output common-mode voltage is generated by the sensing of two resistors R1 and R2. The gain of the second stage amplifier is (g m9 +g m11 )(r o9 ||r o11 ), so the total gain of the two-stage cascade amplifier is (g m9 +g m11 )(r o9 ||r o11 )[g m5 r o5 (g m1 r o1 +g m4 r o4 )+g m1 r o1 +g m7 r o7 (g m3 r o3 +g m2 r o2 )+g m3 r o3 ] to achieve the goal of high gain.

[0033] In order to maintain the stability of the two-stage cascade amplifier, the embodiment uses C1, C2, C3 and C4 to constitute a common-source common-gate compensation circuit, one end of which is connected to the output of the second stage amplifier, and the other end is connected to the source of the load tube in the first stage amplifier, thus cutting off the feedforward path, so that the zeroing resistor required by the Miller compensation is eliminated while maintaining stability.

[0034] The above description of the embodiments is for the purpose of facilitating the understanding and application of the present application by those skilled in the art, and those skilled in the art can easily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative labor. Therefore, the present application is not limited to the above embodiments, and any improvements and modifications made to the present application by those skilled in the art based on the disclosure of the present application should be within the scope of protection of the present application.

Claims

1. A two-stage cascaded high-gain amplifier based on adaptive bias and cascode compensation, characterized in that: It consists of two cascaded amplifier stages. The first stage amplifier uses cross-coupling to form an adaptive bias to improve system gain, while the second stage amplifier uses current multiplexing to achieve higher current efficiency, further improving system gain and output swing.

2. The two-stage cascaded high-gain amplifier according to claim 1, characterized in that: The first-stage amplifier uses an adaptive bias cascode floating inverting amplifier circuit, while the second-stage amplifier uses a current-source biased inverting amplifier circuit.

3. The two-stage cascaded high-gain amplifier according to claim 2, characterized in that: The adaptive bias cascode floating inverting amplifier circuit includes four PMOS transistors M1, M2, M5, and M6, four NMOS transistors M3, M4, M7, and M8, and a capacitor C. RES And six switches S1 to S6, one end of which is connected to the power supply voltage VDD, and the other end of S1 is connected to one end of S3 and C. RES One end of S5 is connected to the source of M1, and the other end of S3 is connected to the source of M2. The gate of M1 is connected to the gate of M3 and serves as the inverting voltage input of the first-stage amplifier. The gate of M2 is connected to the gate of M4 and serves as the non-inverting voltage input of the first-stage amplifier. The drain of M1 is connected to the source of M5 and the gate of M8. The drain of M2 is connected to the source of M6 and the gate of M7. The gate of M5 is connected to the source of M8 and the drain of M4. The gate of M6 is connected to the source of M7 and the drain of M3. The drain of M5 is connected to the drain of M7 and one end of S5 and serves as the non-inverting voltage output of the first-stage amplifier. The drain of M6 is connected to the drain of M8 and one end of S6 and serves as the inverting voltage output of the first-stage amplifier. The other end of S5 is connected to the other end of S6 and connected to an external common-mode voltage V. CM The source of M3 is connected to the source of M4 and one end of S4, and the other end of S4 is connected to C. RES The other end of S1 is connected to one end of S2, and the other end of S2 is grounded; the control electrodes of switches S1, S2, S5, and S6 are connected to the clock signal. The control electrodes of switches S3 and S4 are connected to a clock signal.

4. The two-stage cascaded high-gain amplifier according to claim 2, characterized in that: The current-source biased inverting amplifier circuit includes three PMOS transistors M9, M10, and M13, three NMOS transistors M11, M12, and M14, and two switches S7 to S8. The source of M13 is connected to the power supply voltage VDD, and the gate of M13 is connected to the external bias voltage VDD. BP The drain of M13 is connected to the source of M9 and the source of M10. The gate of M9 is connected to the gate of M11 and serves as the non-inverting voltage input of the second-stage amplifier. The gate of M10 is connected to the gate of M12 and serves as the inverting voltage input of the second-stage amplifier. The drain of M9 is connected to the drain of M11 and one end of S8 and serves as the inverting voltage output of the second-stage amplifier. The drain of M10 is connected to the drain of M12 and one end of S7 and serves as the non-inverting voltage output of the second-stage amplifier. The other end of S7 is connected to the other end of S8 and connected to an external common-mode voltage V. CM The source of M11 is connected to the source of M12 and the drain of M14, and the gate of M14 is connected to the common-mode feedback voltage V. CMFB The source of M14 is grounded; the control terminals of switches S7 and S8 are connected to the clock signal.

5. The two-stage cascaded high-gain amplifier according to claim 3, characterized in that: The clock signal Clock signal used to close the switch during the system reset phase. Used to close the switch during the system amplification phase. and The phases are complementary and there is a certain dead time.

6. The two-stage cascaded high-gain amplifier according to claim 4, characterized in that: The clock signal Clock signal used to close the switch during the system reset phase. Used to close the switch during the system amplification phase. and The phases are complementary and there is a certain dead time.

7. The two-stage cascaded high-gain amplifier according to claim 4, characterized in that: The common-mode feedback voltage V CMFB The common-mode feedback circuit generates and provides the voltage. This circuit includes two resistors R1 and R2, and an amplifier AMP1. One end of R1 is connected to the non-inverting voltage output of the second-stage amplifier, and one end of R2 is connected to the inverting voltage output of the second-stage amplifier. The other end of R1 is connected to the other end of R2 and the non-inverting input of AMP1. The inverting input of AMP1 is connected to the common-mode voltage V. CM The output of AMP1 generates a common-mode feedback voltage V. CMFB .

8. The two-stage cascaded high-gain amplifier according to claim 3, characterized in that: A common-source cascode compensation circuit is provided between the two amplifier stages to provide frequency compensation for the two amplifier stages. It includes four capacitors C1 to C4. One end of C1 is connected to the drain of M3, one end of C2 is connected to the drain of M1, and the other end of C1 is connected to the other end of C2 and connected to the inverting voltage output terminal of the second amplifier stage. One end of C3 is connected to the drain of M4, one end of C4 is connected to the drain of M2, and the other end of C3 is connected to the other end of C4 and connected to the non-inverting voltage output terminal of the second amplifier stage.

9. The two-stage cascaded high-gain amplifier according to claim 1, characterized in that: The basic structure of a two-stage cascaded amplifier is adopted. The first stage adopts an adaptive bias cascode floating inverting amplifier structure, which significantly improves the gain through cross-coupling bias, while obtaining a larger current to improve bandwidth and slew rate, and eliminates the need for external bias circuits and additional common-mode feedback circuits. The second stage adopts a current-source biased inverting amplifier structure, which achieves high current efficiency and obtains a large output swing through current multiplexing.

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