Support structure, electrical component and method for producing an electrical component

Abstract

A support structure (1) for an electrical component (10) comprises a main body (2), a plurality of conductor tracks (3) on a main side (20) of the main body (2) and a structured top layer (4) on the main side (20) of the main body (2). According to a first alternative, in a view of the main side (20), the structured top layer (4) forms a negative image of the conductor tracks (3), so that the conductor tracks (3) are free of the top layer (4). According to a second alternative, in a view of the main side (20), the structured top layer (4) forms a positive image of the conductor tracks (3), so that the conductor tracks (3) are completely covered by the top layer (4) and regions of the main side (20) outside the conductor tracks (3) are free of the top layer (4). An electrical component (10) comprising a µLED is also indicated.

Description

[0001] Description

[0002] Support structure, electrical component and method for manufacturing an electrical component

[0003] A support structure for an electrical component is described. Furthermore, an electrical component, which in particular has such a support structure, is described. Finally, a method for manufacturing such an electrical component is described.

[0004] One task to be solved is to specify an improved support structure on which, in particular, small electrical components can be mounted. Further tasks to be solved include specifying an improved electrical component and a method for manufacturing such an electrical component.

[0005] These tasks are solved by a support structure with the features of independent claim 1, electrical components with the features of independent claims 9 and 11, and by a method with the features of claim 14. Advantageous further developments and more advanced embodiments are the subject of the dependent claims.

[0006] According to at least one embodiment, the support structure comprises a base body. The base body is, for example, a film. The base body is, in particular, comparatively thin. A thickness, measured perpendicular to the principal plane of extension of the base body, is, for example, between 50 pm and 150 pm. Preferably, the base body is transparent. For example, an electronic chip can be applied to the support structure. For example, the electronic chip is a light-emitting element such as an optoelectronic semiconductor chip. Preferably, the base body is transparent to radiation emitted by the optoelectronic semiconductor chip during intended operation. The base body comprises, for example, polyethylene terephthalate (PET).

[0007] According to at least one embodiment, the carrier structure comprises a plurality of conductive traces on a main face of the base body. The conductive traces are formed, for example, with a metal such as copper. In particular, the conductive traces are a structured metallization on the base body. The thickness of the conductive traces, perpendicular to the main face, is, for example, 2 pm. The main face extends, in particular, parallel to the principal extension plane of the base body. The width of the conductive trace, measured, for example, in relation to the main face, is, for example, between 5 pm and 10 pm.

[0008] The conductor tracks can be arranged in a grid pattern. This means, in particular, that the conductor tracks can form a grid pattern. Such a grid pattern is also known as a "mesh". The spacing of the conductor tracks, measured parallel to the main surface, is, for example, between 100 pm and 200 pm.

[0009] For example, if an electrical chip is placed on the carrier structure during its intended use, the electrical chip can be electrically contacted via the conductor track. According to at least one embodiment, the

[0010] The supporting structure consists of a structured cover layer on the main surface of the base body. In particular, the cover layer partially covers the base body when viewed from the main surface.

[0011] According to at least one embodiment, in a first alternative, the structured cover layer forms a negative image of the conductor tracks when viewed from the main surface. That is, the conductor tracks are free of the cover layer. In particular, when viewed from the main surface, the main surface is completely covered by the cover layer together with the conductor tracks, so that the base body is no longer recognizable in this view. Preferably, all areas of the base body that are not covered by the conductor tracks are covered by the cover layer, and vice versa.

[0012] According to at least one embodiment, in a second alternative, the structured top layer forms a positive image of the conductor tracks on the main surface, so that the conductor tracks are completely covered by the top layer and areas of the main surface outside the conductor tracks are free of the top layer. This means, in particular, that when viewed from the main surface, the conductor tracks are covered, so that the conductor tracks are no longer visible.

[0013] According to at least one embodiment, the conductor tracks have a connection structure with a first connection point and a second connection point. Different electrical potentials can be applied to the first and second connection points. The first and second connection points are, in particular, spaced at a maximum distance of 50 pm or at most 25 pm. The distance is measured, in particular, parallel to the main surface.

[0014] During normal use of the carrier structure, the electronic chip can be applied to the connection structure. The electronic chip is then brought into electrical contact at the first or second connection point. For example, the first connection point forms a cathode and the second connection point an anode for the electronic chip, or vice versa. This allows the electronic chip to be energized and contacted during normal operation. Advantageously, the electrical contact surfaces of the electronic chip can be close together, as the connection points themselves are also relatively close together, at most 50 pm or 25 pm apart. Therefore, the electronic chip can be, for example, a pLED, a microsensor, or a small integrated circuit (pIC).

[0015] The following technical considerations underlie the support structure described here. Connection techniques for small electrical components, such as micro LEDs, require the precise application of contact materials like solder without causing a short circuit between the contact surfaces. At the same time, these connection techniques should be cost-effective.

[0016] Typically, anisotropically conductive films and adhesives are used as contact materials. However, these are usually not transparent and can only form a connection through the application of pressure. Alternatively, a solder can be applied via an autocatalytic process, although this only allows the deposition of tin with a melting point of approximately 230 °C. Another alternative is a printing process, which can be combined with scoring a substrate surface to enable the contact surfaces to be encased by the contact material. However, this places high demands on alignment and precise process control.

[0017] The support structure described here utilizes the idea of ​​placing a cover layer between the conductor tracks in the first alternative. This cover layer is preferably electrically insulating, allowing the conductor tracks to be electrically isolated from one another. The cover layer can be structured so finely that it can be positioned between the connection points of the support structure and between the contact surfaces of the electronic chip. This allows both the connection points and the contact surfaces to be kept electrically isolated from each other, significantly reducing the risk of a short circuit.

[0018] Furthermore, the electronic chip can be electrically connected to the substrate using the relatively inexpensive reflow soldering process. In this process, the electronic component is applied to the top layer, and the gap between the component's contact surfaces and the substrate's connection points is filled with solder or solder paste. Advantageously, this eliminates the need for precision printing to apply a contact material. Simultaneously, gaps between the electronic chip and the substrate can be filled easily and reliably with the contact material. For the top layer, the first alternative can be a so-called negative photoresist, which can be cross-linked through the substrate by irradiation. During the development of the negative photoresist, the areas not exposed to radiation are removed.This makes structuring the top layer particularly easy.

[0019] In the second alternative, the support structure described here utilizes the idea of ​​coating the conductor track with a cover layer. A gap can be formed between different areas of the cover layer, allowing them to be electrically isolated from one another. In this alternative, the cover layer is preferably electrically conductive. When the support structure is used as intended, the electronic chip can be placed on the cover layer and electrically connected. The gap provides electrical separation between the connection points or contact surfaces of the electronic chip.

[0020] In the second alternative, the top layer can be a so-called positive photoresist, which can be weakened by irradiation through the substrate. The conductor tracks can then serve as a shadow mask. During development of the positive photoresist, the areas exposed to the radiation are removed. This makes structuring the top layer particularly easy.

[0021] According to at least one embodiment of the support structure, at least one intermediate layer is arranged between the conductive traces and the substrate. The intermediate layer can comprise acrylic, silicone, epoxy, PET, PC, or glass. Preferably, the intermediate layer is transparent, particularly to radiation that may be generated by the electronic chip during its operation.

[0022] It is also possible that multiple intermediate layers are present. In this case, each of the intermediate layers can comprise at least one of the materials mentioned above.

[0023] According to at least one embodiment of the carrier structure, the conductor tracks are at least partially embedded in the intermediate layer(s). This means, in particular, that the intermediate layer(s) at least partially surrounds or encloses the conductor tracks. During the manufacturing process, the conductor track layout can be predetermined, and the conductor tracks can be manufactured particularly easily.

[0024] According to at least one embodiment of the substrate, the conductor tracks are blackened on the side facing away from the substrate. For example, the conductor tracks are coated with palladium, titanium, copper nitride, or copper oxide and thus blackened. Advantageously, this reduces the risk of reflections that can occur on a metallic conductor track. Consequently, the optical properties of the substrate can be improved, especially if a light-emitting element is applied to the substrate as an electronic chip.

[0025] Preferably, both the side of the conductor tracks facing away from the base body and a side facing the base body are blackened, in particular with at least one of the above-mentioned materials.

[0026] According to at least one advantageous embodiment, the conductor tracks are blackened on all sides. That is, all outer surfaces of the conductor tracks can be blackened, in particular by means of at least one of the materials mentioned above. Advantageously, this further reduces the risk of reflections that can occur on a metallic conductor track. Consequently, the optical properties of the substrate can be further improved, especially in the case where a light-emitting element is applied to the substrate as an electronic chip.

[0027] According to at least one embodiment, the width of the conductor track, measured, for example, in relation to the main surface, is between 2 pm and 10 pm. Furthermore, the conductor tracks can be arranged regularly and in a grid pattern. This means, in particular, that the conductor tracks can form a regular grid pattern. In a regular grid pattern, the conductor tracks are preferably equidistant, at least in certain areas. Such a grid pattern is also known as a "mesh." The spacing of conductor tracks, measured parallel to the main surface, is, for example, between 100 pm and 200 pm in the grid pattern.

[0028] According to the present design, the conductor tracks are relatively narrow compared to their spacing. Advantageously, this makes the support structure essentially transparent, especially when transparent or see-through materials are used for the base body. This means, in particular, that the support structure can appear transparent or see-through to a human observer. A uniform, grid-like arrangement of the conductor tracks, in particular, creates a transparent impression, since areas with comparatively closely spaced conductor tracks can appear darker to the human observer.

[0029] If, in the application case, an electrical component such as a chip or an optoelectronic component such as an optoelectronic semiconductor chip, for example a pLED, with relatively small spatial dimensions is arranged on the support structure, the component consisting of the support structure and the chip can appear transparent.

[0030] According to at least one embodiment of the support structure, the top layer is transparent. In particular, the top layer is transparent to radiation that can be generated by the electronic chip during operation, for example, if the electronic chip is a light-emitting element.

[0031] This can advantageously improve the optical properties of the support structure.

[0032] According to at least one embodiment of the support structure, the top layer in the first alternative is a negative photoresist, a silicone, or an epoxy. Preferably, the top layer in this alternative is electrically insulating. Advantageously, an electrically insulating top layer allows conductive traces that can be applied to different potentials to be electrically separated from one another. According to at least one embodiment of the support structure, the top layer in the second alternative is an electrically conductive positive photoresist. Advantageously, this allows an electrical chip to be directly connected to the top layer. That is, a contact material such as solder or the like can be dispensed with.

[0033] Furthermore, an electronic component is specified. The electronic component can comprise a support structure as described here. That is, all features of the support structure described here are also those of the electronic component described here, and vice versa.

[0034] According to at least one first embodiment of the electrical component, the electrical component has a support structure as described here, according to the first alternative. Furthermore, the electrical component has at least one electronic chip.

[0035] The electronic chip has, in particular, a first electrical contact surface and a second electrical contact surface. The first electrical contact surface is, for example, an anode and the second electrical contact surface, for example, a cathode of the electronic chip, or vice versa. The first and second contact surfaces are, for example, each formed with a metal.

[0036] The first electrical contact surface is preferably electrically connected to the first connection point of the support structure's connection element. The second electrical contact surface is preferably electrically connected to the second connection point of the support structure's connection element. The support structure thus allows the electrical chip to be powered and contacted during operation.

[0037] Preferably, at least a portion of the cover layer is arranged between the first and second contact surfaces. More preferably, this portion of the cover layer electrically separates the first and second contact surfaces from each other. For example, the cover layer is arranged in a space between the first and second contact surfaces on a side of the electronic chip facing the substrate. Preferably, the first and second contact surfaces are also arranged on this side. In this embodiment, the cover layer is preferably electrically insulating.

[0038] In a preferred embodiment of the first electrical component, a contact material is arranged between the first contact surface and the first connection point, as well as between the second contact surface and the second connection point. The contact material is, for example, solder, solder paste, or an electrically conductive adhesive.

[0039] For example, the top layer has a greater thickness than the conductor tracks. This allows a gap to form between the conductor tracks and the electronic chip when the electronic chip is placed on the top layer. This gap is preferably filled by the contact material to establish an electrical connection between the electronic chip and the conductor tracks and to fill the gap.

[0040] During the manufacturing of the electrical component, the

[0041] The contact material, for example in liquid or viscous form, is applied and preferentially penetrates the gap. Subsequently, the contact material can be hardened or melted to fill the gap and establish the electrical connection between the conductor tracks and the electronic chip. During this process, a solvent can be removed from the contact material, particularly if the contact material is a solder paste in which solder balls are dissolved in a flux or solvent.

[0042] According to at least one second embodiment of the electrical component, the electrical component has a support structure as described here in the second alternative. Furthermore, the electrical component has at least one electronic chip.

[0043] The electronic chip has, in particular, a first electrical contact surface and a second electrical contact surface. The first electrical contact surface is, for example, an anode and the second electrical contact surface, for example, a cathode of the electronic chip, or vice versa. The first and second contact surfaces are, for example, each formed with a metal.

[0044] The first electrical contact surface is preferably electrically connected to the first connection point of the support structure. The second electrical contact surface is preferably electrically connected to the second connection point of the support structure. The support structure thus allows the electrical chip to be energized and contacted during operation. Preferably, at least a portion of the cover layer is arranged between the first contact surface and the first connection point, as well as between the second contact surface and the second connection point. The cover layer is further preferably electrically conductive.

[0045] Advantageously, in the second design form, the electrical chip can be placed directly on the top layer, and an electrically conductive connection between the chip and the conductor tracks can be achieved via the electrically conductive top layer.

[0046] According to at least one further development of the first or second embodiment of the electrical component, the distance between the first and second contact surfaces is at most 50 pm or at most 25 pm. The distance is measured, for example, parallel to a side of the electrical chip facing the support structure.

[0047] The support structure described here allows the electronic chip to be reliably electrically connected despite the relatively small distance between the contact surfaces. In the first embodiment, electrical insulation between the connection points of the support structure and between the contact surfaces is achieved by means of the cover layer. In the second embodiment, the electronic chip can be applied directly to the cover layer, thus advantageously eliminating a complex bonding process between the electronic chip and the support structure.

[0048] According to at least one advanced training course of the first or second

[0049] In its implemented form, the electronic chip is an optoelectronic semiconductor chip designed to emit electromagnetic radiation. Specifically, the optoelectronic semiconductor chip comprises a semiconductor body with an active zone in which electromagnetic radiation is generated during intended operation. Preferably, the semiconductor body is based on a II-IV compound semiconductor. The optoelectronic semiconductor chip can be configured to emit radiation in the visible region of the electromagnetic spectrum, infrared radiation, or ultraviolet radiation.

[0050] According to at least one further development of the first or second embodiment of the electrical component, the electronic chip is a pLED. Preferably, the electronic chip is a horizontal pLED, also referred to as an hpLED. The electronic chip is, for example, designed as a flip chip.

[0051] As a broad definition, a pLED or micro-LED could be seen as any light-emitting diode (abbreviated "LED") - i.A. not a laser - with a particularly small size.

[0052] In the usual case - this is also a very important criterion besides size - a growth substrate is removed in micro-LEDs, so that typical heights of such micro-LEDs are, for example, in the range of 1.5 pm to 20 pm.

[0053] In principle, a micro-LED does not necessarily have to have a rectangular emission surface. Generally, for example, an LED could have an emission surface where, viewed from above, each lateral extent of the emission surface is less than or equal to 100 g / m² or less than or equal to 70 g / m².

[0054] For example, for rectangular micro-LEDs, an edge length of less than or equal to 70 gm or less than or equal to 50 gm is often cited as a criterion, especially when looking at the layers of the layer stack from above.

[0055] Most of these micro-LEDs are provided on wafers with holding structures that can be removed without damaging the gLED.

[0056] Currently, the primary application for micro-LEDs is in displays. Micro-LEDs form pixels or subpixels and emit light of a defined color. Due to their small pixel size and high density with close spacing, micro-LEDs are suitable for small monolithic displays for AR applications, particularly smart glasses. Further applications are also being developed, especially in data communication and pixelated lighting applications.

[0057] In the literature you will find various spellings for micro-LED, e.g. gLED, g-LED, uLED, u-LED or Micro Light Emitting Diode.

[0058] Alternatively, the electronic chip could be a microsensor or a gIC.

[0059] According to at least one further development of the first or second embodiment of the electrical component, at least one protective layer is applied to a side of the electrical chip facing away from the base body or the support structure. Preferably, the protective layer is transparent, particularly in the case that radiation is emitted by the electrical chip during operation.

[0060] The protective layer can consist of acrylic, silicone, epoxy, PET, PC, PMMA, or glass. This protective layer shields the electronic chip from environmental influences.

[0061] It is possible for the protective layer to extend onto the substrate. For example, the protective layer covers the substrate and / or the electronic chip facing the main surface of the substrate. Advantageously, this can also protect the substrate from environmental influences.

[0062] According to at least one further development of the first or second embodiment of the electrical component, several electronic chips are mounted on the support structure. For example, the support structure comprises several connection structures, each connection structure being assigned to an electronic chip. For example, the electronic chips are attached to nodes of a regular grid.

[0063] The multiple electronic chips can comprise different types of chips. For example, some of the electronic chips can be pLEDs, and at least one electronic chip can be a pIC, for instance, for controlling the pLED. It is also possible that all electronic chips are pLEDs or pICs. Furthermore, a method for fabricating an electronic component is specified. This method can be used, in particular, to fabricate an electronic component as described herein. That is, all features of the electronic component and the support structure described herein are also of the method described herein, and vice versa.

[0064] In at least one embodiment of the method, a base body with a plurality of conductor tracks is provided on a main side of the base body.

[0065] In a subsequent step of the process, a coating material is applied to the main surface of the substrate. This coating material is, for example, viscous. It can be textured or cured to form a coating layer. The coating material could be, for example, a photoresist that can be developed.

[0066] In one step of the process, at least one electronic chip is applied to the substrate. The chip can be applied directly or indirectly to the substrate.

[0067] In one step of the process, the cover material is structured to form the cover layer. During this process, the cover material is irradiated through the base body. That is, the base body is irradiated from a direction opposite the main surface. The base body is preferably transparent to the radiation with which the cover material is irradiated. This radiation is, for example, UV radiation. According to at least one embodiment of the process, the step of applying the at least one electronic chip is carried out before structuring the cover material. In particular, the chip is applied to the cover material. Specifically, the electronic chip is applied to a side of the cover material facing away from the base body.

[0068] According to an alternative embodiment to the one just described, the step of structuring the cover material is performed before the electronic chip is applied. Specifically, the chip is applied to the cover layer. In particular, the electronic chip is applied to a side of the cover layer facing away from the substrate.

[0069] By applying the chip to the structured cover material or cover layer, the risk of the chip slipping or misaligning during structuring, especially during the development of the cover material into the cover layer, can be reduced.

[0070] According to at least one implementation form of the process, the structured cover layer is designed in such a way that the cover layer forms a negative image of the conductor tracks, in view of the main side.

[0071] For example, the coating material is a negative photoresist. Irradiation cross-links the coating material in the areas exposed to the radiation. The conductive traces then form a shadow mask for the coating material. During the development of the photoresist, cross-linked areas remain on the substrate. In particular, an electrical component according to the first embodiment is produced in this process.

[0072] According to at least one embodiment of the method, after structuring the cover material and / or after depositing the chip, the electronic chip is in contact with the substrate exclusively via the cover layer. In a step following the structuring of the cover material, a gap between the substrate and the electronic chip is filled with a contact material, so that the electronic chip is electrically connected to the conductor tracks. In particular, the electronic chip is electrically connected to the terminal structure of the substrate. For example, the first contact surface of the electronic chip is connected to the first terminal of the terminal structure, and the second contact surface of the electronic chip is connected to the second terminal of the terminal structure.

[0073] For example, the cover layer has a greater thickness than the conductor tracks. This allows a gap to form between the conductor tracks and the electronic chip if the cover material is structured. This gap is preferably filled by the contact material to establish an electrical connection between the electronic chip and the conductor tracks and to fill the gap.

[0074] For example, the contact material is applied in liquid or viscous form and preferentially penetrates the gap. For instance, the contact material is applied by printing, such as screen printing or stencil printing, or by dispensing. Advantageously, this allows for a relatively simple and cost-effective process for applying the solder. In particular, no precise alignment is necessary, unlike other soldering methods used to solder pLEDs or small electronic chips.

[0075] The contact material can then be cured to fill the gap and establish the electrical connection between the conductor tracks and the electronic chip. During this process, a solvent can be removed from the contact material, particularly if the contact material is a solder paste in which solder balls are dissolved in a flux or solvent.

[0076] In particular, an electrical component is manufactured according to the first embodiment.

[0077] According to at least one embodiment of the method, the structured cover layer is designed such that, when viewed from the main surface, the cover layer completely covers the conductor tracks and is limited to the conductor tracks. In particular, areas of the main surface outside the conductor tracks are free of the cover layer.

[0078] In particular, an electrical component is manufactured according to the second embodiment.

[0079] According to at least one embodiment of the method, after structuring the cover material and / or after depositing the chip, the electronic chip is in contact with the substrate exclusively via the cover layer. According to at least one embodiment of the method, the cover layer is electrically conductive, and the electronic chip is electrically connected to the conductor tracks, in particular to the connection structure of the substrate, by means of the cover layer. For example, the first contact surface of the electronic chip is connected to the first connection point of the connection structure, and the second contact surface of the electronic chip is connected to the second connection point of the connection structure. Advantageously, a contact material such as solder or the like can be omitted.

[0080] In particular, an electrical component is manufactured according to the second embodiment.

[0081] According to at least one implementation, after structuring the top layer, another layer of top layer material is applied to the main surface. The structured top layer can then be removed, and the additional top layer can be cured to form a further top layer. Specifically, this additional top layer forms a negative image of the conductor tracks. For example, the top layer that is removed forms a positive image of the conductor tracks.

[0082] The additional coating material can be silicone, acrylic, glass, or epoxy. Alternatively, it can be a photoresist. The additional coating material can be cured by radiation, heat, or chemical means. Further advantages and beneficial embodiments and developments of the support structure, the electrical component, and the method will become apparent from the exemplary embodiments presented below in conjunction with schematic drawings. Identical, similar, and similarly functioning elements are designated with the same reference symbols in the figures. The figures and the relative sizes of the elements depicted in the figures are not necessarily to be considered as being to scale. Rather, individual elements may be exaggerated for clarity and / or better understanding.

[0083] They show:

[0084] Figure 1 shows a schematic sectional view of an electrical component described herein comprising a support structure described herein according to a first embodiment.

[0085] Figure 2 shows the electrical component according to the first embodiment in top view.

[0086] Figure 3 shows a schematic sectional view of an electrical component described herein comprising a support structure described herein according to a second embodiment.

[0087] Figure 4 shows an electrical component described herein comprising a support structure described herein according to a third embodiment in a schematic sectional view.

[0088] Figures 5 to 9 show different process stages of a process described here for the manufacture of an electrical component according to a first embodiment in schematic sectional view.

[0089] Figures 10 to 12 show different process stages of a process described here for the manufacture of an electrical component according to a second embodiment in schematic sectional view.

[0090] Figures 13 to 17 show different process stages of a process described here for the manufacture of an electrical component according to a third embodiment in schematic sectional view.

[0091] Figure 1 shows an electrical component 10 described herein, comprising a support structure 1, according to a first embodiment. An electronic chip 6 is arranged on the support structure 1. The electronic chip 6 is a pLED, in particular an hpLED. The electronic chip 6 is configured to emit electromagnetic radiation. The electronic chip 6 comprises a semiconductor body with an active zone in which the radiation is generated during operation.

[0092] The support structure 1 comprises a base body 2. The base body 2 is, for example, a film and comprises polyethylene terephthalate (PET). The base body 2 is transparent to radiation generated during the operation of the chip 6. The base body 2 has a thickness, measured perpendicular to its principal plane of extension, of 100 pm.

[0093] The base body 2 has a main surface 20 on which conductor tracks 3 are arranged. The conductor tracks 3 comprise copper. The conductor tracks 3 each have a thickness of 2 pm.

[0094] The conductor tracks 3 are arranged in a grid or "mesh". The width of the conductor tracks 3, visible in a top view of the main surface 20 (Figure 2), is between 5 pm and 10 pm. The spacing of the conductor tracks 3 in the grid is between 100 pm and 200 pm.

[0095] The conductor tracks 3 are blackened when viewed from the main side 20 (see Figure 2). For example, the conductor tracks 3 are coated with palladium, a copper nitride, or a copper oxide and are thus blackened.

[0096] An intermediate layer 5 comprising acrylic is arranged between the conductive traces 3 and the base body 2. The conductive traces 3 are embedded in the intermediate layer 5. The intermediate layer 5 can simplify the fabrication of the conductive traces 3. The intermediate layer 5 is preferably transparent.

[0097] On the main surface 20 of the base body 2, a cover layer 4 is arranged next to the conductor tracks 3. The cover layer 4 is a photoresist, in particular a negative photoresist. The cover layer 4 forms a negative image of the conductor tracks 3 when viewed from the main surface 20 (Figure 2). That is, when viewed from the main surface 20, the main surface 20 is completely covered by the conductor tracks 3 together with the cover layer 4.

[0098] The electronic chip 6 is arranged on the top layer 4. The electronic chip 6 is located on the side of the top layer 4 facing away from the base body 2. The top layer 4 has a greater thickness than the conductor tracks 3 and / or is applied to the intermediate layer 5, so that a gap is created between the electronic chip 6 and the conductor tracks 3. The gap is filled with a contact material 7. The contact material 7 is a solder, a solder paste, or an electrically conductive adhesive.

[0099] The conductor tracks 3 have a connection structure. The connection structure comprises a first connection point 31 and a second connection point 32. In normal operation, different electrical potentials can be applied to the first connection point 31 and the second connection point 32. The first connection point 31 and the second connection point 32 are spaced 30 apart, measured parallel to the main surface 20, by a distance of at most 50 pm or at most 25 pm.

[0100] The electronic chip 6 has a first electrical contact surface 61 and a second electrical contact surface 62. The first electrical contact surface 61 is connected to the first terminal 31 and the second electrical contact surface 62 is connected to the second terminal 32 by means of the contact material 7. The first contact surface 61 is, for example, a cathode of the electronic chip 6 and the second contact surface 62 is an anode, or vice versa.

[0101] The cover layer 4 is arranged between the connection points 31, 32 (contact surfaces 61, 62). The distance between the contact surfaces 61, 62 is at most 50 pm or at most 25 pm. In the present embodiment, the cover layer 4 is electrically insulating. This allows the connection points 31, 32 and the contact surfaces 61, 62 to be electrically isolated from each other, and the risk of a short circuit is relatively low despite the small distance between the contact surfaces 61, 62 and the connection points 31, 32.

[0102] Figure 3 shows an electrical component 10 described herein, comprising a support structure 1, according to a second embodiment. In contrast to the first embodiment, the conductor tracks 3 and the cover layer 4 are applied directly to the base body 2.

[0103] Furthermore, in contrast to the first embodiment, this embodiment includes a protective layer 8. The protective layer 8 is applied to the support structure 1 and the electronic chip 6. The protective layer 8 is transparent to radiation generated in the chip 6 during operation. The protective layer 8 comprises silicone, acrylic, glass, and / or epoxy. The protective layer 8 protects the support structure 1 and the chip 6 from environmental influences.

[0104] Figure 4 shows an electrical component 10 described herein, comprising a support structure 1, according to a third embodiment. In contrast to the second embodiment, the cover layer 4 forms a positive image of the conductor tracks 3. That is, the cover layer 4 covers the conductor tracks 3 and is limited to them. In this embodiment, the cover layer 4 is an electrically conductive positive photoresist.

[0105] The chip 6 is in direct contact with the cover layer 4. An electrical connection between the chip 6 and the connection points 31, 32 of the support structure 1 is achieved via the cover layer 4. Advantageously, this eliminates the need for a contact material 7 and a relatively complex soldering process.

[0106] In the method according to the first embodiment, a base body 2 with a main surface 20 is provided. Conductive traces 3 are arranged on the main surface 20. A coating material 40 is applied to the main surface 20, in particular as a surface layer. As can be seen in Figure 5, an electronic chip 6 is applied to the coating material 40. The coating material 40 is in particular a negative photoresist that is not yet cross-linked.

[0107] The base body 2 and the conductor tracks 3 preferably have the same features as the base body 2 and the conductor tracks 3 of Figures 1 to 4. The base body 2 has a thickness 21 of 100 pm and the conductor tracks 3 have a thickness 33 of 2 pm. The thickness is determined perpendicular to the main surface 20.

[0108] The chip 6 is a pLED and has a first contact surface 61 and a second contact surface 62 on a side facing the base body 2 for supplying current to the chip 6. On a side facing away from the base body 2, the chip 6 has an edge length 63 of less than 100 pm, for example 80 pm.

[0109] Chip 6 could be the same chip as described in connection with figures 1 to 4.

[0110] In a subsequent process step, the cover material 40 is irradiated with radiation 9 through the base body 2 (Figure 6). The radiation 9 is UV radiation. The base body 9 is transparent to the radiation 9. The conductor tracks 3 are opaque to the radiation 9. That is, the conductor tracks 3 form a shadow mask for the cover material 40.

[0111] The negative photoresist of the top layer material 40 is cross-linked in areas where it is exposed to radiation 9. That is, the top layer material 40 is cross-linked in areas that are not shaded by the conductor tracks.

[0112] The cover material 40 is then developed, whereby non-interlinked areas of the cover material 40 are removed (Figure 7). In this process, the cover material 40 is structured to form the cover layer 4. In the section shown in Figure 7, the cover layer 4 remains only in the area between the first connection point 31 and the second connection point 32 of the support structure 1, or between the first and second contact surfaces 61, 62. This allows the first and second connection points 31, 32, or the first and second contact surfaces 61, 62, to be electrically isolated, thus reducing the risk of a short circuit.

[0113] In an alternative embodiment, it is possible to apply the coating material 40 and develop the negative photoresist of the coating material 40 before applying the chip 6. That is, in a first step, the coating material 40 is applied to the substrate 2 and, as illustrated in Figure 6, irradiated, developing the coating material 40 into the coating layer 4. Subsequently, the chip 6 is applied to a side of the coating layer 4 facing away from the substrate 2, so that the contact surfaces 61, 62 are opposite the corresponding connection points 31, 32. This sequence of steps thus yields an intermediate product as illustrated in Figure 7. The process according to the alternative embodiment can then be continued analogously to the process according to the first embodiment, as described below.

[0114] An advantage of the method according to the alternative embodiment is that during the development of the negative photoresist of the cover material 40, the chip 6 cannot be detached or slip.

[0115] In the method according to the first embodiment and / or the method according to the alternative embodiment, a contact material 7 is applied in a subsequent step to establish an electrical connection between the contact areas 61, 62 and the associated terminals 31, 32. In the present embodiment, the contact material 7 is a solder that is applied in liquid form by means of pressure (Figure 8). Advantageously, this allows for a relatively simple and cost-effective process for applying the solder.

[0116] As illustrated in Figure 9, the contact material 7 penetrates a space between the contact surfaces 61, 62 and the connection points 31, 32, thereby establishing an electrical connection between the chip 6 and the conductor tracks 3. This creates an electrical component 10, for example, a component 10 as described in conjunction with Figure 3.

[0117] The method according to the second embodiment shown in Figures 10 to 12 differs from the method according to the first embodiment (Figures 5 to 9) in that the contact material 7 is a solder paste. The solder paste comprises solder balls 71 dissolved in a solvent, also referred to as flux material 72. In this embodiment, the contact material 7 is applied using a stencil 11 (Figure 10). Advantageously, this allows for a relatively simple and cost-effective process for applying the solder.

[0118] Subsequently, the contact material 7 penetrates the space between the contact surfaces 61, 62 and the connection points 31, 32 (Figure 11). In the process, the flux material 72 can be at least partially removed. For example, the flux material 72 can be at least partially evaporated.

[0119] Residues of the contact material 7, which, for example, remain on the chip 6 (Figure 11), can subsequently be removed to produce an electrical component 10 (Figure 12). For example, the residues of the contact material 7 can be removed using a water jet, compressed air, an adhesive film and / or a brush.

[0120] In the method according to Figures 13 to 17, in contrast to the method according to the first embodiment, a positive photoresist is used as the top layer 40 and arranged on the main surface 20 of the base body 2 (Figure 13). The chip 6 is then applied.

[0121] Figure 14 illustrates how the top layer 40 is irradiated with radiation 9 through the base body 2 for structuring. The radiation 9 is UV radiation. The conductive traces 3 act as a shadow mask. The positive photoresist can be removed during development in areas exposed to the radiation 9 (Figure 15), so that the top layer 40 is structured into a top layer 4 that forms a positive image of the conductive traces 3. That is, the top layer 4 covers the conductive traces 3 and, when viewed from the main surface 20, is limited to them.

[0122] The positive photoresist of the top layer 4 is electrically conductive, thus producing an electrical component 10, for example according to Figure 4. Advantageously, a soldering process can be omitted.

[0123] In another alternative embodiment, the application, irradiation, and development of the coating material 40 or the positive photoresist of the coating material 40 can be carried out before the application of the chip 6. That is, in a first step, the coating material 40 is applied to the substrate 2 and, as illustrated in Figure 14, the coating material 40 is irradiated and developed into the coating layer 4. Subsequently, the chip 6 is applied to a side of the coating layer 4 facing away from the substrate 2, so that the contact surfaces 61, 62 are opposite the associated connection points 31, 32. In particular, a component 10 is produced according to Figure 15.

[0124] An advantage of the method according to the further alternative embodiment is that the chip 6 cannot be detached during the development of the positive photoresist of the cover material 40. Optionally, the method according to the third embodiment and / or according to the further alternative embodiment can be continued by applying another cover material 41 over the entire surface of the main surface 20 (Figure 16). The additional cover material 41 is, for example, a silicone, a glass, or an epoxy resin.

[0125] The additional covering material 41 can subsequently be cured to form a further covering layer 42. Additionally, the covering layer 4 can be removed (Figure 17). This results in the further covering layer 42 forming a negative image of the conductor tracks 3.

[0126] As explained in connection with Figures 8 to 12, a contact material 7 can then be applied to produce an electrical component 10.

[0127] The invention is not limited to the description provided by the exemplary embodiments. Rather, the invention encompasses every new feature as well as every combination of features, which in particular includes every combination of features in the patent claims, even if that feature or combination itself is not explicitly specified in the patent claims or exemplary embodiments.

[0128] This patent application claims priority from German patent application 10 2024 118 074 . 9, the disclosure content of which is hereby incorporated by reference. Reference list

[0129] 1 Support structure

[0130] 2 basic shapes

[0131] 3 conductor track

[0132] 4 Top layer

[0133] 5 Intermediate layer

[0134] 6 electrical chip

[0135] 7 Contact material

[0136] 8 protective layer

[0137] 9 Radiation

[0138] 10 electrical components

[0139] 11 Template

[0140] 20 Main page

[0141] 21 Thickness of the support

[0142] 30 distance

[0143] 31 first junction

[0144] 32 second interchange

[0145] 33 Thickness of the conductor track

[0146] 40 Cover material

[0147] 41 additional decking materials

[0148] 42 additional top layer

[0149] 61 first contact surface

[0150] 62 second contact area

[0151] 63 Edge length of the electronic chip

[0152] 71 Lotkugel

[0153] 72 Flux material of solder paste

Claims

Patent claims 1. Support structure (1) for an electrical component (10) comprising a base body (2) , a plurality of conductor tracks (3) on a main surface (20) of the base body (2) and a structured cover layer (4) on the main surface (20) of the base body (2) , wherein - according to a first alternative, the structured cover layer (4) forms a negative image of the conductor tracks (3) when viewed from the main side (20), so that the conductor tracks (3) are free of the cover layer (4), or - according to a second alternative, the structured cover layer (4) forms a positive image of the conductor tracks (3) in view of the main surface (20), so that the conductor tracks (3) are completely covered by the cover layer (4) and areas of the main surface (20) outside the conductor tracks (3) are free of the cover layer (4).

2. Support structure (1) according to claim 1, wherein - the conductor tracks (3) have a connection structure with a first connection point (31) and a second connection point (32), - different electrical potentials can be applied to the first and second connection points (31, 32), - the first and second interchanges (31, 32) have a distance (30) of no more than 50 pm.

3. Support structure (1) according to claim 1 or 2, wherein at least one intermediate layer (5) is arranged between the conductor tracks (3) and the base body (2), and the conductor tracks (3) are at least partially embedded in the at least one intermediate layer (5).

4. Support structure (1) according to one of the preceding claims, wherein the conductor tracks (3) are blackened at least on one side facing away from the base body (2), and the cover layer (4) is transparent.

5. Support structure (1) according to one of the preceding claims, wherein the conductor tracks (3) are blackened on all sides.

6. Support structure (1) according to one of the preceding claims, wherein the conductor tracks (3) - each have a width between 2 pm and 10 pm, - form a regular grid pattern, and the spacing of the conductor tracks (3) in the grid pattern is between 100 pm and 200 pm.

7. Support structure (1) according to one of the preceding claims, wherein according to the first alternative the cover layer (4) comprises a negative photoresist or a silicone or an epoxy .

8. Support structure (1) according to one of claims 1 to 6, wherein according to the second alternative the top layer (4) comprises an electrically conductive positive photoresist.

9. Electrical component (10) comprising - a support structure (1) according to one of the preceding claims 2 to 7 according to the first alternative and - at least one electronic chip (6) , wherein - the electronic chip (6) a first electrical contact surface (61) and a second electrical contact surface (62) - the first electrical contact surface (61) is connected to the first connection point (31), - the second electrical contact surface (62) is connected to the second connection point (32), - at least part of the cover layer (4) is arranged between the first and second contact surfaces (61, 62) and electrically separates the first and second contact surfaces (61, 62) from each other.

10. Electrical component (10) according to claim 9, wherein between the first contact surface (61) and the first connection point (31) as well as between the second contact surface (62) and the second connection point (32) a contact material (7) is arranged.

11. Electrical component (10) comprising - a support structure (1) according to one of the preceding claims 2 to 6 or 8 according to the second alternative and - at least one electronic chip (6) , wherein - the electronic chip (6) has a first electrical contact surface (61) and a second electrical contact surface (62), - the first electrical contact surface (61) is connected to the first connection point (31), - the second electrical contact surface (62) is connected to the second connection point (32), - at least a part of the cover layer (4) is arranged between the first contact surface (61) and the first connection point (31) as well as between the second contact surface (62) and the second connection point (32), and - the top layer (4) is electrically conductive.

12. Electrical component (10) according to one of claims 9 to 11, wherein a distance (30) between the first and second contact surfaces (61, 62) is at most 50 pm.

13. Electrical component (10) according to one of claims 9 to 12, wherein the electrical chip (6) is a pLED.

14. Method for manufacturing an electrical component (10) comprising the steps: - Providing a basic body (2) of a support structure (1) having a plurality of conductor tracks (3) on a main side (20) of the base body (2) , - Applying a covering material (40) to the main surface (20) of the base body (2) , - Applying at least one electronic chip (6) to the base body (2) , - Structuring the cover material (40) into a cover layer (4) , wherein the cover material (40) is irradiated by the base body (2).

15. Method according to claim 14, wherein the step of applying the at least one electronic chip (6) takes place prior to structuring the cover material (40), so that the chip (6) is applied to the cover material (40).

16. Method according to claim 14, wherein the step of structuring the cover material (40) is carried out before the application of the electronic chip (6), so that the chip (6) is applied to the cover layer (4).

17. Method according to any one of claims 14 to 16, wherein the structured top layer (4) is designed such that the top layer (4) forms a negative image of the conductor tracks (3), in view of the main side (20) .

18. Method according to claim 17, wherein after structuring the cover material (40) the electronic chip (6) is in contact with the base body (2) exclusively via the cover layer (4) and subsequently, after structuring the cover material (40), an intermediate space between the base body (2) and the chip (6) is filled with a contact material (7) so that the chip (6) is electrically connected to the conductor tracks (3).

19. Method according to any one of claims 14 to 16, wherein - the structured cover layer (4) is designed such that the cover layer (4) completely covers the conductor tracks (3) in view of the main surface (20) and is limited to the conductor tracks (3), - after structuring the cover material (40) the electronic chip (6) is in contact with the base body (2) exclusively via the cover layer (4), - the cover layer (4) is electrically conductive and the chip (6) is electrically connected to the conductor tracks (3) by means of the cover layer (4).

20. Method according to claim 19, wherein structuring the cover material (40) is subsequently carried out - another covering material (41) is applied over the entire surface of the main side (20), - the structured top layer (4) is removed, - the further covering material (41) is cured to form a further covering layer (42), so that the further covering layer (42) forms a negative image of the conductor tracks (3).

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