Transmission / reception circuit, semiconductor integrated circuit, signal monitoring method, and transmission / reception system

Abstract

This transmission / reception circuit includes: a transmission circuit that transmits first transmission data on the basis of a clock generated from a reference clock; a reception circuit that receives reception data on the basis of the clock; a connecting pathway on which the first transmission data from the transmission circuit is inputted into the reception circuit as reception data; and a monitor circuit. The monitor circuit performs a monitoring process to generate information indicating a signal quality of the first transmission data by performing linear interpolation processing between pairs of temporally adjacent first input data on the basis of a plurality of temporally continuous first input data. This makes it possible to generate information indicating the quality of signals transmitted and received between semiconductor chips while suppressing an increase in circuit scale.

Description

Transmitter / receiver circuit, semiconductor integrated circuit, signal monitoring method, and transmitter / receiver system

[0001] The present invention relates to a transmitting / receiving circuit, a semiconductor integrated circuit, a signal monitoring method, and a transmitting / receiving system.

[0002] Chiplet technology is known, which builds a system by mounting multiple types of semiconductor chips (chiplets) manufactured using different manufacturing processes on a substrate such as an interposer. For example, in this type of system, the quality of signals transmitted and received between semiconductor chips is measured by an I / O (Input / Output) sensor mounted on the semiconductor chip using signals received by a receive buffer.

[0003] Patent Publication No. 2022-515286 U.S. Patent Application Publication No. 2021 / 0325455

[0004] By using an I / O sensor, the quality of the signal received by the receiving buffer can be measured in real time, but since the I / O sensor has a large circuit scale and is mounted on the semiconductor chip, the cost of the semiconductor chip increases.

[0005] The present invention has been made in view of the above points, and has as its object to generate information indicating the quality of signals transmitted and received between semiconductor chips while suppressing an increase in circuit scale.

[0006] In one aspect of the present invention, a transceiver circuit has a clock generation circuit that generates a clock based on a reference clock, a transmission circuit that transmits first transmission data based on the clock, a reception circuit that receives reception data based on the clock, a connection path that inputs the first transmission data from the transmission circuit to the reception circuit as the reception data, and a monitor circuit that monitors the signal quality of the first transmission data, wherein the monitor circuit performs a monitoring process to generate information indicating the signal quality of the first transmission data by performing linear interpolation processing between sets of first input data that are adjacent in time based on a plurality of first input data that are consecutive in time from the transmission circuit.

[0007] According to the disclosed technology, it is possible to generate information indicating the quality of signals transmitted and received between semiconductor chips while suppressing an increase in circuit size.

[0008] 4 is a cross-sectional view illustrating a problem of a semiconductor device in which multiple semiconductor chips are mounted on an interposer. FIG. 5 is a block diagram illustrating an example of a semiconductor device in a first embodiment. FIG. 6 is a circuit block diagram illustrating an example of a transmission / reception circuit mounted on the slave chip of FIG. 2. FIG. 7 is a flow diagram illustrating an example of a method for generating an eye pattern of transmission data or reception data in the slave chip of FIG. 3. FIG. 8 is a flow diagram illustrating an example of the process of step S210 of FIG. 4. FIG. 9 is a flow diagram illustrating an example of the process of step S220 of FIG. 4. FIG. 10 is an explanatory diagram illustrating an example of an operation for sequentially measuring the amplitude of multiple data by loop processing of steps S220 to S240 of FIG. 4. FIG. 11 is an explanatory diagram illustrating an example of linear interpolation of step S250 of FIG. 4. FIG. 12 is an explanatory diagram illustrating an example of eye pattern drawing processing of step S260 of FIG. 13 is a circuit block diagram illustrating an example of a slave chip in a semiconductor device of a second embodiment.

[0009] Hereinafter, embodiments will be described with reference to the drawings. In the following, a symbol indicating a signal is also used to indicate a signal line, a signal terminal, or a signal node. A single signal line may indicate a multi-bit signal line. Furthermore, when signal lines are complementary signal lines, a single signal line may indicate complementary signal lines.

[0010] 1 shows a problem with a semiconductor device in which multiple semiconductor chips are mounted on an interposer. The semiconductor device 10 shown in FIG. 1 includes a package substrate 1, an interposer 2, a semiconductor chip 11 having a transceiver circuit 15, and a semiconductor chip 12 having a transceiver circuit 16.

[0011] The semiconductor chips 11 and 12 are connected to the interposer 2 via microbumps 13 and 14, respectively. The transmitting / receiving circuit 15 of the semiconductor chip 11 and the transmitting / receiving circuit 16 of the semiconductor chip 12 are connected to each other via the microbumps 13 and 14 and relay wiring 2 a formed in the interposer 2.

[0012] The interposer 2 is connected to the surface of the package substrate 1 via microbumps 5. Ball grid array (BGA) balls 3 for connecting the semiconductor device 10 to the outside are provided on the back surface of the package substrate 1. An external capacitor element 4 or another chip may be connected to the package substrate 1.

[0013] When internal signals processed in the semiconductor chips 11 and 12 are transmitted and received by the transmitter / receiver circuits 15 and 16, respectively, the semiconductor chips 11 and 12 and the relay wiring 2a formed on the interposer 2 do not need to be electrically connected to the wiring in the package substrate 1 and the BGA balls 3. In this case, it is not possible to output the internal signals to a measuring instrument such as a tester electrically connected to the BGA balls 3, and it is not possible to evaluate the eye pattern, etc. of the internal signals transmitted and received between the transmitter / receiver circuits 15 and 16.

[0014] First Embodiment Fig. 2 shows an example of a semiconductor device according to a first embodiment. The semiconductor device 100 shown in Fig. 2 has a master chip 200 and a slave chip 300, which are semiconductor chips. The master chip 200 and the slave chip 300 form a data transmission and reception system. For example, similar to the semiconductor device 10 shown in Fig. 1, the semiconductor device 100 has an interposer connected via microbumps to a package substrate to which BGA balls are connected. The master chip 200 and the slave chip 300 are connected to each other via the interposer.

[0015] The semiconductor device 100 is an example of a chiplet system. The slave chip 300 is an example of a first semiconductor chip or a semiconductor chiplet that constitutes a chiplet system. The master chip 200 is an example of another semiconductor chiplet that constitutes a chiplet system. Furthermore, the master chip 200 and the slave chip 300 are examples of semiconductor integrated circuits.

[0016] The master chip 200 has a transmission / reception circuit 210 and a data processing circuit 280. The transmission / reception circuit 210 has a plurality of transmission / reception channels each including a transmission circuit 220 and a reception circuit 230, a monitor circuit 240, a PLL (Phase Locked Loop) circuit 250, and a DLL (Delay-Locked Loop) circuit 260.

[0017] The slave chip 300 has a transmission / reception circuit 310 and a data processing circuit 380. The transmission / reception circuit 310 has multiple transmission / reception channels, each including a transmission circuit 320 and a reception circuit 330, a monitor circuit 340, and a DLL circuit 360. The transmission / reception circuit 310 is an example of a chiplet transmission / reception circuit that communicates between the master chip 200 and the slave chip 300, and is an example of a first transmission / reception circuit. Note that in FIG. 2 , signal lines other than those used for transmitting and receiving signals between the master chip 200 and the slave chip 300 are omitted from the illustration.

[0018] 1 , signals (internal signals) transmitted and received between the master chip 200 and the slave chip 300 are transmitted to each other via the microbumps 13, 14 and relay wiring 2a formed in the interposer 2. For example, if the signal line transmitting the internal signal is not connected to a signal line provided on the package substrate, it is not possible to evaluate the waveform shape of the internal signal, such as the eye pattern, using a measuring instrument such as a tester electrically connected to the semiconductor device 100.

[0019] Thus, in this embodiment, for example, the monitor circuit 340 may be used to enable evaluation of the eye pattern of a signal transmitted to the master chip 200. Similarly, the monitor circuit 340 may be used to enable evaluation of the eye pattern of a signal received from the master chip 200.

[0020] In the master chip 200, the monitor circuit 240 is connected to each transmitting circuit 220, each receiving circuit 230, and the data processing circuit 280. The monitor circuit 240 outputs transmission data TD1 received from the data processing circuit 280 to each transmitting circuit 220, and outputs data received from each receiving circuit 230 as reception data RD1 to the data processing circuit 280. The monitor circuit 240 also has a function of outputting periodic pattern data having a predetermined data length to the transmitting circuit 220.

[0021] Each transmitting circuit 220 converts the parallel data received from the monitor circuit 240 into 1-bit serial data, and sequentially transmits the converted serial data to the slave chip 300 via a single signal line in synchronization with the transmission clock TXCLK1. The serial data transmitted from each transmitting circuit 220 to the slave chip 300 is also output to the corresponding receiving circuit 230. The transmitting circuit 220 of the master chip 200 is an example of an external transmitting circuit and an example of a second transmitting circuit.

[0022] Each receiving circuit 230 sequentially receives 1-bit serial data from the slave chip 300 in synchronization with the receiving clock RXCLK1, converts the received data into parallel data, and outputs the parallel data to the monitor circuit 240.

[0023] The single signal line connected between the master chip 200 and the slave chip 300 corresponding to each transmission / reception channel is a bidirectional signal line used in common for transmitting and receiving data. That is, the transmission circuit 220 and the reception circuit 230 of the transmission / reception circuit 210 can perform simultaneous bidirectional communication of transmission data and reception data with the slave chip 300 via a common transmission / reception node.

[0024] For example, the bit width of the transmission data TD1 output from the data processing circuit 280 to the monitor circuit 240 is equal to the sum of the bit widths of the transmission data output from the monitor circuit 240 to each transmission circuit 220. For example, the bit width of the reception data RD1 output from the monitor circuit 240 to the data processing circuit 280 is equal to the sum of the bit widths of the reception data output from each reception circuit 230 to the monitor circuit 240.

[0025] The PLL circuit 250 adjusts the phase of the reference clock REFCLK to generate a transmit clock TXCLK1, and outputs the generated transmit clock TXCLK1 to each transmit circuit 220 and the DLL circuit 260. The transmit clock TXCLK1 is also output to the slave chip 300. The PLL circuit 250 is an example of a second clock generation circuit. The DLL circuit 260 adjusts the phase of the transmit clock TXCLK1 to generate a receive clock RXCLK1, and outputs the generated receive clock RXCLK1 to each receive circuit 230.

[0026] The PLL circuit 250 and the DLL circuit 260 allow the transmit clock TXCLK1 and the receive clock RXCLK1 to be adjusted to any phase relative to the phase of the reference clock REFCLK. This makes it possible to independently change the timing of data transmission by the transmitter circuit 220 and the timing of data reception by the receiver circuit 330. Therefore, for example, by mounting an eye monitor that evaluates eye patterns on the master chip 200, the master chip 200 can acquire eye patterns.

[0027] The data processing circuit 280 receives data from the slave chip 300 from the receiving circuit 230 via the monitor circuit 240 and processes the received data. The data processing circuit 280 also outputs the data processing results or data to be processed by the slave chip 300 to the transmitting circuit 220 via the monitor circuit 240.

[0028] In the slave chip 300, the monitor circuit 340 is connected to each transmission circuit 320, each reception circuit 330, and the data processing circuit 380. The monitor circuit 340 outputs transmission data TD2 received from the data processing circuit 380 to each transmission circuit 320, and outputs data received from each reception circuit 330 as reception data RD2 to the data processing circuit 380. The monitor circuit 340 also has a function of outputting periodic pattern data having a predetermined data length to the transmission circuit 320. The monitor circuit 340 also has a function of checking periodic pattern data that the monitor circuit 340 itself outputs via the transmission circuit 320 or periodic pattern data that it receives from the master chip 200 via the reception circuit 330.

[0029] Each transmitting circuit 320 converts the parallel data received from the monitor circuit 340 into 1-bit serial data, and sequentially transmits the converted serial data to the master chip 200 via a single signal line in synchronization with clock CLK2. The serial data transmitted from each transmitting circuit 320 to the master chip 200 is also output to the corresponding receiving circuit 330. The transmitting circuit 320 is an example of a first transmitting circuit.

[0030] Each receiving circuit 330 sequentially receives 1-bit serial data from the master chip 200 in synchronization with the receiving clock CLK2, converts the received data into parallel data, and outputs the parallel data to the monitor circuit 340.

[0031] For example, the bit width of the transmission data TD2 output from the data processing circuit 380 to the monitor circuit 340 is equal to the sum of the bit widths of the transmission data output from the monitor circuit 340 to each transmission circuit 320. For example, the bit width of the reception data RD2 output from the monitor circuit 340 to the data processing circuit 380 is equal to the sum of the bit widths of the reception data output from each reception circuit 330 to the monitor circuit 340.

[0032] The DLL circuit 360 adjusts the phase of the transmission clock TXCLK1 from the master chip 200 to generate a clock CLK2, and outputs the generated clock CLK2 to each transmission circuit 220 and each reception circuit 330. For this reason, the timing of data transmission by each transmission circuit 320 and the timing of data reception by each reception circuit 330 cannot be controlled independently of each other. The DLL circuit 360 is an example of a clock generation circuit, and the transmission clock TXCLK1 is an example of a reference clock.

[0033] The DLL circuit 360 cannot independently control the phases of the clock supplied to the transmitting circuit 320 and the clock supplied to the receiving circuit 330, and therefore cannot shift the timing at which data is received by the receiving circuit 330 relative to the timing at which data is transmitted by the transmitting circuit 320. For this reason, even if an eye monitor for evaluating eye patterns is mounted on the slave chip 300, the slave chip 300 cannot acquire the eye pattern.

[0034] In other words, by incorporating a phase control circuit in the transmission / reception circuit 310 that can generate a clock with a phase different from that of clock CLK2, the phases of the clocks supplied to the transmission circuit 320 and the reception circuit 330 can be controlled independently of each other, making it possible to acquire an eye pattern using an eye monitor. However, incorporating a phase control circuit increases the circuit size of the slave chip 300 and also increases power consumption.

[0035] The data processing circuit 380 receives data from the master chip 200 from the receiving circuit 330 via the monitor circuit 340 and processes the received data. The data processing circuit 380 also outputs the data processing results or data to be processed by the master chip 200 to the transmitting circuit 320 via the monitor circuit 340. The data sampled by the receiving circuit 330 and output from the receiving circuit 330 to the data processing circuit 380 is an example of first output data.

[0036] Fig. 3 shows an example of a transmission / reception circuit 310 mounted on the slave chip 300 of Fig. 2. As shown in Fig. 2, the transmission / reception circuit 310 has multiple transmission circuits 320 and multiple reception circuits 330. However, for ease of understanding, Fig. 3 shows only one transmission circuit 320 and one reception circuit 330.

[0037] The monitor circuit 340 has a CPU (Central Processing Unit) 341, a periodic data generation circuit 342, a selector circuit (SEL) 343, and a periodic data check circuit 344. For example, the periodic data generation circuit 342, the selector circuit 343, and the periodic data check circuit 344 are provided for each of a plurality of transmission / reception channels, each of which includes a transmission circuit 220 and a reception circuit 230, and the CPU 341 is provided in common to the plurality of transmission / reception channels. This makes it possible to measure in parallel the eye patterns of the transmission data TXD2 transmitted to the master chip 200, or to measure in parallel the eye patterns of the reception data RXD2 received from the master chip 200, in the plurality of transmission / reception channels.

[0038] When the eye patterns of the transmission / reception channels are sequentially measured at different timings, the periodic data generation circuit 342, the selector circuit 343, and the periodic data check circuit 344 may be provided in common to the plurality of transmission / reception channels. In this case, in addition to the selector circuit 343, the monitor circuit 340 is provided with an output selector circuit that connects to one of the plurality of transmission circuits 320, and an input selector circuit that connects one of the plurality of reception circuits 330 to the periodic data check circuit 344.

[0039] The transmitting circuit 320 includes multiplexer circuits (MUX) 321 and 322, and buffer circuits 323, 324, and 325. The receiving circuit 330 includes a sampler circuit 331, a selector circuit (SEL) 332, a sampler circuit 333, an adder circuit 334, a demultiplexer circuit (DEMUX) 335, and inverters 336, 337, and 338.

[0040] In the monitor circuit 340, a CPU 341 controls the entire transmission / reception circuit 310. The CPU 341 controls sequentially changing the data determination threshold value VT output to the sampler circuit 333 of the reception circuit 330. The data determination threshold value VT is used as an offset code when the sampler circuit 333 determines the logical value LV of the data.

[0041] The CPU 341 causes the periodic data check circuit 344 to determine the logical value LV of the data output from the receiving circuit 330 in accordance with the sequentially changing data determination threshold VT. The CPU 341 acquires the amplitude of the data output from the receiving circuit 330 based on the logical value LV output from the periodic data check circuit 344.

[0042] The CPU 341 is an example of a processing control circuit that controls a monitoring process that generates information indicating the signal quality of the transmission data TXD2 transmitted by the transmitting circuit 320 or the reception data RXD2 received by the receiving circuit 330 (transmission data transmitted by the transmitting circuit 220 of the master chip 200).

[0043] The periodic data generation circuit 342 generates periodic pattern data having a predetermined data length while receiving an enable signal EN21 at an active level from the CPU 341, and outputs the generated periodic pattern data to the transmission circuit 320 via the selector circuit 343. The periodic data generation circuit 342 is an example of a data generation circuit. The enable signal EN21 is set to an inactive level during a normal operation mode in which the transmission circuit 320 transmits transmission data TD2 from the data processing circuit 380, and is set to an active level during a measurement mode in which the eye pattern of the data output from the transmission circuit 320 is measured.

[0044] When the selection signal S2 from the CPU 341 is at a first logic level (for example, a logic value of 0), the selector circuit 343 selects the transmission data TD2 supplied from the data processing circuit 380 and outputs it to the transmission circuit 320. When the selection signal S2 from the CPU 341 is at a second logic level (for example, a logic value of "1"), the selector circuit 343 selects the periodic pattern data PPD from the periodic data generation circuit 342 and outputs it to the transmission circuit 320. The selector circuit 343 is an example of a first selector circuit.

[0045] For example, the selection signal S2 is set to a first logic level during the normal operation mode and to a second logic level during the measurement mode, and the CPU 341 outputs the selection signal S2 of the second logic level to the selector circuit 343 in accordance with the period during which the enable signal EN21 of the active level is output.

[0046] The periodic data check circuit 344 operates while receiving an enable signal EN22 at an active level from the CPU 341. The periodic data check circuit 344 performs a determination process to determine whether the logical value LV of the data received from the receiving circuit 330 is a logical value "0" or a logical value "1" according to the data determination threshold value VT, and outputs the determined logical value LV (the result of the determination process) to the CPU 341.

[0047] The period data check circuit 344 is an example of a determination circuit. The logical value "0" is an example of a first value, and the logical value "1" is an example of a second value. The enable signal EN22 is set to an active level during the measurement mode and to an inactive level during the normal operation mode.

[0048] When the CPU 341 controls the selector circuit 343 to select the periodic pattern data PPD from the periodic data generation circuit 342 using the selection signal S2, it activates the operation of the periodic data generation circuit 342 and the operation of the periodic data check circuit 344.

[0049] In the transmission circuit 320, the multiplexer circuit 321 converts, for example, 16-bit parallel transmission data received from the monitor circuit 340 into 2-bit transmission data in synchronization with the clock CLK2, and outputs the converted transmission data to the multiplexer circuit 322 (16:2). The multiplexer circuit 322 converts the 2-bit transmission data received from the multiplexer circuit 321 into serial transmission data in synchronization with the clock CLK2, and outputs the converted transmission data to the buffer circuit 323 (2:1).

[0050] The buffer circuit 323 outputs the serial transmission data output from the multiplexer circuit 322 to the buffer circuits 324 and 325. The buffer circuit 324 outputs the serial transmission data output from the buffer circuit 323 to the master chip 200 via the connection node ND2, and also outputs it to the sampler circuit 333 via the connection path CNP. The buffer circuit 325 outputs the serial transmission data output from the buffer circuit 323 to the sampler circuit 331. The node ND2 is an example of a transmitting / receiving node common to the transmitting circuit 320 and the receiving circuit 330. The data transmitted to the sampler circuit 333 via the connection path CNP is an example of received data.

[0051] In the receiving circuit 330 , the sampler circuit 331 determines the logical value of the transmission data received from the buffer circuit 325 , and outputs the determined logical value to the selector circuit 332 .

[0052] During a first measurement mode in which the eye pattern of the transmission data generated by the periodic data generation circuit 342 is measured in the measurement mode, the selector circuit 332 selects internal data inRXD2 having the same logic value as dummy reception data RXD2 corresponding to the dummy data output from the transmission circuit 22 of the master chip 200, and supplies this to the negative input of the adder circuit 334. For example, the dummy reception data RXD2 and the internal data inRXD2 have a logic value of "1." The selector circuit 332 is an example of a second selector circuit.

[0053] The selector circuit 332 selects the output of the sampler circuit 331 and supplies it to the negative input of the adder circuit 334 during the normal mode or during the second measurement mode in which the eye pattern of the transmission data from the transmission circuit 220 of the master chip 200 is measured in the measurement mode.

[0054] The monitor circuit 240 of the master chip 200 may include a periodic data generation circuit that generates data corresponding to the received data RXD2 during the second measurement mode, and a CPU that controls the operation of the periodic data generation circuit. In this case, the monitor circuit 240 of the master chip 200 may include a selector circuit that selects either the transmission data TD1 supplied from the data processing circuit 280 or the periodic pattern data from the periodic data generation circuit and outputs the selected data to the transmission circuit 220. In other words, the monitor circuit 240 may have a configuration in which the periodic data check circuit 344 is omitted from the monitor circuit 340 of the slave chip 300.

[0055] During normal operation mode, the sampler circuit 333 receives, via the connection path CNP, data in which transmission data TXD2 corresponding to transmission data TD2 output from the data processing circuit 380 and reception data RXD2 corresponding to transmission data output from the transmission circuit 220 of the master chip 200 are superimposed. The transmission data TXD2 is an example of first transmission data. The transmission data output from the transmission circuit 220 of the master chip 200 is an example of second transmission data.

[0056] During the first measurement mode for measuring the eye pattern of the transmission data TXD2, the sampler circuit 333 receives, via the connection path CNP, data that is superimposed between the reception data RXD2 corresponding to the dummy data output from the transmission circuit 220 of the master chip 200 and the transmission data TXD2 corresponding to each data included in the periodic pattern data PPD having a predetermined data length output from the periodic data generation circuit 342.

[0057] During a second measurement mode in which the eye pattern of the received data RXD2 is measured, the sampler circuit 333 receives, via the connection path CNP, data in which the received data RXD2 corresponding to each data included in the periodic pattern data having a predetermined data length output from the periodic data generation circuit provided in the data processing circuit 280 of the master chip 200 and the transmitted data TXD2 transmitted from the transmitting circuit 320 are superimposed. During the second measurement mode, the transmitted data TXD2 transmitted from the transmitting circuit 320 may be data corresponding to the transmitted data TD2 output from the data processing circuit 380, or may be data corresponding to the periodic pattern data PPD output from the periodic data generation circuit 342.

[0058] The plurality of transmission data TXD2 having a predetermined data length and being continuous in time, which are input from the transmission circuit 320 to the reception circuit 330 in response to the periodic pattern data PPD, are an example of first input data. Also, the reception data RXD2 having a predetermined data length and corresponding to the periodic pattern data being continuous in time, which are input from the periodic data generation circuit provided in the data processing circuit 380 of the master chip 200 to the reception circuit 330, are an example of first input data.

[0059] The sampler circuit 333 uses the data determination threshold value VT from the CPU 341 to sequentially sample multiple data received via the connection path CNP to determine the logical value, and outputs data indicating the determined logical value to the adder circuit 334.

[0060] The adder circuit 334 removes the component of the data output from the selector circuit 332 from the data output from the sampler circuit 333, and outputs the extracted data component to the demultiplexer circuit 335. During the normal operation mode, the adder circuit 334 extracts the logical value of the received data RXD2 by removing the component corresponding to the transmitted data TXD2 from the logical value of the data in which the transmitted data TXD2 and the received data RXD2 are superimposed.

[0061] During the first measurement mode, the adder circuit 334 extracts the logical value of the transmission data TXD2 by removing the component corresponding to the internal data inRXD2 from the logical value of the data in which the transmission data TXD2 and the dummy reception data RXD2 are superimposed. During the second measurement mode, the adder circuit 334 extracts the logical value of the reception data RXD2 corresponding to the periodic pattern data from the master chip 200 by removing the component corresponding to the transmission data TXD2 from the logical value of the data in which the transmission data TXD2 and the reception data RXD2 corresponding to the periodic pattern data are superimposed.

[0062] The selector circuit 332 and the adder circuit 334 are an example of a data extraction circuit that extracts the component corresponding to the transmit data TXD2 during the first measurement mode and extracts the component corresponding to the receive data RXD2 during the second measurement mode.

[0063] The demultiplexer circuit 335 converts the serial data sequentially received from the adder circuit 334 into 16-bit parallel data, and outputs the converted data to the monitor circuit 340 and the data processing circuit 380 (1:16).

[0064] The DLL circuit 360 adjusts the phase of the transmission clock TXCLK1 received from the master chip 200 via the buffer circuit 351 and outputs it as the clock CLK2. The DLL circuit 360 is an example of a clock generation circuit. The phase adjustment by the DLL circuit 360 may be performed by the CPU 341. The clock CLK2 is supplied to the sampler circuit 333 via inverters 337 and 336, and to the multiplexer circuits 321 and 322 via an inverter 338.

[0065] Fig. 4 shows an example of a method for generating an eye pattern of the transmission data TXD2 or the reception data RXD2 in the slave chip 300 of Fig. 3. The flow shown in Fig. 4 shows an example of a signal monitoring method for monitoring the signal quality of the transmission data TXD2 or the reception data RXD2 by the monitor circuit 340 mounted on the transmission / reception circuit 310. Below, an example of operation in the first measurement mode for measuring the eye pattern of the transmission data TXD2 transmitted from the transmission circuit 320 of the slave chip 200 will be described.

[0066] First, in step S210, the CPU 341 prepares for measurement by setting the monitor circuit 340 and the receiving circuit 330 to the first measurement mode. An example of step S210 is shown in FIG.

[0067] Next, in step S220, the CPU 341 operates the periodic data generation circuit 342 and the periodic data check circuit 344 to measure the amplitude of data TXD2 corresponding to each of the multiple data included in the periodic pattern data PPD from the periodic data generation circuit 342. The subscript n of data Dn is any value between 0 and L-1 when the data length of the periodic pattern data PPD is L. An example of step S220 is shown in FIG.

[0068] Next, in step S230, the CPU 341 increments the counter value n, which indicates the position of the data Dn for which amplitude is to be measured (n=n+1). Note that the initial value of the counter value n is 0.

[0069] Next, in step S240, the CPU 341 determines whether or not the amplitude measurement of all data Dn included in the periodic pattern data PPD has been completed. If the measurement has been completed, the CPU 341 performs step S250. If the measurement has not been completed, the CPU 341 performs step S220. For example, if the counter value n becomes "L", the CPU 341 determines that the amplitude measurement has been completed, and if the counter value n is less than "L", the CPU 341 determines that there is data Dn for which the amplitude has not been measured.

[0070] In step S250, the CPU 341 performs linear interpolation between adjacent data Dn and Dn-1 in the plurality of data Dn included in the periodic pattern data PPD based on the amplitude of the data Dn and the amplitude of the data Dn-1. Linear interpolation will be described with reference to FIG. 8.

[0071] Next, in step S260, the CPU 341 draws an eye pattern using line segments between the multiple sets of data Dn and Dn-1 obtained by linear interpolation in step S250, and ends the eye pattern generation process shown in FIG.

[0072] Fig. 5 shows an example of the processing flow of step S210 in Fig. 4. Steps S211 and S212 show transmission settings for measuring the amplitude of transmission data TXD2 transmitted from the transmission circuit 320. Steps S213 and S214 show reception settings for measuring the amplitude of transmission data TXD2 or reception data RXD2 received by the reception circuit 330.

[0073] First, in step S211, the CPU 341 controls the selector circuit 343 to select the output of the periodic data generation circuit 342. Next, in step S212, the CPU 341 outputs an enable signal EN21 of active level to the periodic data generation circuit 342, causing the periodic data generation circuit 342 to generate periodic pattern data PPD.

[0074] Next, in step S213, the CPU 341 outputs an active level enable signal EN22 to the periodic data check circuit 344, enabling periodic data determination of the logical value LV of the data by the periodic data check circuit 344. Next, in step S214, the CPU 341 initializes to "0" a counter value n indicating the position of data Dn whose amplitude is to be measured in the data supplied from the receiving circuit 330 to the monitor circuit 340 in response to the data included in the periodic pattern data PPD, and ends preparation for measurement.

[0075] Fig. 6 shows an example of the processing flow of step S220 in Fig. 4. First, in step S221, the CPU 341 initializes the offset code (i.e., the data determination threshold value VT) used when the sampler circuit 333 determines the logical value of data to a minimum value (e.g., "0").

[0076] Next, in step S222, the CPU 341 causes the periodic data check circuit 344 to determine the logical value ("0" or "1") of the data Dn supplied from the receiving circuit 330. Next, in step S223, if the periodic data check circuit 344 determines the logical value "0", the data determination threshold value VT is equal to the amplitude of the data Dn, so the CPU 341 performs step S225. On the other hand, if the periodic data check circuit 344 determines the logical value "0", the CPU 341 performs step S224, because the data determination threshold value VT is smaller than the amplitude of the data Dn.

[0077] In step S224, the CPU 341 increments the offset code of the sampler circuit 333 and executes step S222. The offset code is incremented by the CPU 341 increasing the data determination threshold value VT by a predetermined amount. In step S225, the CPU 341 records the data determination threshold value VT corresponding to the current offset code as the amplitude of the data Dn, and ends the process shown in FIG. 6.

[0078] Fig. 7 shows an example of an operation for sequentially measuring the amplitude of a plurality of data Dn by the loop processing of steps S220 to S240 in Fig. 4. In measuring the amplitude of each data Dn (n="0" to "L-1"), the CPU 341 causes the periodic data generation circuit 342 to repeatedly generate periodic pattern data PPD of a data length L.

[0079] Then, in measuring the amplitude of each piece of data Dn (n = "0" to "L-1"), the CPU 341 increases the data judgment threshold VT by a predetermined amount ΔV for each piece of periodic pattern data PPD, while causing the periodic data check circuit 344 to sequentially judge the logical value LV of the bold-framed data Dn indicated by the counter value n among the multiple pieces of data included in the periodic pattern data PPD. For example, while the data judgment threshold VT is lower than the level corresponding to the voltage value of the data Dn whose amplitude is being measured, the periodic data check circuit 344 judges the data Dn to have a logical value of "1." When the data judgment threshold VT becomes equal to or higher than the level corresponding to the voltage value of the data Dn, the periodic data check circuit 344 judges the data Dn to have a logical value of "0."

[0080] The determination of the logical value of each data Dn using the data determination threshold VT ends when the logical value "0" is determined and the amplitude is measured. Then, the CPU 341 records the data determination threshold VT when the logical value "0" is determined as the amplitude of the data Dn. By sequentially incrementing the counter value n, the amplitudes of the L pieces of data Dn included in the periodic pattern data PPD can be sequentially measured and recorded.

[0081] 8 shows an example of the linear interpolation in step S250 in FIG. 4. In the example shown in FIG. 8, the logical values ​​of each data Dn included in the periodic pattern data PPD are "1", "0", "1", "1", "0", "1", "0", "0", .... While FIG. 8 visually shows an example of linear interpolation, in reality, the linear interpolation is performed by the CPU 341 performing calculation processing using the amplitude value and a UI (Unit Interval), which is the acquisition period of the data Dn. Line segment data indicating the line segment obtained by linear interpolation is stored in a memory or the like mounted on the slave chip 300.

[0082] 7, the CPU 341 repeatedly generates periodic pattern data PPD for each of a plurality of data Dn. Then, the CPU 341 causes the sampler circuit 333 to perform downsampling using a data determination threshold value VT that is sequentially increased, and causes the periodic data check circuit 344 to determine the logic value LV of the data Dn, thereby measuring the amplitude of the data Dn. For example, the amplitude of each data Dn is stored in a memory or the like mounted on the slave chip 300.

[0083] For each of n from "0" to "L-1", the CPU 341 performs linear interpolation using the difference between the amplitude of data Dn and the amplitude of the previous data Dn-1 and the UI, to find a line segment corresponding to the waveform of the voltage change of data Dn, Dn-1. That is, the CPU 341 performs linear interpolation between a pair of data Dn, Dn-1 that are adjacent in time. The line segment is an example of information resulting from the linear interpolation process.

[0084] The CPU 341 then sequentially superimposes the line segments obtained by the linear interpolation process on a common coordinate axis using the amplitude information of each data Dn, Dn-1, to generate information on a graphic representation of multiple line segments corresponding to the waveforms of voltage changes of multiple data Dn included in the periodic pattern data PPD, as information indicating the signal quality of the data Dn. The multiple line segments sequentially superimposed are used to draw a pseudo eye pattern, as shown in FIG.

[0085] 9 shows an example of the eye pattern drawing process of step S260 in FIG. 4. The CPU 341 draws a pseudo eye pattern by arranging two figures, each of which is made by overlapping multiple line segments output in FIG. 8, along the time axis at an interval of UI. In practice, the CPU 341 generates information such as drawing data used to draw the eye pattern. For example, by outputting the eye pattern drawing data generated by the CPU 341 to the outside of the semiconductor device 100, the eye pattern can be visually represented and the eye pattern can be evaluated.

[0086] In the above example, the operation in the first measurement mode for measuring the eye pattern of the transmission data TXD2 transmitted from the transmission circuit 320 of the slave chip 200 has been described. However, the operation in the second measurement mode for measuring the eye pattern of the reception data RXD2 transmitted from the transmission circuit 320 of the master chip 200 is similar, except that the transmission settings shown in FIG. 5 are performed in the master chip 200.

[0087] As described above, in the first embodiment, it is possible to generate information indicating the signal quality of the data and to use it to draw an eye pattern, even when data transmitted and received between a plurality of chiplets (master chip 200 and slave chip 300) mounted on semiconductor device 100 is not output to the outside of semiconductor device 100. In this case, by performing linear interpolation processing between pairs of data Dn and Dn-1 using the amplitude of each of the consecutive data Dn and Dn-1, it is possible to generate information indicating the quality of signals transmitted and received between semiconductor chips while suppressing an increase in the circuit scale of the slave chip 300.

[0088] The periodic data generation circuit 342 can cause the periodic data generation circuit 342 to repeatedly output the periodic pattern data PPD without operating the data processing circuit 380. Because it is not necessary to operate the data processing circuit 380, the CPU 341 can generate the periodic pattern data PPD through simple control.

[0089] The selector circuit 343 selects the transmission data TD2 from the data processing circuit 280 or the periodic pattern data PPD from the periodic data generation circuit 342 depending on the operation mode and outputs it to the transmission circuit 320, so that the periodic pattern data PPD can be output to the transmission circuit 320 without colliding with the transmission data TD2. This allows the monitor circuit 340 to measure the amplitude of the transmission data TXD2 based on the data received from the reception circuit 330 corresponding to the correct periodic pattern data PPD.

[0090] The sampler circuit 333 performs logic value determination multiple times for each data Dn using the sequentially changing data determination threshold VT, and the data determination threshold VT when the logic value is inverted can be set as the amplitude of the data Dn by the simple periodic data check circuit 344. This makes it possible to suppress an increase in the circuit size of the monitor circuit 340.

[0091] When measuring the amplitude of the transmit data TXD2 corresponding to the periodic pattern data PPD generated by the periodic data generation circuit 342, the selector circuit 332 selects internal data inRXD2 having the same logical value as the dummy receive data RXD2 from the master chip 200 and outputs it to the adder circuit 334. This allows the adder circuit 334 to remove the component of the receive data RXD2 from the transmit data TXD2, thereby preventing the receive data RXD2 from affecting the measurement of the amplitude of the data Dn. As a result, linear interpolation processing can be performed with high precision, and information used to draw an eye pattern can be generated with high precision.

[0092] Furthermore, by providing the selector circuit 332, it is possible to prevent the components of the transmission data TXD2 output from the sampler circuit 333 from being lost due to the components of the transmission data TXD2 output from the sampler circuit 331.

[0093] Second Embodiment Figure 10 shows an example of a slave chip in a semiconductor device of a second embodiment. Elements similar to those in Figure 3 are given the same reference numerals, and detailed description thereof will be omitted. The configuration of a slave chip 300A shown in Figure 10 is similar to the configuration of the slave chip 300 in Figure 3, except that a transceiver circuit 310A is provided instead of the transceiver circuit 310 in Figure 3. The configuration of a semiconductor device 100 including the slave chip 300A is similar to the configuration of the semiconductor device 100 in Figure 2, except that a slave chip 300A is provided instead of the slave chip 300.

[0094] The transmission / reception circuit 310A has the same configuration as the transmission / reception circuit 310 in FIG. 3, except that it has a reception circuit 330A and a monitor circuit 340A instead of the reception circuit 330 and the monitor circuit 340 in FIG.

[0095] The receiving circuit 330A is different from the receiving circuit 330 in Fig. 3 in that the sampler circuit 331, selector circuit 332, sampler circuit 333, adder circuit 334, and demultiplexer circuit 335 are deleted and an inverter 339, an analog-to-digital conversion circuit (ADC) 371, and a DSP (Digital Signal Processor) 373 are added. The monitor circuit 240A is different from the monitor circuit 240 in Fig. 3 in that the periodic data check circuit 344 is deleted and a memory 372 is added. Note that the memory 372 may be provided outside the monitor circuit 340A.

[0096] The analog-to-digital conversion circuit 371 converts the voltage data supplied via the connection path CNP into digital data in synchronization with the clock CLK2, and supplies the digital data obtained by the conversion to the DSP 373. The digital data obtained by the analog-to-digital conversion circuit 371 indicates the logic value of the received data RXD2 and also indicates the amplitude of the data at the connection node ND2.

[0097] For example, when the analog-to-digital conversion circuit 371 measures the amplitude of the transmission data TXD2 from the transmission circuit 320 of the slave chip 300A, the master chip 200 transmits transmission data with a fixed logical value of "1" to the slave chip 300A, and the transmission data is superimposed on the transmission data TXD2 as the reception data RXD2. Also, when the analog-to-digital conversion circuit 371 measures the amplitude of the reception data RXD2 corresponding to the transmission data from the transmission circuit 220 of the master chip 200, the periodic data generation circuit 342 of the slave chip 300A generates periodic pattern data PPD with a fixed logical value of "1", and the periodic pattern data PPD is superimposed on the reception data RXD2 as the transmission data TXD2.

[0098] The DSP 373 receives a mode signal MODE indicating the operating mode of the transmission / reception circuit 310A from the CPU 341. In normal mode, the DSP 373 measures the amplitude of the transmission data TXD2 from the transmission circuit 320 of the slave chip 300A or the amplitude of the reception data RXD2 corresponding to the transmission data from the transmission circuit 220 of the master chip 200, by subtracting the value of the corresponding digital data supplied from the buffer circuit 325 from the value of the digital data obtained by the analog-to-digital conversion circuit 371 based on the mode signal MODE. The DSP 373, for example, determines the logical value of the reception data RXD2 based on the measured amplitude of the reception data RXD2, and supplies the determined logical value to the data processing circuit 380 as the reception data RD2.

[0099] Based on the mode signal MODE from the CPU 341, in the first measurement mode, the DSP 373 measures the amplitude (amplitude of data Dn) of the transmission data TXD2 (periodic pattern data output from the periodic data generation circuit 342 of the slave chip 300A) from the transmission circuit 320 of the slave chip 300A, for example, by subtracting a digital value corresponding to the logical value "1" from the value of the digital data obtained by analog-to-digital conversion.

[0100] In the second measurement mode, the DSP 373 measures the amplitude (amplitude of data Dn) of the received data RXD2 (periodic pattern data output from the periodic data generation circuit 342 of the master chip 200) corresponding to the transmission data from the transmission circuit 220 of the master chip 200, for example, by subtracting a digital value corresponding to the logical value "1" from the value of the digital data obtained by analog-to-digital conversion, based on the mode signal MODE from the CPU 341. The data of the amplitude of the received data RXD2 (amplitude of data Dn) measured by the DSP 373 in the first measurement mode and the second measurement mode is stored in the memory 372.

[0101] The CPU 341 executes the linear interpolation process shown in step 250 and the eye pattern drawing process shown in step 260 in Fig. 4 based on the data on the amplitude of the received data RXD2 (the amplitude of data Dn) stored in the memory 372. Because the amplitude of data Dn is directly measured by the analog-to-digital conversion circuit 371, the monitor circuit 340A does not need to have the period data check circuit 344 in Fig. 3. Therefore, the CPU 341 does not need to have the function of outputting the enable signal EN22 in Fig. 3.

[0102] In the second embodiment, the method for generating an eye pattern of the transmission data TXD2 or the reception data RXD2 by the slave chip 300A is the same as that in the first embodiment, except that the loop processing of steps S220 to S240 in Fig. 4 is not performed, and the reception setting of steps S213 and S214 in Fig. 5 is not performed. In the second embodiment, the amplitude of the data Dn can be measured directly using the analog-to-digital conversion circuit 371 without performing steps S220 to S240 shown in Fig. 4, and therefore the amplitude of the data Dn can be measured in real time.

[0103] Note that the measurement of amplitude by the analog-to-digital conversion circuit 371 may be performed using actual data transmitted from the master chip 200 or actual data output from the slave chip 300A, instead of each data Dn of the periodic pattern data PPD. Here, the actual data is data generated by the data processing circuit 280 of the master chip 200 or the data processing circuit 380 of the slave chip 300A. In this case, for example, the monitor circuit 240 of the slave chip 300A may not have the periodic data generation circuit 342 and the selector circuit 343, and the CPU 341 may not have the function of outputting the enable signal EN21 and the selection signal S2.

[0104] In this embodiment, the downsampling operation shown in Fig. 7 is not required, and therefore the time required to measure the amplitude of data can be significantly reduced compared to the first embodiment. For example, in the first embodiment (Fig. 7), it takes "L x number of increases in data determination threshold VT x L" cycles to measure the amplitude of L pieces of data Dn, but in the second embodiment, it takes only L cycles.

[0105] As described above, in the second embodiment, as in the first embodiment, even when data transmitted and received between multiple chiplets mounted on the semiconductor device 100 is not output to the outside of the semiconductor device 100, information indicating the signal quality of the data and used to draw an eye pattern can be generated.

[0106] Furthermore, in the second embodiment, by incorporating the analog-to-digital conversion circuit 371 and memory 372 in the transmission / reception circuit 310A, the time required to measure the amplitude of the data Dn can be significantly reduced compared to the first embodiment.

[0107] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form.

[0108] REFERENCE SIGNS LIST 1 package substrate 2 interposer 2a relay wiring 3 BGA ball 4 capacitor element 5 microbump 10 semiconductor device 11, 12 semiconductor chip 13, 14 microbump 15, 16 transmitting / receiving circuit 100 semiconductor device 200 master chip 210 transmitting / receiving circuit 220 transmitting circuit 230 receiving circuit 240 monitor circuit 250 PLL circuit 260 DLL circuit 280 data processing circuit 300, 300A slave chip 310, 310A transmitting / receiving circuit 320 transmitting circuit 321, 322 multiplexer circuit 323, 324, 325 buffer circuit 330, 330A receiving circuit 331 sampler circuit 332 selector circuit 333 sampler circuit 334 adder circuit 335 demultiplexer circuit 336, 337, 338, 339 Inverter 340 Monitor circuit 341 CPU 342 Periodic data generation circuit 343 Selector circuit 344 Periodic data check circuit 351 Buffer circuit 360 DLL circuit 371 Analog-to-digital conversion circuit 372 Memory 373 DSP 380 Data processing circuit CLK2 Clock CNP Connection path EN21, EN22 Enable signal LV Logical value MODE Mode signal ND2 Node PPD Periodic pattern data RD1, RD2 Received data REFCLK Reference clock RXCLK1 Received clock RXD2 Received data S2 Selection signal TD1, TD2 Transmitted data TXCLK1 Transmitted clock TXD2 Transmitted data VT Data judgment threshold

Claims

1. A transceiver circuit having: a clock generation circuit that generates a clock based on a reference clock; a transmission circuit that transmits first transmission data based on the clock; a reception circuit that receives reception data based on the clock; a connection path that inputs the first transmission data from the transmission circuit to the reception circuit as the reception data; and a monitor circuit that monitors the signal quality of the first transmission data, wherein the monitor circuit performs a monitoring process to generate information indicating the signal quality of the first transmission data by performing linear interpolation between sets of the first input data that are adjacent in time based on a plurality of first input data that are consecutive in time from the transmission circuit.

2. The transmitting / receiving circuit according to claim 1, wherein the information indicating the signal quality of the first transmission data is information used to draw an eye pattern.

3. The transmitter / receiver circuit according to claim 1, wherein the monitor circuit receives a plurality of first output data that are successive in time and output from the receiver circuit based on the plurality of first input data, and performs the linear interpolation processing based on the plurality of first output data.

4. The transmitter / receiver circuit according to claim 1, wherein the plurality of first input data are periodic pattern data, and the monitor circuit performs the linear interpolation process based on the periodic pattern data.

5. The transmitter / receiver circuit according to claim 1, wherein the monitor circuit acquires a data amplitude for each of the plurality of first input data, and performs the linear interpolation process based on the data amplitude.

6. The transmitter / receiver circuit according to claim 5, wherein the monitor circuit generates information used to draw an eye pattern based on information on the results of the linear interpolation processing and information on the data amplitude.

7. The transmitter / receiver circuit according to claim 1, wherein the monitor circuit comprises: a data generation circuit that generates periodic pattern data having a predetermined data length; and a first selector circuit that selects and outputs either the periodic pattern data or data supplied from a data processing circuit that receives and processes first output data from the receiver circuit; and the transmitter circuit outputs the plurality of first input data based on the output data of the first selector circuit.

8. The transmitter / receiver circuit according to claim 1, wherein the monitor circuit has a determination circuit that determines whether the first output data from the receiver circuit is a first value or a second value different from the first value.

9. The transmission / reception circuit according to claim 1, wherein the transmission circuit and the reception circuit perform simultaneous bidirectional communication to communicate the first transmission data and the reception data via a common transmission / reception node.

10. The transmitting / receiving circuit according to claim 9, further comprising a data extraction circuit that receives second transmission data transmitted from an external transmitting circuit, and extracts a component corresponding to the first transmission data from the received data by removing a component corresponding to the second transmission data from the received data.

11. A transmission / reception circuit as claimed in claim 10, wherein the data extraction circuit has a second selector circuit that selects and outputs either internal data corresponding to the second transmission data or the first transmission data, and extracts the component corresponding to the first transmission data or the second transmission data from the reception data by removing the component corresponding to the output data of the second selector circuit from the reception data.

12. The transmitter / receiver circuit according to claim 1, wherein said clock generation circuit receives said reference clock from an external device of said transmitter / receiver circuit and generates said clock.

13. The transmission / reception circuit according to claim 1, wherein the clock generation circuit is unable to control the phases of the clock supplied to the transmission circuit and the clock supplied to the reception circuit independently of each other.

14. The transmitter / receiver circuit according to claim 1, wherein the monitor circuit has a processing control circuit that controls the monitoring process.

15. A transmitter / receiver circuit as claimed in claim 14, wherein the monitor circuit comprises: a data generation circuit that generates periodic pattern data having a predetermined data length; and a first selector circuit that selects and outputs either the periodic pattern data or data supplied from a data processing circuit that receives and processes first output data from the receiver circuit; and the processing control circuit controls the operation of the data generation circuit and the first selector circuit.

16. The transmitter / receiver circuit according to claim 15, wherein the monitor circuit has a determination circuit that determines whether the first output data output from the receiver circuit is a first value or a second value different from the first value, and the processing control circuit activates the operation of the data generation circuit and the determination circuit when it controls the first selector circuit to select the periodic pattern data.

17. The transmission / reception circuit according to claim 14, wherein the reception circuit has a sampler circuit that samples the plurality of first input data to generate a plurality of first output data, and the processing control circuit controls a data decision threshold of the sampler circuit.

18. The transmitter / receiver circuit according to claim 14, wherein the monitoring process performed by the monitor circuit includes: a process of inputting periodic pattern data having a predetermined data length to the transmitter circuit; a process of inputting the plurality of first input data corresponding to the periodic pattern data from the transmitter circuit to the receiver circuit; a process of outputting a plurality of first output data from the receiver circuit based on the plurality of first input data; a determination process of determining whether the plurality of first output data are a first value or a second value different from the first value; a process of acquiring a data amplitude for each of the plurality of first input data based on a result of the determination process; a process of performing the linear interpolation process based on the data amplitude; and a process of generating information used to draw an eye pattern as information indicating the signal quality of the first transmission data based on information on the result of the linear interpolation process and information on the data amplitude.

19. The transmitter / receiver circuit according to claim 1, wherein the transmitter / receiver circuit is a chiplet transmitter / receiver circuit that performs communication between a plurality of semiconductor chiplets that constitute a chiplet system.

20. The transmitting / receiving circuit according to claim 1, wherein the receiving circuit includes an analog-to-digital conversion circuit that samples the plurality of first input data and generates a plurality of first output data.

21. A semiconductor integrated circuit having a transmitter / receiver circuit and a data processing circuit that communicates and processes data with the transmitter / receiver circuit, wherein the transmitter / receiver circuit has: a clock generation circuit that generates a clock based on a reference clock; a transmitter circuit that transmits first transmission data based on the clock; a receiver circuit that receives reception data based on the clock; a connection path that inputs the first transmission data from the transmitter circuit to the receiver circuit as the reception data; and a monitor circuit that monitors the signal quality of the first transmission data, wherein the monitor circuit performs a monitoring process to generate information indicating the signal quality of the first transmission data by performing linear interpolation between sets of first input data that are adjacent in time, based on a plurality of first input data that are consecutive in time from the transmitter circuit.

22. The semiconductor integrated circuit according to claim 21, wherein the semiconductor integrated circuit is a semiconductor chiplet that constitutes a chiplet system, and the transceiver circuit is a chiplet transceiver circuit that communicates with other semiconductor chiplets that constitute the chiplet system.

23. A signal monitoring method for a transmission / reception circuit having a clock generation circuit that generates a clock based on a reference clock, a transmission circuit that transmits first transmission data based on the clock, a reception circuit that receives reception data based on the clock, and a connection path that inputs the first transmission data from the transmission circuit to the reception circuit as the reception data, wherein the signal quality of the first transmission data is monitored by a monitor circuit, the signal monitoring method comprising: the monitor circuit generating a signal indicating the signal quality of the first transmission data by performing linear interpolation processing between sets of temporally adjacent first input data based on a plurality of temporally consecutive first input data from the transmission circuit.

24. A signal monitoring method according to claim 23, comprising the steps of: inputting periodic pattern data having a predetermined data length to the transmitting circuit; inputting the plurality of first input data corresponding to the periodic pattern data from the transmitting circuit to the receiving circuit; outputting a plurality of first output data from the receiving circuit based on the plurality of first input data; determining whether the plurality of first output data are a first value or a second value different from the first value; acquiring a data amplitude for each of the plurality of first input data based on a result of the determination; performing the linear interpolation processing by the monitor circuit based on the data amplitude; and generating information used to draw an eye pattern as information indicating the signal quality of the first transmission data based on information on the processing result of the linear interpolation processing and information on the data amplitude by the monitor circuit.

25. A transceiver circuit having: a clock generation circuit that generates a clock based on a reference clock; a transmission circuit that transmits first transmission data based on the clock; a reception circuit that receives second transmission data from an external transmission circuit as received data based on the clock; and a monitor circuit that monitors the signal quality of the second transmission data, wherein the monitor circuit performs a monitoring process to generate information indicating the signal quality of the second transmission data by performing linear interpolation between sets of temporally adjacent first input data based on a plurality of temporally consecutive first input data from the external transmission circuit.

26. The transmitting / receiving circuit according to claim 25, wherein the information indicating the signal quality of the second transmission data is information used to draw an eye pattern.

27. The transmitter / receiver circuit according to claim 25, wherein the monitor circuit receives a plurality of temporally consecutive first output data output from the receiver circuit based on the plurality of first input data, and performs the linear interpolation processing based on the plurality of first output data.

28. The transmission / reception circuit according to claim 25, wherein the monitor circuit acquires a data amplitude for each of the plurality of first input data, and performs the linear interpolation process based on the data amplitude.

29. The transmitter / receiver circuit according to claim 28, wherein the monitor circuit generates information used to draw an eye pattern based on information on the results of the linear interpolation processing and information on the data amplitude.

30. The transmitting / receiving circuit according to claim 25, wherein said receiving circuit receives periodic pattern data having a predetermined data length from said external transmitting circuit as said plurality of first input data.

31. The transmitter / receiver circuit according to claim 25, wherein the monitor circuit has a determination circuit that determines whether the first output data from the receiver circuit is a first value or a second value different from the first value.

32. The transmission / reception circuit according to claim 25, wherein the transmission / reception circuit performs simultaneous bidirectional communication in which the transmission circuit and the reception circuit communicate the first transmission data and the reception data via a common transmission / reception node.

33. The transmitting / receiving circuit according to claim 32, further comprising a data extraction circuit that receives the first transmission data transmitted from the transmitting circuit, and extracts a component corresponding to the second transmission data from the received data by removing a component corresponding to the first transmission data from the received data.

34. The transmission / reception circuit according to claim 25, wherein the clock generation circuit receives the reference clock from an external device and generates the clock.

35. The transmission / reception circuit according to claim 25, wherein the clock generation circuit cannot control the phases of the clock supplied to the transmission circuit and the clock supplied to the reception circuit independently of each other.

36. The transceiver circuit according to claim 25, wherein the monitor circuit has a processing control circuit that controls the monitoring process.

37. The transmitter / receiver circuit according to claim 36, wherein the monitor circuit has a determination circuit that determines whether first output data output from the receiver circuit is a first value or a second value different from the first value, and the processing control circuit controls the operation of the determination circuit.

38. The transmission / reception circuit according to claim 36, wherein the reception circuit has a sampler circuit that samples the plurality of first input data to generate a plurality of first output data, and the processing control circuit controls a data decision threshold of the sampler circuit.

39. The transmitter-receiver circuit according to claim 36, wherein the monitoring process performed by the monitor circuit includes: a process of receiving periodic pattern data having a predetermined data length from the external transmitter circuit as the plurality of first input data; a process of outputting a plurality of first output data from the receiver circuit based on the plurality of first input data; a determination process of determining whether the plurality of first output data are a first value or a second value different from the first value; a process of acquiring a data amplitude for each of the plurality of first input data based on a result of the determination process; a process of performing the linear interpolation process based on the data amplitude; and a process of generating information used to draw an eye pattern as information indicating the signal quality of the second transmission data based on information on the result of the linear interpolation process and information on the data amplitude.

40. The transmitter / receiver circuit according to claim 25, wherein the transmitter / receiver circuit is a chiplet transmitter / receiver circuit that performs communication between a plurality of semiconductor chiplets that make up a chiplet system.

41. The transmitting / receiving circuit according to claim 25, wherein the receiving circuit includes an analog-to-digital conversion circuit that samples the plurality of first input data and generates a plurality of first output data.

42. A semiconductor integrated circuit having a transmitter / receiver circuit and a data processing circuit that communicates and processes data with the transmitter / receiver circuit, wherein the transmitter / receiver circuit has: a clock generation circuit that generates a clock based on a reference clock; a transmitter circuit that transmits first transmission data based on the clock; a receiver circuit that receives second transmission data from an external transmitter circuit based on the clock as received data; and a monitor circuit that monitors the signal quality of the second transmission data, wherein the monitor circuit performs a monitoring process to generate information indicating the signal quality of the second transmission data by performing linear interpolation between sets of temporally adjacent first input data based on a plurality of temporally consecutive first input data from the external transmitter circuit.

43. The semiconductor integrated circuit according to claim 42, wherein the semiconductor integrated circuit is a semiconductor chiplet that constitutes a chiplet system, and the transceiver circuit is a chiplet transceiver circuit that communicates with other semiconductor chiplets that constitute the chiplet system.

44. A signal monitoring method for a transmitter / receiver circuit having a clock generation circuit that generates a clock based on a reference clock, a transmitter circuit that transmits first transmission data based on the clock, and a receiver circuit that receives second transmission data from an external transmitter circuit as received data based on the clock, wherein the monitor circuit monitors the signal quality of the second transmission data, the signal monitoring method comprising: generating information indicating the signal quality of the second transmission data by performing linear interpolation processing between sets of temporally adjacent first input data based on a plurality of temporally consecutive first input data from the external transmitter circuit.

45. A signal monitoring method as claimed in claim 44, further comprising the steps of: receiving periodic pattern data having a predetermined data length from the external transmitting circuit as the plurality of first input data; outputting a plurality of first output data from the receiving circuit based on the plurality of first input data; determining whether the plurality of first output data is a first value or a second value different from the first value; acquiring a data amplitude for each of the plurality of first input data based on a result of the determination; performing the linear interpolation processing based on the data amplitude by the monitor circuit; and generating information used to draw an eye pattern as information indicating the signal quality of the second transmission data based on information on the processing result of the linear interpolation processing and information on the data amplitude by the monitor circuit.

46. ​​A transmission / reception system comprising: a first semiconductor chip having a first transmission / reception circuit that operates based on a reference clock; and a second semiconductor chip having a second transmission / reception circuit that generates the reference clock and operates based on the reference clock, wherein the second transmission / reception circuit comprises: a second clock generation circuit that generates the reference clock; and a second transmission circuit that transmits second transmission data based on the reference clock, wherein the first transmission / reception circuit comprises: a clock generation circuit that generates a clock based on the reference clock; a first transmission circuit that transmits the first transmission data based on the clock; a reception circuit that receives the second transmission data from the second transmission circuit as received data based on the clock; and a monitor circuit that monitors the signal quality of the second transmission data, wherein the monitor circuit performs a monitoring process to generate information indicating the signal quality of the second transmission data by performing linear interpolation between sets of temporally adjacent first input data based on a plurality of temporally consecutive first input data from the second transmission circuit.

47. The transmission / reception system according to claim 46, wherein the transmission / reception system is a chiplet system configured by the first semiconductor chip and the second semiconductor chip, each of which is a chiplet, and has an interposer on which the first semiconductor chip and the second semiconductor chip are mounted and which includes connection wiring that electrically connects the first transmission / reception circuit and the second transmission / reception circuit.

48. A transmission / reception system according to claim 46, wherein the first transmission / reception circuit and the second transmission / reception circuit perform simultaneous bidirectional communication in which the first transmission circuit, the reception circuit, and the second transmission circuit communicate the first transmission data, the reception data, and the second transmission data via a common transmission / reception node.

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