Track-and-hold circuit

Abstract

In a track-and-hold circuit (10) according to the present invention, the emitter of a first transistor and the collector of a second transistor are connected to each other, a first capacitor is connected to the emitter of the first transistor, the emitter of a fifth transistor and the collector of a sixth transistor are connected to each other, a second capacitor is connected to the emitter of the fifth transistor, a clock signal is input to the first capacitor and the second capacitor, an inverted signal of the clock signal is input to the bases of the second transistor and the sixth transistor, a positive phase signal is input to and output from the first transistor, a reversed phase signal is input to and output from the fifth transistor, and when the clock signal changes from low voltage to high voltage, the potential differences between the bases and the emitters of the first transistor and the fifth transistor decrease, whereby switching from a track mode to a hold mode occurs.　Accordingly, the present invention makes it possible to provide a track-and-hold circuit that allows high-speed switching between track / hold modes.

Description

Track-and-hold circuit

[0001] The present invention relates to a track-and-hold circuit used for analog-to-digital conversion in digital signal processing.

[0002] In digital signal processing, an analog-to-digital converter (ADC) is used as a circuit block for converting signals into digital signals.

[0003] A simplified block diagram of an ADC is shown in Figure 13. A signal input to the ADC is fixed (held) at a voltage at a predetermined point in time (hold operation) by a track-and-hold circuit (T / H circuit) 61. The held signal is compared with a reference voltage by a voltage comparator circuit 62, and the signal is digitized.

[0004] The operation of the T / H circuit 61 requires a clock signal CLK. The T / H circuit 61 performs track and hold operations in synchronization with the clock signal CLK. In track operation, the input signal is output as is. In hold operation, the signal value at the time of transition to hold mode is maintained. Here, the clock signal CLK is usually a periodic signal, but it does not have to be a periodic signal depending on the application. For example, if conversion is required only at a specified timing, the signal input to the T / H circuit may be a non-periodic trigger signal.

[0005] Conventionally, a configuration using an emitter follower switch is known as a T / H circuit (Non-Patent Document 1).

[0006] Philipp Thomas et al., “64-GS / s 6-bit Track-and-Hold Circuit With More Than 61 GHz Bandwidth at 1.0 Vpp Input Voltage Swing in 90-nm SiGe BiCMOS Technology”, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea 22-28 May 2021, DOI:10.1109 / ISCAS51556.2021.9401211

[0007] Because an ADC digitizes an analog signal by comparing the value held by a T / H circuit with a reference voltage, the accuracy of the signal held by the T / H circuit directly affects the accuracy of the conversion to a digital signal. Therefore, a T / H circuit is required to be able to output the high-speed input signal without attenuating it, i.e., to have a wide target input signal bandwidth, and to be able to quickly switch between track and hold operations in order to hold the signal at high speed. Regarding the former, signal attenuation can be suppressed by increasing (shifting) the signal to be attenuated. Regarding the latter, by using a square wave as the clock signal to increase the slew rate, a high-speed transition from track mode (transmission mode) to hold mode (sustain mode) can be achieved, thereby realizing a hold operation for a high-speed input signal. As a result, sampling accuracy can be improved.

[0008] However, when the bandwidth is limited by the performance limits of the device or the wiring that transmits the signals, it is difficult to switch between the track operation and the hold operation at high speed.

[0009] In order to solve the above-mentioned problems, a track and hold circuit according to the present invention comprises a first transistor, a second transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor, wherein the emitter or source of the first transistor is connected to the collector or drain of the second transistor, the first capacitor is connected to the emitter or source of the first transistor, the emitter or source of the fifth transistor is connected to the collector or drain of the sixth transistor, the second capacitor is connected to the emitter or source of the fifth transistor, a clock signal is input to the first capacitor and the second capacitor, An inverted signal of the clock signal is input to the base or gate of the second transistor and the sixth transistor, a positive phase input signal is input to the base or gate of the first transistor, and a positive phase output signal is output from the emitter or source of the first transistor, a negative phase input signal is input to the base or gate of the fifth transistor, and a negative phase output signal is output from the emitter or source of the fifth transistor, and when the clock signal changes from a low voltage to a high voltage, the potential difference between the base or gate and the emitter or source of the first transistor and the fifth transistor decreases, and the mode switches from track mode to hold mode.

[0010] Furthermore, a track and hold circuit according to the present invention includes a first transistor, a second transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, and a seventh terminal, wherein the base or gate of the first transistor is connected to the first terminal to which a positive phase input signal is input, the emitter or source of the first transistor is connected to the second terminal to which a positive phase output signal is output, the base or gate of the second transistor is connected to the third terminal to which an inverted signal of a clock signal is input, and the collector or drain of the second transistor is connected to the emitter or source of the first transistor. a base or gate of the fifth transistor is connected to the fourth terminal to which an input signal of a reverse phase side is input, an emitter or source of the fifth transistor is connected to the fifth terminal to which an output signal of a reverse phase side is output, a base or gate of the sixth transistor is connected to a sixth terminal to which the inverted signal is input, a collector or drain of the sixth transistor is connected to the emitter or source of the fifth transistor, one end of the first capacitor is connected to the emitter or source of the first transistor, the other end of the first capacitor is connected to a seventh terminal to which the clock signal is input, one end of the second capacitor is connected to the emitter or source of the fifth transistor, and the other end of the second capacitor is connected to the seventh terminal.

[0011] According to the present invention, it is possible to provide a track-and-hold circuit that can switch between track mode and hold mode at high speed.

[0012] FIG. 1 is a circuit diagram showing the configuration of a track-and-hold circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram for explaining the operation of the track-and-hold circuit according to the first embodiment of the present invention. FIG. 3 is a diagram for explaining the operation of the track-and-hold circuit according to the first embodiment of the present invention. FIG. 4 is a diagram for explaining the operation of the track-and-hold circuit according to the first embodiment of the present invention. FIG. 5 is a circuit diagram showing an example of the configuration of the track-and-hold circuit according to the first embodiment of the present invention. FIG. 6 is a circuit diagram showing the configuration of a track-and-hold circuit according to a second embodiment of the present invention. FIG. 7 is a circuit diagram showing an example of the configuration of a track-and-hold circuit according to the second embodiment of the present invention. FIG. 8 is a circuit diagram showing the basic configuration of a track-and-hold circuit according to an embodiment of the present invention. FIG. 9 is a circuit diagram showing the configuration of a track-and-hold circuit according to a third embodiment of the present invention. FIG. 10 is a diagram for explaining the operation of the track-and-hold circuit according to the third embodiment of the present invention. FIG. 11 is a diagram for explaining the configuration of a track-and-hold circuit according to an embodiment of the present invention. FIG. 12A is a diagram for explaining the configuration of a track-and-hold circuit according to an embodiment of the present invention. Fig. 12B is a diagram for explaining the configuration of the track-and-hold circuit according to the embodiment of the present invention, and Fig. 13 is a diagram for explaining a conventional track-and-hold circuit.

[0013] First Embodiment A track-and-hold circuit according to a first embodiment of the present invention will be described with reference to FIGS.

[0014] <Configuration of Track-and-Hold Circuit> As shown in FIG. 1 , the track-and-hold circuit 10 according to this embodiment includes an NPN bipolar transistor (hereinafter also referred to as a “transistor”) Tr1 having an input terminal IN for a positive-phase input signal connected to its base and an output terminal OUT for a positive-phase output signal connected to its emitter, a transistor Tr2 having an input terminal CLKB for an inverted clock signal connected to its base and an emitter of Tr1 connected to its collector, a transistor Tr3 having an input terminal CLK for a clock signal connected to its base and an input terminal IN connected to its collector, a transistor Tr4 having a bias voltage terminal Vb connected to its base and an emitter of Tr2 and Tr3 connected to its collector, an NPN bipolar transistor Tr5 having an input terminal INB for a negative-phase input signal connected to its base and an output terminal OUTB for a negative-phase output signal connected to its emitter, and an inverted clock signal Tr6 having an input terminal CLKB for an inverted clock signal connected to its base and an emitter of Tr6 connected to its collector. a transistor Tr6 having a base connected to the clock signal input terminal CLKB and a collector connected to the emitter of Tr5; a transistor Tr7 having a base connected to the clock signal input terminal CLK and a collector connected to the input terminal INB; a transistor Tr8 having a base connected to a bias voltage terminal Vb and a collector connected to the emitters of Tr6 and Tr7; a resistor R1 having one end connected to the power supply voltage VCC and the other end connected to the collector of the transistor Tr1; a resistor R2 having one end connected to the emitter of Tr4 and the other end connected to ground; a resistor R3 having one end connected to the power supply voltage VCC and the other end connected to the collector of the transistor Tr5; a resistor R4 having one end connected to the emitter of Tr8 and the other end connected to ground; and a capacitor C1 having one end connected to the emitter of Tr1 and the other end connected to the clock signal input terminal CLK. ＨＬ and a capacitance C1 having one end connected to the emitter of Tr5 and the other end connected to the clock signal input terminal CLK. ＨＲ It is equipped with:

[0015] <Operation of Track-and-Hold Circuit> The operating principle of the track-and-hold circuit 10 according to this embodiment will be described with reference to FIGS.

[0016] The track-and-hold circuit 10 is a differential circuit, in which a positive-phase input signal is input to the base of Tr1, an output signal is output from the emitter, and a negative-phase input signal is input to the base of Tr5, an output signal is output from the emitter.

[0017] First, a configuration using an emitter follower switch shown in FIG. 2 will be described as a conventional track-and-hold circuit.

[0018] In this circuit configuration, when CLK is LOW (CLK terminal is LOW, CLKB terminal is HIGH), the track mode is active, and when CLK is HIGH (CLK terminal is HIGH, CLKB terminal is LOW), the hold mode is active.

[0019] When CLK is LOW, the transistor connected to CLK is turned off and the transistor connected to CLKB is turned on. As a result of these operations, the signal input to the IN terminal is level-shifted and output to the OUT terminal, just like an emitter follower. The signal input to the INB terminal is level-shifted and output to the OUTB terminal (track mode).

[0020] When CLK switches from LOW to HIGH, the transistor connected to CLK turns ON, and the transistor connected to CLKB turns OFF. This lowers the potential of the IN terminal, and the transistor whose base is connected to the IN terminal also turns OFF. These actions isolate the capacitance connected to the OUT terminal and OUTB terminal, and it becomes stray capacitance. This prevents charge from flowing in or out, so the signal value is maintained (hold mode).

[0021] In a track-and-hold circuit, switching from track mode to hold mode is performed in an analog manner, and a transition state exists during this switching process. In the transition state, charge flows in and out of the capacitance incompletely in response to the input signal. This causes the signal to deviate from the ideal signal, resulting in reduced accuracy. Therefore, in order to improve the accuracy of the T / H circuit, it is necessary to shorten the transition time.

[0022] In a conventional track-and-hold circuit using an emitter-follower switch, the time it takes for the transistor operating as the switch to switch from on to off depends on the clock transition time. Therefore, when holding a high-speed signal using a square-wave clock, using a clock with a high slew rate can improve accuracy. Since a clock with a high slew rate contains high-frequency components and requires wide bandwidth, using a wide-band clock can improve accuracy when holding a high-speed signal.

[0023] FIG. 3 shows clock waveforms for a high slew rate and a low slew rate. In the figure, the slew rate is ｌｏｗ From V ｈｉｇｈ Since the transition time t ｈｔｒ is the transition time t at low slew rate ｌｔｒ Shorter.

[0024] However, when a square wave with a high slew rate is input as a clock, the slew rate of the square wave clock is limited by the bandwidth of the wiring. As a result, it takes a long time for the transistor acting as a switch to switch from ON to OFF, and the signal quality deteriorates during the process up to the hold.

[0025] When a sine wave is input as a clock and the circuit is operated at the same amplitude, the transition time is determined by the frequency, so just like in the case of a square wave, it takes a long time for the transistor to switch from ON to OFF, and the quality of the signal deteriorates in the process up to the hold.

[0026] Focusing on the amplitude, as shown in FIG. ｈｉｇｈIn a circuit that operates in track mode when the input voltage exceeds 10 V, it is possible to shorten the transition time by increasing the amplitude. However, even with this configuration, it is difficult to shorten the transition time due to bandwidth limitations. The output amplitude of the circuit that drives the clock is limited by the device characteristics (e.g., breakdown voltage), and the bandwidth of the clock wiring is also limited, resulting in signal attenuation. Furthermore, limitations such as the breakdown voltage of the device and the power supply voltage impose upper and lower limits on the clock amplitude. These limitations limit the amplitude that can be input to the T / H circuit, so there is a limit to how much the transition time can be shortened by increasing the clock amplitude.

[0027] Next, the operating principle of the track-and-hold circuit 10 according to the present embodiment will be described with reference to FIG.

[0028] The basic structure of the track-and-hold circuit 10 is an emitter-follower switch. As mentioned above, this structure limits the slew rate due to the bandwidth limitations of the clock wiring, and also limits the reduction of the transition time, making it difficult to improve the accuracy of the hold mode operation.

[0029] Therefore, as shown in FIG. 1, the track-and-hold circuit 10 further includes a capacitance C ＨＬ and C ＨＲ The clock signal may be a square wave, a sine wave, or any other waveform.

[0030] To hold a signal, it is necessary to turn off the transistors Tr1 and Tr5, which are on (conducting) during the track operation. Based on the symmetry of this circuit configuration, the operation of Tr1 and Tr5 is the same. Below, we will explain Tr1. The operation of the transistor is determined by the voltage between the base and emitter, and the amount of current I that flows between the collector and emitter of Tr1 is ｔｒ１ is expressed by equation (1) assuming that Tr1 operates in the active region in the output characteristics.

[0031]

[0032] Here, it is assumed that Tr1 operates in the active region, but even if it operates in another operating region, the amount of current is V ＩＮ -V ＯＵＴ Depends on V ＩＮ -V ＯＵＴ The same is true when an NMOS transistor is used for Tr1. Ｔｒ１ When the tolerance is set, the threshold value for the mode transition is V. ＩＮ -V ＯＵＴ This can be understood at the design stage.

[0033] In the track-and-hold circuit 10, similar to the emitter-follower switch described above, when CLK switches from LOW (track mode) to HIGH (hold mode), V ＩＮ decreases, and therefore, based on equation (1), the current flowing through Tr1 decreases. ＩＮ As a result, the current flowing through Tr1 decreases to the current required to switch to the hold mode, and the hold operation is achieved. In this way, in a configuration with only the basic structure of the emitter follower switch, switching to the hold mode is achieved by V ＩＮ depends only on the change in

[0034] In the track and hold circuit 10, the hold capacitance C ＨＬ and C ＨＲ The CLK signal is input to the emitters of Tr1 and Tr5 through these transistors. With this configuration, when CLK switches from LOW (track mode) to HIGH (hold mode), V ＯＵＴ By increasing V when switching from track mode to hold mode, ＩＮ -V ＯＵＴ By increasing the amount of change in the voltage Vcc, the rate at which the current flowing through Tr1 decreases can be increased.

[0035] In addition, the hold capacitance C ＨＬ and C ＨＲ are isolated, and no charge flows in or out, so the signal value is maintained.

[0036] This reduces the time required for the mode transition threshold to be exceeded, similar to the case where an increase in the slew rate of CLK is assumed, and enables high-speed switching from track mode to hold mode.

[0037] In the track-and-hold circuit 10, the CLK signals input to the emitters of Tr1 and Tr5 are input as in-phase signals, but because this circuit is composed of differential circuits, it can be configured so that the in-phase signals do not affect the differential signal, which is the main signal.

[0038] In the track and hold circuit 10, V ＩＮ decreases, and at the same time, V ＯＵＴ Increase I Ｔｒ１ This allows Tr1 and Tr5 to be turned off at a higher speed, thereby enabling high-speed switching from track mode to hold mode.

[0039] According to the track-and-hold circuit of this embodiment, the switching speed of the transistors is increased, thereby enabling high-speed switching from track mode to hold mode, and also improving hold accuracy.

[0040] In the track and hold circuit 10, the OUT terminal and OUTB terminal at both ends of the hold capacitance operate differentially, and the potential fluctuation of the OUTM node, which is the midpoint, is small, so that even if the potential of the OUTM node changes, the potential difference between OUT and OUTB does not change. The OUTM node can be considered to be virtually grounded. Therefore, C ＨＬ and C ＨＲ One end of the resistor may be connected to a location other than ground. With this configuration, the circuit operates as a track-and-hold circuit with an improved slew rate, independent of the bandwidth of the wiring. This improves hold accuracy.

[0041] It is desirable that the circuit parameters be approximately symmetrical in the configuration of the differential circuit of the track-and-hold circuit 10. Approximately symmetrical includes perfect symmetry and also includes a range in which the circuit parameters are asymmetrical due to manufacturing errors or the like.

[0042] The circuit parameters may not be symmetrical, which will introduce clock-induced errors into the track-and-hold operation.

[0043] In the track mode, a high voltage is applied to the CLKB node of the transistors in the track-and-hold circuit 10. In other words, a high voltage is applied to the base terminals of Tr2, Tr3, Tr6, and Tr7. In this case, as with the conventional configuration, the high voltage that can be applied to the base terminals is limited by the withstand voltage of the elements.

[0044] On the other hand, when switching to hold mode, a low voltage is applied to the CLKB node, and the potentials of the OUT and OUTB nodes rise. However, the emitter-base voltage, which is theoretically the most unfavorable in terms of breakdown voltage because the base film is thin, is the same as in the conventional structure for Tr2, Tr3, Tr6, and Tr7, and the voltage applied to Tr1 and Tr5 acts in the relaxation direction, so there is no effect on the breakdown voltage.

[0045] In the track-and-hold circuit, a skew (delay adjustment circuit) may be placed between the CLK connected to the OUTM node and the CLK connected to Tr3 and Tr7. As the skew (delay adjustment circuit), a phase control circuit, a skew adjustment circuit, a delay circuit, and wiring may be placed for each CLK terminal, as shown in FIG. 5. In the configuration shown in FIG. 5, the clock for the bases of Tr3 and Tr7 can be delayed. The clock for the other transistors Tr2 and Tr6 can also be delayed in a similar manner.

[0046] This results in C ＨＬ and C ＨＲ This can suppress the influence of a case where a phase difference occurs due to the difference in load between the CLK connected to the OUTM node and the CLK connected to Tr3 and Tr7.

[0047] The track-and-hold circuit according to this embodiment can switch between track mode and hold mode at high speed, thereby enabling a hold operation with higher accuracy.

[0048] In the track and hold circuit, different circuits may be used as buffer circuits for driving the CLK and CLKB terminals, and they may be driven with different output amplitudes. Also, the waveform input to the CLK terminal is not limited to a periodic waveform such as a sine wave or a square wave, but may also be a single waveform such as a pulse waveform. ＨＬ and C ＨＲ However, similar to the prior art, earth capacitances may be provided for the OUT node and the OUTB node.

[0049] Second Embodiment A track-and-hold circuit according to a second embodiment of the present invention will be described with reference to FIGS.

[0050] 6, the track-and-hold circuit 20 according to this embodiment is the same as the track-and-hold circuit according to the first embodiment, except that it includes a resistor R5 connected to the emitter of transistor Tr3 and a resistor R6 connected to the emitter of transistor Tr7. The collectors of transistors Tr3 and Tr7 are not connected to the input terminal IN.

[0051] In detail, the track and hold circuit 20 includes an NPN bipolar transistor (hereinafter also referred to as "transistor") Tr1 having a base connected to an input terminal IN of a positive-phase input signal and an emitter connected to an output terminal OUT of a positive-phase output signal, a transistor Tr2 having a base connected to an input terminal CLKB of an inverted clock signal and an emitter of Tr1 connected to a collector, a transistor Tr3 having a base connected to an input terminal CLK of a clock signal and a collector connected to a resistor R5, a transistor Tr4 having a base connected to a bias voltage terminal Vb and a collector connected to the emitters of Tr2 and Tr3, an NPN bipolar transistor Tr5 having a base connected to an input terminal INB of a negative-phase input signal and an emitter connected to an output terminal OUTB of a negative-phase output signal, and a transistor Tr6 having a base connected to an input terminal CLKB of an inverted clock signal and an emitter of Tr5 connected to a collector. a transistor Tr7 having a base connected to a clock signal input terminal CLK and a collector connected to a resistor R6; a transistor Tr8 having a base connected to a bias voltage terminal Vb and having the emitters of Tr6 and Tr7 connected to its collector; a resistor R1 having one end connected to a power supply voltage VCC and the other end connected to the collector of the transistor Tr1; a resistor R2 having one end connected to the emitter of Tr4 and the other end connected to ground; a resistor R3 having one end connected to the power supply voltage VCC and the other end connected to the collector of the transistor Tr5; a resistor R4 having one end connected to the emitter of Tr8 and the other end connected to ground; a resistor R5 having one end connected to the power supply voltage VCC and the other end connected to the collector of the transistor Tr3; a resistor R6 having one end connected to the power supply voltage VCC and the other end connected to the collector of the transistor Tr7; ＨＬ and a capacitance C1 having one end connected to the emitter of Tr5 and the other end connected to the clock signal input terminal CLK. ＨＲ It is equipped with:

[0052] <Operation of Track-and-Hold Circuit> In a conventional circuit configuration, it is difficult to completely turn off the transistor to which the IN terminal is connected due to the potential difference between the IN terminal and the OUT terminal.

[0053] On the other hand, in the track-and-hold circuit 20, the potential of the OUT terminal rises when the circuit enters hold mode, reducing the potential difference between the IN terminal and the OUT terminal and suppressing the current flowing from the emitter of the transistor, thereby enabling the circuit to perform a hold operation at higher speed and with higher accuracy.

[0054] According to the track-and-hold circuit of this embodiment, it is possible to switch from the track mode to the hold mode at high speed, thereby improving the hold accuracy.

[0055] Furthermore, the track-and-hold circuit according to this embodiment may be configured without the transistors (Tr3, Tr7) to which the CLK terminal is connected, as shown in FIG.

[0056] As shown in FIG. 8, the basic configuration of the track-and-hold circuit according to the first and second embodiments of the present invention is a transistor Tr1 having a base connected to an input terminal IN for a positive phase input signal and an emitter connected to an output terminal OUT for a positive phase output signal, a transistor Tr2 having a base connected to an input terminal CLKB for an inverted clock signal and an emitter connected to the collector of the transistor Tr1, an NPN bipolar transistor Tr5 having a base connected to an input terminal INB for a negative phase input signal and an emitter connected to an output terminal OUTB for a negative phase output signal, a transistor Tr6 having a base connected to an input terminal CLKB for an inverted clock signal and an emitter connected to the collector of the transistor Tr5, and a capacitor C1 having one end connected to the emitter of the transistor Tr1 and the other end connected to the clock signal input terminal CLK. ＨＬ and a capacitance C1 having one end connected to the emitter of Tr5 and the other end connected to the clock signal input terminal CLK. ＨＲ It is equipped with:

[0057] With this configuration, when CLK switches from LOW (track mode) to HIGH (hold mode), V ＯＵＴ By increasing V when switching from track mode to hold mode, ＩＮ -V ＯＵＴThe rate of change of the hold capacitance C ＨＬ and C ＨＲ are isolated, and no charge flows in or out, so the signal value is maintained.

[0058] Third Embodiment A track-and-hold circuit according to a third embodiment of the present invention will be described with reference to FIGS.

[0059] <Configuration of Track-and-Hold Circuit> As shown in FIG. 9, the track-and-hold circuit 30 according to this embodiment is the same as the track-and-hold circuit according to the first embodiment except that the capacitance C ＨＬ The other end and capacitance C ＨＲ and the other end of the matching circuit 31 is connected to the clock signal input terminal CLK. A buffer 32 may be connected to the matching circuit 31. This makes it possible to optimize the voltage fluctuations at the OUT node and the OUTB node. This embodiment can also be applied to the second embodiment.

[0060] <Operation of Track-and-Hold Circuit> In the track-and-hold circuit 30, the output impedance can be controlled by the matching circuit 31, and the signal changes at the emitter nodes of Tr1 and Tr5 due to CLK can be optimized. The matching circuit 31 can suppress an increase in the amplitude of the input CLK, and a sufficient signal change can be achieved.

[0061] In the track-and-hold circuit 30, the first circuit 30_1 and the second circuit 30_2 operate symmetrically, so the first circuit 30_1 will be described below, and the same applies to the second circuit 30_2.

[0062] 10 shows an equivalent circuit of an AC signal of the track-and-hold circuit 30. At the OUT node, the impedance of the first circuit (emitter follower switch) 30_1 is modeled as Zesw, the impedance of the matching circuit as Zmat, and the clock signal source as Vclk.

[0063] In this circuit, the potentials of the OUT node and the OUTB node change as Vclk changes. For simplicity, let us assume that the differential signal is 0 V and the voltages of the OUT node and the OUTB node are Ve. The amount of change in Ve is expressed by equation (2).

[0064]

[0065] Here, since Ve=IeZ'esw, equation (3) is obtained.

[0066]

[0067] Here, Z'esw = Z'esw / 2, C'H = 2C Ｈ The impedance taking into account Tr1 and Tr2 is Zesw. Similarly, due to the symmetry of the circuit configuration, the impedance taking into account TR5 and TR6 is Zesw. In this way, by introducing Zmat, the amount of change in Ve can be controlled without changing VCLK.

[0068] Assuming that Zesw=re and Zmat=sL and matching is performed by an inductive load L, equation (4) is obtained.

[0069]

[0070] According to equation (4), the amplitude at Ve can be controlled by appropriately setting L. Therefore, by appropriately designing L, the voltages output to the OUT node and the OUTB node can be appropriately controlled.

[0071] The track-and-hold circuit according to the present embodiment can switch from track mode to hold mode at high speed, improve hold accuracy, and control the voltage of the output signal.

[0072] In the embodiment of the present invention, a buffer may be provided as a subsequent stage. Also, a buffer may be provided to input a main signal. As shown in FIG. 11, the buffer configuration may be such that an emitter follower circuit 41 and a grounded emitter amplifier stage 42 are connected to the OUT and OUTB terminals. Also, as shown in FIGS. 12A and 12B, the OUT and OUTB terminals may be connected to the inputs of differential amplifier circuits 51 and 52.

[0073] In the embodiment of the present invention, the clock signal CLK input to each terminal is synchronized, while the signal CLKB, which is the inverse of the clock signal input to each terminal, is synchronized.

[0074] In the embodiment of the present invention, an example using a bipolar transistor has been shown, but this is not limiting and a MOS transistor may also be used. When a MOS transistor is used, the emitter, base, and collector of the bipolar transistor correspond to the source, base, and drain of the MOS transistor, respectively. Furthermore, although an example using an N-type transistor such as an NPN type or NMOS transistor has been shown, a P-type transistor such as a PNP type or PMOS transistor may also be used.

[0075] In the embodiments of the present invention, at least one of a resistor and a capacitor may be disposed at the emitter of the bipolar transistor (the source of the MOS transistor) to adjust the gain and frequency response. Also, an arbitrary amplifier circuit such as an emitter follower may be disposed as necessary to adjust the level and driving force.

[0076] In the embodiment of the present invention, the CLK terminal and the CLKB terminal may be skewed to optimize performance. Although perfect phase matching is not required, the phases must match in principle, so the phase difference between CLK and CLKB is usually within a range of ±90 degrees with 180 degrees as the center.

[0077] In an embodiment of the present invention, a delay element may be inserted between the CLK terminals to optimize the operation timing of each transistor. In this case, a phase control circuit, a skew adjustment circuit, a delay circuit, wiring, or the like may be used as the delay element. Furthermore, since the loads of each CLK terminal may be different, the buffer circuits that drive each terminal may be different, and the terminals may be driven with different output amplitudes.

[0078] In the embodiment of the present invention, since the bias point can be controlled by placing a resistor for each node, a resistor, a diode, or a diode-connected transistor may be placed in the DC path.

[0079] In the embodiments of the present invention, examples of the structure, dimensions, materials, etc. of each component in the configuration of the track-and-hold circuit etc. are shown, but the present invention is not limited to these examples. Anything that can demonstrate the function and effect of the track-and-hold circuit may be used.

[0080] It should be noted that the present invention is not limited to the above-described embodiments, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.

[0081] A part or all of the above-described embodiment or an example thereof can be described as, but is not limited to, the following supplementary notes.

[0082] (Supplementary Note 1) A circuit includes a first transistor, a second transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor, wherein the emitter or source of the first transistor is connected to the collector or drain of the second transistor, the first capacitor is connected to the emitter or source of the first transistor, the emitter or source of the fifth transistor is connected to the collector or drain of the sixth transistor, the second capacitor is connected to the emitter or source of the fifth transistor, a clock signal is input to the first capacitor and the second capacitor, and the bases of the second transistor and the sixth transistor are connected to each other. or a gate of the first transistor, a signal that is an inverted version of the clock signal is input; a positive-phase input signal is input to the base or gate of the first transistor, and a positive-phase output signal is output from the emitter or source of the first transistor; a negative-phase input signal is input to the base or gate of the fifth transistor, and a negative-phase output signal is output from the emitter or source of the fifth transistor; and when the clock signal changes from a low voltage to a high voltage, a potential difference between the base or gate and the emitter or source of the first transistor and the fifth transistor decreases, switching from a track mode to a hold mode.

[0083] (Supplementary Note 2) A circuit includes a first transistor, a second transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, and a seventh terminal, wherein a base or a gate of the first transistor is connected to the first terminal to which a positive phase side input signal is input, an emitter or a source of the first transistor is connected to the second terminal to which a positive phase side output signal is output, a base or a gate of the second transistor is connected to a third terminal to which an inverted signal of a clock signal is input, a collector or a drain of the second transistor is connected to the emitter or a source of the first transistor, and a base or a gate of the fifth transistor is connected to the third terminal to which a positive phase side output signal is output. a gate of the fifth transistor is connected to the fourth terminal to which an inverted input signal is input, an emitter or a source of the fifth transistor is connected to the fifth terminal to which an inverted output signal is output, a base or a gate of the sixth transistor is connected to the sixth terminal to which the inverted signal is input, a collector or a drain of the sixth transistor is connected to the emitter or a source of the fifth transistor, one end of the first capacitor is connected to the emitter or a source of the first transistor, the other end of the first capacitor is connected to a seventh terminal to which the clock signal is input, one end of the second capacitor is connected to the emitter or a source of the fifth transistor, and the other end of the second capacitor is connected to the seventh terminal.

[0084] (Supplementary Note 3) The track-and-hold circuit according to Supplementary Note 1 or Supplementary Note 2, further comprising a third transistor, a fourth transistor, a seventh transistor, and an eighth transistor, wherein collectors or drains of the third transistor and the seventh transistor are connected to bases or gates of the first transistor and the fifth transistor, emitters or sources of the second transistor and the third transistor are connected to the collector or drain of the fourth transistor, and emitters or sources of the sixth transistor and the seventh transistor are connected to the collector or drain of the eighth transistor, and the clock signal is input to the third transistor and the seventh transistor.

[0085] (Supplementary Note 4) The track-and-hold circuit according to Supplementary Note 1 or Supplementary Note 2, further comprising a third transistor, a fourth transistor, a seventh transistor, an eighth transistor, a first resistor, a fifth resistor, a third resistor, and a sixth resistor, wherein a collector or a drain of the first transistor is connected to a power supply voltage via the first resistor, a collector or a drain of the third transistor is connected to a power supply voltage via the fifth resistor, a collector or a drain of the fifth transistor is connected to a power supply voltage via the third resistor, a collector or a drain of the seventh transistor is connected to a power supply voltage via the sixth resistor, emitters or sources of the second transistor and the third transistor are connected to a collector or a drain of the fourth transistor, and emitters or sources of the sixth transistor and the seventh transistor are connected to a collector or a drain of the eighth transistor, and the clock signal is input to the third transistor and the seventh transistor.

[0086] (Supplementary Note 5) The track-and-hold circuit according to Supplementary Note 3 or Supplementary Note 4, further comprising a delay adjustment circuit connected to the base or gate of the third transistor and the base or gate of the seventh transistor, respectively.

[0087] (Supplementary Note 6) The track-and-hold circuit according to any one of Supplementary Note 1 to Supplementary Note 5, further comprising a matching circuit and a buffer connected in series between the other end of the first capacitance and the other end of the second capacitance and the input terminal of the clock signal.

[0088] The present invention is applicable to analog-to-digital converters and to digital signal processing devices and systems.

[0089] 10 Track and hold circuit

Claims

1. A power supply comprising a first transistor, a second transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor, wherein the emitter or source of the first transistor is connected to the collector or drain of the second transistor, the first capacitor is connected to the emitter or source of the first transistor, the emitter or source of the fifth transistor is connected to the collector or drain of the sixth transistor, the second capacitor is connected to the emitter or source of the fifth transistor, a clock signal is input to the first capacitor and the second capacitor, a signal that is an inverted version of the clock signal is input to the bases or gates of the second transistor and the sixth transistor, a positive-phase input signal is input to the base or gate of the first transistor, a positive-phase output signal is output from the emitter or source of the first transistor, and a negative-phase input signal is input to the base or gate of the fifth transistor, a track-and-hold circuit in which an output signal of a reverse phase is output from the emitter or source of the fifth transistor, and when the clock signal changes from a low voltage to a high voltage, a potential difference between the base or gate and the emitter or source of the first transistor and the fifth transistor decreases, thereby switching from a track mode to a hold mode.

2. A circuit comprising a first transistor, a second transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, and a seventh terminal, wherein the base or gate of the first transistor is connected to the first terminal to which a positive phase input signal is input, and the emitter or source of the first transistor is connected to the second terminal to which a positive phase output signal is output, the base or gate of the second transistor is connected to the third terminal to which an inverted clock signal is input, and the collector or drain of the second transistor is connected to the emitter or source of the first transistor, the base or gate of the fifth transistor is connected to the fourth terminal to which a negative phase input signal is input, and the emitter or source of the fifth transistor is connected to the fifth terminal to which a negative phase output signal is output, a base or gate of the sixth transistor is connected to a sixth terminal to which the inverted signal is input, and a collector or drain of the sixth transistor is connected to the emitter or source of the fifth transistor; one end of the first capacitor is connected to the emitter or source of the first transistor, and the other end of the first capacitor is connected to a seventh terminal to which the clock signal is input; and one end of the second capacitor is connected to the emitter or source of the fifth transistor, and the other end of the second capacitor is connected to the seventh terminal.

3. The track and hold circuit according to claim 1 or 2, further comprising a third transistor, a fourth transistor, a seventh transistor, and an eighth transistor, wherein the collectors or drains of the third transistor and the seventh transistor are connected to the bases or gates of the first transistor and the fifth transistor, the emitters or sources of the second transistor and the third transistor are connected to the collector or drain of the fourth transistor, and the emitters or sources of the sixth transistor and the seventh transistor are connected to the collector or drain of the eighth transistor, and the clock signal is input to the third transistor and the seventh transistor.

4. The track and hold circuit according to claim 1 or 2, further comprising a third transistor, a fourth transistor, a seventh transistor, an eighth transistor, a first resistor, a fifth resistor, a third resistor, and a sixth resistor, wherein the collector or drain of the first transistor is connected to a power supply voltage via the first resistor, the collector or drain of the third transistor is connected to a power supply voltage via the fifth resistor, the collector or drain of the fifth transistor is connected to a power supply voltage via the third resistor, the collector or drain of the seventh transistor is connected to a power supply voltage via the sixth resistor, the emitters or sources of the second transistor and the third transistor are connected to the collector or drain of the fourth transistor, and the emitters or sources of the sixth transistor and the seventh transistor are connected to the collector or drain of the eighth transistor, and the clock signal is input to the third transistor and the seventh transistor.

Images