Transistor drive circuit

Abstract

This transistor drive circuit 8 comprises: a pulse transformer PT; a first control circuit 81 having a first portion 811 connected between a control terminal T1a and a first current terminal T1b; a second control circuit 82 connected between a second secondary winding N3, the control terminal T1a, and the first current terminal T1b; a drive pulse generation unit 83; and a stop pulse generation unit 84. The first portion 811 is in a maintenance state in which a voltage of a drive pulse signal is maintained, drives a drive target transistor T1 by using the maintained voltage, and when a stop pulse signal is input from the pulse transformer PT to the second control circuit 82, the second control circuit 82 releases the maintenance state of the first portion 811.

Description

Transistor drive circuit

[0001] The present disclosure relates to a transistor driver circuit.

[0002] An insulated gate drive circuit using a pulse transformer is known as a drive circuit for transistors such as FETs and IGBTs (see, for example, Patent Document 1). In the drive circuit described in Patent Document 1, when the FET is turned off, the excitation energy of the pulse transformer is stored in a capacitor to form a reverse bias source, and the voltage of this reverse bias source is used to turn off the FET at high speed.

[0003] Japanese Patent Application Laid-Open No. 2005-136942

[0004] In the drive circuit described in Patent Document 1, the excitation energy of a pulse transformer is used to drive an FET. Therefore, it is assumed that the pulse width of the pulse signal output from the pulse transformer to the FET must match the pulse width of the voltage between the gate terminal and source terminal of the FET (in other words, the time required for the FET to turn on and off). In this case, the minimum operating frequency of the pulse transformer becomes low, which may make it difficult to use a small pulse transformer. Therefore, in order to miniaturize pulse transformers, there is a demand for increasing the minimum operating frequency of pulse transformers. Meanwhile, because transistors such as FETs tend to have a longer off time than on time, there is a demand for transistors to be turned off quickly and reliably.

[0005] The present disclosure provides a transistor driver circuit that can reduce the size of a pulse transformer and can turn off a transistor quickly and reliably.

[0006] A transistor drive circuit according to one aspect of the present disclosure is [1] "a transistor drive circuit comprising: a pulse transformer having a primary winding, a first secondary winding, and a second secondary winding, the first secondary winding being connected to a control terminal of a transistor to be driven; a first control circuit having a first portion connected between the control terminal of the transistor to be driven and a first current terminal of the transistor to be driven; a second control circuit connected between the second secondary winding, the control terminal of the transistor to be driven, and the first current terminal of the transistor to be driven; a drive pulse generation unit connected to the primary winding and generating a drive pulse signal; and a stop pulse generation unit connected to the primary winding and generating a stop pulse signal; when the drive pulse signal is input from the pulse transformer to the first control circuit, the first portion enters a hold state in which it holds the voltage of the drive pulse signal and drives the transistor to be driven by the held voltage; and when the stop pulse signal is input from the pulse transformer to the second control circuit, the second control circuit releases the hold state of the first portion."

[0007] In the transistor drive circuit of [1] above, the pulse transformer outputs a drive pulse signal from the first secondary winding to the first control circuit. When the drive pulse signal is input from the pulse transformer to the first control circuit, the first section enters a hold state in which it holds the voltage value of the drive pulse signal, and the held voltage drives the transistor to be driven. As a result, while the first section is in the hold state, a voltage corresponding to the drive pulse signal continues to be applied between the control terminal and the first current terminal of the transistor to be driven, and the transistor to be driven continues to be driven. This allows the pulse width of the drive pulse signal to be set narrower relative to the drive time of the transistor to be driven. This allows the minimum operating frequency of the pulse transformer to be increased, thereby enabling the pulse transformer to be made more compact. Meanwhile, the pulse transformer outputs a stop pulse signal from the second secondary winding to the second control circuit. When the stop pulse signal is input from the pulse transformer, the second control circuit releases the voltage holding state of the first section. As a result, the voltage value between the control terminal and the first current terminal of the transistor to be driven decreases. The transistor drive circuit can reduce the size of the pulse transformer and can turn off the transistor to be driven quickly and reliably by causing the voltage between the control terminal and the first current terminal of the transistor to be driven to fall below the threshold voltage.

[0008] A transistor driver circuit according to one aspect of the present disclosure may be [2] "the transistor driver circuit of [1] above, further including a second portion connected between the first secondary winding and a control terminal of the driven transistor, the second portion including a diode connected in a forward direction between one end of the first secondary winding and the control terminal of the driven transistor, and the first portion including an input capacitance of the driven transistor located between the control terminal of the driven transistor and a first current terminal of the driven transistor." According to the transistor driver circuit of [2], the voltage value of the drive pulse signal can be maintained by charging the input capacitance with a charge corresponding to the voltage value of the drive pulse signal. In addition, the diode can prevent the charged charge from flowing back toward one end of the first secondary winding. This allows the voltage value of the drive pulse signal to be stably maintained, and the driven transistor to be stably driven.

[0009] A transistor drive circuit according to one aspect of the present disclosure may be [3] "the transistor drive circuit of the above [2], wherein the second control circuit has a discharge transistor including a control terminal connected to one end of the second secondary winding, a first current terminal connected to the other end of the second secondary winding and to a first current terminal of the driven transistor, and a second current terminal connected to the control terminal of the driven transistor." According to the transistor drive circuit of [3], when a stop pulse signal is input from one end of the second secondary winding to the second control circuit, the discharge transistor is driven. At that time, the charge accumulated in the input capacitance of the driven transistor is discharged via the discharge transistor. This more reliably releases the held state of the first portion.

[0010] A transistor drive circuit according to one aspect of the present disclosure may be [4] "the transistor drive circuit of the above [3], further including an auxiliary transistor including a second current terminal connected to the control terminal of the discharge transistor, a first current terminal connected to the first current terminal of the discharge transistor, and a control terminal connected to one end of the first secondary winding." According to the transistor drive circuit of [4], when a drive pulse signal is input from the pulse transformer to the first control circuit, the auxiliary transistor is driven, and no signal is input to the control terminal of the discharge transistor. This prevents erroneous firing of the discharge transistor, and enables stable driving of the transistor to be driven.

[0011] A transistor drive circuit according to one aspect of the present disclosure may be [5] "the transistor drive circuit of [3] or [4] above, further including a reverse bias capacitor having a positive terminal connected to the first current terminal of the transistor to be driven and a negative terminal connected to the first current terminal of the discharge transistor, and a Zener diode connected in parallel to the reverse bias capacitor." According to the transistor drive circuit of [5], when the transistor to be driven is driven, a current flows from the transistor to be driven toward the reverse bias capacitor, and the reverse bias capacitor is charged. Subsequently, when the discharge transistor is driven, the negative terminal of the reverse bias capacitor is connected to the control terminal of the transistor to be driven via the discharge transistor. The voltage based on the charge stored in the reverse bias capacitor is controlled to a constant voltage by the Zener diode and applied as a reverse bias voltage between the control terminal and the first current terminal of the transistor to be driven. This makes it possible to more reliably turn off the transistor to be driven.

[0012] According to the present disclosure, it is possible to provide a transistor drive circuit that can reduce the size of a pulse transformer and can turn off a transistor quickly and reliably.

[0013] 1 is a block diagram showing a power supply circuit including a transistor drive circuit according to an embodiment of the present disclosure; FIG. 2 is a circuit diagram of an inverter circuit including a transistor drive circuit according to an embodiment of the present disclosure; FIG. 3 is a diagram showing an example of operation of the transistor drive circuit shown in FIG. 2; FIG. 4 is a timing chart showing an example of operation of the transistor drive circuit shown in FIG. 2; FIG. 5 is a circuit diagram of a transistor drive circuit according to a second modification; FIG. 7 is a timing chart showing an example of operation of the transistor drive circuit shown in FIG. 7; FIG. 8 is a circuit diagram of a transistor drive circuit according to a third modification; FIG. 9 is a circuit diagram of a transistor drive circuit according to the third modification; FIG. 10 is a circuit diagram of a transistor drive circuit according to a fourth modification; FIG. 11 is a circuit diagram of a transistor drive circuit according to the fourth modification; FIG. 12 is a circuit diagram of a transistor drive circuit according to a fifth modification; FIG. 13 is a circuit diagram of a transistor drive circuit according to the fifth modification; FIG. 14 is a circuit diagram of a transistor drive circuit according to a sixth modification; FIG. 15 is a circuit diagram of a transistor drive circuit according to the sixth modification; FIG. 16 is a circuit diagram of a transistor drive circuit according to the seventh modification; FIG. 17 is a circuit diagram of a transistor drive circuit according to the seventh modification; FIG. 18 is a circuit diagram of a transistor drive circuit according to an eighth modification; FIG. 19 is a circuit diagram of a transistor drive circuit according to the eighth modification.

[0014] Hereinafter, a preferred embodiment of a transistor drive circuit according to an embodiment of the present disclosure will be described in detail with reference to the drawings.

[0015] FIG. 1 is a block diagram showing a power supply circuit 1 including a transistor drive circuit according to an embodiment of the present disclosure. The power supply circuit 1 is a power supply circuit for supplying a high voltage to a load. In the following embodiments and modifications, an X-ray tube will be used as an example of the load of the power supply circuit 1. As an example, the power supply circuit 1 can be applied to, for example, an electron beam irradiation device in addition to an X-ray tube. Furthermore, the power supply circuit 1 is not limited to X-ray tubes and electron beam irradiation devices, but can also be applied to devices that use an input voltage of several hundred volts.

[0016] The power supply circuit 1 includes an AC / DC conversion unit 2, an inverter circuit 3, a resonance circuit 4, and a rectifier circuit 5. An X-ray tube 6 is connected to the output side of the rectifier circuit 5.

[0017] The AC / DC conversion unit 2 is a functional unit that converts an AC voltage generated in the AC power supply AP into a DC voltage. The AC / DC conversion unit 2 is, for example, a switching-type AC / DC converter. In this case, the AC / DC conversion unit 2 may include a switching element (not shown) and a DC voltage control circuit (not shown) for controlling the magnitude of the DC voltage output from the AC / DC conversion unit 2. The DC voltage control circuit may detect the magnitude of a load voltage supplied to the X-ray tube 6, which is a load. The DC voltage control circuit may then control the switching element so that the magnitude of the load voltage approaches a desired value.

[0018] The inverter circuit 3 is a functional unit that converts the DC voltage generated by the AC / DC conversion unit 2 into an AC voltage. The configuration of the inverter circuit 3 will be described later. In the example of FIG. 1 , the power supply circuit 1 further includes an inverter control unit 7 for controlling the drive frequency of the inverter circuit 3. The inverter control unit 7 may detect the output current of the inverter circuit 3 using a current detection element CT and adjust the drive frequency of the inverter circuit 3 to follow the phase of the output current. The output current of the inverter circuit 3 is supplied to a resonant circuit 4 connected downstream of the inverter circuit 3. To suppress losses occurring in the inverter circuit 3, it is desirable that the frequency of the output current of the inverter circuit 3 match the resonant frequency of the resonant circuit 4. Therefore, the inverter control unit 7 adjusts the drive frequency of the inverter to follow the phase of the output current. The current detection element CT may be a current transformer or a power resistor. Alternatively, the inverter control unit 7 may adjust the drive frequency of the inverter without following the phase of the output current. The inverter control unit 7 may adjust the drive frequency of the inverter based on, for example, a parameter other than the phase of the output current.

[0019] The resonant circuit 4 is a functional unit that boosts the AC voltage output from the inverter circuit 3 to generate a load voltage. In the example of FIG. 1 , the resonant circuit 4 includes a transformer TR including a primary winding and a secondary winding, and a resonant capacitor Cr and a resonant inductor Lr connected between one end of the primary winding of the transformer TR and the output side of the inverter circuit 3. The resonant capacitor Cr is connected in series with the resonant inductor Lr. The resonant inductor Lr is, for example, the leakage inductance of the transformer TR. The resonant frequency of the resonant circuit 4 is determined mainly based on the resonant capacitor Cr and the resonant inductor Lr. The AC voltage output from the inverter circuit 3 is boosted to a voltage value corresponding to the turns ratio between the primary winding and the secondary winding of the transformer TR.

[0020] The rectifier circuit 5 is a functional unit that converts the AC voltage boosted in the resonant circuit 4 into a DC voltage and supplies it to the X-ray tube 6. The rectifier circuit 5 includes a rectifier diode unit 51 and a smoothing capacitor 52. The rectifier diode unit 51 is composed of, for example, four bridge-connected diodes. The AC voltage boosted in the resonant circuit 4 is rectified in the rectifier diode unit 51 and smoothed in the smoothing capacitor 52, thereby being converted into a DC voltage. [Configuration and Operation of Transistor Drive Circuit]

[0021] FIG. 2 is a circuit diagram of an inverter circuit 3 including transistor drive circuits 8 and 9 according to an embodiment of the present disclosure. In this embodiment, the inverter circuit 3 is a half-bridge circuit in which a drive target transistor T1 and a drive target transistor T2 are connected in series. The inverter circuit 3 includes an upper (high-side) drive target transistor T1, a lower (low-side) drive target transistor T2, a transistor drive circuit 8 for driving the upper drive target transistor T1, and a transistor drive circuit 9 for driving the lower drive target transistor T2. The upper drive target transistor T1 and the lower drive target transistor T2 may be metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs). The upper drive target transistor T1 includes a control terminal T1a to which a drive signal is input, a first current terminal T1b, and a second current terminal T1c. The upper drive target transistor T1 passes a current from the second current terminal T1c to the first current terminal T1b. When the upper drive target transistor T1 is an N-channel MOSFET, the control terminal T1a is a gate terminal, the first current terminal T1b is a source terminal, and the second current terminal T1c is a drain terminal. Like the upper drive target transistor T1, the lower drive target transistor T2 includes a control terminal T2a to which a drive signal is input, a first current terminal T2b, and a second current terminal T2c. In this embodiment, unless otherwise specified, the upper drive target transistor T1 and the lower drive target transistor T2 will be described as N-channel MOSFETs.

[0022] The second current terminal T1c of the upper drive target transistor T1 is connected to the output side of the AC / DC converter 2. Therefore, the DC voltage generated by the AC / DC converter 2 serves as the power supply voltage for the inverter circuit 3. The first current terminal T1b of the upper drive target transistor T1 is connected to the second current terminal T2c of the lower drive target transistor T2. The first current terminal T2b of the lower drive target transistor T2 is connected to the reference potential line GND. The output terminal Pa of the inverter is located between the first current terminal T1b of the upper drive target transistor T1 and the second current terminal T2c of the lower drive target transistor T2, and is connected to the resonant circuit 4. With the above configuration, the drive target transistor T1 functions as a power (signal) transmission transistor for turning on / off two nodes having different potentials (between the second current terminal T1c and the first current terminal T1b).

[0023] In the example of FIG. 2 , the upper drive target transistor T1 and the lower drive target transistor T2 are driven alternately. The inverter control unit 7 generates an inverter control signal such that the phase of the voltage supplied between the control terminal T1a and the first current terminal T1b of the upper drive target transistor T1 is inverted relative to the phase of the voltage supplied between the control terminal T2a and the first current terminal T2b of the lower drive target transistor T2. The inverter control unit 7 sets a dead time to prevent the upper drive target transistor T1 and the lower drive target transistor T2 from being driven simultaneously. The dead time here refers to the time from when the upper drive target transistor T1 stops until the lower drive target transistor T2 starts driving, or the time from when the lower drive target transistor T2 stops until the upper drive target transistor T1 starts driving.

[0024] Next, the configurations of the transistor drive circuit 8 for driving the upper drive target transistor T1 and the transistor drive circuit 9 for driving the lower drive target transistor T2 will be described. Since the configuration of the transistor drive circuit 9 is the same as that of the transistor drive circuit 8, only the transistor drive circuit 8 will be described here. The transistor drive circuit 8 has a pulse transformer PT, a first control circuit 81, a second control circuit 82, a drive pulse generator 83, and a stop pulse generator 84. The pulse transformer PT includes a primary winding N1, a first secondary winding N2, and a second secondary winding N3. The primary winding N1 is insulated from the first secondary winding N2 and the second secondary winding N3.

[0025] The first control circuit 81 includes a first portion 811 and a second portion 812. The first portion 811 is connected between the control terminal T1a and the first current terminal T1b of the driven transistor T1. The first portion 811 includes an input capacitance Ci1 and Zener diodes Z1 and Z4 located between the control terminal T1a and the first current terminal T1b of the driven transistor T1. The Zener diode Z1 and the Zener diode Z4 are connected in series in opposite directions. The input capacitance Ci1 and the series circuit of the Zener diodes Z1 and Z4 are connected in parallel. The second portion 812 is connected between the first secondary winding N2 and the control terminal T1a of the driven transistor T1. The second portion 812 includes a resistor R1 connected to one end N2a of the first secondary winding N2 and a diode D1 connected in the forward direction between the resistor R1 and the control terminal T1a. The anode of the diode D1 is connected to the resistor R1, and the cathode of the diode D1 is connected to the control terminal T1a. One end N2a of the first secondary winding N2, the resistor R1, the diode D1, and the control terminal T1a are all connected in series.

[0026] The second control circuit 82 is connected between the second secondary winding N3, the control terminal T1a of the driven transistor T1, and the first current terminal T1b of the driven transistor T1. The second control circuit 82 includes a diode D2 and a discharge transistor T3. The control terminal T3a of the discharge transistor T3 is connected to one end N3a of the second secondary winding N3. The first current terminal T3b of the discharge transistor T3 is connected to the other end N3b of the second secondary winding N3 and to the first current terminal T1b of the driven transistor T1. The second current terminal T3c of the discharge transistor T3 is connected to the control terminal T1a of the driven transistor T1 via the diode D2. The cathode of the diode D2 is connected to the second current terminal T3c of the discharge transistor T3. The anode of the diode D2 is connected to the control terminal T1a of the driven transistor T1. The diode D2 is provided to reduce the apparent parasitic capacitance existing between the first current terminal T3b and the second current terminal T3c of the discharge transistor T3 by combining with the diode D2. This allows the discharge transistor T3 to be driven and stopped at high speed. If the magnitude of the parasitic capacitance existing between the first current terminal T3b and the second current terminal T3c of the discharge transistor T3 is sufficiently small, the diode D2 may be omitted.

[0027] The inputs of the drive pulse generator 83 and the stop pulse generator 84 are connected to the output of the inverter control unit 7. The output of the drive pulse generator 83 is connected to one end N1a of the primary winding N1 via a damping resistor R2 and a DC blocking capacitor C1. The output of the drive pulse generator 83, the damping resistor R2, the DC blocking capacitor C1, and the one end N1a of the primary winding N1 are all connected in series. On the other hand, the output of the stop pulse generator 84 is connected to the other end N1b of the primary winding N1 via a damping resistor R3 and a DC blocking capacitor C2. The output of the stop pulse generator 84, the damping resistor R3, the DC blocking capacitor C2, and the other end N1b of the primary winding N1 are all connected in series. In the example of FIG. 2 , a pull-down resistor R4 is provided between a node between the DC blocking capacitor C1 and the one end N1a of the primary winding N1 and the reference potential line GND. A pull-down resistor R5 is provided between the reference potential line GND and a node between the DC blocking capacitor C2 and the other end N1b of the primary winding N1. The pull-down resistors R4 and R5 may be omitted depending on the values ​​of the exciting inductance of the pulse transformer PT and the DC blocking capacitors C1 and C2.

[0028] Next, we will explain the operation of the transistor drive circuit 8, from the time when the signals generated by the drive pulse generator 83 and the stop pulse generator 84 are transmitted to the first secondary winding N2 and the second secondary winding N3 of the pulse transformer PT. FIGS. 3A to 3C are diagrams showing the drive pulse signal DP, the stop pulse signal SP, and the signal waveforms generated in the primary winding N1, respectively. Upon receiving a control signal from the inverter control unit 7, the drive pulse generator 83 generates the drive pulse signal DP shown in FIG. 3A. Upon receiving a control signal from the inverter control unit 7, the stop pulse generator 84 generates the stop pulse signal SP shown in FIG. 3B. A predetermined phase difference PD is set between the phase of the drive pulse signal DP and the phase of the stop pulse signal SP. As will be described in detail later, this phase difference PD corresponds to the length of time the driven transistor T1 is driven. The frequencies of the drive pulse signal DP and the stop pulse signal SP are the inverter drive frequency controlled by the inverter control unit 7. The drive pulse signal DP and the stop pulse signal SP have a shorter high-level period than a low-level period. The high level is, for example, the potential of the power supply voltage of the drive pulse generating unit 83 and the stop pulse generating unit 84. The low level is, for example, the potential of the reference potential line GND. The high-level duration of the drive pulse signal DP and the stop pulse signal SP is required to reliably transition (drive) the driven transistor T1 to the ON state. For example, when the output impedance of the drive pulse generating unit 83 and the stop pulse generating unit 84 is approximately 1 Ω and the driven transistor T1 has an input capacitance of approximately 10 nF, the high-level duration of the drive pulse signal DP and the stop pulse signal SP is 500 ns to 1 μs. The duty ratio of the drive pulse signal DP and the stop pulse signal SP (the value obtained by dividing the high-level duration by the sum of the high-level duration and the low-level duration) is 1% or more and 5% or less. In other words, the drive pulse signal DP and the stop pulse signal SP are one-shot pulse signals.

[0029] The drive pulse signal DP generated by the drive pulse generator 83 is transmitted to one end N1a of the primary winding N1. At this time, the damping resistor R2 reduces overshoot of the drive pulse signal DP and ringing due to parasitic components, and the DC blocking capacitor C1 reduces the offset of the drive pulse signal DP. The stop pulse signal SP generated by the stop pulse generator 84 is transmitted to the other end N1b of the primary winding N1. At this time, the damping resistor R3 reduces overshoot of the stop pulse signal SP and ringing due to parasitic components, and the DC blocking capacitor C2 reduces the offset of the stop pulse signal SP. Because the duty ratios of the drive pulse signal DP and the stop pulse signal SP are very small, at 5% or less, almost the entire output amplitude value of the drive pulse generator 83 is transmitted to the input capacitance Ci1, sufficiently reducing the on-resistance of the driven transistor T1. The capacitance values ​​of the DC blocking capacitors C1 and C2 are, for example, several μF.

[0030] As shown in FIG. 3C, the pulse transformer PT generates a signal in the primary winding N1 in which the drive pulse signal DP and the stop pulse signal SP overlap, centered around the potential of the midpoint of the pulse transformer PT. Here, the midpoint of the pulse transformer PT is, for example, the potential of a center tap (not shown) of the pulse transformer PT. The pulse transformer PT transmits the signal shown in FIG. 3C to the first secondary winding N2 and transmits a signal obtained by inverting the signal shown in FIG. 3C to the second secondary winding N3. The above-described operation is similar for the lower transistor drive circuit 9. Here, the drive pulse signal DP shown in FIG. 3C has a waveform with a blunt rising edge. This illustrates, for example, the blunting that occurs when the input capacitance of the driven transistor T1 is significantly larger than the input capacitance of the discharge transistor T3.

[0031] Here, the operation of the upper transistor drive circuit 8 and the lower transistor drive circuit 9 will be described in detail. FIG. 4 is a timing chart showing an example of the operation of the upper transistor drive circuit 8 and the lower transistor drive circuit 9. FIG. 4(a) shows a signal transmitted to the first secondary winding N2 of the pulse transformer PT of the upper transistor drive circuit 8. As described above, a signal in which a positive drive pulse signal DP and a negative stop pulse signal SP are superimposed on each other, with the potential of the midpoint of the pulse transformer PT at the center, is transmitted to the first secondary winding N2. In the first secondary winding N2, the low level of the drive pulse signal DP coincides with the potential of the midpoint of the pulse transformer PT. FIG. 4(b) shows a signal transmitted to the second secondary winding N3 of the pulse transformer PT of the upper transistor drive circuit 8. A signal in which a negative drive pulse signal DP and a positive stop pulse signal SP are superimposed on each other is transmitted to the second secondary winding N3. In the second secondary winding N3, the low level of the stop pulse signal SP coincides with the potential at the midpoint of the pulse transformer PT.

[0032] 4(c) shows a signal transmitted to the first secondary winding N2 of the pulse transformer PT of the transistor drive circuit 9. FIG. 4(d) shows a signal transmitted to the second secondary winding N3 of the pulse transformer PT of the transistor drive circuit 9. The time waveforms of the signals shown in FIGS. 4(c) and 4(d) are similar to those shown in FIGS. 4(a) and 4(b), except that the phases of the signals are different from those of the signals shown in FIGS. 4(a) and 4(b). A dead time DT1 is set between the drive pulse signal DP (see FIG. 4(a)) transmitted to the first secondary winding N2 of the transistor drive circuit 8 and the stop pulse signal SP (see FIG. 4(d)) transmitted to the second secondary winding N3 of the transistor drive circuit 9. Similarly, a dead time DT2 is set between the stop pulse signal SP transmitted to the second secondary winding N3 of the transistor drive circuit 8 and the drive pulse signal DP transmitted to the first secondary winding N2 of the transistor drive circuit 9. The lengths of the dead times DT1 and DT2 may be the same or different.

[0033] Next, the operation of the transistor drive circuit 8, from the generation of the drive pulse signal DP and the stop pulse signal SP to the driving and stopping of the drive target transistor T1, will be described with reference to FIGS. 2 and 4 . The drive pulse signal DP is input to the control terminal T1a of the drive target transistor T1 via the second portion 812. This drives the drive target transistor T1. At the same time, a charge corresponding to the voltage value of the drive pulse signal DP is charged into the input capacitance Ci1. As a result, the first portion 811 enters a holding state in which it holds the voltage value of the drive pulse signal DP. During the holding state, the voltage held by the first portion 811 continues to be applied between the control terminal T1a and the first current terminal T1b of the drive target transistor T1. Therefore, the drive target transistor T1 continues to be driven. The capacitance value of the input capacitance Ci1 changes little with changes in the magnitude of the voltage applied between the second current terminal T1c and the first current terminal T1b. Therefore, even if the magnitude of the DC voltage generated by the AC / DC conversion unit 2 fluctuates, the input capacitance Ci1 can stably maintain the voltage holding state of the first portion 811. Furthermore, the diode D1 prevents the stored charge from flowing back toward one end N2a of the first secondary winding N2. The Zener diodes Z1 and Z4 prevent the gate-source of the driven transistor T1 from being destroyed due to an overvoltage caused by surge noise or the like flowing into the driven transistor T1 from the outside.

[0034] 4(e) shows the voltage waveform between the control terminal T1a and the first current terminal T1b of the driven transistor T1. In synchronization with the drive pulse signal DP in the first secondary winding N2 of the transistor drive circuit 8 rising from low to high, the voltage between the control terminal T1a and the first current terminal T1b rises from low to high. The low level of the voltage between the control terminal T1a and the first current terminal T1b is 0 V (the potential of the reference potential line GND). Even after the drive pulse signal DP in the first secondary winding N2 of the transistor drive circuit 8 falls from high to low, the voltage between the control terminal T1a and the first current terminal T1b remains high. As described above, the phase difference PD between the phase of the drive pulse signal DP and the phase of the stop pulse signal SP corresponds to the length of time the driven transistor T1 is driven.

[0035] Then, a stop pulse signal SP is input from one end N3a of the second secondary winding N3 to the control terminal T3a of the discharge transistor T3 of the second control circuit 82. The discharge transistor T3 is driven, and the charge accumulated in the input capacitance Ci1 is discharged via the diode D2 and the discharge transistor T3. This reduces the voltage between the control terminal T1a and the first current terminal T1b of the driven transistor T1, releasing the hold state of the first portion 811. Referring to (b) and (e) of FIG. 4, the voltage between the control terminal T1a and the first current terminal T1b falls from high to low in synchronization with the stop pulse signal SP rising from low to high. In the example of FIG. 2, Zener diodes Z2 and Z3 are provided between the control terminal T3a and the first current terminal T3b of the discharge transistor. The Zener diodes Z2 and Z3 are connected in series and in opposite directions between the control terminal T3a and the first current terminal T3b of the discharge transistor T3. The Zener diodes Z2 and Z3 prevent external noise from flowing into the discharge transistor T3.

[0036] The above-described operation is also applicable to the transistor drive circuit 9. (f) in FIG. 4 shows a voltage waveform between the control terminal T2a and the first current terminal T2b of the driven transistor T2. The voltage between the control terminal T2a and the first current terminal T2b rises from low to high in synchronization with the drive pulse signal DP in the first secondary winding N2 of the transistor drive circuit 9 rising from low to high. Meanwhile, the voltage between the control terminal T2a and the first current terminal T2b falls from high to low in synchronization with the stop pulse signal SP in the second secondary winding N3 of the transistor drive circuit 9 rising from low to high. The aforementioned dead time DT1 is set between the fall of the voltage between the control terminal T2a and the first current terminal T2b and the rise of the voltage between the control terminal T1a and the first current terminal T1b. Similarly, the aforementioned dead time DT2 is set between the falling edge of the voltage between the control terminal T1a and the first current terminal T1b and the rising edge of the voltage between the control terminal T2a and the first current terminal T2b, thereby preventing the drive target transistor T1 and the drive target transistor T2 from being driven simultaneously.

[0037] In the transistor drive circuit 8, the pulse transformer PT outputs a drive pulse signal DP from the first secondary winding N2 to the first control circuit 81. When the drive pulse signal DP is input from the pulse transformer PT to the first control circuit 81, the first portion 811 enters a hold state, retaining the voltage value of the drive pulse signal DP. The first portion 811 drives the drive target transistor T1 with the retained voltage. As a result, while the first portion 811 is in the hold state, a voltage corresponding to the drive pulse signal DP continues to be applied between the control terminal T1a and the first current terminal T1b of the drive target transistor T1, thereby driving the drive target transistor T1. This allows the pulse width of the drive pulse signal DP to be set narrower relative to the drive time of the drive target transistor T1. This allows the minimum operating frequency of the pulse transformer PT to be increased, thereby enabling the pulse transformer PT to be made more compact. Meanwhile, the pulse transformer PT outputs a stop pulse signal SP from the second secondary winding N3 to the second control circuit 82. When the stop pulse signal SP is input from the pulse transformer PT, the second control circuit 82 releases the hold state of the first portion 811. This reduces the voltage between the control terminal T1a and the first current terminal T1b of the driven transistor T1. Then, when the voltage between the control terminal T1a and the first current terminal T1b of the driven transistor T1 falls below the threshold voltage, the driven transistor T1 can be quickly and reliably turned off. As described above, the transistor drive circuit 8 can reduce the size of the pulse transformer PT and quickly and reliably turn off the driven transistor T1. Furthermore, the transistor drive circuit 8 can input a floating potential difference, based on the first current terminal T1b, to the control terminal T1a of the driven transistor T1 (in other words, the high-side transistor in the half-bridge circuit) of the power supply voltage supplied from the AC / DC conversion unit 2. For example, when a power supply voltage of 100 V is supplied from the AC / DC conversion unit 2, a floating potential difference (gate-source voltage Vgs (e.g., 15 V) of the driven transistor T1) based on the first current terminal T1b is input in a state where it is superimposed on 100 V.As a result, the potential of the control terminal T1a relative to the reference potential line GND becomes 115 V. This allows the high-side transistor to be driven appropriately.

[0038] The drive circuit may further include a second portion 812 connected between the first secondary winding N2 and the control terminal T1a of the driven transistor T1. The second portion 812 may include a diode D1 connected in a forward direction between one end N2a of the first secondary winding N2 and the control terminal T1a of the driven transistor T1. The first portion 811 may include an input capacitance Ci1 of the driven transistor T1 located between the control terminal T1a of the driven transistor T1 and the first current terminal T1b of the driven transistor T1. This allows a charge corresponding to the voltage value of the drive pulse signal DP to be stored in the input capacitance Ci1, thereby maintaining the voltage value of the drive pulse signal DP. Additionally, the diode D1 prevents the stored charge from flowing back toward the one end N2a of the first secondary winding N2. This allows the voltage value of the drive pulse signal DP to be stably maintained, thereby enabling stable driving of the driven transistor T1.

[0039] The second control circuit 82 includes a discharge transistor T3, which includes a control terminal T3a connected to one end N3a of the second secondary winding N3, a first current terminal T3b connected to the other end N3b of the second secondary winding N3 and connected to the first current terminal T1b of the driven transistor T1, and a second current terminal T3c connected to the control terminal T1a of the driven transistor T1. When a stop pulse signal SP is input from one end N3a of the second secondary winding N3 to the second control circuit 82, the discharge transistor T3 is driven. At this time, the charge accumulated in the input capacitance Ci1 of the driven transistor T1 is discharged via the discharge transistor T3. This more reliably releases the voltage holding state of the first portion 811.

[0040] The effects described above also apply to the transistor drive circuit 9. [First Modification]

[0041] Although the embodiments of the present disclosure have been described above, the present disclosure is not necessarily limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present disclosure.

[0042] FIG. 5 is a circuit diagram of an inverter circuit 3A including transistor drive circuits 8A and 9A according to a first modification. Regarding the configuration of the transistor drive circuit 8A, only differences from the transistor drive circuit 8 of the embodiment will be described. In addition to the configuration of the transistor drive circuit 8, the transistor drive circuit 8A also includes an auxiliary transistor T4 and a diode D3. The auxiliary transistor T4 is a transistor that provides a Miller clamp function to the discharge transistor T3. The control terminal T4a of the auxiliary transistor T4 is connected to one end N2a of the first secondary winding N2. The first current terminal T4b of the auxiliary transistor T4 is connected to the first current terminal T3b of the discharge transistor T3. The second current terminal T4c of the auxiliary transistor T4 is connected to the control terminal T3a of the discharge transistor T3. The anode of the diode D3 is connected to one end N3a of the second secondary winding N3 of the pulse transformer PT. The cathode of the diode D3 is connected to the control terminal T3a of the discharge transistor T3 and the second current terminal T4c of the auxiliary transistor T4. The transistor drive circuit 9A has a similar configuration.

[0043] Next, the operation of the transistor drive circuit 8A will be described, focusing only on the differences from the transistor drive circuit 8 of the embodiment. The drive pulse signal DP is input to the control terminal T1a of the driven transistor T1 and simultaneously to the control terminal T4a of the auxiliary transistor T4. This drives the auxiliary transistor T4, shorting one end N3a and the other end N3b of the second secondary winding N3 via the auxiliary transistor T4, and no signal is input to the control terminal T3a of the discharge transistor T3. When the drive pulse signal DP falls, the auxiliary transistor T4 is no longer driven, and the state in which no signal is input to the control terminal T3a is released.

[0044] Thereafter, the discharge transistor T3 is driven by the stop pulse signal SP, and simultaneously, an electric charge is charged into the input capacitance Ci2 present between the control terminal T3a and the first current terminal T3b of the discharge transistor T3. As a result, a voltage continues to be applied between the control terminal T3a and the first current terminal T3b of the discharge transistor T3, and the discharge transistor T3 continues to be driven. Furthermore, the diode D3 prevents the electric charge stored in the input capacitance Ci2 from flowing back toward the one end N3a of the second secondary winding N3. This allows the input capacitance Ci2 to stably maintain the voltage across it, enabling the discharge transistor T3 to be stably driven.

[0045] Fig. 6 is a timing chart showing an example of the operation of the transistor drive circuits 8A and 9A according to the first modification. In addition to the waveforms shown in Fig. 4(a) to (f) (i.e., Fig. 6(a) to (e) and (g)), Fig. 6 also shows a voltage waveform (Fig. 6(f)) between the control terminal T3a and the first current terminal T3b of the discharge transistor T3 in the transistor drive circuit 8A, and a voltage waveform (Fig. 6(h)) between the control terminal T3a and the first current terminal T3b of the discharge transistor T3 in the transistor drive circuit 9A.

[0046] 6, attention is focused on the voltage waveform between the control terminal T1a and the first current terminal T1b of the driven transistor T1 ((e) of FIG. 6) and the voltage waveform between the control terminal T3a and the first current terminal T3b of the discharge transistor T3 of the transistor drive circuit 8A ((f) of FIG. 6). In synchronization with the voltage between the control terminal T1a and the first current terminal T1b rising from low to high, the voltage between the control terminal T3a and the first current terminal T3b falls from high to low. Here, the low level is 0 V (the potential of the reference potential line GND). While the voltage between the control terminal T1a and the first current terminal T1b is high, the voltage between the control terminal T3a and the first current terminal T3b is low. As a result, the discharge transistor T3 is stopped while the driven transistor T1 is being driven. Meanwhile, in synchronization with the voltage between the control terminal T1a and the first current terminal T1b falling from high to low, the voltage between the control terminal T3a and the first current terminal T3b rises from low to high. While the voltage between the control terminal T1a and the first current terminal T1b is low, the voltage between the control terminal T3a and the first current terminal T3b is high. As a result, the discharge transistor T3 is driven while the drive target transistor T1 is stopped. The above-described operation is similar to that of the transistor drive circuit 9A if the drive target transistor T1 is replaced with the drive target transistor T2.

[0047] The transistor drive circuit 8A includes an auxiliary transistor T4. The auxiliary transistor T4 includes a second current terminal T4c connected to the control terminal T3a of the discharge transistor T3, a first current terminal T4b connected to the first current terminal T3b of the discharge transistor T3, and a control terminal T4a connected to one end N2a of the first secondary winding N2. When a drive pulse signal DP is input from the pulse transformer PT to the first control circuit 81, the auxiliary transistor T4 is driven, explicitly shorting the control terminal T3a of the discharge transistor T3. This ensures that the discharge transistor T3 transitions to the OFF state (falls from high to low). This ensures that the discharge transistor T3 is turned OFF by the auxiliary transistor T4, even if the discharge transistor T3 remains ON until just before the driven transistor T1 transitions to the ON state (rises from low to high). This prevents erroneous firing of the driven transistor T1 and ensures stable driving of the driven transistor T1. The above-described effects are similarly achieved in the transistor drive circuit 9A if the driven transistor T1 is replaced with the driven transistor T2. [Second Modification]

[0048] FIG. 7 is a circuit diagram of an inverter circuit 3B including transistor drive circuits 8B and 9B according to a second modification. Regarding the configuration of the transistor drive circuit 8B, only differences from the transistor drive circuit 8A of the first modification will be described. In addition to the configuration of the transistor drive circuit 8A, the transistor drive circuit 8B also includes a reverse bias capacitor C3 and a Zener diode Z5. The reverse bias capacitor C3 is a capacitor having a positive and negative terminal. The positive terminal of the reverse bias capacitor C3 is connected to the first current terminal T1b of the transistor T1 to be driven. The negative terminal of the reverse bias capacitor C3 is connected to the first current terminal T3b of the discharge transistor T3 and to the other end N2b of the first secondary winding N2 of the pulse transformer PT. In the transistor drive circuit 8B, the other end N2b of the first secondary winding N2 is not connected to the first current terminal T1b of the transistor T1 to be driven. The Zener diode Z5 is connected in parallel with the reverse bias capacitor C3. Specifically, the Zener diode Z5 is connected between the positive electrode of the reverse bias capacitor C3 and the negative electrode of the reverse bias capacitor C3. If the driven transistor T1 is replaced with the driven transistor T2, the transistor drive circuit 9A has a similar configuration.

[0049] Next, the operation of the transistor drive circuit 8B will be described, focusing on the differences from the transistor drive circuit 8A of the first modification. When the drive target transistor T1 is driven, a current flows from the first current terminal T1b of the drive target transistor T1 to the reverse bias capacitor C3. The reverse bias capacitor C3 is charged with a charge based on this current. When the discharge transistor T3 is driven, the negative terminal of the reverse bias capacitor C3 is connected to the control terminal T1a of the drive target transistor T1 via the discharge transistor T3. The voltage based on the charge stored in the reverse bias capacitor C3 is controlled to a constant voltage by the Zener diode Z5. The controlled voltage is applied as a reverse bias voltage between the control terminal T1a and the first current terminal T1b of the drive target transistor T1. This more reliably maintains the OFF state (low level) of the drive target transistor T1 when the discharge transistor T3 is driven. The above-described operation is similar to that of the transistor drive circuit 9B if the drive target transistor T1 is replaced with the drive target transistor T2.

[0050] FIG. 8 is a timing chart showing an example of the operation of the transistor drive circuits 8B and 9B according to the second modification. Below, only the differences from the operation of the transistor drive circuits 8A and 9A according to the first modification will be described. In (e) of FIG. 8, the low level of the voltage between the control terminal T1a and the first current terminal T1b of the drive target transistor T1 is lower than 0 V. This is because, when the drive target transistor T1 is stopped, a reverse bias is applied between the control terminal T1a and the first current terminal T1b of the drive target transistor T1 by the reverse bias capacitor C3. Similarly, in (g) of FIG. 8, the low level of the voltage between the control terminal T2a and the first current terminal T2b of the drive target transistor T2 is lower than 0 V. This is because, when the drive target transistor T2 is stopped, a reverse bias is applied between the control terminal T2a and the first current terminal T2b of the drive target transistor T2 by the reverse bias capacitor C3.

[0051] The transistor drive circuit 8B includes a reverse bias capacitor C3, the positive terminal of which is connected to the first current terminal T1b of the transistor T1 to be driven and the negative terminal of which is connected to the first current terminal T3b of the discharge transistor T3, and a Zener diode Z5 connected in parallel to the reverse bias capacitor C13. When the transistor T1 to be driven is driven, a current flows from the transistor T1 to the reverse bias capacitor C3, charging the reverse bias capacitor C3. When the discharge transistor T3 is driven, the negative terminal of the reverse bias capacitor C3 is connected to the control terminal T1a of the transistor T1 to be driven via the discharge transistor T3. The voltage based on the charge stored in the reverse bias capacitor C3 is controlled to a constant voltage by the Zener diode Z5 and applied as a reverse bias voltage between the control terminal T1a and the first current terminal T1b of the transistor T1 to be driven. This more reliably turns off the transistor T1 to be driven and maintains the OFF state until the next ON state transition. The above-described effects are similarly achieved in the transistor drive circuit 9B if the driven transistor T1 is replaced with the driven transistor T2.

[0052] 9 and 10 are circuit diagrams of an inverter circuit 3C including transistor drive circuits 8C and 9C according to a third modification. The inverter circuit 3C is a circuit in which the transistor drive circuit 8C shown in FIG. 9 and the transistor drive circuit 9C shown in FIG. 10 are coupled together. The primary side of the transistor drive circuit 8C has the same configuration as the primary side of the transistor drive circuit 8. The secondary side of the transistor drive circuit 8C has the same configuration as the secondary side of the transistor drive circuit 8 and the secondary side of the transistor drive circuit 9. That is, in the pulse transformer PT in the transistor drive circuit 8C, two first secondary windings N2 and two second secondary windings N3 correspond to one primary winding N1.

[0053] The configuration of the primary side of the transistor drive circuit 9C is similar to the configuration of the primary side of the transistor drive circuit 9. The configuration of the secondary side of the transistor drive circuit 9C is similar to the configuration of the secondary side of the transistor drive circuit 8 and the configuration of the secondary side of the transistor drive circuit 9. That is, in the pulse transformer PT of the transistor drive circuit 9C, one primary winding N1 corresponds to two first secondary windings N2 and two second secondary windings N3.

[0054] In the inverter circuit 3C, the first current terminal T2b of the transistor T2 to be driven in the transistor drive circuit 8C and the second current terminal T1c of the transistor T1 to be driven in the transistor drive circuit 9C are connected to each other at a connection point Pb. The connection point Pb is connected to the resonant circuit 4. The inverter circuit 3C operates as a full-bridge circuit.

[0055] In the pulse transformers PT in the transistor drive circuits 8C and 9C, three or more first secondary windings N2 and three or more second secondary windings N3 may correspond to one primary winding N1. For example, a first additional drive target transistor may be newly provided on the secondary side of the transistor drive circuit 8C. A second additional drive target transistor may be newly provided on the secondary side of the transistor drive circuit 9C. The second current terminal of the first additional drive target transistor may be connected to the first current terminal T2b of the drive target transistor T2 in the transistor drive circuit 8C. The first current terminal of the first additional drive target transistor may be connected to the connection point Pb. The circuit for driving the first additional drive target transistor may have the same configuration as the circuit for driving the drive target transistors T1 and T2. In addition, the second current terminal of the second additional drive target transistor may be connected to the first current terminal T2b of the drive target transistor T2 in the transistor drive circuit 9C. In addition, the first current terminal of the second additional transistor to be driven may be connected to the reference potential line GND. A circuit for driving the second additional transistor to be driven may have the same configuration as the circuits for driving the transistors to be driven T1 and T2.

[0056] 11 and 12 are circuit diagrams of an inverter circuit 3D including transistor drive circuits 8D and 9D according to a fourth modification. The inverter circuit 3D is a circuit in which the transistor drive circuit 8D shown in FIG. 11 and the transistor drive circuit 9D shown in FIG. 12 are combined. The primary side of the transistor drive circuit 8D has the same configuration as the primary side of the transistor drive circuit 8A. The secondary side of the transistor drive circuit 8D has the same configuration as the secondary side of the transistor drive circuit 8A and the secondary side of the transistor drive circuit 9A. That is, in the pulse transformer PT of the transistor drive circuit 8D, one primary winding N1 corresponds to two first secondary windings N2 and two second secondary windings N3.

[0057] The primary side of the transistor drive circuit 9D has the same configuration as the primary side of the transistor drive circuit 9A. The secondary side of the transistor drive circuit 9D has the same configuration as the secondary side of the transistor drive circuit 8A and the secondary side of the transistor drive circuit 9A. That is, in the pulse transformer PT of the transistor drive circuit 9D, one primary winding N1 corresponds to two first secondary windings N2 and two second secondary windings N3.

[0058] In the inverter circuit 3D, the first current terminal T2b of the transistor T2 to be driven in the transistor drive circuit 8D and the second current terminal T1c of the transistor T1 to be driven in the transistor drive circuit 9D are connected to each other at a connection point Pb. The connection point Pb is connected to the resonant circuit 4. The inverter circuit 3D operates as a full-bridge circuit.

[0059] In the pulse transformers PT in the transistor driver circuits 8D and 9D, three or more first secondary windings N2 and three or more second secondary windings N3 may correspond to one primary winding N1. In this case, the configuration example is the same as the modified example described above for the transistor driver circuits 8C and 9C.

[0060] 13 and 14 are circuit diagrams of an inverter circuit 3E including transistor drive circuits 8E and 9E according to a fifth modification. The inverter circuit 3E is a circuit in which the transistor drive circuit 8E shown in FIG. 13 and the transistor drive circuit 9E shown in FIG. 14 are combined. The primary side of the transistor drive circuit 8E has the same configuration as the primary side of the transistor drive circuit 8B. The secondary side of the transistor drive circuit 8E has the same configuration as the secondary side of the transistor drive circuit 8B and the secondary side of the transistor drive circuit 9B. In other words, in the pulse transformer PT of the transistor drive circuit 8E, one primary winding N1 corresponds to two first secondary windings N2 and two second secondary windings N3.

[0061] The primary side of the transistor drive circuit 9E has the same configuration as the primary side of the transistor drive circuit 9B. The secondary side of the transistor drive circuit 9E has the same configuration as the secondary side of the transistor drive circuit 8B and the secondary side of the transistor drive circuit 9B. That is, in the pulse transformer PT of the transistor drive circuit 9E, one primary winding N1 corresponds to two first secondary windings N2 and two second secondary windings N3.

[0062] In the inverter circuit 3E, the first current terminal T2b of the transistor T2 to be driven in the transistor drive circuit 8E and the second current terminal T1c of the transistor T1 to be driven in the transistor drive circuit 9E are connected to each other at a connection point Pb. The connection point Pb is connected to the resonant circuit 4. The inverter circuit 3E operates as a full-bridge circuit.

[0063] The transistor drive circuits 8C to 8E and 9C to 9E according to the third to fifth modifications can achieve the same effects as the transistor drive circuits 8 and 9 according to the above embodiment.

[0064] In the pulse transformers PT in the transistor drive circuits 8E and 9E, three or more first secondary windings N2 and three or more second secondary windings N3 may correspond to one primary winding N1. In this case, the configuration example is the same as the modified examples described above for the transistor drive circuits 8C and 9C. [Modifications 6 to 8]

[0065] 15 and 16 are circuit diagrams of an inverter circuit 3F including transistor drive circuits 8F and 9F according to a sixth modification. Only differences from the inverter circuit 3C according to the third modification will be described. The first current terminal T1b of the drive target transistor T1 in the transistor drive circuit 8F is connected to the second current terminal T2c of the drive target transistor T2 in the transistor drive circuit 9F. The second current terminal T2c of the drive target transistor T2 in the transistor drive circuit 8F is connected to the output side of the AC / DC converter 2. The first current terminal T2b of the drive target transistor T2 in the transistor drive circuit 8F is connected to the second current terminal T1c of the drive target transistor T1 in the transistor drive circuit 9F.

[0066] In the inverter circuit 3F, the first current terminal T2b of the transistor T2 to be driven in the transistor drive circuit 8F and the second current terminal T1c of the transistor T1 to be driven in the transistor drive circuit 9F are connected to each other at a connection point Pb. Similarly, the first current terminal T1b of the transistor T1 to be driven in the transistor drive circuit 8F and the second current terminal T2c of the transistor T2 to be driven in the transistor drive circuit 9F are connected to each other at a connection point Pc. The connection points Pb and Pc are connected to the resonant circuit 4.

[0067] In the pulse transformers PT in the transistor drive circuits 8F and 9F, three or more first secondary windings N2 and three or more second secondary windings N3 may correspond to one primary winding N1. In this case, the configuration example is the same as the modified example described above for the transistor drive circuits 8C and 9C. Any combination of the drive target transistors T1 and T2 and the second additional drive target transistor included in the transistor drive circuit 9F may be connected to the drive target transistors T1 and T2 and the first additional drive target transistor included in the transistor drive circuit 8F, respectively.

[0068] 17 and 18 are circuit diagrams of an inverter circuit 3G including transistor drive circuits 8G and 9G according to a seventh modification. Only differences from the inverter circuit 3D according to the fourth modification will be described. The first current terminal T1b of the drive target transistor T1 in the transistor drive circuit 8G is connected to the second current terminal T2c of the drive target transistor T2 in the transistor drive circuit 9G. The second current terminal T2c of the drive target transistor T2 in the transistor drive circuit 8G is connected to the output side of the AC / DC converter 2. The first current terminal T2b of the drive target transistor T2 in the transistor drive circuit 8G is connected to the second current terminal T1c of the drive target transistor T1 in the transistor drive circuit 9G.

[0069] In the inverter circuit 3G, the first current terminal T2b of the drive target transistor T2 of the transistor drive circuit 8G and the second current terminal T1c of the drive target transistor T1 of the transistor drive circuit 9G are connected to each other at a connection point Pb. Similarly, the first current terminal T1b of the drive target transistor T1 of the transistor drive circuit 8G and the second current terminal T2c of the drive target transistor T2 of the transistor drive circuit 9G are connected to each other at a connection point Pc. The connection points Pb and Pc are connected to the resonant circuit 4.

[0070] In the pulse transformers PT in the transistor drive circuits 8G and 9G, three or more first secondary windings N2 and three or more second secondary windings N3 may correspond to one primary winding N1. In this case, the configuration example is the same as the modified example described above for the transistor drive circuits 8C and 9C. Any combination of the drive target transistors T1, T2 and the second additional drive target transistor included in the transistor drive circuit 9G may be connected to the drive target transistors T1, T2 and the first additional drive target transistor included in the transistor drive circuit 8G, respectively.

[0071] 19 and 20 are circuit diagrams of an inverter circuit 3H including transistor drive circuits 8H and 9H according to an eighth modification. Only differences from the inverter circuit 3E according to the fourth modification will be described. The first current terminal T1b of the drive target transistor T1 in the transistor drive circuit 8H is connected to the second current terminal T2c of the drive target transistor T2 in the transistor drive circuit 9H. The second current terminal T2c of the drive target transistor T2 in the transistor drive circuit 8H is connected to the output side of the AC / DC converter 2. The first current terminal T2b of the drive target transistor T2 in the transistor drive circuit 8H is connected to the second current terminal T1c of the drive target transistor T1 in the transistor drive circuit 9H.

[0072] In the inverter circuit 3H, the first current terminal T2b of the drive target transistor T2 of the transistor drive circuit 8H and the second current terminal T1c of the drive target transistor T1 of the transistor drive circuit 9H are connected to each other at a connection point Pb. Similarly, the first current terminal T1b of the drive target transistor T1 of the transistor drive circuit 8H and the second current terminal T2c of the drive target transistor T2 of the transistor drive circuit 9H are connected to each other at a connection point Pc. The connection points Pb and Pc are connected to the resonant circuit 4.

[0073] In the pulse transformers PT in the transistor drive circuits 8H and 9H, three or more first secondary windings N2 and three or more second secondary windings N3 may correspond to one primary winding N1. In this case, the configuration example is the same as that of the modified examples described above for the transistor drive circuits 8C and 9C. Any combination of the drive target transistors T1, T2 and the second additional drive target transistor included in the transistor drive circuit 9H may be connected to the drive target transistors T1, T2 and the first additional drive target transistor included in the transistor drive circuit 8H, respectively. [Ninth Modification]

[0074] The drive pulse signal DP generated by the drive pulse generating unit 83 may include two or more pulses. Similarly, the stop pulse signal SP generated by the stop pulse generating unit 84 may include two or more pulses. When the drive pulse signal DP includes two or more pulses, the drive target transistor T1 can be kept driven more stably. Similarly, when the stop pulse signal SP includes two or more pulses, the drive target transistor T1 can be kept stopped more stably.

[0075] 8, 8A, 8B, 9, 9A, 9B...transistor drive circuit, 81...first control circuit, 82...second control circuit, 811...first section, 812...second section, 83...drive pulse generation section, 84...stop pulse generation section, C3...reverse bias capacitor, Ci1...input capacitance, D1...diode, DP...drive pulse signal, N1...primary winding, N1a...one end of primary winding, N1b...other end of primary winding, N2...first secondary winding, N2a...one end of first secondary winding, N2b...other end of first secondary winding, N3...second secondary winding, N3a...one end of second secondary winding, N3b...other end of second secondary winding, PT...pulse transformer, SP ...stop pulse signal, T1, T2...transistor to be driven, T1a, T2a...control terminal of transistor to be driven, T1b, T2b...first current terminal of transistor to be driven, T1c, T2c...second current terminal of transistor to be driven, T3...discharging transistor, T3a...control terminal of discharge transistor, T3b...first current terminal of discharge transistor, T3c...second current terminal of discharge transistor, T4...auxiliary transistor, T4a...control terminal of auxiliary transistor, T4b...first current terminal of auxiliary transistor, T4c...second current terminal of auxiliary transistor, Z5...Zener diode.

Claims

1. A transistor drive circuit comprising: a pulse transformer having a primary winding, a first secondary winding, and a second secondary winding, the first secondary winding being connected to a control terminal of a transistor to be driven; a first control circuit having a first portion connected between the control terminal of the transistor to be driven and a first current terminal of the transistor to be driven; a second control circuit connected between the second secondary winding, the control terminal of the transistor to be driven, and the first current terminal of the transistor to be driven; a drive pulse generation unit connected to the primary winding and generating a drive pulse signal; and a stop pulse generation unit connected to the primary winding and generating a stop pulse signal; when the drive pulse signal is input from the pulse transformer to the first control circuit, the first portion enters a hold state in which it holds the voltage of the drive pulse signal, and drives the transistor to be driven by the held voltage; and when the stop pulse signal is input from the pulse transformer to the second control circuit, the second control circuit releases the hold state of the first portion.

2. The transistor drive circuit according to claim 1, further comprising a second portion connected between the first secondary winding and a control terminal of the driven transistor, the second portion including a diode connected in a forward direction between one end of the first secondary winding and the control terminal of the driven transistor, and the first portion including an input capacitance of the driven transistor located between the control terminal of the driven transistor and a first current terminal of the driven transistor.

3. The transistor drive circuit of claim 2, wherein the second control circuit has a discharge transistor including a control terminal connected to one end of the second secondary winding, a first current terminal connected to the other end of the second secondary winding and to a first current terminal of the transistor to be driven, and a second current terminal connected to the control terminal of the transistor to be driven.

4. The transistor driver circuit of claim 3, further comprising an auxiliary transistor including a second current terminal connected to the control terminal of said discharge transistor, a first current terminal connected to the first current terminal of said discharge transistor, and a control terminal connected to one end of said first secondary winding.

5. The transistor drive circuit according to claim 3 or 4, further comprising: a reverse bias capacitor having a positive terminal connected to the first current terminal of the driven transistor and a negative terminal connected to the first current terminal of the discharge transistor; and a Zener diode connected in parallel to the reverse bias capacitor.

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