Circuit board, and semiconductor package comprising same

Abstract

An embodiment of the present invention provides a circuit board comprising: a first insulation layer including glass and including a first through-hole extending through an upper surface and a lower surface; a bonding layer disposed on the first insulation layer; and a first electrode unit including a first via electrode disposed in the first through-hole, and a first wiring unit disposed on the upper surface and the lower surface, wherein the bonding layer is disposed on the upper surface, the lower surface, and an inner wall of the first through-hole.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices, such as mobile devices, and the adoption of High Bandwidth Memory (HBM) have led to larger package sizes. Furthermore, as the number of functions required for application processors increases, there is a growing demand for separate processor chips for each function, along with circuit boards capable of mounting these processor chips. Even when the application processor is split into two processor chips, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal quantity. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability issues such as warpage of circuit boards, and product price increases. Therefore, increasing the density of circuit patterns is more advantageous in terms of product price, reliability issues such as warpage, and product miniaturization than increasing the area and thickness of circuit boards. Therefore, miniaturization of circuit patterns and through-holes is required.

[0006] In particular, as circuit boards become increasingly thinner, deformations such as warping and twisting that occur during circuit board manufacturing are increasing. To prevent this, a glass core structure, in which a glass plate is formed in the core portion of the circuit board, has been proposed.

[0007] An embodiment of the present invention implements a circuit board and a semiconductor package including the same, in which warpage is suppressed and electrical characteristics are improved through a glass layer having high rigidity and a small coefficient of thermal expansion.

[0008] In addition, the embodiment can realize a circuit board with improved reliability and a semiconductor package including the same by forming a bonding layer with high adhesion on an insulating layer of glass.

[0009] In addition, the embodiment can implement a circuit board with improved structural reliability through a uniform bonding layer and a semiconductor package including the same.

[0010] In addition, the embodiment can implement a circuit board and a semiconductor package including the same in which the bonding strength between the electrode part and the insulating layer is further improved through a bonding layer including a home or hole.

[0011] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, which can structurally effectively disperse external pressure or thermal stress by having an area in which the inner surface of the through hole has a curvature.

[0012] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved structural reliability by improving stress relief by placing a buffer layer on the upper and lower surfaces of the core layer.

[0013] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, in which mechanical reliability is improved and thermal stress is alleviated through a structure having different curvatures at opposite points.

[0014] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, in which electrical characteristics are improved and thermal deformation is effectively suppressed through a connection buffer layer and an inner via hole.

[0015] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved manufacturing ease and improved heat dissipation effect through a cavity penetrating at least a part of a core layer or a part of a buffer layer.

[0016] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0017] A circuit board according to an embodiment of the present invention comprises: a first insulating layer including glass and a first through-hole penetrating an upper surface and a lower surface; a bonding layer disposed on the first insulating layer; and a first electrode portion including a first via electrode disposed in the first through-hole and a first wiring portion disposed on the upper surface and the lower surface; wherein the bonding layer is disposed on the upper surface, the lower surface, and an inner wall of the first through-hole.

[0018] The above bonding layer may have a thickness on the upper or lower surface of the first insulating layer that is the same as the thickness on the inner wall of the first through hole.

[0019] The above bonding layer may include a metal oxide.

[0020] The above bonding layer may include a salt composed of Na.

[0021] The salt may be located inside or on the surface of the bonding layer.

[0022] It may include a second insulating layer disposed on the first insulating layer.

[0023] The above bonding layer may include a first region in contact with the second insulating layer and a second region other than the first region.

[0024] The first region may be in contact with the second insulating layer on the first insulating layer, and the second region may be in contact with the first electrode portion on the first insulating layer.

[0025] The above bonding layer includes a salt composed of Na, and the salt may be present in a large proportion in the first region compared to the second region.

[0026] The above bonding layer may be located on the outermost surface of the first insulating layer.

[0027] A circuit board according to an embodiment includes a first insulating layer including glass and a first through-hole penetrating an upper surface and a lower surface; a bonding layer disposed on the first insulating layer; and a first electrode portion including a first via electrode disposed in the first through-hole and a first wiring portion disposed on the upper surface and the lower surface; wherein the bonding layer may have a thickness greater on an upper surface or a lower surface of the first insulating layer than a thickness on an inner surface of the first through-hole.

[0028] The thickness of the above bonding layer may decrease from the inner side of the first through hole toward the center of the through hole.

[0029] The above bonding layer may include holes or grooves.

[0030] The angle between the hole or groove of the bonding layer and the upper surface in the inner region of the first through hole may be different from the angle between the hole or groove of the bonding layer and the upper surface in the outer region of the first through hole.

[0031] The first electrode portion may be placed in a hole or groove of the bonding layer.

[0032] The hole or groove of the above bonding layer may have a void portion.

[0033] It may include a second insulating layer disposed on the first insulating layer.

[0034] The above bonding layer includes a hole or a groove, and the second insulating layer can be placed in the hole or groove of the bonding layer.

[0035] The bonding layer may be disposed between the second insulating layer and the first insulating layer or between the first electrode portion and the first insulating layer.

[0036] The above bonding layer may include polysilazane or parylene.

[0037] A circuit board according to an embodiment comprises a first insulating layer including glass and a first through-hole penetrating an upper surface and a lower surface; and a first electrode portion including a first via electrode disposed in the first through-hole and a first wiring portion disposed on the upper surface and the lower surface; wherein the first through-hole has a different curvature and a maximum width is less than or equal to twice the minimum width.

[0038] The first through hole may include a central region having a region of zero curvature.

[0039] The first through hole includes a first region and a second region that are arranged crosswise on the central region, and one of the first region and the second region may be a region with a negative curvature and the other may be a region with a positive curvature.

[0040] The first region may have a negative curvature, and the second region may have a positive curvature.

[0041] The above first region can be in contact with the above central region.

[0042] The thickness of the first region may be greater than the thickness of the second region.

[0043] The thickness of the first region may be greater than the thickness of the central region.

[0044] The second region may have a region in which the absolute value of curvature is greater than that of the first region.

[0045] The second region may be adjacent to the upper surface and the lower surface.

[0046] The first region may be located between the second region and the central region.

[0047] The second region may include a 2-1 region that contacts the first region and a 2-2 region that contacts the 2-1 region.

[0048] The curvature in the above 2-1 region may be smaller than the curvature in the above 2-2 region.

[0049] The thickness of the above 2-1 region or the thickness of the above 2-2 region may be smaller than the thickness of the above 1 region or the thickness of the above central region.

[0050] The thickness of the first region may be greater than the thickness of the central region or the thickness of the second region.

[0051] The above first through hole may have the minimum width in the first central region and the maximum width in the second region.

[0052] A circuit board according to an embodiment includes a core layer including glass; a buffer layer disposed on an upper surface and a lower surface of the core layer; a first electrode portion disposed on the core layer and the buffer layer; and a via hole penetrating the core layer and the buffer layer, wherein the via hole includes a first region within the core layer and a second region within the buffer layer, and side surfaces of each of the first region and the second region have different inclination angles with respect to an upper surface of the core layer.

[0053] In the first region, the first inclination angle with respect to the side surface and the upper surface of the core layer may be greater than the second inclination angle with respect to the side surface and the upper surface of the core layer in the second region.

[0054] In the first region, the side surface may include a first portion having a first curvature in a plane and spaced apart from each other.

[0055] In the first region, the side surfaces may have different curvatures in regions that face each other planarly along the stacking direction.

[0056] The above first parts can be connected to each other.

[0057] In the second region, the side surface may include a second portion having a second curvature in a plane and spaced apart from each other.

[0058] In the second region, the side surfaces may have different curvatures in regions that face each other planarly along the stacking direction.

[0059] The first electrode portion includes a first via electrode disposed in the via hole and a first wiring portion disposed on the upper surface and the lower surface, and the first via electrode can be disposed within the via hole.

[0060] The core layer may include a groove arranged in at least one of the upper surface, lower surface, and via hole of the core layer.

[0061] It may include a first insulating layer disposed on the buffer layer; a second insulating layer disposed under the buffer layer; a second electrode portion disposed on the first insulating layer; and a third electrode portion disposed on the second insulating layer.

[0062] The thickness of the core layer may be greater than the thickness of the buffer layer.

[0063] A circuit board according to an embodiment includes a core layer including glass; a buffer layer disposed on an upper surface and a lower surface of the core layer; a first electrode portion disposed on the core layer and the buffer layer; a via hole penetrating the core layer; and a connection buffer layer disposed within the via hole; wherein the buffer layer and the connection buffer layer include an inner via hole located inside the via hole; and an inclination angle of a side surface of the via hole with respect to an upper surface of the core layer is different from an inclination angle of a side surface of the inner via hole with respect to an upper surface of the core layer.

[0064] The above connection buffer layer can be connected to buffer layers disposed on the upper and lower surfaces of the core layer.

[0065] The first electrode portion includes a first via electrode disposed in the inner via hole and a first wiring portion disposed on the upper surface and the lower surface, and the first via electrode can be disposed in the inner via hole.

[0066] The above first via electrode can be in contact with the inner via hole.

[0067] The direction of expansion of the side surface of the inner via hole may be different from the direction of expansion of the side surface of the via hole.

[0068] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, in which warpage is suppressed and electrical characteristics are improved through a glass layer having high rigidity and a small coefficient of thermal expansion.

[0069] In addition, the embodiment can provide a circuit board with improved reliability and a semiconductor package including the same by forming a bonding layer with high adhesion on an insulating layer of glass.

[0070] In addition, the embodiment can provide a circuit board with improved structural reliability through a uniform bonding layer and a semiconductor package including the same.

[0071] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, in which the bonding strength between the electrode part and the insulating layer is further improved through a bonding layer including a home or hole.

[0072] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, which can structurally effectively disperse external pressure or thermal stress by having an area in which the inner surface of the through hole has a curvature.

[0073] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved structural reliability by improving stress relief by disposing a buffer layer on the upper and lower surfaces of the core layer.

[0074] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, in which mechanical reliability is improved and thermal stress is alleviated through a structure having different curvatures at opposite points.

[0075] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, in which electrical characteristics are improved and thermal deformation is effectively suppressed through a connection buffer layer and an inner via hole.

[0076] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved manufacturing ease and improved heat dissipation effect through a cavity penetrating at least a part of a core layer or a part of a buffer layer.

[0077] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0078] Figure 1 is a plan view of a circuit board according to an embodiment of the present invention;

[0079] Figure 2 is a drawing taken along line AA' in Figure 1,

[0080] Figure 3 is an enlarged view of part K in Figure 2,

[0081] Figure 4 is an enlarged view of K1 in Figure 2,

[0082] FIG. 5 is a plan view of a portion of a first insulating layer and a first via electrode in a circuit board according to an embodiment;

[0083] Figure 6 is an enlarged view of K2 in Figure 2,

[0084] Figure 7 is an enlarged view of K3 in Figure 2,

[0085] Fig. 8 is a cross-sectional view of a circuit board according to another embodiment;

[0086] Figure 9 is an enlarged view of K4 in Figure 8,

[0087] Figures 10 to 15 are drawings explaining a method for manufacturing a circuit board according to an embodiment.

[0088] Figure 16 is a drawing of another example taken along line AA' in Figure 1.

[0089] Figure 17 is an enlarged view of the K0 portion in Figure 16,

[0090] Figure 18 is an enlarged view of K5 in Figure 16,

[0091] Fig. 19 is a plan view of a portion of a first insulating layer and a first via electrode in a circuit board according to an embodiment;

[0092] Figure 20 is an enlarged view of K6 in Figure 16,

[0093] Fig. 21 is a modified example of Fig. 20,

[0094] Figure 22 is an enlarged view of K7 in Figure 16.

[0095] Figures 23 to 28 are drawings explaining a method for manufacturing a circuit board according to an embodiment.

[0096] Figure 29 is a photograph of the first insulating layer and the bonding layer.

[0097] Figure 30 is a drawing showing an XPS (X-ray Photoelectron Spectroscopy) spectrum from the surface of the first insulating layer and the bonding layer to a predetermined depth.

[0098] Fig. 31 is a cross-sectional view of a circuit board according to another embodiment;

[0099] Figure 32 is an enlarged view of K8 in Figure 31,

[0100] Figure 33 is another example drawing viewed along the line AA' in Figure 1.

[0101] Figure 34 is an enlarged view of the K9 portion in Figure 33,

[0102] Figure 35 is an enlarged view of K10 in Figure 33,

[0103] Figure 36 is an enlarged view of the M1 portion in Figure 35,

[0104] Figure 37 is an enlarged view of the M2 portion in Figure 35,

[0105] Fig. 38 is an enlarged view of part M3 in Fig. 35,

[0106] Fig. 39 is a cross-sectional view of a circuit board according to another embodiment;

[0107] Fig. 40 is a cross-sectional view of a circuit board according to another embodiment;

[0108] Fig. 41 is a cross-sectional view of a circuit board according to another embodiment;

[0109] Figure 42 is an enlarged view of part K11 in Figure 41,

[0110] Figures 43 to 48 are drawings explaining a method for manufacturing a circuit board according to an embodiment.

[0111] Figure 49 is a cross-sectional view of a circuit board according to another embodiment of the present invention.

[0112] Figure 50 is a drawing for K12 in Figure 49,

[0113] FIG. 51 is a plan view of a via hole and a first via electrode in a circuit board according to another embodiment;

[0114] FIG. 52(a) and FIG. 52(b) are plan views at different locations on the outer area of ​​a via hole in a circuit board according to another embodiment;

[0115] FIG. 53(a), FIG. 53(b) and FIG. 53(c) are plan views at different locations of the inner area of ​​a via hole in a circuit board according to another embodiment;

[0116] Fig. 54 is a plan view photograph of a via hole in a circuit board according to another embodiment;

[0117] Fig. 55 is a cross-sectional photograph of a via hole in a circuit board according to another embodiment;

[0118] Fig. 56a is a partial photograph on the plane in II' of Fig. 50,

[0119] Fig. 56b is a partial photograph on the plane at BB' in Fig. 50,

[0120] Fig. 56c is a partial photograph on the plane from CC' in Fig. 50,

[0121] Fig. 57 is a cross-sectional view of a circuit board according to a modified example,

[0122] Fig. 58 is a plan view of a via hole and a first via electrode in the circuit board of Fig. 57.

[0123] FIG. 59 is a cross-sectional view of a circuit board according to another embodiment of the present invention;

[0124] Figure 60 is an enlarged view of K13 in Figure 59,

[0125] Figure 61 is a plan view of the inner via hole, via hole, and first via electrode of the circuit board in Figure 59.

[0126] Figures 62 to 67 are drawings explaining a method for manufacturing a circuit board according to another embodiment of the present invention.

[0127] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0128] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0129] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0130] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0131] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0132] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0133] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as a "first component," and similarly, a first component may also be referred to as a "second component." The terms "and / or" include a combination of multiple related items described herein or any of multiple related items described herein. These terms are only used to distinguish the component from other components and are not limited by the nature, order, or sequence of the component.

[0134] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0135] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0136] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0137] Additionally, the expression that configuration A is positioned between configurations B and C should also include the meaning that configuration A is positioned so that it overlaps configurations B and C at least partially in the horizontal and / or vertical directions.

[0138] Expressions referring to directions include horizontal directions, vertical directions, and include a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as a first horizontal direction (X-axis), a second horizontal direction (Y-axis), and a vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of overlapping along the horizontal direction should also include the meaning of overlapping along the first horizontal direction and / or overlapping along the second horizontal direction.

[0139] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0140] Furthermore, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood only as being in "direct contact" with a component B, it is described as being in "direct contact."

[0141] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0142] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0143] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. Various connecting members (e.g., semiconductor elements) may be mounted on the semiconductor package.

[0144] A connecting member can connect different dies (e.g., a central processor (CPU), a graphics processor (GPU), a digital signal processor, an application processor (AP), etc.). The connecting member can be disposed within an interposer or a package substrate. The connecting member can include active components and / or passive components. The active components can be semiconductor chips in the form of integrated circuits (ICs) in which hundreds to millions of components are integrated into a single chip. The connecting member can be a logic chip, a memory chip, etc. The logic chip can be a central processor (CPU), a graphics processor (GPU), etc. For example, the logic chip can be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a chip set including a specific combination of the foregoing.

[0145] The memory chip may be a stacked memory such as HBM. Furthermore, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory. A semiconductor element (not shown) may be electrically connected to the electrode portion through the conductive member described above.

[0146] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0147] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0148] In the circuit board according to the embodiment of the present invention, the insulating layer may be formed of a plurality of insulating layers. The insulating layer may include a first insulating layer (a glass layer described below) and an insulating layer.

[0149] In particular, as the integration density of semiconductor devices increases and multi-pin and miniaturization are promoted, a circuit board according to an embodiment, on which a semiconductor device having an increased number of pins and miniaturization is mounted, may be a multilayer printed circuit board using a built-up method. For example, the circuit board may be a multilayer circuit board having a build-up layer formed on the surface and back surface of a first insulating layer.

[0150] In such multilayer circuit boards, the first insulating layer is, as described above, a resin substrate (e.g., a glass epoxy substrate) in which reinforcing fibers are impregnated with resin. Furthermore, by utilizing the rigidity of the core substrate, a plurality of build-up layers can be formed by alternately laminating resin insulating layers and conductor layers on the front and back surfaces of the core substrate. Accordingly, the insulating layer (110) can correspond to a "build-up layer."

[0151] The build-up layer serves as an internal insulating layer of a circuit board on which circuit patterns, etc. are formed, and an insulating material is used as the forming material. As the insulating material, as described below, a thermosetting resin and / or a photocurable resin may be used, and an Ajinomoto build-up film may also be used, but is not particularly limited thereto.

[0152] Additionally, when forming dummy grooves and / or via holes in the build-up layer, laser processing and / or photolithography may be used depending on the insulating material.

[0153] Alternatively, a material with a high modulus can be used as the insulating material, and in addition, a material with a small curing shrinkage itself can be used, or an anisotropic material with a dominant vertical shrinkage can be used.

[0154] These build-up layers may be multiple layers and may be formed using the same materials or may be formed using different materials.

[0155] FIG. 1 is a plan view of a circuit board according to an embodiment of the present invention, FIG. 2 is a view taken along line AA' in FIG. 1, FIG. 3 is an enlarged view of a portion K in FIG. 2, FIG. 4 is an enlarged view of K1 in FIG. 2, FIG. 5 is a plan view of a portion of a first insulating layer and a first via electrode in a circuit board according to an embodiment, FIG. 6 is an enlarged view of K2 in FIG. 2, and FIG. 7 is an enlarged view of K3 in FIG. 2.

[0156] Referring to FIGS. 1 and 2, a circuit board (100) according to an embodiment may include an insulating layer (110), an electrode portion (120), and a bonding layer (AL). The circuit board (100) may include a protective layer (130). In addition, the circuit board (100) according to an embodiment may include a semiconductor element (SD) and a conductive member (CB1, CB2) positioned on one side (e.g., an upper side). There may be a plurality of chips such as the semiconductor element (SD).

[0157] The first insulating layer (111) may be a 'core layer' or a 'substrate layer'. The first insulating layer (111) can suppress warpage that occurs due to thinning of the circuit board. In other words, warpage can be reduced by placing a glass layer (or glass core) with high rigidity and a low coefficient of thermal expansion (CTE) at the center or core of the circuit board. For example, the first insulating layer (111) may have high rigidity and a low coefficient of thermal expansion compared to other insulating layers or protective layers.

[0158] And the first insulating layer (111) can be made of a glass material. For example, the first insulating layer (111) can include pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, alumino-silicate glass, etc., and is not limited to silicon-based glass compositions, and alternative glass materials, such as fluorine glass, phosphate glass, chalcogen glass, etc., can also be used. In addition, the first insulating layer (111) can further include other additives to form glass having specific physical properties. These additives can include not only calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), but also magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of these elements and other elements. In addition, the first insulating layer (111) can include an insulating material.

[0159] In addition, the first insulating layer (111) may be arranged at the center of the insulating layer (110). In addition, the first insulating layer (111) may include a first through hole (111h) as described below. The first through hole (111h) may have various shapes and be formed at various locations, different from the number and structure illustrated in the drawing.

[0160] And the insulating layer (110) may include an insulating layer other than the first insulating layer (111). For example, the insulating layer (110) may include a second insulating layer (112) and a third insulating layer (113). The second insulating layer (112) and the third insulating layer (113) may be made of an insulating material.

[0161] And the second insulating layer (112) and the third insulating layer (113) may be positioned above and below the first insulating layer (111), respectively. For example, the second insulating layer (112) may be positioned above the first insulating layer (111). And the third insulating layer (113) may be positioned below the first insulating layer (111). For example, the second insulating layer (112) may be in contact with the upper surface of the first insulating layer (111). And the third insulating layer (113) may be in contact with the lower surface or bottom surface of the first insulating layer (111).

[0162] And in the embodiment, the second insulating layer (112) and / or the third insulating layer (113) may be formed of multiple insulating layers. The multiple insulating layers may be formed of the same insulating material or different insulating materials. For example, the second insulating layer (112) may be formed of multiple layers according to the structure or design of the circuit board (100) as described above. For example, the second insulating layer (112) may be formed of multiple insulating layers. And the third insulating layer (113) may be formed of multiple insulating layers.

[0163] Additionally, a plurality of circuit patterns, via holes, etc. may be positioned in the second insulating layer (112) and / or the third insulating layer (113). For example, the via hole of the second insulating layer (112) and / or the third insulating layer (113) may be connected to the first through hole (111h) of the first insulating layer (111). In other words, the via electrode positioned in the via hole of the second insulating layer (112) may be electrically connected to the via electrode positioned in the first through hole (111h) of the first insulating layer (111).

[0164] The second insulating layer (112) and / or the third insulating layer (113) may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. In addition, the second insulating layer (112) and / or the third insulating layer (113) may further include a reinforcing material in the resin. The reinforcing material may be, for example, a fabric reinforcing material, an inorganic filler, etc. The fabric reinforcing material may be glass fiber, and the glass fiber may be impregnated into the resin to form a prepreg (PPG).

[0165] For example, the second insulating layer (112) and / or the third insulating layer (113) may be formed of any insulating resin, such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., may be used, and a material such as prepreg (PPG) containing glass fiber may be used. As the photocurable resin, any insulating resin, such as PID (Photo Imageable Dielectric) resin, may be used. The above-described arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material formed of glass fiber or aramid fiber. For example, the second insulating layer (112) may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., as an example, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the second insulating layer (112) and / or the third insulating layer (113) may include a plurality of layers composed of ABF.

[0166] In an embodiment, the electrode portion (120) may be arranged for electrical connection between a main board, etc. and a chip (or semiconductor device (SD), die). In addition, the electrode portion (120) may include a circuit pattern (or circuit pattern layer), a pad, and a via electrode. Here, the electrode portion (120) includes a wiring portion, and the wiring portion may include the aforementioned pad and circuit pattern.

[0167] In the electrode portion (120), the circuit pattern can be designed in various forms for transmitting signals and / or power to the semiconductor element and can be placed on the laminated insulating layer.

[0168] In the electrode section (120), via electrodes are arranged to penetrate a portion of each insulating layer for vertical connection between each vertically stacked insulating layer and the circuit patterns arranged on the insulating layers. That is, the insulating layer may include a via hole for arrangement of the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and may be freely designed.

[0169] In the electrode portion (120), pads may be placed on each insulating layer. The pads may be electrically connected to circuit patterns. In addition, the pads may be electrically connected to semiconductor elements and / or main boards or substrates. In addition, the pads may be electrically connected to via electrodes.

[0170] The electrode portion (120) may include a first electrode portion (121), a second electrode portion (122), and a third electrode portion (123). The first electrode portion (121) to the third electrode portion (123) may function as a circuit connected to a semiconductor element.

[0171] The first electrode portion (121) may be located in the first insulating layer (111). The second electrode portion (122) may be located in the second insulating layer (112). The third electrode portion (123) may be located in the third insulating layer (113).

[0172] The first electrode portion (121) may include a first via electrode (121a) and a first wiring portion (121b). The first via electrode (121a) may be positioned in a first through hole (111h) of the first insulating layer (111). The via (Vertical Interconnect Access, VIA) electrode penetrates the insulating layer to perform electrical connection in a vertical direction or a stacking direction. The first wiring portion (121b) may be arranged on the upper and lower surfaces of the first insulating layer (111).

[0173] The second electrode portion (122) may include a second via electrode (122a) and a second wiring portion (122b). The second via electrode (122a) may be positioned in a through hole penetrating the second insulating layer (112). The second wiring portion (122b) may be positioned on one surface (e.g., the upper surface) of the second insulating layer (112).

[0174] The third electrode portion (123) may include a third via electrode (123a) and a third wiring portion (123b). The third via electrode (123a) may be positioned in a through hole penetrating the third insulating layer (113). The third wiring portion (123b) may be positioned on one surface (e.g., the lower surface) of the third insulating layer (113).

[0175] In particular, pads positioned on the outer side of the pads can be bonded to semiconductor elements, substrates, boards, etc. using solder, wires, conductive adhesives, etc., and may be positioned with a width greater than the width of the circuit pattern to solve problems such as securing yield. However, this is not limited to this, and may have a width equal to the width of the circuit pattern depending on the technical limitations of the bonding process.

[0176] And the pads arranged on the inside have the function of connecting the via electrodes and the circuit patterns. When the via electrodes are arranged with a wider width than the circuit patterns, pads having a wider width than the circuit patterns are provided for positional alignment during the manufacturing process of the via electrodes to be arranged on each circuit pattern. Therefore, each via electrode may have an upper surface that is positioned on the same plane as the lower surface of the upper pad that is in direct contact with the via electrode, and a lower surface that is positioned on the same plane as the upper surface of the lower pad that is in direct contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean flat surfaces, and it should be understood that even concave or convex surfaces that may appear depending on various processes may be present.

[0177] The protective layer (130) may be positioned on top or bottom of the second insulating layer (112) and / or the third insulating layer (113). For example, the protective layer (130) may include a first protective layer (131) positioned on top of the second insulating layer (112) and a second protective layer (132) positioned on bottom of the third insulating layer (113).

[0178] The protective layer (130) can have the function of protecting the pad from external moisture or contaminants, and to prevent short circuit problems caused by the occurrence of solder bridges, etc. during solder bonding between the semiconductor element and / or the main board and the circuit board, the protective layer (130) may be provided with a solder resist that does not have good solder and wettability, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals may be arranged at a high density. When the plurality of terminals and the pads of the circuit board are joined, solder may be used, for example. When solder is used, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist that does not have good solder and wettability may be arranged to solve this short circuit problem. In addition, the protective layer (130) may be formed of a material that has insulating properties for electrical connection. The protective layer (130) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the third insulating layer (not shown) may include any one of a photo solder resist layer, a cover-lay, and a polymer material.

[0179] And the insulating layer or protective layer (130) located in the outer laminated area of ​​the circuit board may have an opening. Through the opening, it may be electrically connected to other semiconductor elements, circuit boards, etc.

[0180] For the electrical connection described above, conductive members (CB1, CB2) may be positioned on the upper or lower portion of the circuit board (100). The conductive member (CB1) positioned on the upper portion may perform electrical connection with the semiconductor element (SD) and the electrode portion (120). In addition, the conductive member (CB2) positioned on the lower portion may perform electrical connection with another substrate, etc.

[0181] The bonding layer (AL) may be positioned on the first insulating layer (111). The bonding layer (AL) may be positioned on the entire area of ​​the first insulating layer (111) or the entire surface except for the side surfaces. The bonding layer (AL) may cover the first insulating layer (111). For example, the bonding layer (AL) may be positioned on the upper surface (US), the lower surface (BS) of the first insulating layer (111), and the inner wall (IS) of the through hole (111h).

[0182] The bonding layer (AL) may be made of a material that improves bonding strength between the first insulating layer (111), the electrode portion (120), and the other insulating layers (112, 113). For example, the bonding layer (AL) may include a metal oxide. For example, the bonding layer (AL) may be SnO. 2, It may include ZnO, 2MoO3, etc. The bonding layer (AL) may be a coating layer. As a result, the bonding strength of other insulating layers or electrode portions to the first insulating layer (111) made of glass is improved, thereby providing a circuit board with improved reliability. In particular, the bonding strength between the electrode portion and the first insulating layer (111) can be significantly improved by the bonding layer (AL). A detailed description thereof will be provided later.

[0183] The semiconductor device (SD) may be mounted on the upper portion of the circuit board (100). The semiconductor device (SD) may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an AP including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set including a specific combination of those listed so far. And the memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory. The semiconductor device (SD) may be electrically connected to the electrode unit (120) through the conductive member (CB2) described above.

[0184] Furthermore, the circuit board illustrated may be a BGA board. However, the circuit board and package board described in the embodiments are not limited to such BGAs. For example, the circuit board and package board described in the embodiments may be applied to various circuit boards (bridge boards, packages, interposers, etc.) in which a bonding layer is disposed on a first insulating layer, which is a glass layer.

[0185] Circuit boards can be divided into package boards and interposers based on their function. The package board serves the function of mounting semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, to improve the yield of circuit boards with a high number of layers, the yield of the circuit board can be improved by separating them into an interposer and a package board. In addition, as the terminal density of semiconductor devices increases, it can be difficult to implement pads on the package board with an area corresponding to the terminals of the semiconductor devices. Therefore, the pad size of the package board can act as a buffer between the size of the pad and the fine pattern size of the terminals of the semiconductor devices.

[0186] The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In an embodiment according to the present invention, a circuit substrate having a first insulating layer including glass is described.

[0187] In addition, as described above, for example, a bonding layer (AL) may be positioned on the outermost surface (OS) of the first insulating layer (111). The bonding layer (AL) may be positioned on at least one of the plurality of outermost surfaces (OS) of the first insulating layer (111). When manufacturing a circuit board, the bonding layer (AL) positioned on the outermost surface (OS) of the first insulating layer (111) may be removed during dicing, or a portion of the bonding layer (AL) may remain. When the bonding layer (AL) remains, the bonding layer (AL) may be present by being removed up to a portion of the area. Accordingly, the thickness of the bonding layer (AL) on the outermost surface (OS) may be less than or equal to the thickness of the bonding layer (AL) on the upper surface (US), the lower surface (BS), and the inner wall (IS) of the through hole other than the outermost surface (OS).

[0188] Referring further to FIGS. 3 and 4, the first insulating layer (111) according to the embodiment may include a bottom surface (BS) and an upper surface (US). The bottom surface (BS) and the upper surface (US) may be outer surfaces facing each other in the lamination direction or the vertical direction in the first insulating layer (111).

[0189] In an embodiment, the second insulating layer (112) may be positioned on the first insulating layer (111) based on the vertical direction or the stacking direction (Z-axis direction). And the second insulating layer (112) may be adjacent to the first insulating layer (111). That is, the bottom surface of the second insulating layer (112) may be adjacent to the top surface (US) of the first insulating layer (111). And the third insulating layer (113) may be adjacent to the bottom surface (BS) of the first insulating layer (111). In a state where the bonding layer (AL) is removed, the top surface (US) of the first insulating layer (111) may face the bottom surface of the second insulating layer (112), and the bottom surface (BS) of the first insulating layer (111) may face the top surface of the third insulating layer (113).

[0190] The first insulating layer (111) may be a ‘glass layer’, a ‘glass core’, or a ‘glass insulating layer’ as described above, and may be made of glass material.

[0191] As an example, the first insulating layer (111) may include a first through hole (111h). The first insulating layer (111) may include a first through hole (111h). The first through hole (111h) may penetrate the upper surface (US) and the lower surface (BS) (or the lower surface) of the first insulating layer (111). For example, the first through hole (111h) may penetrate the upper surface (US) and the lower surface (BS) of the first insulating layer (111).

[0192] The first through hole (111h) may have a structure in which the diameter or width (W) increases from the center toward the upper surface and the lower surface (bottom surface) of the first insulating layer (111). For example, the diameter of the first through hole (111h) may increase from the center of the first insulating layer (111) toward the upper surface (US) and the lower surface (BS) within the first insulating layer (111). Accordingly, the inner wall (or inner wall or inner side wall) (IS) of the first through hole (111h) may be inclined with respect to the upper surface (US) and the lower surface (BS).

[0193] Furthermore, there may be a plurality of first insulating layers (111). In addition, there may also be a plurality of first through-holes (111h) in the first insulating layer (111). For example, when a plurality of first insulating layers (111) exist, each of the first insulating layers (111) may overlap or may not partially overlap in the stacking direction. For example, the central axis (AX) of the first through-hole (111h) of one first insulating layer may be misaligned with the central axis of the via-hole of another first insulating layer or may overlap.

[0194] The point at which the diameter of the first through hole (111h) increases from the minimum may be the center or a region other than the center. In an embodiment, the diameter of the first through hole (111h) may increase from the center toward the bottom surface (BS). The diameter of the first through hole (111h) may increase from the center toward the top surface (US). That is, in an embodiment, the diameter may increase toward the surface where adjacent via holes contact each other. For example, the first through hole (111h) may have a diameter expansion direction that changes at the center of the first insulating layer (111). Alternatively, the diameter expansion direction of the first through hole (111h) may be a direction from the center toward the top surface of the first insulating layer (111) and a direction from the center toward the bottom surface.

[0195] The bonding layer (AL) may be positioned on the upper surface (US) and the lower surface (BS) of the first insulating layer (111). In addition, the bonding layer (AL) may be disposed on the inner wall of the first through hole (111h). In an embodiment, the bonding layer (AL) may be positioned between the second insulating layer (112) and the first insulating layer (111) or between the first electrode portion (121) and the first insulating layer (111). Specifically, at least a portion of the bonding layer (AL) may overlap the first wiring portion (121b) of the first electrode portion (121) in the vertical direction (Z-axis direction). In addition, a portion of the bonding layer (AL) may not overlap the first wiring portion (121b) of the first electrode portion (121) in the vertical direction (Z-axis direction). A portion of the bonding layer (AL) may be in contact with the second insulating layer (112) or the third insulating layer (113).

[0196] Specifically, the bonding layer (AL) can be divided into a region in contact with the electrode portion and a region in contact with an insulating layer (112, 113) other than the first insulating layer (111). In an embodiment, the bonding layer (AL) can include a first region (AR1) in contact with the second insulating layer (112) and a second region (AR2) other than the first region (AR1).

[0197] On the first insulating layer (111), the first region (AR1) may be in contact with the second insulating layer (112), and the second region (AR2) may be in contact with the first electrode portion (121). The first region (AR1) may overlap with the second insulating layer (112) in the vertical direction. The second region (AR2) may overlap with the first electrode portion (121) in the vertical direction.

[0198] In addition, the bonding layer (AL) according to the embodiment may include a salt (SA) composed of Na. The salt (SA) may be generated by a heat treatment process. As described below, the bonding layer (AL) may be generated by heat treating a surfactant and a metal precursor. For example, the surface of the first insulating layer (111) may be modified with sodium dodecyl sulfate (SDS), and the bonding layer (AL), which is a metal oxide, may be coated on the surface of the first insulating layer (111). At this time, the thickness of the bonding layer (AL) may be controlled by adjusting the acidity (pH) through the surfactant. That is, the content of the metal oxide coated on the first insulating layer (111) may be controlled. Specifically, sodium lauryl sulfate is one of the surfactants having a hydrophilic part and a hydrophobic part, and when sodium lauryl sulfate is dissolved in deionized water, it can be dissociated into C12H25SO4- and Na+. Here, the hydrophobic carbon chain portion may be adsorbed on the surface of the first insulating layer, and the hydrophilic portion -SO4- may be exposed to the outside. At this time, the -SO4- portion can easily adsorb metal ions such as tin ions. Accordingly, the amount of metal ions adsorbed can be increased and the amount of metal oxide particle coating on the surface can be increased by controlling the amount of surfactant. Furthermore, during the heat treatment process of forming the bonding layer, which is a metal oxide, a salt may be generated by the bonding between the metal and chloride (Cl), and the salt (SA) may be located on the surface or inside the bonding layer (AL). A detailed process for this will be described later. As an example, the salt may include Na (ion). In addition, the salt may include chloride (ion).

[0199] And the salt (SA) may be present in a large proportion in the first region (AR1) compared to the second region (AR2). For example, based on the same area or volume, the salt (SA) may be present in a larger proportion in the second region (AR2) compared to the first region (AR1). As described above, by controlling the amount of surfactant, etc. for each region, the salt (SA) may be present differently for each region. By this configuration, the reduction in bonding strength between the second insulating layer (112) and the first insulating layer (111) can be prevented.

[0200] In an embodiment, the bonding layer (AL) may have the same or different thicknesses. As described above, when the surfactant is formed differently in each region, the bonding layer (AL) may have a different thickness depending on the region.

[0201] In an embodiment, the bonding layer (AL) may have a thickness (d1) on the upper surface (US) or the lower surface (BS) of the first insulating layer (111) that is the same as the thickness (d2) on the inner wall (IS) of the first through-hole (111h). For example, the bonding layer (AL) may have a thickness (d1) on the upper surface (US) or the lower surface (BS) of the first insulating layer (111) that is the same as the thickness (d2) on the inner wall (IS) of the first through-hole (111h). This configuration provides a uniform bonding layer and prevents peeling or delamination from occurring during the formation of the first electrode portion by sputtering or the like, even within the through-hole (111h).

[0202] And, within the first through hole (111h), the bonding layer (AL) can be maintained as the thickness moves toward the center. For example, within the first through hole (111h), the bonding layer (AL) can be maintained as the thickness moves toward the center. That is, the thickness (d2) of the bonding layer in the region adjacent to the upper surface (US) or the lower surface (BS) can be the same as the thickness (d2) adjacent to the center of the first through hole (111h). In this case, the salt (SA) can exist in greater numbers in the region adjacent to the center of the first through hole (111h) compared to the region adjacent to the upper surface (US) or the lower surface (BS).

[0203] In addition, the bonding layer (AL) can be formed with the same thickness within the first through hole (111h) based on the central axis (AX) of the first through hole (111h). Accordingly, the same bonding force can be provided based on the central axis between the first insulating layer (111) and the first via electrode (121a), thereby suppressing structural imbalance.

[0204] Referring further to FIGS. 5 and 6, in the circuit board according to the embodiment, the bonding layer (AL) may be applied to the entire upper surface (US) of the first insulating layer (111). FIG. 5 is a plan view taken along the upper surface (US) of the first insulating layer (111). As shown in the drawing, the bonding layer (AL) may have a ring shape on the plane inside the first through hole (111h). Furthermore, the bonding layer (AL) may include a groove structure (GV) due to at least a portion of the salt formed on the upper surface being removed. Accordingly, the bonding layer (AL) may include an uneven structure on the upper surface at least in a portion thereof. As a result, the bonding area of ​​the bonding layer (AL) with the first electrode portion may be improved. Similarly, the bonding area of ​​the bonding layer (AL) with the second insulating layer (112) may also be improved. Accordingly, the bonding layer (AL) can further improve the bonding strength between the first insulating layer (111) and the second insulating layer (112) (first electrode portion).

[0205] Referring further to Fig. 7, the bonding layer (AL) can be applied equally to the lower surface (BS) of the first insulating layer (111). Accordingly, the bonding layer (AL) can include a first region in contact with the third insulating layer (113) and a second region in contact with the first electrode portion on the lower surface (BS) of the first insulating layer (111). In addition, the bonding layer (AL) can include salt located on the surface or inside. The salt can be present in different ratios in each region. As a result, the bonding area between each component and the bonding layer (AL) increases, and the bonding strength can be improved.

[0206] FIG. 8 is a cross-sectional view of a circuit board according to another embodiment, and FIG. 9 is an enlarged view of K4 in FIG. 8.

[0207] A circuit board according to another embodiment may include an insulating layer (110), an electrode portion (120), and a bonding layer (AL). The circuit board (100) may include a protective layer (130). In addition, the circuit board (100) according to the embodiment may include a semiconductor element (SD) and conductive members (CB1, CB2) positioned on one side (e.g., an upper side). There may be a plurality of chips such as the semiconductor element (SD). The above-described contents may be equally applied, except for the contents described below.

[0208] The bonding layer (AL) may be positioned on the inner surface (IS) of the first through hole (111h). And the bonding layer (AL) may be positioned between the first wiring portion (121b) and the upper surface (US) of the first insulating layer (111). Accordingly, the bonding layer (AL) may be in contact with the first wiring portion (121b) and the upper surface of the first insulating layer (111). In addition, the bonding layer (AL) may overlap with the first electrode portion (121) in the lamination direction (Z-axis direction). And the bonding layer (AL) may not exist between the spaced-apart first wiring portions (121b). That is, the bonding layer (AL) may be positioned only in a region disposed below the first wiring portion (121b) on the upper surface (US) of the first insulating layer (111), and may not be positioned in a region that does not overlap with the first wiring portion (121b) in the lamination direction. Accordingly, the upper surface (US) of the first insulating layer (111) may be in contact with the second insulating layer (112) in some areas. At this time, the area where the first insulating layer (111) and the second insulating layer (112) are in contact may be misaligned in the vertical direction with respect to the first wiring portion (121b) located on the upper portion (or upper surface) of the first insulating layer (111). That is, the area where the first insulating layer (111) and the second insulating layer (112) are in contact may not vertically overlap with the first wiring portion (121b). In addition, the lower surface (BS) of the first insulating layer (111) may be in contact with the third insulating layer (113) in some areas. Similarly, the area where the first insulating layer (111) and the third insulating layer (113) are in contact may be misaligned in the vertical direction with respect to the first wiring portion (121b) located on the lower portion (or lower surface) of the first insulating layer. That is, the area where the first insulating layer (111) and the second insulating layer (112) come into contact may not overlap in the vertical direction with the first wiring portion (121b).

[0209] The bonding layer (AL) positioned below the first wiring portion (121b) may have a side in contact with the second insulating layer (112). For example, the aforementioned salt (SA) may be positioned on the side of the bonding layer (AL). In addition, a portion of the salt (SA) may be exposed on the side of the bonding layer (AL). The exposed salt (SA) may be in contact with the second insulating layer (112).

[0210] In this way, the second insulating layer (112) can cover the bonding layer (AL) and the first wiring portion (121a). With this configuration, peeling of the bonding layer (AL) and the like can be easily suppressed. Accordingly, the structural reliability of the circuit board can be improved.

[0211] In addition, as described above, a groove structure may be formed by removing at least a portion of the salt (SA) formed on the side of the bonding layer (AL). Accordingly, a portion of the side of the bonding layer (AL) may have a rough structure. As a result, the bonding area of ​​the bonding layer (AL) and the second insulating layer (112) may be improved. Accordingly, the bonding layer (AL) may further improve the bonding strength between the second insulating layer (112).

[0212] These contents can be equally applied to the third insulating layer (113), the first insulating layer (111) and the bonding layer (AL) below.

[0213] Figures 10 to 15 are drawings explaining a method for manufacturing a circuit board according to an embodiment.

[0214] The same components described above are given the same drawing reference numerals, and duplicate descriptions of the same components are omitted, with only the differences described.

[0215] Additionally, the circuit board according to the embodiment may correspond to a unit circuit board. That is, during the manufacturing process, the mother circuit board may be composed of multiple unit circuit boards. The mother circuit board may be separated into multiple unit circuit boards along a sawing line. To form such a mother circuit board, a glass layer may be first placed. The following description will focus on the manufacturing of the unit circuit board.

[0216] A method for manufacturing a circuit board according to an embodiment may include a step of providing a first insulating layer, a step of forming a first through hole in the first insulating layer, a step of forming a bonding layer on an upper surface and a lower surface of the first insulating layer and an inner surface of the first through hole, a step of forming a seed layer, a step of forming a first via electrode through plating and etching, a step of forming a second insulating layer and a third insulating layer, a step of forming a second electrode portion and a third electrode portion, and a step of forming a protective layer and a pad, etc.

[0217] Referring to Fig. 10, a method for manufacturing a first insulating layer (or core substrate) in a circuit board according to an embodiment may first provide a first insulating layer (111) made of glass. The first insulating layer (111) may correspond to the first insulating layer or core layer described above.

[0218] Referring to Fig. 11, a first through hole (111h) can be formed in the first insulating layer (111). The first through hole (111h) can correspond to the via hole described above. The first through hole (111h) can be formed by performing etching on both sides of the first insulating layer (111). For example, a via electrode can be formed in a via hole or a through hole of a glass layer. For example, the first through hole (111h) can be formed by a photolithography process using a photomask or various etching methods such as a laser method.

[0219] Referring to Fig. 12, a bonding layer (AL) can be formed on one surface (upper surface or lower surface) of the first insulating layer (111). For example, the bonding layer (AL) can be formed on the upper surface (US), the lower surface (BS) of the first insulating layer (111) and the inner wall of the first through hole (111h). For example, the formation of the bonding layer can be applied by a dry method (e.g., sputtering), wet method, etc. In particular, spin coating, diffusion coating, spray coating, dip coating, etc., or CVD, ALD, etc. can be applied here. For example, the bonding layer (AL) can be formed by glass dipping.

[0220] Specifically, the bonding layer can be formed through a solution manufacturing process, a glass dipping process, a heat treatment process, and a washing process.

[0221] In the solution manufacturing process, water, a metal precursor, and a surfactant can be prepared. For example, the water can include high-purity deionized water, etc. As described above, various chlorides can be used as the metal precursor. Accordingly, metal chlorides of various metals can be coated. Hereinafter, tin (Sn) is described as a metal. Tin chloride, which is a metal precursor, is dissolved in water, and a surfactant (SDS) can also be added to the solution to dissolve it. At this time, the surfactant is dissolved in water, and sodium ions (Na + ) and dodecyl sulfate ion (C12H25SO4 - ) can be dissociated into dodecyl sulfate ion (C12H25SO4 - ) is a tin ion (Sn 2+ ) can be combined to form a complex.

[0222] And the solution can be dipped into the first insulating layer (111), which is a glass substrate. The first insulating layer (111) can also be washed before dipping.

[0223] And by performing heat treatment, a bonding layer of metal oxide can be formed on the first insulating layer. For example, the heat treatment can be performed at 300°C or higher. During the heat treatment, metal ions can be oxidized to form metal oxides. For example, tin ions can be oxidized to form tin oxides. And the surfactant can be removed through thermal decomposition into the first portion (P1) of water, carbon dioxide, etc. Furthermore, the second portion (P2), which is a sulfate group, can be discharged as sulfuric acid gas or sulfur trioxide, etc. by heat treatment. Some sulfur (S) may remain. And in the third portion (P3), sodium ions can combine with chloride ions to form sodium chloride as a salt. Furthermore, some sodium may also remain.

[0224] And by performing a washing process, residual salts and the like can be removed. Afterwards, by sufficient drying and the like, residual salts can be minimized.

[0225] Referring to Fig. 13, a seed electrode layer or seed layer (SE) can be formed on the bonding layer (AL). The seed layer (SE) can be formed on the bonding layer (AL) by various methods. For example, the seed layer (SE) can be formed on the bonding layer (AL) by sputtering. Sputtering is a technology that causes an inert element such as argon to collide with a target (metal plate) to expel metal molecules and then attach a film to the surface. When a direct current is applied to the target while flowing an inert gas as a sputtering gas in a vacuum chamber, plasma can be generated between the substrate to be deposited and the target. In addition, the inert gas can be ionized into positive ions by a high-power direct current field within this plasma. At this time, the positive ions of the inert gas can be accelerated to the cathode by the direct current field and collide with the surface of the target. In this way, target materials that collide with the surface of a target can be ejected from the surface by exchanging momentum through perfectly elastic collisions between atoms. When ions collide with kinetic energy greater than the interatomic binding energy of the material, the ion impact pushes the atoms between the lattices of the material to a different location, resulting in the escape of atoms from the surface. This phenomenon is called sputtering.

[0226] Accordingly, by performing sputtering on a metal plate made of the metal material to be plated, a thin and uniform metal film can be formed by adhering to the metal atom bonding layer (AL) protruding from the metal plate. Examples of metal materials include Ni, Cr, Cu, and Ti.

[0227] Referring to Fig. 14, an electrode portion (EE) can be formed by various plating methods such as electroplating or chemical plating. In addition, a first electrode portion consisting of a via electrode and a wiring portion can be formed by mask formation, etching, etc.

[0228] Referring further to Fig. 15, after the first electrode portion (121) is formed on the first insulating layer (111), a second insulating layer (112), a third insulating layer (113), etc. may be further formed. Similarly, a through hole may be formed in each insulating layer, and a second electrode portion, a third electrode portion, etc. may be formed in each insulating layer. The wiring portion of each electrode portion may be formed by a manufacturing process of a printed circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), or a semi-additive process (SAP).

[0229] Additionally, a protective layer may be formed on top or bottom of the insulating layer. Additionally, an opening area for a conductive member may be formed in the protective layer.

[0230] FIG. 16 is a drawing of another example taken along line AA' in FIG. 1, FIG. 17 is an enlarged view of a portion K0 in FIG. 16, FIG. 18 is an enlarged view of K5 in FIG. 16, FIG. 19 is a plan view of a portion of a first insulating layer and a first via electrode in a circuit board according to an embodiment, FIG. 20 is an enlarged view of K6 in FIG. 16, FIG. 21 is a modified example of FIG. 20, and FIG. 22 is an enlarged view of K7 in FIG. 16.

[0231] Referring to FIGS. 16 to 18, the contents described in other embodiments can be applied equally except for the contents described below.

[0232] The bonding layer (AL) may be formed of a material that improves bonding strength between the first insulating layer (111), the electrode portion (120), and the other insulating layers (112, 113). For example, the bonding layer (AL) may include polysilazane or parylene. Furthermore, the bonding layer (AL) may include an internal metal oxide layer. The metal oxide layer may be in contact with the other insulating layer and the electrode portion. The metal oxide layer may include an insulating material such as ZnO2 or TiO2. As a result, the bonding strength of the other insulating layer or the electrode portion to the first insulating layer (111) made of glass is improved, thereby providing a circuit board with improved reliability.

[0233] The bonding layer (AL) may have the same or different thicknesses. For example, the bonding layer (AL) may have a different thickness depending on the region. For example, the bonding layer (AL) may have a thickness (d1) on the upper surface (US) or the lower surface (BS) of the first insulating layer (111) that is different from the thickness (d2) on the inner surface (IS) of the first through hole (111h). For example, the bonding layer (AL) may have a thickness (d1) greater than the thickness (d2) on the inner surface (IS) of the first through hole (111h) on the upper surface (US) or the lower surface (BS) of the first insulating layer (111). In addition, the bonding layer (AL) may have a thickness (d1) different from the thickness (d2) on the inner surface (IS) of the first through hole (11h) in a region where it comes into contact with the second insulating layer (112) or the third insulating layer (113) on the inner surface (IS) of the first through hole (11h). This configuration can be realized by the fact that the liquid-state bonding layer has high flowability when dipping-coated on an inclined surface and low flowability on a flat surface. By this configuration, the bonding strength of the bonding layer (AL) can be increased in the area where the interface between each component is concentrated. In addition, the inner surface (IS) of the first through hole (11h) can be referred to as an "inner wall," "inner side wall," "side wall," etc.

[0234] And, within the first through hole (111h), the thickness of the bonding layer (AL) may change as it moves toward the center. For example, within the first through hole (111h), the thickness of the bonding layer (AL) may decrease as it moves toward the center. That is, the thickness (d2') of the bonding layer in the region adjacent to the upper surface (US) or the lower surface (BS) may be greater than the thickness (d2'') adjacent to the center of the first through hole (111h). Accordingly, the spacing between the bonding layers (AL) at the center of the first through hole (111h) can be easily secured.

[0235] Referring further to FIGS. 19 and 20, in a circuit board according to an embodiment, the bonding layer (AL) may include a groove or a hole. FIG. 19 is a plan view taken along the upper surface (US) of the first insulating layer (111).

[0236] In an embodiment, the bonding layer (AL) may include a groove penetrating the bonding layer (AL) or penetrating to a hole or a portion of the bonding layer (AL). Hereinafter, these are described as grooves, holes, etc. In addition, some of the grooves and holes are described interchangeably below.

[0237] A hole or groove (P1) may exist in an area in contact with the second insulating layer (112) (or the third insulating layer) on the upper surface (US) (or lower surface) of the first insulating layer (111). In addition, a hole or groove (P2) may exist in an area in contact with the first wiring portion (121b) on the upper surface (US) (or lower surface) of the first insulating layer (111). In addition, a hole or groove (P3) may exist in an area in contact with the first via electrode (121a) within the first through hole (111h). By these grooves or holes, the second insulating layer (112) and the first electrode portion (121) (in particular, the first wiring portion (121b) and the first via electrode (121a)) may be positioned within the grooves or holes of the bonding layer (AL). As a result, the bonding area between each component and the bonding layer (AL) may increase. Therefore, the bonding strength between components through the bonding layer (AL) can be further improved.

[0238] And the angles formed between the holes or grooves (P1 to P3) of the bonding layer (AL) and the upper surface (US) (or lower surface) of the first insulating layer (111) may be different depending on the location. For example, the angle (θ2) between the holes or grooves (P1 to P3) of the bonding layer (AL) and the upper surface (US) in the inner region of the first through hole (111h) may be different from the angle (θ1) between the holes or grooves (P1 to P3) of the bonding layer (AL) and the upper surface in the outer region of the first through hole (111h). Specifically, the angle (θ2) between the holes or grooves (P1 to P3) of the bonding layer (AL) and the upper surface (US) in the inner region of the first through hole (111h) may be smaller than the angle (θ1) between the holes or grooves (P1 to P3) of the bonding layer (AL) and the upper surface in the outer region of the first through hole (111h).

[0239] In the case of a hole, the length of the hole may be greater within the first through hole (111h) than on the upper surface of the first insulating layer (111). For example, the hole (P3) may be longer than the hole (P2 or P1). By this configuration, the bonding strength between the first electrode portion (121) and the first insulating layer (111) may be further improved.

[0240] As a variation, if the thickness (d1) of the first insulating layer (111) on the upper surface (US) or the lower surface (BS) of the bonding layer (AL) is greater than a certain thickness (d2) of the inner surface (IS) of the first through hole (111h), the length of the hole may be smaller within the first through hole (111h) than on the upper surface of the first insulating layer (111). Accordingly, the area in which the first insulating layer (111) is exposed by the hole within the first through hole (111h) may be smaller. That is, there may be more grooves than holes. Accordingly, the contact area between the first electrode portion and the first insulating layer (111) is reduced, so that a peeling phenomenon due to direct contact between the first insulating layer (111) and the first electrode portion (121) can be easily suppressed.

[0241] Referring further to FIGS. 21 and 22, the second insulating layer (112), the first wiring portion (121b), and the first via electrode (121a) may be positioned within the groove or hole of the bonding layer (AL), and a void (OP) may exist within the groove or hole. For example, air may exist in the void region within the groove or hole. This may be applied to all of the holes or grooves (P1 to P3) of the bonding layer (AL). In particular, in the first through hole (111h), the void (OP) exists in the hole or groove (P3) in the region in contact with the first via electrode (121a), so that a peeling phenomenon due to direct contact between the first insulating layer (111) and the first via electrode (121a) can be easily suppressed. In addition, a gap (OP) may exist in a hole or groove (P2) in the area in contact with the first wiring portion (121b) on the upper surface (US) (or lower surface) of the first insulating layer (111). As a result, the direct contact area between the first insulating layer (111) and the first wiring portion (121b) is reduced, so that the peeling phenomenon due to such direct contact can be easily suppressed.

[0242] Furthermore, as described above, a bonding layer (AL) may be applied to the entire surface of the lower surface (BS) of the first insulating layer (111). A hole or groove may exist in the area of ​​the lower surface (BS) of the first insulating layer (111) in contact with the third insulating layer (113). In addition, a hole or groove may exist in the area of ​​the lower surface (BS) of the first insulating layer (111) in contact with the first wiring portion (121b). By virtue of these grooves or holes, the third insulating layer (113) and the first electrode portion (121) may be positioned within the grooves or holes of the bonding layer (AL). As a result, the bonding area between each component and the bonding layer (AL) may increase.

[0243] Figures 23 to 28 are drawings explaining a method for manufacturing a circuit board according to an embodiment.

[0244] The same components described above are given the same drawing reference numerals, and duplicate descriptions of the same components are omitted, with only the differences described.

[0245] Additionally, the circuit board according to the embodiment may correspond to a unit circuit board. That is, during the manufacturing process, the mother circuit board may be composed of multiple unit circuit boards. The mother circuit board may be separated into multiple unit circuit boards along a sawing line. To form such a mother circuit board, a glass layer may be first placed. The following description will focus on the manufacturing of the unit circuit board.

[0246] A method for manufacturing a circuit board according to an embodiment may include a step of providing a first insulating layer, a step of forming a first through hole in the first insulating layer, a step of forming a bonding layer on an upper surface and a lower surface of the first insulating layer and an inner surface of the first through hole, a step of forming a seed layer, a step of forming a first via electrode through plating and etching, a step of forming a second insulating layer and a third insulating layer, a step of forming a second electrode portion and a third electrode portion, and a step of forming a protective layer and a pad, etc.

[0247] Referring to Fig. 23, a method for manufacturing a first insulating layer (or core substrate) in a circuit board according to an embodiment may first prepare a first insulating layer (111) made of glass. Additional processes such as rounding may be performed. The first insulating layer (111) may correspond to the first insulating layer or core layer described above.

[0248] Referring to Fig. 24, a first through hole (111h) can be formed in the first insulating layer (111). The first through hole (111h) can correspond to the via hole described above. The first through hole (111h) can be formed by performing etching on both sides of the first insulating layer (111). For example, a via electrode can be formed in a via hole or a through hole of a glass layer. For example, the first through hole (111h) can be formed by a photolithography process using a photomask or various etching methods such as a laser method.

[0249] Referring to Fig. 25, a bonding layer (AL) can be formed on one surface (upper surface or lower surface) of the first insulating layer (111). For example, the bonding layer (AL) can be formed on the upper surface (US), the lower surface (BS) of the first insulating layer (111) and the inner surface of the first through hole (111h). For example, the formation of the bonding layer can be applied by a dry method (e.g., sputtering), wet method, etc. In particular, spin coating, diffusion coating, spray coating, dip coating, etc., or CVD, ALD, etc. can be applied here. For example, the bonding layer (AL) can be formed by glass dipping.

[0250] Before forming this bonding layer (AL), the surface of the first insulating layer (111) can be treated with an ion beam. An ion beam is a mass of ion flow, which means a group of charged molecules or atoms. When an electric field or a magnetic field is applied to this ion beam, the flow of ions can be accelerated. The accelerated ions become high-energy, and by shooting these ions at the surface of the first insulating layer (111), the electrical properties of the surface of the first insulating layer (111) are changed. Examples of gases used in the ion beam treatment process include argon (Ar) and nitrogen gas. Since the surface roughness is higher when the ion beam treatment is performed than when the ion beam treatment is not performed, it can be omitted if necessary.

[0251] And as illustrated, the bonding layer (AL) may be made of polysilazane. For example, polysilazane may be cured while being dissolved in an organic solvent, and then coated on the first insulating layer (111). This polysilazane is a polymer containing silicon (Si) and nitrogen (N), and may have a Si-N bonding structure. And, during curing, polysilazane reacts with water (H2O) and oxygen (O2), and ammonia (NH3) and hydrogen (H2) may be released. As a result, polysilazane is at least partially transformed into a SiO2 structure.

[0252] Additionally, the bonding layer (AL) may include Parylene. In this case, Parylene may be coated on the first insulating layer (111) through vaporization, pyrolysis, and deposition.

[0253] Referring to Fig. 26, a seed electrode layer or seed layer (SE) can be formed on the bonding layer (AL). The seed layer (SE) can be formed on the bonding layer (AL) by various methods. For example, the seed layer (SE) can be formed on the bonding layer (AL) by sputtering. Sputtering is a technology that causes an inert element such as argon to collide with a target (metal plate) to expel metal molecules and then attach a film to the surface. When a direct current is applied to the target while flowing an inert gas as a sputtering gas in a vacuum chamber, plasma can be generated between the substrate to be deposited and the target. In addition, the inert gas can be ionized into positive ions by a high-power direct current field within this plasma. At this time, the positive ions of the inert gas can be accelerated to the cathode by the direct current field and collide with the surface of the target. In this way, target materials that collide with the surface of a target can be ejected from the surface by exchanging momentum through perfectly elastic collisions between atoms. When ions collide with kinetic energy greater than the interatomic binding energy of the material, the ion impact pushes the atoms between the lattices of the material to a different location, resulting in the escape of atoms from the surface. This phenomenon is called sputtering.

[0254] Accordingly, by performing sputtering on a metal plate made of the metal material to be plated, a thin and uniform metal film can be formed by adhering to the metal atom bonding layer (AL) protruding from the metal plate. Examples of metal materials include Ni, Cr, Cu, and Ti.

[0255] Referring to Fig. 27, the electrode portion (EE) can be formed by various plating methods, such as electroplating or chemical plating. For example, electroplating can be used to plate an area within the seed layer within the through hole. In addition, a first electrode portion consisting of a via electrode and a wiring portion can be formed by mask formation, etching, etc.

[0256] Referring further to Fig. 28, after the first electrode portion (121) is formed on the first insulating layer (111), a second insulating layer (112), a third insulating layer (113), etc. may be further formed. Similarly, a through hole may be formed in each insulating layer, and a second electrode portion, a third electrode portion, etc. may be formed in each insulating layer. The wiring portion of each electrode portion may be formed by an additive process, a subtractive process, a modified semi-additive process (MSAP), a semi-additive process (SAP), etc., which are manufacturing processes for printed circuit boards.

[0257] Additionally, a protective layer may be formed on top or bottom of the insulating layer. Additionally, an opening area for a conductive member may be formed in the protective layer.

[0258] Fig. 29 is a photograph of the first insulating layer and the bonding layer, and Fig. 30 is a drawing showing an XPS (X-ray Photoelectron Spectroscopy) spectrum from the surface of the first insulating layer to a predetermined depth.

[0259] Referring to Fig. 29, Figs. 29(a) to 29(c) are photographs taken by a Focused Ion Beam Scanning Electron Microscope (FIB SEM). In Fig. 29, (a), (b), and (c) show a bonding layer (AL) and a first insulating layer (111) made of glass, each having a different rotation speed (RPM). It can be seen that the thickness of the component decreases as the rotation speed increases.

[0260] Referring to Fig. 30, XPS in Fig. 30 stands for X-ray Photoelectron Spectroscopy. XPS is a powerful analytical technique used to analyze the surface chemical composition of a sample. For example, it can be performed by irradiating the sample surface with X-rays and then measuring the energy of photoelectrons emitted from atoms of the sample by the X-rays. For example, the elemental composition and chemical state of the sample surface are determined by analyzing the energy of the emitted photoelectrons. Fig. 30(a) and Fig. 30(b) analyze the energy of photoelectrons emitted along the inner depth from the sample surface. In this graph, the X-axis represents the binding energy (eV), and the Y-axis represents the normalized intensity. The unit of the Y-axis is arbitrary units (au). Therefore, the normalized intensity can be used to compare the relative concentration and abundance ratio of elements. In Fig. 30(a) and Fig. 30(b), each data curve in R3Si(O)1 was measured at various depths. Here, R3Si(O)1 corresponds to the aforementioned bonding layer. And the depth ranges from the surface to the maximum depth (e.g., 5.7 nm), and the curve located at the lowest point in the data curves consists of data at the surface, and the curve located at the highest point consists of data at the maximum depth. In addition, among the data curves located at the lowest point, ref may be a comparison curve as a data curve for SiO2. Furthermore, as shown in the graph, it can be seen that R3Si(O)1 has different peaks depending on the depth compared to ref. That is, since 'Ga' has a more distinct peak change at the surface than 'Gb', it can be seen that R3Si(O)1 is detected adjacent to the surface.

[0261] Fig. 31 is a cross-sectional view of a circuit board according to another embodiment, and Fig. 32 is an enlarged view of K8 in Fig. 31.

[0262] Referring to FIGS. 31 and 32, a circuit board according to another embodiment may include an insulating layer (110), an electrode portion (120), and a bonding layer (AL). The circuit board (100A) may include a protective layer (130). In addition, the circuit board (100A) according to the embodiment may include a semiconductor element (SD) and conductive members (CB1, CB2) positioned on one side (e.g., an upper portion). There may be a plurality of chips such as the semiconductor element (SD). Except for the contents described below, the above-described contents may be equally applied.

[0263] The bonding layer (AL) may be positioned on the inner surface (IS) of the first through hole (111h). And the bonding layer (AL) may be positioned between the first wiring portion (121b) and the upper surface (US) of the first insulating layer (111). Accordingly, the bonding layer (AL) may be in contact with the first wiring portion (121b) and the upper surface of the first insulating layer (111). In addition, the bonding layer (AL) may overlap with the first electrode portion (121) in the lamination direction (Z-axis direction). And the bonding layer (AL) may not exist between the spaced-apart first wiring portions (121b). That is, the bonding layer (AL) may be positioned only in a region disposed below the first wiring portion (121b) on the upper surface (US) of the first insulating layer (111), and may not be positioned in a region that does not overlap with the first wiring portion (121b) in the lamination direction. Accordingly, the upper surface (US) of the first insulating layer (111) may be in contact with the second insulating layer (112) in some areas. At this time, the area where the first insulating layer (111) and the second insulating layer (112) are in contact may be misaligned in the vertical direction with respect to the first wiring portion (121b) located on the upper portion (or upper surface) of the first insulating layer (111). That is, the area where the first insulating layer (111) and the second insulating layer (112) are in contact may not vertically overlap with the first wiring portion (121b). In addition, the lower surface (BS) of the first insulating layer (111) may be in contact with the third insulating layer (113) in some areas. Similarly, the area where the first insulating layer (111) and the third insulating layer (113) are in contact may be misaligned in the vertical direction with respect to the first wiring portion (121b) located on the lower portion (or lower surface) of the first insulating layer. That is, the area where the first insulating layer (111) and the second insulating layer (112) come into contact may not overlap in the vertical direction with the first wiring portion (121b).

[0264] The bonding layer (AL) positioned below the first wiring portion (121b) may have a side in contact with the second insulating layer (112). For example, the aforementioned groove may be located on the side of the bonding layer (AL) in contact with the second insulating layer (112). The second insulating layer (112) may be positioned in the groove. In addition, a void may exist in the groove.

[0265] In this way, the second insulating layer (112) can cover the bonding layer (AL) and the first wiring portion (121a). With this configuration, peeling of the bonding layer (AL) and the like can be easily suppressed. Accordingly, the structural reliability of the circuit board can be improved.

[0266] These contents can be equally applied to the third insulating layer (113), the first insulating layer (111) and the bonding layer (AL) below.

[0267] FIG. 33 is a drawing of another example taken along line AA' in FIG. 1, FIG. 34 is an enlarged view of part K9 in FIG. 33, FIG. 35 is an enlarged view of part K10 in FIG. 33, FIG. 36 is an enlarged view of part M1 in FIG. 35, FIG. 37 is an enlarged view of part M2 in FIG. 35, and FIG. 38 is an enlarged view of part M3 in FIG. 35.

[0268] Referring to FIGS. 33 to 35, a circuit board (100B) according to an embodiment may include an insulating layer (110), an electrode portion (120), and a protective layer (130). Furthermore, the circuit board (100B) may further include a bonding layer (AL) disposed on a first insulating layer (111) among the insulating layers (110).

[0269] The bonding layer (AL) can cover the first insulating layer (111). For example, the bonding layer (AL) can be located on the upper surface (US), the lower surface (BS) of the first insulating layer (111), and the inner surface (IS) of the through hole (111h).

[0270] In addition, the bonding layer (AL) can be formed of various materials that improve the bonding strength between the electrode portion and the first insulating layer (111). As a result, the bonding strength between the first insulating layer (111) made of glass and other insulating layers or the electrode portion is improved, thereby providing a circuit board with improved reliability.

[0271] In addition, in the present embodiment, the first through hole (111h) can be adjusted to various shapes. The first through hole (111h) may have different curvatures for each region of the inner surface (IS), and the maximum width may be less than or equal to twice the minimum width. Specifically, the first through hole (111h) may have a maximum width (W2) at the upper surface (US) or the lower surface (BS) of the first insulating layer (111). In addition, the first through hole (111h) may have a minimum width (W1) at the center in the vertical direction or at a point where the expansion direction changes. The maximum width (W2) may be less than or equal to twice the minimum width (W1). Furthermore, the minimum width (W1) may be 4% or more of the maximum width (W2). Accordingly, when forming an electrode portion in the first through hole, which is a via hole, seed electrode formation and via filling can be performed. Furthermore, if the minimum width (W1) becomes greater than 0.5 times the maximum width (W2), seed formation according to the inclination angle of the inner surface (IS) may become difficult.

[0272] The first through hole (111h) may include multiple regions depending on the curvature of the inner surface (IS). Here, the curvature refers to the degree to which a line or curve is bent on a cross-section or plane with respect to the inner surface (IS). For example, the curvature at a point of a curve on a plane may be the rate of change in the tangential direction at that point. Accordingly, the curvature may be a value that numerically indicates the degree to which the curve is bent. For example, if the curvature is large, the curve is bent greatly, and if the curvature is small, the curve may be bent less. Furthermore, since the inner surface (IS) of the first through hole (111h) is formed in a three-dimensional space, the curvature in the present specification may be the curvature of a curved surface. Accordingly, the curvature may refer to how the curved surface is bent.

[0273] Additionally, according to an embodiment, the curvature may be determined in size and positive / negative based on the central axis (AX) of the first through hole (111h). The central axis (AX) may correspond to the center of a plane perpendicular to the stacking direction in the first through hole (111h) or the intersection of a bisector in a perpendicular direction on the plane.

[0274] The first through hole (111h) may include a central area (MA), a first sub-area (A1), and a second area (A2). In the first through hole (111h) (or inner surface), the first sub-area (A1) and the second area (A2) may be arranged crosswise above or below the central area (MA).

[0275] The central region (MA) may include a region having a minimum width (W1) of the first through hole (111h). The central region (MA) may include a region having a curvature of 0. For example, the central region (MA) may include a curvature of 0 to ±0.3. Since the curvature is 0, the inner side (IS) in the central region (MA) may be parallel to the stacking direction and perpendicular to the horizontal direction. In addition, the inner side (IS) may have an infinite radius of curvature in the central region (MA). In addition, the central region (MA) may be adjacent to a bisecting point (center) in the stacking direction of the first through hole (111h) with respect to the upper surface (US) or the lower surface (BS).

[0276] One of the first sub-region (A1) and the second region (A2) may be a region with negative curvature, and the other may be a region with positive curvature. Furthermore, one of the first sub-region (A1) and the second region (A2) may be a region including a plurality of regions with negative curvature, and the other may be a region including a plurality of regions with positive curvature.

[0277] The first sub-area (A1) may be adjacent to the central area (MA). The second area (A2) may be adjacent to the first sub-area (A1). The first sub-area (A1) may be located between the second area (A2) and the central area (MA).

[0278] The first sub-area (A1) on the inner side (IS) may include an area with a negative or negative curvature. Hereinafter, the first sub-area (A1) on the inner side (IS) will be described based on the case where the curvature is negative. The curvature in the first sub-area (A1) may be -1.1 to 0. Preferably, the curvature in the first sub-area (A1) may be -1.1 to -0.3.

[0279] Referring further to FIG. 36, the central area (MA) may include an area with a curvature of 0 and a very large radius of curvature, as illustrated. The absolute value of the curvature of the first sub-area (A1) may decrease as it approaches the central area (MA). The curvature of the first sub-area (A1) may be smallest at the center, which is central in the stacking direction. In other words, the first sub-area (A1) may have the largest absolute value of the curvature at the center, which is central in the stacking direction.

[0280] In addition, the curvature may increase in the first sub-area (A1) as it approaches the central area (MA) or the second area (A2). For example, the curvature of the area adjacent to the central area (or the second area) in the first sub-area (A1) may be greater than the curvature of the area adjacent to the center (center in the stacking direction). In addition, the radius of curvature (r1) of the area adjacent to the central area (or the second area) in the first sub-area (A1) may be smaller than the radius of curvature (r2) of the area adjacent to the center (center in the stacking direction).

[0281] In the inner side (IS), the second area (A2) may have a positive curvature. The second area (A2) may include an area where the curvature is negative in the entire area or is partially negative. Hereinafter, the second area (A2) in the inner side (IS) will be described based on the case where the curvature is positive. The curvature in the second area (A2) may be 0 to 2.3. In addition, the first sub-area (A1) and the second area (A2) may have an inflection portion where the curvature changes from negative to positive (e.g., the curvature is 0). This inflection portion may be located at the border between the first sub-area (A1) and the second area (A2). However, as described above, the central area (MA) is a different area from the inflection portion between the first sub-area (A1) and the second area (A2). Referring further to Fig. 37, since the curvature is negative in the central portion of the first sub-area (A1), the inner surface may be convex toward the central axis (AX) of the first through-hole. In other words, the first sub-area (A1) may have a shape that is concave inward in the central portion. And, past the inflection portion, the curvature may be positive in the second area (A2). Accordingly, the inner surface of the first through-hole (111h) may be convex outward with respect to the central axis (AX) in the second area. In addition, the radius of curvature (r3) in the area adjacent to the second area in the first sub-area (A1) may be negative, and the radius of curvature (r4) in the area adjacent to the second area (A2) may be positive. Accordingly, the radius of curvature (r3) in the area adjacent to the second area in the first sub-area (A1) may be smaller than the radius of curvature (r4) in the area adjacent to the second area in the second area (A2).

[0282] The second region (A2) may be adjacent to the upper surface (US) and the lower surface (BS) of the first insulating layer (111). In the second region (A2), the curvature may increase as it becomes closer to the upper surface (US) and the lower surface (BS) of the first insulating layer (111).

[0283] It may include a second-first sub-area (A21) and a second-second sub-area (A22). The second-second sub-area (A2) may be an area having a greater curvature than the second-first sub-area (A21). The second-first sub-area (A21) may be located between the second-second sub-area (A22) and the first sub-area (A1).

[0284] For example, in the 2-1 sub-area (A21), the curvature may be 0 to 1.1. And in the 2-2 sub-area (A22), the curvature may be 1.1 to 2.3. The 2-1 sub-area (A21) and the 2-2 sub-area (A22) may be areas divided based on a point that is half the maximum curvature in the 2nd area (A2).

[0285] The second region (A2) may have an area in which the absolute value of curvature is greater than that of the first sub-region (A1). The second-first sub-region (A21) and the second-second sub-region (A22) may have a greater curvature than that of the first sub-region (A1). The second-first sub-region (A21) may have a similar absolute value of curvature to that of the first sub-region (A1).

[0286] For example, the absolute values ​​of curvature of the second-first sub-area (A21) and the first sub-area (A1) may be at least partially identical. Furthermore, the curvature and absolute value of curvature of the second-second sub-area (A22) may be greater than that of the first sub-area (A1).

[0287] Accordingly, the curvature and the absolute value of the curvature of the 2-2 sub-area (A22) may be greater than those of the 2-1 sub-area (A21). Conversely, the curvature of the 2-1 sub-area (A21) may be smaller than that of the 2-2 sub-area (A22). Referring further to FIG. 38, the radius of curvature (r5) in the 2-1 sub-area (A21) may be greater than the radius of curvature (r6) in the 2-2 sub-area (A22).

[0288] Additionally, the 2-2 sub-area (A22) may have the largest curvature or absolute value of curvature at the first through hole (111h) or the inner side (IS).

[0289] Furthermore, the angle (θ1) with respect to the virtual line or plane extending from the central region (MA) to the upper surface (US) or lower surface (BS) may be greater than the angle (θ2) formed by the upper surface (US) or lower surface (BS) and the inner surface (IS). As a result, a through hole can be formed while maintaining the ratio between the maximum width and the minimum width even if the inner surface (IS) does not have a vertical inclination angle. In addition, as described above, the flow of fluid or energy or the structural strength can be optimized or improved through the inner surface having a curvature. That is, by having various curvature changes (the first sub-region and the second region) based on the central region, external pressure or thermal stress can be effectively distributed. As a result, stress distribution applied to the electrode portion and the insulating layer can be easily achieved. In addition, this inner surface may include a surface having a curvature due to the structure (e.g., tetrahedron) of the silica (SiO2) of the first insulating layer, which is a glass layer, being distorted and scattered by a laser or the like applied to form the first through hole. Alternatively, the inner surface of the first through hole may include a surface having a curve, such as a hole, formed by a phenomenon in which particles are melted by the energy of the laser.

[0290] Additionally, the first through hole (111h) may have a total thickness (tt) of 1.5T or less. As the thickness (Th) of the first through hole (111h) increases, the thickness (Tm) of the central region (MA) may increase.

[0291] In addition, the thickness (tm) of the central region (MA) in the first through-hole (111h) may be greater than the thickness (t21) of the 2-1 sub-region (A21) or the thickness (t22) of the 2-2 sub-region (A22). And the thickness (tm) of the central region (MA) may be less than the thickness of the first sub-region (A1). The thickness (t1) of the first sub-region (A1) may be the largest in each region of the first through-hole. For example, the thickness (t1) of the first sub-region (A1) may be greater than the thickness (t2) of the second region (A2). The thickness (t1) of the first sub-region (A1) may be greater than the thickness (tm) of the central region (MA). Accordingly, the structure of the first through-hole can be provided in which the formation of the seed layer and the filling of the via electrode are easy by reducing the minimum width of the first through-hole.

[0292] And the thickness (t21) of the 2-1 sub-region (A21) or the thickness (t22) of the 2-2 sub-region (A22) may be smaller than the thickness (t1) of the 1st sub-region (A1) or the thickness (tm) of the central region (MA). And the thickness (t21) of the 2-1 sub-region (A21) may be smaller than the thickness (t22) of the 2-2 sub-region (A22). Accordingly, the maximum width of the first through-hole (111h) can be minimized. Accordingly, the electrode portion can be easily formed by appropriately maintaining the ratio of the maximum width and the minimum width in the first through-hole.

[0293] Fig. 39 is a cross-sectional view of a circuit board according to another embodiment.

[0294] Referring to FIG. 39, a circuit board according to another embodiment may include an insulating layer (110), an electrode portion (120), and a protective layer (130). Furthermore, the circuit board (100B) may further include a bonding layer (AL) disposed on a first insulating layer (111) among the insulating layers (110). Except for the contents described below, the above-described contents may be equally applied.

[0295] The first through-hole (111h) may have a total thickness (tt) of 1.5T or less. In the present embodiment, the thickness (t1) of the first sub-region (A1) may be smaller than the thickness (tm) of the central region (MA). The thickness (tm) of the central region (MA) may be the largest in each region of the first through-hole. For example, the thickness (tm) of the central region (MA) may be larger than the thickness (t1) of the first sub-region (A1) or the thickness (t2) of the second region (A2). In addition, as the thickness (Th) of the first through-hole (111h) increases, the thickness (Tm) of the central region (MA) may further increase. By this configuration, by forming a plurality of first sub-regions having a small width, the increase ratio of the width relative to the thickness (tt) of the first through-hole (111h) may be reduced, thereby facilitating the manufacture of a plurality of electrode portions.

[0296] In addition, the thickness (t1) of the first sub-region (A1) may be smaller than the thickness (t21) of the second-first sub-region (A21) or the thickness (t22) of the second-second sub-region (A22). And the thickness (t21) of the second-first sub-region (A21) may be smaller than the thickness (t22) of the second-second sub-region (A22). Accordingly, the maximum width of the first through-hole (111h) can be minimized. Accordingly, the electrode portion can be easily formed by appropriately maintaining the ratio of the maximum width and the minimum width in the first through-hole.

[0297] Figure 40 is a cross-sectional view of a circuit board according to another embodiment.

[0298] Referring to FIG. 40, a circuit board according to another embodiment may include an insulating layer (110), an electrode portion (120), and a protective layer (130). Furthermore, the circuit board (100B) may further include a bonding layer (AL) disposed on a first insulating layer (111) among the insulating layers (110). Except for the contents described below, the above-described contents may be equally applied.

[0299] As described above, the central area (MA) may be or include an area with a curvature of 0. The central area (MA) on the inner surface (IS) of the first through hole (111h) may be a plane parallel to the stacking direction. That is, the central area (MA) on the inner surface (IS) of the first through hole (111h) may be a point where the curvature changes.

[0300] And, based on the central area (MA), a plurality of first sub-areas and second areas may alternately exist toward the upper surface (US) / lower surface (BS) of the first insulating layer (111).

[0301] The first sub-area (A1) is in contact with the central area (MA) and may be or include an area with negative curvature. The first sub-area (A1) is located outside the central area (MA) and may have a concave structure due to negative curvature.

[0302] The second region (A2) may have a positive curvature and a convex structure. The second region (A2) may be in contact with the first sub-region (A1).

[0303] And a first sub-region (A1) may be positioned between the second region (A2) and the upper surface (or lower surface). The second region (A2) may be positioned between the spaced first sub-regions (A1). Furthermore, an additional inflection portion may exist between the first sub-region (A1) and the second region (A2). The second region (A2) may be positioned again at the outermost side. The second region (A2) may have a very large curvature. On the inner side (IS) of the first through hole (111h), the first sub-region (A1) and the second region (A2) may be applied differently depending on the thickness of the first through hole (111h). The curvature may gradually change toward the outer side (upper surface or lower surface) based on the central region (MA). That is, the curvature can change from 0 to minimum (negative) to maximum (positive) and then from minimum (negative) to maximum (positive) at least once based on the central area (MA). By this configuration, external pressure or thermal stress can be more effectively distributed. In the circuit board according to the embodiment, stress applied to the electrode portion and the insulating layer can be easily distributed.

[0304] Fig. 41 is a cross-sectional view of a circuit board according to another embodiment, and Fig. 42 is an enlarged view of part K11 in Fig. 41.

[0305] A circuit board according to another embodiment may include an insulating layer (110), an electrode portion (120), and a bonding layer (AL). The circuit board (100B) may include a protective layer (130). In addition, the circuit board (100B) according to the embodiment may include a semiconductor element (SD) and conductive members (CB1, CB2) positioned on one side (e.g., an upper portion). There may be a plurality of chips such as the semiconductor element (SD). The above-described contents may be equally applied, except for the contents described below.

[0306] The bonding layer (AL) may be positioned on the inner surface (IS) of the first through hole (111h). And the bonding layer (AL) may be positioned between the first wiring portion (121b) and the upper surface (US) of the first insulating layer (111). Accordingly, the bonding layer (AL) may be in contact with the first wiring portion (121b) and the upper surface of the first insulating layer (111). In addition, the bonding layer (AL) may overlap with the first electrode portion (121) in the lamination direction (Z-axis direction). And the bonding layer (AL) may not exist between the spaced-apart first wiring portions (121b). That is, the bonding layer (AL) may be positioned only in a region disposed below the first wiring portion (121b) on the upper surface (US) of the first insulating layer (111), and may not be positioned in a region that does not overlap with the first wiring portion (121b) in the lamination direction. Accordingly, the upper surface (US) of the first insulating layer (111) may be in contact with the second insulating layer (112) in some areas. At this time, the area where the first insulating layer (111) and the second insulating layer (112) are in contact may be vertically misaligned with the first wiring portion (121b) located on the upper portion (or upper surface) of the first insulating layer (111). That is, the area where the first insulating layer (111) and the second insulating layer (112) are in contact may not vertically overlap with the first wiring portion (121b). In addition, the lower surface (BS) of the first insulating layer (111) may be in contact with the third insulating layer (113) in some areas. Similarly, the area where the first insulating layer (111) and the third insulating layer (113) are in contact may be vertically misaligned with the first wiring portion (121b) located on the lower portion (or lower surface) of the first insulating layer. That is, the area where the first insulating layer (111) and the second insulating layer (112) come into contact may not overlap in the vertical direction with the first wiring portion (121b).

[0307] The bonding layer (AL) positioned below the first wiring portion (121b) can have its side in contact with the second insulating layer (112). As a result, the second insulating layer (112) can cover the bonding layer (AL) and the first wiring portion (121a). With this configuration, peeling of the bonding layer (AL) can be easily suppressed. Accordingly, the structural reliability of the circuit board can be improved.

[0308] These contents can be equally applied to the third insulating layer (113), the first insulating layer (111) and the bonding layer (AL) below.

[0309] Figures 43 to 48 are drawings explaining a method for manufacturing a circuit board according to an embodiment.

[0310] The same components described above are given the same drawing reference numerals, and duplicate descriptions of the same components are omitted, with only the differences described.

[0311] Additionally, the circuit board according to the embodiment may correspond to a unit circuit board. That is, during the manufacturing process, the mother circuit board may be composed of multiple unit circuit boards. The mother circuit board may be separated into multiple unit circuit boards along a sawing line. To form such a mother circuit board, a glass layer may be first placed. The following description will focus on the manufacturing of the unit circuit board.

[0312] A method for manufacturing a circuit board according to an embodiment may include a step of providing a first insulating layer, a step of forming a first through hole in the first insulating layer, a step of forming a bonding layer on an upper surface and a lower surface of the first insulating layer and an inner surface of the first through hole, a step of forming a seed layer, a step of forming a first via electrode through plating and etching, a step of forming a second insulating layer and a third insulating layer, a step of forming a second electrode portion and a third electrode portion, and a step of forming a protective layer and a pad, etc.

[0313] Referring to Fig. 43, a method for manufacturing a first insulating layer (or core substrate) in a circuit board according to an embodiment may first prepare a first insulating layer (111) made of glass. Additional processes such as rounding may be performed. The first insulating layer (111) may correspond to the first insulating layer or core layer described above.

[0314] Referring to Fig. 44, a first through hole (111h) can be formed in the first insulating layer (111). The first through hole (111h) can correspond to the via hole described above. The first through hole (111h) can be formed by performing etching on both sides of the first insulating layer (111). The first through hole (111h) can be formed to have a curvature as described above. In addition, a via electrode can be formed in the via hole or the through hole of the glass layer. For example, the first through hole (111h) can be formed by a photolithography process using a photomask or various etching methods such as a laser method.

[0315] Referring to Fig. 45, a bonding layer (AL) can be formed on one surface (upper surface or lower surface) of the first insulating layer (111). For example, the bonding layer (AL) can be formed on the upper surface (US), the lower surface (BS) of the first insulating layer (111) and the inner surface of the first through hole (111h). For example, the formation of the bonding layer can be applied by a dry method (e.g., sputtering), wet method, etc. In particular, spin coating, diffusion coating, spray coating, dip coating, etc., or CVD, ALD, etc. can be applied here. For example, the bonding layer (AL) can be formed by glass dipping.

[0316] Referring to Fig. 46, a seed electrode layer or seed layer (SE) can be formed on the bonding layer (AL). The seed layer (SE) can be formed on the bonding layer (AL) by various methods. For example, the seed layer (SE) can be formed on the bonding layer (AL) by sputtering. Sputtering is a technology that causes an inert element such as argon to collide with a target (metal plate) to expel metal molecules and then attach a film to the surface. When a direct current is applied to the target while flowing an inert gas as a sputtering gas in a vacuum chamber, plasma can be generated between the substrate to be deposited and the target. In addition, the inert gas can be ionized into positive ions by a high-power direct current field within this plasma. At this time, the positive ions of the inert gas can be accelerated to the cathode by the direct current field and collide with the surface of the target. In this way, target materials that collide with the surface of a target can be ejected from the surface by exchanging momentum through perfectly elastic collisions between atoms. When ions collide with kinetic energy greater than the interatomic binding energy of the material, the ion impact pushes the atoms between the lattices of the material to a different location, resulting in the escape of atoms from the surface. This phenomenon is called sputtering.

[0317] Accordingly, by performing sputtering on a metal plate made of the metal material to be plated, a thin and uniform metal film can be formed by adhering to the metal atom bonding layer (AL) protruding from the metal plate. Examples of metal materials include Ni, Cr, Cu, and Ti.

[0318] Referring to Fig. 47, an electrode portion (EE) can be formed by various plating methods such as electroplating or chemical plating. In addition, a first electrode portion consisting of a via electrode and a wiring portion can be formed by mask formation, etching, etc.

[0319] Referring further to Fig. 48, after the first electrode portion (121) is formed on the first insulating layer (111), a second insulating layer (112), a third insulating layer (113), etc. may be further formed. Similarly, a through hole may be formed in each insulating layer, and a second electrode portion, a third electrode portion, etc. may be formed in each insulating layer. The wiring portion of each electrode portion may be formed by an additive process, a subtractive process, a modified semi-additive process (MSAP), a semi-additive process (SAP), etc., which are manufacturing processes for printed circuit boards.

[0320] Additionally, a protective layer may be formed on top or bottom of the insulating layer. Additionally, an opening area for a conductive member may be formed in the protective layer.

[0321] FIG. 49 is a cross-sectional view of a circuit board according to another embodiment of the present invention, FIG. 50 is a drawing for K12 in FIG. 49, FIG. 51 is a plan view of a via hole and a first via electrode in a circuit board according to another embodiment, FIGS. 52(a) and 52(b) are plan views at different positions for an outer region of a via hole in a circuit board according to another embodiment, FIGS. 53(a), 53(b) and 53(c) are plan views at different positions for an inner region of a via hole in a circuit board according to another embodiment, FIG. 54 is a plan view of a via hole in a circuit board according to another embodiment, FIG. 55 is a cross-sectional view of a via hole in a circuit board according to another embodiment, FIG. 56a is a plan view of a portion of II' in FIG. 50, FIG. 56b is a plan view of a portion of BB' in FIG. 50, and FIG. 56c is a plan view of CC' in FIG. 50. Here are some photos of the top.

[0322] Referring to FIGS. 49 and 50, a circuit board (100C) according to another embodiment may include a core layer (110), a buffer layer (BF), an insulating layer (111, 112), an electrode portion (120), and a protective layer (not shown). In addition, the circuit board (100C) according to the embodiment may include a semiconductor element (not shown) and a conductive member (not shown) positioned on one side (e.g., an upper side).

[0323] The core layer (110) may be a 'core layer' or a 'substrate layer'. The core layer (110) can suppress warpage that occurs due to thinning of the circuit board. In other words, warpage can be reduced by placing a glass layer (or glass core) with high rigidity and a low coefficient of thermal expansion (CTE) at the center or core of the circuit board. For example, the core layer (110) may have high rigidity and a low coefficient of thermal expansion compared to an insulating layer or a protective layer. In addition, the core layer (110) may have a lower coefficient of thermal expansion compared to the electrode portion (120) (e.g., copper) or the buffer layer (BF). And the buffer layer (BF) or the insulating layer may have a similar coefficient of thermal expansion to that of the electrode portion. The core layer (110) may further include impurities and thus may have a coefficient of thermal expansion of, for example, 5 ppm / ℃ or more. Accordingly, the principal stress and shear stress of the structure on the circuit board are reduced, so that the reliability of the circuit board can be improved.

[0324] Additionally, the core layer (110) may have a greater thickness than the buffer layer (BF) or the insulating layer (111, 112). In an embodiment, the thickness of the core layer (110) in the stacking direction (Y-axis direction) may be greater than the thickness of the buffer layer (BF) in the stacking direction (Y-axis direction). By this configuration, the circuit board according to the embodiment can provide improved stress relief while preventing deterioration of electrical characteristics.

[0325] And the core layer (110) can be made of a glass material. For example, the core layer (110) can include pure silicon dioxide (SiO2), soda-lime glass, borosilicate glass, alumino-silicate glass, etc., and is not limited to silicon-based glass compositions, and alternative glass materials, such as fluorine glass, phosphate glass, chalcogen glass, etc., can also be used. In addition, the core layer (110) can further include other additives to form a glass having specific physical properties. These additives can include calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), as well as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of these and other elements.

[0326] Additionally, the core layer (110) may be made of an insulating material. Accordingly, the core layer (110) may be made of an insulating material and may be referred to as an ‘insulating layer’.

[0327] Additionally, the core layer (110) may be arranged at the center of the insulating layers (111, 112). Additionally, as described below, the buffer layer (BF) and the core layer (110) may include via holes (110h). The via holes (110h) may have various shapes and be formed at various locations, different from the number and structure illustrated in the drawing.

[0328] The core layer (110) may be composed of at least one layer. And the core layer (110) and the buffer layer (BF) may be arranged alternately.

[0329] In an embodiment, the core layer (110) may include an upper surface (US) and a lower surface (BS). A buffer layer (BF) may be positioned on the upper surface (US) and the lower surface (BS) of the core layer (110). The buffer layer (BF), the core layer (110), and the buffer layer (BF) may be sequentially arranged along the stacking direction (thickness direction) or the vertical direction (Y-axis direction).

[0330] As an example, a via hole (110h) may be positioned in the core layer (110). The via hole (110h) may penetrate the core layer (110). In addition, a first electrode portion (121) (first via electrode) of an electrode portion (120) described later may be positioned in the via hole (110h).

[0331] The buffer layers (BF) may be arranged on the upper surface (US) and the lower surface (BS) (or lower surface) of the core layer (110) and may be spaced apart from each other. In an embodiment, a plurality of buffer layers (BF) may be spaced apart from each other along the stacking direction (Y-axis direction).

[0332] The buffer layer (BF) may be formed of various insulating materials. The buffer layer (BF) may be formed of an organic or inorganic material. For example, the buffer layer (BF) may be an organic thin film or an inorganic thin film, and may include, for example, SiO2, Si3N4, etc. Furthermore, the buffer layer (BF) may be formed of a material having a low Poisson ratio. For example, the buffer layer (BF) may have a ratio similar to that of the core layer (110). By such a configuration, the stress relaxation effect may be improved.

[0333] The buffer layer (BF) may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide, similar to the insulating layers (111, 112) described below. In addition, the insulating layers (111, 112) may further include a reinforcing material in the resin.

[0334] The spaced buffer layers (BF) according to the embodiment may have the same or different thicknesses. These buffer layers (BF) are arranged on the upper surface (US) and the lower surface (BS) of the core layer (110) to distribute the force (e.g., stress) applied to the circuit board (100C) to each layer. That is, the buffer layer (BF) can alleviate the stress generated due to the difference in the coefficient of thermal expansion when the process is repeatedly performed at high temperature, room temperature, etc. due to the difference in the coefficient of thermal expansion between the buffer layer (BF) and the electrode portion (120). Accordingly, the effect of stress alleviation, etc. is improved, and the reliability of the circuit board can be improved.

[0335] The insulating layers (111, 112) can surround at least a portion of the core layer (110) and the buffer layer (BF). For example, the insulating layers (111, 112) can be positioned on the outer side of the core layer (110) and the buffer layer (BF). Accordingly, damage to the core layer (110) can be prevented. The insulating layers (111, 112) can be positioned on the upper or lower side of the core layer (110) and the buffer layer (BF). In an embodiment, the insulating layers (111, 112) can be in contact with the upper or lower surface of the buffer layer (BF). When the buffer layer (BF) is disposed on either the upper surface (US) or the lower surface (BS) of the core layer (110), the insulating layer can be in contact with the buffer layer (BF) and the core layer (110). For example, when the core layer (110) is present at the outermost side among the core layer (110) and the buffer layer (BF), the insulating layers (111, 112) can be in contact with the outermost core layer (110) in the lamination direction (Y-axis direction). In addition, when the buffer layer (BF) is present at the outermost side among the core layer (110) and the buffer layer (BF), the insulating layers (111, 112) can be in contact with the outermost buffer layer (BF) in the lamination direction (Y-axis direction).

[0336] Specifically, the buffer layer (BF) may exist only on the upper surface (US) of the core layer (110). At this time, the insulating layer may contact the buffer layer (BF) on the upper surface of the core layer (110) and the lower surface (BS) on the lower surface of the core layer (110). The following description will be given based on the drawings.

[0337] As an example, the insulating layer (111, 112) may be formed of at least one insulating layer. For example, the insulating layer (111, 112) may include multiple insulating layers. And the multiple insulating layers of the insulating layer may be formed of the same insulating material or different insulating materials.

[0338] As an example, the insulating layer (111, 112) may include a first insulating layer (111) and a second insulating layer (112) disposed above or below the core layer (110) and the buffer layer (BF).

[0339] The first insulating layer (111) and the second insulating layer (112) may be positioned above and below the buffer layer (BF), respectively. That is, the insulating layers (111, 112) may be laminated on the outermost side, with the core layer (110) and the buffer layer (BF) at the center. In the present specification, the upper part is a region facing the lamination direction (Y-axis direction), and the lower part is a region facing the opposite direction to the lamination direction (Y-axis direction).

[0340] Specifically, the first insulating layer (111) may be positioned on top of the buffer layer (BF). The first insulating layer (111) may be positioned on top of the first insulating layer (111) above the core layer (110). And the second insulating layer (112) may be positioned on the bottom of the buffer layer (BF) below the core layer (110).

[0341] In addition, a plurality of wiring portions (pads, circuit patterns), through holes (or via holes), via electrodes, etc. may be positioned in the insulating layers (111, 112). For example, the through holes of the insulating layers (111, 112) may be connected to the via holes of the core layer (110). In other words, the via electrodes positioned in the through holes of the insulating layers (111, 112) may be electrically connected to the via electrodes (first via electrodes) positioned in the via holes of the core layer (110).

[0342] The insulating layers (111, 112) may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. In addition, the insulating layers (111, 112) may further include a reinforcing material in the resin. The reinforcing material may be, for example, a fabric reinforcing material, an inorganic filler, etc. The fabric reinforcing material may be glass fiber, and the glass fiber may be impregnated into the resin to form a prepreg (PPG).

[0343] For example, the insulating layers (111, 112) may be formed of any insulating resin, such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin, such as PID (Photo Imageable Dielectric) resin, can be used. The above-described arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material formed of glass fiber or aramid fiber. For example, the insulating layers (111, 112) may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., as an example, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the insulating layers (111, 112) may include a plurality of layers composed of ABF.

[0344] Furthermore, the circuit board (100C) may include a cavity (not shown). In an embodiment, the cavity (not shown) may penetrate at least a portion of at least one core layer and at least a portion of a plurality of buffer layers. For example, the cavity (not shown) may penetrate a buffer layer (or core layer) located on top of a core layer that does not penetrate or partially penetrates the buffer layer.

[0345] The electrode portion (120) may be positioned on the core layer (110), the buffer layer (BF), and the insulating layer (111, 112). The electrode portion (120) according to the embodiment may include a plurality of electrode portions. Each electrode portion may include a wiring portion (circuit pattern, pad, etc.) and a via electrode. The electrode portion (120) may be made of a material other than copper, such as a metal having electrical conductivity, such as tungsten or gold.

[0346] The wiring portion (circuit pattern) can be designed in various forms for transmitting signals and / or power to and from semiconductor devices, and is disposed within the core layer (110) or the insulating layer (111, 112). For example, the electrode portion (120) may include a via electrode, which is a through-hole electrode. The via electrode may be positioned within a through-hole or via hole penetrating the core layer (110), the buffer layer (BF), and the insulating layer (111, 112). The via electrode is described interchangeably with the term 'through-hole electrode'.

[0347] In this way, in the electrode portion (120), the via electrode is arranged to penetrate a portion of each insulating layer for vertical connection between circuit patterns arranged on each vertically stacked core layer, buffer layer, and insulating layer. That is, the insulating layer, etc. may include a via hole or a through hole for arrangement of the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for optimization of impedance or heat dissipation, but is not limited thereto and may be freely designed.

[0348] The wiring portion of the electrode portion (120) may include a circuit pattern, pads, etc. The wiring portion of the electrode portion (120) may be arranged on each insulating layer. The pads may be electrically connected to the circuit patterns. In addition, the pads may be electrically connected to semiconductor elements and / or a main board or substrate, etc. In addition, the pads may be electrically connected to via electrodes.

[0349] In particular, pads arranged on the outside in the stacking direction (Y-axis direction) among the pads can be bonded to semiconductor elements, substrates, boards, etc. using solder, wires, conductive adhesives, etc., and can be arranged with a width larger than the width of the circuit pattern to solve problems such as securing yield. However, the present invention is not limited thereto, and may have the same width as the width of the circuit pattern depending on the technical limitations of the bonding process.

[0350] And the pads arranged inside in the stacking direction (Y-axis direction) among the pads have the function of connecting the via electrode and the circuit pattern. When the via electrode is arranged with a wider width than the circuit pattern, a pad having a wider width than the circuit pattern is provided for positional alignment during the manufacturing process of the via electrode to be arranged on each circuit pattern. Therefore, each via electrode may have an upper surface that is located on the same plane as the bottom surface of the upper pad that is in direct contact with the via electrode, and a bottom surface that is located on the same plane as the top surface of the lower pad that is in direct contact with the bottom surface of the via electrode. Here, the bottom surface of the upper pad and the top surface of the lower pad do not necessarily mean a flat surface, and it should be understood that even concave or convex surfaces that may appear depending on various processes may be present.

[0351] According to an embodiment, the electrode portion (120) may include a first electrode portion (121), a second electrode portion (122), and a third electrode portion (123).

[0352] The first electrode portion (121) may include a first via electrode (121a) penetrating the core layer (110) and the buffer layer (BF) and a first wiring portion (121b) disposed above and below the buffer layer (BF).

[0353] The second electrode portion (122) may be disposed on the first insulating layer (111). The second electrode portion (122) may include a second via electrode (122a) penetrating an insulating layer (e.g., a first insulating layer) disposed on the upper portion of the core layer (110) and the buffer layer (BF), and a second wiring portion (122b) disposed on the insulating layer (e.g., a first insulating layer) disposed on the upper portion of the core layer (110) and the buffer layer (BF). For example, the second electrode portion (122) may include the first insulating layer (111) and a second via electrode (122a) penetrating the first insulating layer (111), and the first insulating layer (111) and a second wiring portion (122b) disposed on the first insulating layer (111).

[0354] The third electrode portion (123) may be disposed on the second insulating layer (112). The third electrode portion (123) may include a third via electrode (123a) penetrating an insulating layer (e.g., a second insulating layer) disposed under the core layer (110) and the buffer layer (BF), and a third wiring portion (123b) disposed on an insulating layer (e.g., a second insulating layer) disposed under the core layer (110) and the buffer layer (BF). For example, the third electrode portion (123) may include a third via electrode (123a) penetrating the second insulating layer (112), and a third wiring portion (123b) disposed on the second insulating layer (112).

[0355] The protective layer (not shown) may be positioned above or below the insulating layer (111, 112). For example, the protective layer (not shown) may be positioned below or above the insulating layer that is positioned at the outermost side in the stacking direction (Y-axis direction). Accordingly, the protective layer (not shown) may be positioned at the outermost side in the stacking direction (Y-axis direction) on the circuit board.

[0356] A protective layer (not shown) can have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when joining a semiconductor element and / or a main board and a circuit board, the protective layer (not shown) may be formed of, for example, a solder resist. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals may be arranged at a high density. When the plurality of terminals and the pads of the circuit board are joined, solder may be used, for example. When solder is used, a solder short circuit problem may occur between terminals with a high density, and thus, a solder resist that does not have good wettability with the solder may be arranged to solve this short circuit problem. In addition, the protective layer (not shown) may be formed of a material that has insulating properties for electrical connection. The protective layer (not shown) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc.

[0357] And the protective layer (not shown) located at the outermost side of the circuit board may have an opening. Through the opening, it can be electrically connected to other semiconductor elements, the circuit board, etc.

[0358] For the electrical connection described above, a conductive member (not shown) may be positioned on the upper or lower portion of the circuit board (100C). The conductive member positioned on the upper portion may perform electrical connection with a semiconductor element (e.g., a chip) or another circuit board, etc. In addition, the conductive member positioned on the lower portion may perform electrical connection with another board, etc.

[0359] In an embodiment, wiring or electrodes may be arranged for electrical connection between a main board, etc. and a chip (or semiconductor element (not shown), die).

[0360] A semiconductor device (not shown) may be mounted on a circuit board (100C). The semiconductor device (not shown) may be mounted in a cavity (not shown) of the circuit board (100C). The semiconductor device may be a logic chip, a memory chip, or the like, as described above.

[0361] Circuit boards can be divided into package boards and interposers based on their function. The package board serves the function of mounting semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, to improve the yield of circuit boards with a high number of layers, the yield of the circuit board can be improved by separating them into an interposer and a package board. In addition, as the terminal density of semiconductor devices increases, it can be difficult to implement pads on the package board with an area corresponding to the terminals of the semiconductor devices. Therefore, the pad size of the package board can act as a buffer between the size of the pad and the fine pattern size of the terminals of the semiconductor devices.

[0362] The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In an embodiment according to the present invention, a circuit substrate having a core layer including glass is described.

[0363] According to an embodiment, the via hole (110h) may include an inner region (AR1) within the core layer (110) and an outer region (AR2) within the buffer layer (BF). The inner region (AR1) may overlap with the core layer (110) in a horizontal direction (X-axis direction). The outer region (AR2) may overlap with the buffer layer (BF) in a horizontal direction (Y-axis direction). The inner region (AR1) may be positioned between the spaced-apart outer regions (AR2). A first via electrode (121a) may be positioned in the inner region (AR1) and the outer region (AR2). That is, the first via electrode (121a) may be positioned within the via hole (110h). The horizontal direction (X-axis direction) may be a direction perpendicular to the stacking direction (Y-axis direction).

[0364] Furthermore, the first via electrode (121a) may include a first sub-via electrode (121aa) that overlaps the inner region (AR1) in a horizontal direction (X-axis direction) and a second sub-via electrode (121ab) that overlaps the outer region (AR2) in a horizontal direction (X-axis direction). The first sub-via electrode (121aa) may be positioned between the spaced-apart second sub-via electrodes (121ab).

[0365] And in the embodiment, the side surface in each of the inner region (AR1) and the outer region (AR2) may have different inclination angles with respect to the upper surface of the core layer (110). For example, the first inclination angle (θ1) between the side surface and the upper surface (US) of the core layer (110) in the inner region (AR1) may be greater than the second inclination angle (θ2) between the side surface and the upper surface (US) of the core layer (110) in the outer region (AR2).

[0366] Accordingly, the width (Wa) of the first sub-via electrode (121aa) or the inner region (AR1) may vary along the stacking direction. However, the width (Wb) of the second sub-via electrode (121ab) or the outer region (AR2) may decrease toward the core layer (110). For example, the width (or diameter) of the second sub-via electrode (121ab) or the outer region (AR2) may be in a direction in which the environmental direction is directed upward and downward from the center of the core layer (110) (e.g., a bisecting point in the stacking direction). In addition, the maximum width of the first sub-via electrode (121aa) or the inner region (AR1) may be smaller than the maximum width of the second sub-via electrode (121ab) or the outer region (AR2).

[0367] By this configuration, electrical connection between the first wiring portion (122b) and the first via electrode (121a) is easily achieved, peeling of the buffer layer (BF) is suppressed, and electrical characteristics can also be improved. Furthermore, the structural strength of the circuit board is also improved, and thermal expansion can be absorbed even during repeated thermal cycles or improved resistance to thermal shock can be provided.

[0368] In addition, in the circuit board according to the embodiment, the core layer (110) may include a groove (PT) located on the outer surface. The groove (PT) may be disposed on at least one of the upper surface (US), the lower surface (BS), and the via hole (110h) of the core layer (110). For example, the groove (PT) may be disposed on the upper surface (US) and the lower surface (BS) of the core layer (110). In addition, the groove (PT) may be located on the side of the via hole (110h). In this way, the groove (PT) may exist in the outer core layer due to the manufacturing process or stress, etc. The bonding strength between the core layer (110) and another insulating layer may be improved by the groove (PT). As a variation, a void such as air may be formed within the groove (PT).

[0369] In addition, as described above, the circuit board (100C) according to the embodiment may include a cavity (not shown), and the core layer (110) may be exposed by the cavity (not shown). In particular, the cavity (not shown) may penetrate a portion of the core layer (110). Accordingly, the cavity (not shown) may also penetrate the first insulating layer (111).

[0370] In addition, a bonding layer (not shown) may be further disposed on the exposed core layer (110). The bonding layer (not shown) may improve bonding strength between the core layer (110) and an additional via electrode or wiring portion. For example, the additional via electrode may be electrically connected to a semiconductor chip mounted in a cavity (not shown). The bonding layer (not shown) may be a coating layer, and may be made of a material that improves bonding strength between the core layer (110) and the insulating layers (111, 112) or the electrode portion (120). Accordingly, a delamination phenomenon between the core layer (110) and other components may be suppressed, thereby improving the structural reliability of the circuit board. Furthermore, the bonding layer (not shown) may be disposed on the entire surface of the core layer (110). In addition, the bonding layer (not shown) may be selectively positioned on the outer surface of the core layer (110). For example, a bonding layer (not shown) may be placed in an area of ​​the core layer (110) that comes into contact with the first electrode portion (121).

[0371] Referring to FIG. 51, in the embodiment, the side surface of the via hole (110h) and the first via electrode (121a) may have an edge or edges that are curved on a plane.

[0372] Specifically, in the inner region (AR1), the side surface may have a first portion spaced apart from each other and having a first curvature (or a first radius of curvature, r1) in a plane. The first curvature is the reciprocal of the first radius of curvature (r1). In the drawing, the curvature is denoted as 'r'.

[0373] And the first portions having the first curvature are spaced apart from each other and can be connected. There may be a plurality of first portions having the first curvature. And the plurality of first portions may be present at different positions for each of the plurality of via holes (110h). For example, the positions of the first portions on the upper surfaces of at least two of the plurality of via holes (110h) may be different.

[0374] Similarly, in the outer region (AR2), the side surface may have a second curvature (or a second radius of curvature, r2) in plane and may have a second portion spaced apart from each other. The second curvature is the reciprocal of the second radius of curvature (r2).

[0375] In addition, the second portions having the second curvature may be spaced apart from each other and connected. There may be a plurality of second portions having the second curvature. And the plurality of second portions may be present at different positions in each of the plurality of via holes (110h). For example, the positions of the first portions on the upper surfaces of at least two of the plurality of via holes (110h) may be different.

[0376] And the position of the first curvature and the position of the second curvature may be different from each other or adjacent to each other. For example, the first part having the first curvature and the second part having the second curvature may be located on overlapping curvature radii based on the central axis (AX) of the via hole (110h). For example, the center for the first curvature radius (r1) and the center for the second curvature radius (r2) may be located on the same line or the same plane from the central axis (AX). For example, the center for the second curvature radius (r2) may be located between the central axis (AX) and the center for the first curvature radius (r1).

[0377] Furthermore, the side in the inner region (AR1) may be positioned medially relative to the side in the outer region (AR2). For example, the side in the inner region (AR1) may be positioned adjacent to the central axis (AX) relative to the side in the outer region (AR2). Additionally, the first portion may be positioned medially relative to the second portion.

[0378] Referring further to FIG. 52, in the outer region (AR2), the side surfaces may have different curvatures in regions facing each other on a plane (e.g., a plane perpendicular to the Y-axis direction) along the stacking direction (Y-axis direction). For example, FIG. 52(a) and FIG. 52(b) are plan views of the outer region and the first electrode portion at different positions in the stacking direction.

[0379] For example, Fig. 52(a) is a plan view of the outer region and the uppermost surface of the first electrode portion. And Fig. 52(b) is a plan view of the outer region and the lowermost surface of the first electrode portion.

[0380] As shown in FIG. 52(a) and FIG. 52(b), in the outer region (AR2), the side surfaces may have different curvatures in areas that face each other on a plane along the stacking direction (Y-axis direction). In addition, the curvatures between antipodal points with respect to the central axis (AX) of the via hole (110h) (or the first via electrode) may be different. The antipodal point refers to the opposite end point (or side surface) of a straight line drawn from a point along the side surface on a plane and passing through the central axis (AX).

[0381] For example, the curvature (or curvature radius) at the first point (P1) on the outer region (AR2) and the uppermost surface of the first electrode portion may be different from the curvature (or curvature radius) at the second point (P2) that is the opposite point to the first point (P1). In addition, the curvature (or curvature radius) at the third point (P3) on the outer region (AR2) and the lowermost surface of the first electrode portion may be different from the curvature (or curvature radius) at the fourth point (P4) that is the opposite point to the third point (P3).

[0382] Furthermore, in the outer region (AR2), the side surface may also have a curvature that varies along the stacking direction. As illustrated in FIG. 50, in the outer region (AR2), the side surface may have a width or diameter that varies along the stacking direction (Y-axis direction), and the curvature may vary along the stacking direction at a portion positioned at the same angle on the plane with respect to the central axis (AX). For example, in FIG. 52(a), the curvature may be different based on a point below the first point (P1) and a plane (a plane perpendicular to the stacking direction) between the first point (P1).

[0383] By this configuration, when the first via electrode (or buffer layer, bonding layer, insulating layer, etc.) is placed on the core layer (110), the bonding strength between the first via electrode and the core layer can be improved. In addition, thermal expansion can be easily absorbed by the rough side surface, thermal stress relief can be improved, and mechanical stability can be easily maintained. Furthermore, resistance to vibration or impact can also be improved by the rough and differently curvatured side surface or edge (surface).

[0384] Referring to FIGS. 53(a), 53(b), and 53(c), the side surfaces in the inner region (AR1) may have different curvatures in regions facing each other on a plane (e.g., a plane perpendicular to the Y-axis direction) along the stacking direction (Y-axis direction). For example, FIGS. 53(a), 53(b), and 53(c) are plan views of the inner region and the first electrode portion (first via electrode) at different positions in the stacking direction (Y-axis direction).

[0385] For example, Fig. 53(a) is a plan view of the inner region and the uppermost surface of the first electrode portion. Fig. 53(b) is a plan view of the center of the inner region and the first electrode portion. And Fig. 53(c) is a plan view of the lowermost surface of the inner region and the first electrode portion.

[0386] As shown in FIG. 53(a), FIG. 53(b), and FIG. 53(c), in the inner region (AR1), the side surfaces may have different curvatures in areas that face each other planarly along the stacking direction (Y-axis direction). As in the outer region, in the inner region (AR1), the curvatures between opposing points with respect to the central axis (AX) of the via hole (110h) (or the first via electrode) may also be different.

[0387] For example, the curvature (or radius of curvature) at the fifth point (P5) in the inner region (AR1) and the uppermost surface of the first electrode portion may be different from the curvature (or radius of curvature) at the sixth point (P6), which is the opposite point to the fifth point (P5). For example, the radius of curvature at the fifth point (P5) may be the first radius of curvature (r1), but the radius of curvature at the sixth point may not be the first radius of curvature.

[0388] Additionally, the curvature (or radius of curvature) at the seventh point (P7) in the center (center in the stacking direction) of the inner region (AR1) and the first electrode portion may be different from the curvature (or radius of curvature) at the eighth point (P8), which is the opposite point of the seventh point (P7). For example, the radius of curvature at the eighth point (P8) may be the first radius of curvature (r1), but the radius of curvature at the seventh point (P7) may not be the first radius of curvature.

[0389] Additionally, in the inner region (AR1) and the lowest surface of the first electrode portion, the curvature (or curvature radius) at the ninth point (P9) may be different from the curvature (or curvature radius) at the tenth point (P10), which is the opposite point of the ninth point (P9). For example, the curvature radius at the tenth point (P10) may be the first curvature radius (r1), but the curvature radius at the ninth point (P9) may not be the first curvature radius.

[0390] Furthermore, in the inner region (AR1), the side surface may also have a curvature that varies along the stacking direction. As illustrated in FIG. 50, in the inner region (AR1), the width or diameter of the side surface may vary along the stacking direction (Y-axis direction), and the curvature may vary along the stacking direction at portions positioned at the same angle on the plane with respect to the central axis (AX). For example, in FIG. 53(a), the curvature may differ based on a point below the fifth point (P5) and a plane (a plane perpendicular to the stacking direction) between the fifth point (P5). Furthermore, in FIGS. 53(a), 5(b), and 53(c), with a plane cut perpendicular to the horizontal direction as a reference plane, the curvature may differ at points rotated at the same angle clockwise about the central axis (AX) in each plane (a plane perpendicular to the vertical direction) of the inner region (AR1). Simply put, the curvature (or radius of curvature) at one point on either the upper or lower surface in the inner region (AR1) may be different from the curvature (or radius of curvature) at the same location moved upward or downward in the stacking direction from said one point.

[0391] Referring to FIG. 54(a) and FIG. 54(b), the side surface of the via hole (110h) and the first via electrode (121a) in the core layer (110) are shown to have edges or edges that are curved in a plane. FIG. 54(a) is a microscope photograph of the via hole (110h) in the core layer (110), and FIG. 54(b) is an X-ray CT image as a cross-sectional photograph.

[0392] In this way, the curvature (or radius of curvature) between one point and the antipodal point of one point on the side of the plane via hole (110h) in the core layer (110) may be different from each other.

[0393] In addition, as in FIG. 54(b), a plurality of first via holes (110h) on the same plane may have different radii of curvature at points in the same direction / angle of inclination with respect to the central axis of each via hole.

[0394] Referring to FIG. 55, the first via hole (110h) or the first via electrode (121a) includes a surface with different curvatures along the stacking direction, and may have a somewhat larger roughness on the side surface. For example, the roughness on the side surface of the first via hole (110h) or the first via electrode (121a) may be larger than the roughness on the upper / lower surface of the core layer. In addition, as described above, the curvature (or radius of curvature) between a point (P11) on the side surface of the via hole (110h) on a plane (a plane perpendicular to the Y-axis) in the core layer (110) and the antipodal point (P12) of the point may be different from each other.

[0395] In addition, referring to FIGS. 56a, 8b and 56c, the curvature at a point on the side of the first via hole (110h) or the first via electrode (121a) may not be maintained along the stacking direction. That is, it can be seen that the curvature (or curvature radius) at a point either above or below the side of the first via hole (110h) or the first via electrode (121a) is different from the curvature (or curvature radius) at the same position moved upward or downward in the stacking direction from the point.

[0396] Fig. 57 is a cross-sectional view of a circuit board according to a modified example, and Fig. 58 is a plan view of a via hole and a first via electrode in the circuit board of Fig. 57.

[0397] Referring to FIGS. 57 and 58, a circuit board according to a modified example may include a core layer (110), a buffer layer (BF), an insulating layer (111, 112), an electrode portion (120), and a protective layer (not shown). In addition, the circuit board according to the embodiment may include a semiconductor element (not shown) and a conductive member (not shown) positioned on one side (e.g., the upper side). Except for the contents described below, the above-described contents may be equally applied.

[0398] In an embodiment, the side surface in each of the inner region (AR1) and the outer region (AR2) may have the same inclination angle with respect to the upper surface of the core layer (110). For example, a first inclination angle between the side surface and the upper surface (US) of the core layer (110) in the inner region (AR1) may be the same as a second inclination angle between the side surface and the upper surface (US) of the core layer (110) in the outer region (AR2). For example, the first inclination angle and the second inclination angle may have an error of less than 5% depending on the position.

[0399] In this example, a point having a second radius of curvature (r2) in the outer region (AR2) and a point having a first radius of curvature (r1) in the inner region (AR1) may partially overlap in the stacking direction or the vertical direction (Y-axis direction). In addition, even if the outer region (AR2) and the inner region (AR1) overlap in the vertical direction (Y-axis direction), the curvature or the radius of curvature may be different.

[0400] However, due to the difference in the inclination angle, the maximum width of the first sub-via electrode or the inner region (AR1) may be the same as the maximum width of the second sub-via electrode (or the outer region (AR2). In this case, the maximum width may have an error of within 5%.

[0401] This configuration maintains a straight electrical signal path along the first electrode portion, thereby improving signal transmission speed and reducing electrical loss. Furthermore, the width of the outer region facilitates precise positioning between the first electrode portions. In other words, the integration density of the electrode portions can be improved.

[0402] FIG. 59 is a cross-sectional view of a circuit board according to another embodiment of the present invention, FIG. 60 is an enlarged view of K13 in FIG. 59, and FIG. 61 is a plan view of an inner via hole, a via hole, and a first via electrode of the circuit board in FIG. 59.

[0403] Referring to FIGS. 59 to 61, a circuit board (100D) according to another embodiment may include a core layer (110), a buffer layer (BF), an insulating layer (111, 112), an electrode portion (120), and a protective layer (not shown). In addition, the circuit board according to the embodiment may include a semiconductor element (not shown) and a conductive member (not shown) positioned on one side (e.g., the upper side). Except for the contents described below, the above-described contents may be equally applied.

[0404] The circuit board (100D) according to the present embodiment may include a connection buffer layer (BFH) disposed within a via hole (110h). In addition, the buffer layer (BF) and the connection buffer layer (BFH) may include an inner via hole (ITH).

[0405] The connection buffer layer (BFH) is located on the inner side of the via hole (110h) and can be in contact with the core layer (110). Furthermore, the connection buffer layer (BFH) can be connected to the buffer layer (BF) disposed on the upper surface (US) and the lower surface (BS) of the core layer (110). That is, the connection buffer layer (BFH) can be in contact with the buffer layer (BF) disposed on the upper surface (US) and the lower surface (BS) of the core layer (110).

[0406] The connection buffer layer (BFH) may overlap at least partially in the stacking direction with the buffer layer (BF) disposed on the upper surface (US) and the lower surface (BS) of the core layer (110). The connection buffer layer (BFH) may overlap with the core layer (110) in the horizontal direction (X-axis direction). Furthermore, the connection buffer layer (BFH) may also overlap with the via hole (110h) of the core layer (110) in the horizontal direction.

[0407] The inner via hole (ITH) is located on the inner side of the via hole (110h) and can penetrate the buffer layer (BF) and the connection buffer layer (BFH). A first via electrode (121a) can be located in the inner via hole (ITH). The inner via hole (ITH) may have a length in the stacking direction greater than a length of the via hole (110h) in the stacking direction. For example, at least a portion of the inner via hole (ITH) may not overlap with the via hole (110h) in the horizontal direction (X-axis direction). Accordingly, a portion of the first via electrode (121a) in the inner via hole (ITH) may not overlap with the via hole (110h) in the horizontal direction.

[0408] Additionally, the third inclination angle (θ3) of the side surface of the via hole (110h) with respect to the upper surface (US) of the core layer (110) may be different from the fourth inclination angle (θ4) of the side surface of the inner via hole (ITH) with respect to the upper surface (US) of the core layer (110). For example, the third inclination angle (θ3) of the side surface of the via hole (110h) with respect to the upper surface (US) of the core layer (110) may be greater than the fourth inclination angle (θ4) of the side surface of the inner via hole (ITH) with respect to the upper surface (US) of the core layer (110).

[0409] And the width (Wd) (or diameter, area on a plane, etc.) of the via hole (110h) may be the same or similar along the stacking direction (Y-axis direction). As described above, the width, etc. may vary along the stacking direction depending on the roughness of the side surface of the via hole (110h).

[0410] The inner via hole (ITH) may have a width (Wc) (or diameter) that is maintained or changed along the stacking direction (Y-axis direction). For example, the width (or diameter) of the inner via hole (ITH) may decrease as it moves toward the center. Conversely, the width (or diameter) of the inner via hole (ITH) may increase as it moves from the center toward the upper or lower surface. Accordingly, the direction of expansion of the inner via hole (ITH) may be a direction from the center where the width (or diameter) is narrow toward the upper or lower surface. The direction of expansion may be a direction in which the width (or diameter, area in plan view) structurally increases. That is, the direction of expansion of the side surface of the inner via hole (ITH) and the direction of expansion of the side surface of the via hole (110h) may be different in at least some areas.

[0411] And the gap in the horizontal direction (X-axis direction) between the via hole (110h) and the inner via hole (ITH) may increase from the center toward the top / bottom. For example, the gap at the top (or bottom) of the via hole (110h) may be larger than the gap at the center of the via hole (110h).

[0412] In this way, an inner via hole (ITH) having a different structure from the via hole (110h) in the core layer (110) can be formed. By this configuration, the first via electrode (121a) can be in contact with the buffer layer (BF) and the connection buffer layer (BFH). Accordingly, direct contact between the core layer (110) and the first via electrode (121a) is prevented, and a peeling phenomenon between the first via electrode and the core layer can be suppressed. Furthermore, through the hourglass-like structure of the first via electrode, electrical characteristics can be improved and resistance to thermal deformation can also be improved.

[0413] Furthermore, in the embodiment, the side surfaces of the via hole (110h) and the inner via hole (ITH) may have edges or edges that are curvatures in a plane. And the side surfaces of the via hole (110h) may have different curvatures in areas that face each other in a plane along the stacking direction (Y-axis direction). However, the side surfaces of the inner via hole (ITH) may have the same curvatures in areas that face each other in a plane along the stacking direction (Y-axis direction). Accordingly, the distance between the side surfaces of the via hole (110h) and the inner via hole (ITH) may vary depending on the position in one plane.

[0414] In addition, in this example, the first wiring portion may overlap with the inner via hole (ITH) and the via hole (110h) in the stacking direction (Y-axis direction). As a variation, the maximum width of the via hole (110h) may be larger than the maximum width of the first wiring portion. And the maximum width of the first wiring portion may be larger than the maximum width of the inner via hole (ITH). Accordingly, at least a portion of the via hole (110h) may not overlap with the first wiring portion in the stacking direction (Y-axis direction). By this configuration, the formation of the connection buffer layer (BFH) disposed in the inner via hole (ITH) can be easily achieved while securing electrical characteristics. Furthermore, the thickness of the connection buffer layer (BFH) located in the inner via hole (ITH) can be larger than the thickness of the buffer layer (BF) in at least some areas. Therefore, cracks occurring in the via hole (110h) due to stress, etc., can be easily suppressed.

[0415] Figures 62 to 67 are drawings explaining a method for manufacturing a circuit board according to another embodiment of the present invention.

[0416] A method for manufacturing a circuit board according to another embodiment of the present invention may include the steps of providing a core layer and a buffer layer, alternating buffer layers on the upper and lower surfaces of the core layer, forming a via hole, forming a first electrode portion, laminating an insulating layer, and forming a second electrode portion and a third electrode portion. Furthermore, the method may further include the step of forming a cavity that at least partially penetrates the core layer. In addition, the method may include the step of mounting a semiconductor element or the like in the cavity, or further disposing a protective layer (e.g., solder resist) or a conductive member on top. Furthermore, the step of forming the cavity may not be performed when each core layer has a hole structure. As another example, in a circuit board composed of core layers, after laminating the core layer and the buffer layer, a cavity may be formed, and then an insulating layer, the second electrode portion, and the third electrode portion may be formed.

[0417] And for the same components described above, the same drawing symbols are assigned, and duplicate descriptions for the same components are omitted, and only the differences are described.

[0418] Additionally, the circuit board according to the embodiment may correspond to a unit circuit board. That is, during the manufacturing process, the mother circuit board may be composed of multiple unit circuit boards. The mother circuit board may be separated into multiple unit circuit boards along a sawing line. To form such a mother circuit board, a glass layer may be first placed. The following description will focus on the manufacturing of the unit circuit board.

[0419] Referring to Fig. 62, in a method for manufacturing a circuit board according to an embodiment, a core layer made of glass can be provided. The core layer can undergo a rounding process. For example, in the rounding process, the radius of curvature at the edge or periphery can be 0.5R (e.g., 0.5 mm). Additionally, surface treatment can be performed to reduce surface roughness. Furthermore, a buffer layer can be formed on the upper and / or lower surfaces of each core layer.

[0420] Referring to Figure 63, a buffer layer can be laminated on the upper and lower surfaces of the core layer.

[0421] Referring to FIG. 64, a via hole (110h) can be formed for the core layer (110) and the buffer layer (BF). The via hole (110h) can be formed by performing etching on the core layer (110) and the buffer layer (BF). For example, the via hole (110h) can be formed by a photolithography process using a photomask, a laser method, mechanical or chemical etching, etc. Accordingly, the via hole (110h) can include an inner region (AR1) formed in the core layer (110) and an outer region (AR2) formed in the buffer layer (BF). The inner region (AR1) can be located between the spaced outer regions (AR2).

[0422] Referring further to FIG. 65, in forming a via hole (110h), a sub hole (VH) penetrating the upper surface and the lower surface of the core layer (110i) and the buffer layer (BF) can be formed. There may be a plurality of sub holes (VH), and they can be arranged according to the shape of a desired via hole. For example, the plurality of sub holes (VH) can be spaced apart from each other and arranged along the edge of the shape of a desired via hole. For example, when designing a circular via hole, the plurality of sub holes (VH) can be arranged along the edge of the circle. Thereafter, an etching solution (ET) can be injected. Various solutions such as acidic or basic solutions can be used as the etching solution (ET). When the etching solution (ET) is injected into the plurality of sub holes (VH), the plurality of sub holes (VH) can be connected to each other by etching by the etching solution. Through this, a via hole (110h) according to each embodiment can be formed. This method of forming a via hole can be applied to the core layer (110). Furthermore, it can be equally applied to the buffer layer (BF) disposed on the upper and lower surfaces of the core layer.

[0423] Referring to FIG. 67, a first electrode portion (121) may be formed on the core layer (110) and the buffer layer (BF). As an example, a first via electrode (121a) may be formed on a via hole (110h). In addition, a first wiring portion (121b) may be formed on the upper or lower portion of the buffer layer (BF).

[0424] For example, a seed layer can be formed in a via hole (110h). Then, plating can be performed to form a first via electrode (121a). The first via electrode (121a) can be positioned within the via hole (110h). That is, the first via electrode (121a) can penetrate the buffer layer (BF) and the core layer (110).

[0425] The first wiring section (121b) can be formed by a manufacturing process of a printed circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP).

[0426] Referring to Fig. 68, insulating layers (111, 112) may be applied to the upper and lower portions of the core layer (110) and the buffer layer (BF). For example, a first insulating layer (111) may be formed on the buffer layer (BF) disposed on the upper portion of the core layer (110). A second insulating layer (112) may be formed on the lower surface of the buffer layer (BF) disposed on the lower portion of the core layer (110).

[0427] And a second electrode portion (122) and a third electrode portion (123) can be formed on the first insulating layer (111) and the second insulating layer (112). The formation of the electrode portion can be applied in the same manner as described above. Furthermore, there can be a plurality of insulating layers.

[0428] Accordingly, the first insulating layer (111) and the second insulating layer (112) may be formed of multiple layers. Additionally, electrode portions may be formed on the laminated insulating layers. For example, a second electrode portion (122) and a third electrode portion (123) may be additionally formed on each of the added first insulating layer (111) and second insulating layer (112).

[0429] Furthermore, a cavity (not shown) can be formed in the core layer (110), the insulating layers (111, 112), and the buffer layer (BF). The cavity (not shown) can penetrate at least a portion of the buffer layer (BF) and the core layer (110). For example, the cavity (not shown) can penetrate at least a portion of the core layer (110).

[0430] As described above, the cavity (not shown) can be formed by various methods such as a laser. Furthermore, a through hole for a via electrode in each electrode section described above can also be formed by various methods. For example, a photoresist (or resist layer) as a mask can be placed, and exposure can be performed by irradiating light (e.g., ultraviolet (UV)). Alternatively, selective etching can be performed using a photoresist, a chrome mask, an etch-resistant film, etc. Then, etching can be performed to remove the mask, etc. The mask can be removed by etching.

[0431] A circuit board according to an embodiment can be manufactured using the method described above. Subsequently, a protective layer can be formed on or below the insulating layer. Additionally, an opening area for a conductive member can be formed in the protective layer.

[0432] Furthermore, the structures of the various embodiments and modifications described above can be equally applied to the circuit board according to the present embodiment.

[0433] In various semiconductor packages, circuit boards according to the various embodiments described above may be located in some areas or correspond to one substrate.

[0434] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0435] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0436] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0437] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. A first insulating layer including glass and a first through hole penetrating the upper surface and the lower surface; A bonding layer disposed on the first insulating layer; and A first electrode part including a first via electrode disposed in the first through hole and a first wiring part disposed on the upper surface and the lower surface; A circuit board in which the bonding layer is disposed on the upper surface, the lower surface, and the inner wall of the first through hole.

2. In paragraph 1, A circuit board in which the bonding layer has a thickness on the upper or lower surface of the first insulating layer that is the same as the thickness on the inner wall of the first through hole.

3. In paragraph 1, A circuit board wherein the bonding layer comprises a metal oxide.

4. In paragraph 1, A circuit board wherein the bonding layer comprises a salt composed of Na.

5. In paragraph 4, The above salt is a circuit board located inside or on the surface of the bonding layer.

6. In paragraph 1, A circuit board comprising a second insulating layer disposed on the first insulating layer.

7. In paragraph 6, A circuit board wherein the bonding layer includes a first region in contact with the second insulating layer and a second region other than the first region.

8. In paragraph 7, The first region is in contact with the second insulating layer on the first insulating layer, The second region is a circuit board that comes into contact with the first electrode portion on the first insulating layer.

9. In paragraph 7, The above bonding layer comprises a salt composed of Na, A circuit board in which the salt is present in a large proportion in the first region compared to the second region.

10. In paragraph 1, A circuit board in which the bonding layer is located on the outermost surface of the first insulating layer.

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