Trench gate transistor

Abstract

The embodiments of the present application relate to a trench gate transistor, comprising: a semiconductor material layer; a gate trench comprising a side wall and a bottom wall, wherein the side wall comprises at least two first portions spaced apart in an extending direction and second portions located between adjacent first portions; first electric-field shielding structures located outside the gate trench and adjacent to the first portions; a body region located outside the gate trench and adjacent to the second portions, wherein the portion of the body region near the gate trench is used for forming channel regions; a drift region located below the channel regions; and second electric-field shielding structures located below the first electric-field shielding structures and having at least a portion extending below the channel regions, such that in the extending direction, the width of the drift region located between adjacent second electric-field shielding structures is smaller than the width of the channel regions. In this way, the saturation current of a device is significantly reduced, and the short-circuit performance of the device is optimized, thereby achieving a good balance among specific on-resistance (Rsp), a protection effect, and short-circuit performance.

Description

Trench gate transistor TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a trench gate transistor. BACKGROUND

[0002] Compared with planar gate transistor, the trench gate transistor can greatly reduce the cell size, and thus greatly improve the current density. For example, compared with planar gate metal-oxide-semiconductor field-effect transistor (MOSFET), the performance of the trench gate MOSFET is greatly improved, not only the channel mobility can be higher, but also the specific on-resistance Rsp is reduced, and the on-current density and on-state performance of the device are improved.

[0003] However, the trench gate transistor faces the problem of gate dielectric layer reliability, because when the device is in the blocking state, the bottom of the gate trench is exposed to the high field region in the drift region, so that the part of the gate dielectric layer at the bottom of the gate trench bears a high intensity electric field, and thus the insulation performance is easily degraded or even prematurely broken down, reducing the stability and life of the device during long-term operation. Especially for silicon carbide (SiC) based trench gate transistor, because the critical breakdown field strength of silicon carbide is much higher than that of silicon, the gate dielectric layer will bear a higher electric field, and the insulation performance is more likely to degrade or even prematurely break down.

[0004] In order to protect the gate dielectric layer, an electric field shielding structure is introduced into the trench gate transistor, one way is to inject multiple P pillar structures at intervals in the direction intersecting with the gate trench, to achieve the effect of reducing the electric field distribution in the gate dielectric layer at the bottom of the gate trench. However, the protection effect of this method needs to be improved, and the saturation current of the device is large and the short circuit performance is poor. SUMMARY

[0005] Therefore, the embodiments of the present application provide a trench gate transistor to solve at least one problem in the background art.

[0006] In a first aspect, the embodiments of the present application provide a trench gate transistor, comprising:

[0007] a semiconductor material layer;

[0008] a gate trench extending from the upper surface of the semiconductor material layer to the inside, the gate trench comprising a side wall and a bottom wall, the side wall comprising at least two first parts arranged at intervals along the extension direction and a second part between adjacent first parts, the extension direction being the extension direction of the side wall in the plane of the upper surface of the semiconductor material layer;

[0009] a first electric field shielding structure located outside the gate trench and adjacent to the first portion;

[0010] a body region located outside the gate trench and adjacent to the second portion, a portion of the body region close to the gate trench being used to form a channel region;

[0011] a drift region located below the channel region;

[0012] a second electric field shielding structure located below the first electric field shielding structure and extending at least partially below the channel region, such that along the extension direction, a width of the drift region between adjacent second electric field shielding structures is less than a width of the channel region.

[0013] With reference to the first aspect of the present application, in an optional implementation, a bottom of the first electric field shielding structure is farther away from an upper surface of the semiconductor material layer than a bottom of the body region, so that there is a gap between the second electric field shielding structure and the body region.

[0014] With reference to the first aspect of the present application, in an optional implementation, along the extension direction, a width of the drift region between adjacent second electric field shielding structures is less than a width between adjacent first electric field shielding structures.

[0015] With reference to the first aspect of the present application, in an optional implementation, the second electric field shielding structure is spaced apart from the body region by 0.25 μm to 1.2 μm.

[0016] With reference to the first aspect of the present application, in an optional implementation, an ion doping concentration of the second electric field shielding structure is greater than an ion doping concentration of the first electric field shielding structure.

[0017] With reference to the first aspect of the present application, in an optional implementation, an ion doping concentration of the body region is less than an ion doping concentration of the first electric field shielding structure and less than an ion doping concentration of the second electric field shielding structure.

[0018] With reference to the first aspect of the present application, in an optional implementation, the width of the drift region between adjacent second electric field shielding structures increases from a direction close to the gate trench to a direction away from the gate trench.

[0019] With reference to the first aspect of the present application, in an optional implementation, the second electric field shielding structure is adjacent to a bottom of the first electric field shielding structure.

[0020] With reference to the first aspect of the present application, in an optional implementation, the second electric field shielding structure and the first electric field shielding structure are both connected to a ground potential.

[0021] In an optional implementation of the first aspect of the present disclosure, the first electric field shielding structure surrounds two sides and a bottom wall of the gate trench.

[0022] In an optional implementation of the first aspect of the present disclosure, further comprising: a third electric field shielding structure, located below the gate trench, and having an overlapping area with the first electric field shielding structure and / or the second electric field shielding structure, through which the third electric field shielding structure is electrically connected with the first electric field shielding structure and / or the second electric field shielding structure.

[0023] In an optional implementation of the first aspect of the present disclosure, further comprising: a current diffusion layer, located in a JFET region below the body region, and having an ion doping concentration greater than that of the drift region.

[0024] In an optional implementation of the first aspect of the present disclosure, further comprising:

[0025] a gate dielectric layer, covering the sidewall and the bottom wall of the gate trench;

[0026] a gate, formed on the gate dielectric layer and filling the gate trench;

[0027] an interlayer dielectric layer, located in the gate trench and above the gate;

[0028] a conductive layer, located on the semiconductor material layer, and insulated and separated from the gate through the interlayer dielectric layer.

[0029] The trench gate transistor provided by the embodiment of the present application comprises: a semiconductor material layer; a gate trench extending from the upper surface of the semiconductor material layer to the inside, the gate trench comprising a side wall and a bottom wall, the side wall comprising at least two first parts arranged at intervals along the extension direction and a second part between the adjacent first parts, the extension direction being the extension direction of the side wall in the plane where the upper surface of the semiconductor material layer is located; a first electric field shielding structure located outside the gate trench and adjacent to the first part; a body region located outside the gate trench and adjacent to the second part, the part of the body region close to the gate trench being used to form a channel region; a drift region located below the channel region; a second electric field shielding structure located below the first electric field shielding structure and extending at least partially to below the channel region, so that the width of the drift region between the adjacent second electric field shielding structures along the extension direction is smaller than the width of the channel region; in this way, the interval of the adjacent first electric field shielding structures and the interval of the adjacent second electric field shielding structures can be set respectively, so that the width of the drift region between the adjacent second electric field shielding structures can be set to be smaller while the width of the channel region is ensured, the JFET resistance of the interval where the part is located can be adjusted, and the channel resistance is not affected, the saturation current of the device is greatly reduced, and the short-circuit performance of the device is optimized; and the protection effect of the gate trench bottom gate dielectric layer is enhanced through the second electric field shielding structure, so that the specific on-resistance Rsp and the protection effect and the short-circuit performance are taken into account.

[0030] Additional aspects and advantages of the present application will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0031] The accompanying drawings, which are included to provide a further understanding of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and serve to explain the present application. In the drawings:

[0032] FIG. 1 is a schematic diagram of a perspective structure of a trench gate transistor in the related art;

[0033] FIG. 2 is a schematic diagram of a projection in a second direction in FIG. 1;

[0034] FIG. 3 is a schematic diagram of a perspective structure of a trench gate transistor provided by the embodiment of the present application;

[0035] FIG. 4 is a schematic diagram of a projection in a second direction in FIG. 3;

[0036] FIG. 5 is a schematic diagram of a structure of an A-A section in FIG. 3;

[0037] FIG. 6 is a schematic diagram of a structure of a B-B section in FIG. 3;

[0038] FIG. 7 is a schematic diagram of a perspective view of the trench gate transistor along the C-C section in FIG. 3;

[0039] FIG. 8 is a schematic diagram of a projection of the trench gate transistor along the second direction in an optional embodiment;

[0040] FIG. 9 is a schematic diagram of a perspective view of the trench gate transistor in another optional embodiment of the present application;

[0041] FIG. 10 is a schematic diagram of a projection of the trench gate transistor along the second direction in still another optional embodiment of the present application;

[0042] FIG. 11 is a schematic diagram of a projection of the trench gate transistor along the second direction in yet another optional embodiment of the present application;

[0043] FIG. 12 is a schematic diagram of a perspective view of the trench gate transistor in yet another optional embodiment of the present application;

[0044] FIG. 13 is a schematic diagram of a structure of the B-B section in FIG. 12;

[0045] FIG. 14 is a schematic diagram of a perspective view of the trench gate transistor in yet another optional embodiment of the present application;

[0046] FIG. 15 is a schematic diagram of a structure of the A-A section in FIG. 14;

[0047] FIG. 16 is a schematic diagram of a structure of the B-B section in FIG. 14;

[0048] FIG. 17 is a schematic diagram of a perspective view of the trench gate transistor along the C-C section in FIG. 14;

[0049] FIG. 18 is a comparison diagram of Ids-Vds curves of the trench gate transistor provided by the embodiment of the present application and the trench gate transistor in the related art respectively, where Vds is in the range of 0V-500V;

[0050] FIG. 19 is a comparison diagram of Ids-Vds curves of the trench gate transistor provided by the embodiment of the present application and the trench gate transistor in the related art respectively, where Vds is in the range of 0V-1V.

[0051] Reference numerals: 100, substrate; 110, semiconductor material layer; 111, upper surface; 112, lower surface; 113, drift region; 114, JFET region; 120, gate trench; 121, sidewall; 1211, first portion; 1212, second portion; 122, bottom wall; 130, gate dielectric layer; 140, gate; 150, first electric field shielding structure; 157, P-pillar structure; 160, body region; 161, channel region; 170, second electric field shielding structure; 180, third electric field shielding structure; 190, first electric field shielding structure contact region; 200, source contact region; 210, interlayer dielectric layer; 220, conductive layer; 230, current spreading layer. DETAILED DESCRIPTION

[0052] Exemplary embodiments of the present application will be described more fully hereinafter with reference to the accompanying drawings. While example embodiments of the present application are shown in the drawings, it is to be understood that the present application can be embodied in various forms without being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0053] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail in order to avoid obscuring aspects of the present application.

[0054] In the drawings, the size of layers, regions, elements and the relative sizes of the same can be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0055] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are simply used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0056] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0058] For a thorough understanding of the application, detailed descriptions will be made in the following description and detailed structures will be presented in order to explain the technical solutions of the application. The preferred embodiments of the application are described in detail as follows. However, in addition to these detailed descriptions, the application can have other implementation manners.

[0059] FIG. 1 and FIG. 2 show a trench gate transistor structure in the related art. As shown, in order to protect the gate dielectric layer 130, a plurality of P-pillar structures 157 are arranged at intervals in the direction intersecting the gate trench 120. The presence of the P-pillar structure 157 occupies the position that should have formed the channel region, and the body region 160 is arranged between two adjacent P-pillar structures 157. The bottom electric field of the gate trench 120 is greatly affected by the interval of the P-pillar structure 157. If the interval is set to be small in order to obtain better protection effect, the occupation of the channel region is more, and the specific on-resistance Rsp is larger; on the contrary, if the interval is set to be large, the protection effect needs to be improved, and the saturation current of the device is large, and the short circuit performance is poor. Therefore, it is often necessary to face the problem that the specific on-resistance Rsp and the protection effect and the short circuit performance are difficult to balance and take into account.

[0060] Based on this, the embodiment of the application provides a trench gate transistor, please refer to FIG. 3 to FIG. 7, the trench gate transistor includes: a semiconductor material layer 110; a gate trench 120 extending from the upper surface 111 of the semiconductor material layer 110 to the inside, the gate trench 120 includes a side wall 121 and a bottom wall 122, the side wall 121 includes at least two first parts 1211 arranged at intervals along the extension direction and a second part 1212 located between two adjacent first parts 1211; a first electric field shielding structure 150 located outside the gate trench 120 and adjacent to the first part 1211; a body region 160 located outside the gate trench 120 and adjacent to the second part 1212, the part of the body region 160 close to the gate trench 120 is used to form a channel region 161; a drift region 113 located below the channel region 161; a second electric field shielding structure 170 located below the first electric field shielding structure 150 and at least partially extending to below the channel region 161, so that along the extension direction, the width W1 of the drift region 113 between two adjacent second electric field shielding structures 170 is less than the width W2 of the channel region 161.

[0061] It can be understood that, by improving the P-pillar structure in the related art to include the first electric field shielding structure 150 and the second electric field shielding structure 170 located below the first electric field shielding structure 150, the distance between two adjacent first electric field shielding structures 150 and the distance between two adjacent second electric field shielding structures 170 can be set respectively, that is, the distance between adjacent first electric field shielding structures 150 and the distance between adjacent second electric field shielding structures 170 can be adjusted individually. Specifically, the width W1 of the drift region 113 between adjacent second electric field shielding structures 170 is set to be smaller than the width W2 of the channel region 161, so that the width W1 of the drift region 113 between adjacent second electric field shielding structures 170 can be set to be small while the width W2 of the channel region 161 is ensured, the JFET resistance of the region where the drift region 113 is located can be adjusted, and the channel resistance is not affected, the saturation current of the device is greatly reduced, and the short-circuit performance of the device is optimized. Moreover, the protection effect of the gate dielectric layer 130 at the bottom of the gate trench 120 is enhanced by the second electric field shielding structure 170, so that the specific on-resistance Rsp and the protection effect and the short-circuit performance are taken into account.

[0062] Furthermore, since W1 and W2 in the embodiments of the present application are the widths along the extension direction, the adjustment of W1 and W2 will not affect the distance between adjacent gate trenches 120, and thus the number of gate trenches 120 arranged per unit area will not be reduced.

[0063] In the embodiments of the present application, the trench gate transistor is specifically, for example, a SiC MOSFET. 4H-SiC has a large band gap, a high critical breakdown field, and a fast saturated electron drift speed, and is an ideal material for manufacturing high-voltage MOSFETs. Of course, the present application does not exclude the case where the trench gate transistor is another possible type of transistor.

[0064] As shown in FIG. 3, the trench gate transistor can further include a substrate 100. The semiconductor material layer 110 can be an epitaxial layer grown on the substrate 100. The substrate 100 can be the base of the transistor and is the carrier for forming subsequent material layers.

[0065] The semiconductor material layer 110 can include an upper surface 111 for forming the gate trench 120 and a lower surface 112 opposite to the upper surface 111. The direction perpendicular to the upper surface 111 and the lower surface 112 of the semiconductor material layer 110 is defined as a thickness direction of the semiconductor material layer 110 or a thickness direction of the device, which is also a stacking direction of the subsequently deposited material layers on the substrate 100, and thus can also be referred to as a height direction or a depth direction of the device, which is shown as a second direction in the figure. Two first and third directions intersecting with each other are defined on the plane where the upper surface 111 of the semiconductor material layer 110 is located; for example, the first and third directions are two perpendicular directions.

[0066] In some embodiments, the semiconductor material layer 110 includes a silicon carbide epitaxial layer.

[0067] The semiconductor material layer 110 has a first conductivity type. The first conductivity type can be N-type or P-type.

[0068] In some embodiments, the first conductivity type is N-type. The semiconductor material layer 110 is an N-type semiconductor material layer. The substrate 100 is an N-type semiconductor substrate.

[0069] The gate trench 120 extends from the upper surface 111 of the semiconductor material layer 110 to the inside of the semiconductor material layer 110, and includes a side wall 121 and a bottom wall 122.

[0070] Exemplarily, the gate trench 120 can be formed by a photolithography process. Specifically, a mask material is first deposited on the semiconductor material layer 110, and then a photolithography process is performed to define a preset formation position of the gate trench 120 in the mask material, thereby forming a patterned mask layer. Next, the semiconductor material layer 110 is etched with the patterned mask layer as a mask until the gate trench 120 is formed. This process is well known to those skilled in the art and will not be described in detail here.

[0071] The side wall 121 includes at least two first portions 1211 arranged at intervals along an extension direction and a second portion 1212 located between the two adjacent first portions 1211. The extension direction refers to the extension direction of the side wall 121 on the plane where the upper surface 111 of the semiconductor material layer 110 is located. Referring to FIG. 4, as an optional specific embodiment, the projection of the gate trench 120 on the upper surface 111 of the semiconductor material layer 110 is a rectangle, wherein the width of the rectangle is the line width of the gate trench 120, and the length of the rectangle is the extension length of the gate trench 120. Further, the side wall 121 of the gate trench 120 extends along a straight line, and the extension of the side wall 121 along the third direction is specifically shown in FIG. 4.

[0072] Of course, the present application is not limited thereto, the planar shape of the gate trench 120 (i.e. the projected shape on the upper surface 111 of the semiconductor material layer 110) can also be other shapes, such as triangle, square, pentagon, hexagon, circle, etc.; thus, the sidewall 121 can not extend along a straight line, and the extending direction of the sidewall 121 can not be a fixed direction, but constantly changes as the sidewall 121 extends. For example, in FIG. 8, the planar shape of the gate trench 120 is hexagonal, and the extending direction of the sidewall 121 is along the direction of the side of the hexagon. Thus, the case of the first portion 1211 and the second portion 1212 is shown in the figure.

[0073] In a specific application, the first portion 1211 and the second portion 1212 can be arranged alternately. Specifically, along the above-mentioned extending direction, the sidewall 121 includes the first portion 1211, the second portion 1212, the first portion 1211, the second portion 1212, and so on, wherein the number of the first dielectric portion 131 and the second dielectric portion 132 is not necessarily equal, for example, one of them can be more than the other by 1.

[0074] For the case where the planar shape of the gate trench 120 is a symmetrical shape, the sidewall 121 can include two sides opposite to each other with respect to the symmetry axis, and the distribution of the first portion 1211 and the second portion 1212 on the two sides can be the same.

[0075] Please continue to refer to FIG. 3, the trench gate transistor can further include: a gate dielectric layer 130 covering the sidewall 121 and the bottom wall 122 of the gate trench 120; a gate electrode 140 located on the gate dielectric layer 130 and filling the gate trench 120.

[0076] Exemplarily, the gate dielectric layer 130 can be an oxide layer, thus, it can also be called a gate oxide layer; specifically, for example, a silicon dioxide layer. In the actual preparation process, the gate oxide layer can be formed by an oxidation process, can also be formed by a deposition process, and can also be formed by a process of first oxidation and then deposition.

[0077] Exemplarily, the material of the gate electrode 140 includes, for example, polysilicon.

[0078] The first electric field shielding structure 150 is located outside the gate trench 120 and abuts against the first portion 1211. The first electric field shielding structure 150 can also play a role of attracting electric field and alleviating the problem of electric field concentration at the bottom of the gate dielectric layer 130.

[0079] The first electric field shielding structure 150 can be formed by a doping process, for example, an ion implantation process. Exemplarily, the first electric field shielding structure 150 can have a second conductivity type, which is different from the first conductivity type. In other words, the first electric field shielding structure 150 has a different conductivity type from the semiconductor material layer 110; thus, it can function to attract or deplete a portion of the electric field. In practical applications, the first electric field shielding structure 150 can be P-type; the first electric field shielding structure 150 can also be referred to as a P-link structure.

[0080] The first electric field shielding structure 150 can surround both sides and the bottom wall of the gate trench 120. In the plane where the upper surface 111 of the semiconductor material layer 110 is located, the projection of the first electric field shielding structure 150 intersects with the projection of the gate trench 120; further, the two can intersect perpendicularly.

[0081] The adjacent first electric field shielding structures 150 can be parallel or not parallel. As shown in FIG. 4, the adjacent first electric field shielding structures 150 are parallel; and further, each first electric field shielding structure 150 is perpendicular to the gate trench 120, or perpendicular to the extension direction of the sidewall 121. In other embodiments, the adjacent first electric field shielding structures 150 can also be parallel but not perpendicular to the gate trench 120. The embodiments of the present application do not make specific limitations in this regard. As shown in FIG. 8, the adjacent first electric field shielding structures 150 are not parallel; and further, specifically, the adjacent first electric field shielding structures 150 intersect. For any two first electric field shielding structures 150 intersecting, the position of the intersection can be located below the gate trench 120; of course, the present application does not exclude the case where the intersection is at other positions. At the sidewall of the gate trench 120, the adjacent first electric field shielding structures 150 are arranged alternately.

[0082] The body region 160 is located outside the gate trench 120 and adjacent to the second portion 1212, and the portion of the body region 160 close to the gate trench 120 is used to form a channel region 161 (see FIG. 6). It can be understood that, in the case where the first portion 1211 and the second portion 1212 are arranged alternately, along the sidewall 121, the first electric field shielding structure 150 and the body region 160 are arranged alternately.

[0083] The body region 160 can be formed by a doping process, for example, an ion implantation process. Exemplarily, the body region 160 can have a second conductivity type, which is different from the first conductivity type. In other words, the body region 160 has a different conductivity type from the semiconductor material layer 110. In practical applications, the body region 160 can be P-type; the body region 160 can also be referred to as a P-body region.

[0084] Specifically, the ion doping concentration of the body region 160 is less than the ion doping concentration of the first electric field shielding structure 150.

[0085] The surface layer of the body region 160 can include a source contact region 200. The source contact region 200 extends from the upper surface 111 of the semiconductor material layer 110 to the interior of the semiconductor material layer 110.

[0086] The source contact region 200 has the first conductivity type. The source contact region 200 has the same conductivity type as the semiconductor material layer 110, and is opposite to the conductivity type of the body region 160. The ion doping concentration of the source contact region 200 is higher than the semiconductor material layer 110. Exemplarily, the source contact region 200 is an N+ doped region; the source contact region 200 is formed, for example, by performing a reverse type heavy doping on the surface layer of the body region 160.

[0087] Referring to FIG. 4 and FIG. 6, during device operation, the part of the body region 160 close to the gate trench 120 forms a channel region 161. For FIG. 4, for the sake of clarity of the labels, only the left side of the gate trench 120 in the figure schematically shows the channel region 161, but it should be understood that the right side of the gate trench 120 in the figure (i.e., the second part 1212) also forms the channel region 161.

[0088] The drift region 113 is located below the channel region 161. In an actual device, the remaining part of the semiconductor material layer 110 is used to form the drift region of the device.

[0089] The second electric field shielding structure 170 is located below the first electric field shielding structure 150. The second electric field shielding structure 170 can play a role of attracting electric field and alleviating the problem of electric field concentration at the bottom of the gate dielectric layer 130.

[0090] Specifically, in the semiconductor material layer 110, the second electric field shielding structure 170 includes, for example, at least the part located at a depth greater than or equal to the depth of the gate trench bottom wall 122.

[0091] The second electric field shielding structure 170 can be formed by a doping process, for example, an ion implantation process. Exemplarily, the second electric field shielding structure 170 can have a second conductivity type, which is different from the first conductivity type. In other words, the second electric field shielding structure 170 has a different conductivity type from the semiconductor material layer 110; in this way, it can play a role of attracting or depleting a part of the electric field. The second electric field shielding structure 170 has the same conductivity type as the first electric field shielding structure 150. In actual applications, the second electric field shielding structure 170 can be P-type.

[0092] The second electric field shielding structure 170 is formed in a different doping process from the first electric field shielding structure 150. In actual production, the second electric field shielding structure 170 and the first electric field shielding structure 150 can be both selectively doped; a mask is used respectively in the process of forming the second electric field shielding structure 170 and the first electric field shielding structure 150 to define the forming area of the two. The mask used in forming the second electric field shielding structure 170 is different from the mask used in forming the first electric field shielding structure 150.

[0093] As an optional embodiment, the ion doping concentration of the second electric field shielding structure 170 is greater than the ion doping concentration of the first electric field shielding structure 150; thus, the second electric field shielding structure 170 plays a better role in protecting the gate dielectric layer 130.

[0094] As an optional embodiment, the ion doping concentration of the second electric field shielding structure 170 is greater than the ion doping concentration of the body region 160. Further, the ion doping concentration of the body region 160 is less than the ion doping concentration of the first electric field shielding structure 150 and less than the ion doping concentration of the second electric field shielding structure 170. Thus, the device can work effectively while the gate dielectric layer 130 is better protected.

[0095] The projection of the first electric field shielding structure 150 on the upper surface 111 of the semiconductor material layer 110 can fall within the projection range of the second electric field shielding structure 170. The planar shape of the second electric field shielding structure 170 (i.e. the projection shape on the upper surface 111 of the semiconductor material layer 110) can be the same as the planar shape of the first electric field shielding structure 150, only in the extension direction of the side wall 121, the boundary of the second electric field shielding structure 170 exceeds that of the first electric field shielding structure 150. In the extension direction of the side wall 121, the second electric field shielding structure 170 protrudes from the first electric field shielding structure 150. In an actual device, in the extension direction of the side wall 121, there is a clear interval between the boundary of the part of the second electric field shielding structure 170 extending below the channel region 161 and the boundary of the first electric field shielding structure 150 above it.

[0096] It should be understood that the present application also does not exclude the case where the planar shape of the second electric field shielding structure 170 is different from the planar shape of the first electric field shielding structure 150. In addition, the present application also does not exclude the case where the second electric field shielding structure 170 does not completely cover the first electric field shielding structure 150 below.

[0097] In the embodiment of the present application, the width W1 of the drift region 113 located between two adjacent second electric field shielding structures 170 is less than the width W2 of the channel region 161, so as to balance the specific on-resistance Rsp and the saturation current of the device.

[0098] Please refer to FIG. 18 and FIG. 19, in which solid lines correspond to embodiments of the present application, and dashed lines correspond to related art. As shown in FIG. 18, simulation tests are performed under the condition that Vgs (Gate To Source Voltage) is equal to 18V, and Ids-Vds curves are obtained in the range of 0V-500V of Vds (Drain To Source Voltage); it can be understood that FIG. 18 mainly represents the saturation region of the device. By comparing Ids (Drain To Source Current) at the same Vds in FIG. 18, it can be seen that the trench gate transistor provided by embodiments of the present application has a significantly reduced Ids compared with the trench gate transistor in related art. As shown in FIG. 19, simulation tests are performed under the condition that Vgs is equal to 18V, and Ids-Vds curves are obtained in the range of 0V-1V of Vds; it can be understood that FIG. 19 mainly represents the linear region of the device. The reciprocal of the slope of the curve in FIG. 19 represents Rdson (Drain To Source Resistance), and since the specific on-resistance Rsp=Rdson*chip active area, Rsp can represent Rdson under the condition that the active area is unchanged; by comparing the linear region, it can be seen that the trench gate transistor provided by embodiments of the present application has a slightly increased Rdson compared with the trench gate transistor in related art, thereby greatly reducing the saturation current of the device at the expense of a slight Rsp, thereby optimizing the short-circuit performance. It should be understood that the present application does not necessarily sacrifice Rsp, and in some embodiments, the relationship between Rsp and Rdson can be further balanced by adjusting the size of W1.

[0099] Please refer to FIG. 3, FIG. 5 and FIG. 6, as an optional specific embodiment, the bottom of the first electric field shielding structure 150 is farther away from the upper surface 111 of the semiconductor material layer 110 than the bottom of the body region 160, so that there is a gap D1 between the second electric field shielding structure 170 and the body region 160.

[0100] Further, along the extending direction, the width W1 of the drift region 113 between adjacent second electric field shielding structures 170 is less than the width W3 between adjacent first electric field shielding structures 150. It can be understood that, in the case that the boundary of the first electric field shielding structure 150 is substantially constant along the depth direction, W3 is substantially equal to W2, both of which are greater than W1. In the case that the boundary of the first electric field shielding structure 150 varies along the depth direction, the upper half of the first electric field shielding structure 150 is in a relationship of either-or with the body region 160, the interval between adjacent upper halves of the first electric field shielding structure 150 is equal to the width W2 of the channel region 161, but the lower half of the first electric field shielding structure 150 can extend below the channel region 161, so that W3 can be less than W2, and in this case W3 is still greater than W1, to ensure that the specific on-resistance Rsp and the short-circuit performance are both taken into account.

[0101] Further, the second electric field shielding structure 170 is spaced apart from the body region 160 by 0.25 μm to 1.2 μm, i.e., D1 is in the range of 0.25 μm to 1.2 μm. It should be noted that, in the case that D1 is less than 0.25 μm, due to longitudinal diffusion, the ions doped in the second electric field shielding structure 170 can invade into the body region 160, causing Rdson to become large; in the case that D1 is greater than 1.2 μm, the process implementation difficulty is increased.

[0102] It should be noted that the present application does not exclude the case that D1 is equal to 0. Please refer to FIG. 9, in the semiconductor material layer 110, the depth at which the bottom of the first electric field shielding structure 150 is located can be substantially the same as the depth at which the bottom of the body region 160 is located, so that at least part of the second electric field shielding structure 170 extends below the channel region 161, specifically, at least part of the second electric field shielding structure 170 is adjacent to the body region 160 below the channel region 161.

[0103] As an optional specific embodiment, the second electric field shielding structure 170 is adjacent to the bottom of the first electric field shielding structure 150. The second electric field shielding structure 170 and the first electric field shielding structure 150 form an electrically conductive connection by direct contact.

[0104] Further, the second electric field shielding structure 170 and the first electric field shielding structure 150 are both connected to the ground potential. In this way, the shielding effect can be better exerted, to better achieve the effect of weakening the electric field intensity at the bottom of the gate dielectric layer 130.

[0105] The surface layer of the first electric field shielding structure 150 can include a first electric field shielding structure contact region 190. The first electric field shielding structure contact region 190 extends from the upper surface 111 of the semiconductor material layer 110 to the interior of the semiconductor material layer 110; the first electric field shielding structure contact region 190 is specifically located above the portion of the first electric field shielding structure 150 distributed on both sides of the gate trench 120.

[0106] The first electric field shielding structure contact region 190 is in electrically conductive connection with the first electric field shielding structure 150 and the source contact region 200, and the first electric field shielding structure 150 is in electrically conductive connection with the source contact region 200 through the first electric field shielding structure contact region 190, thereby being collectively connected to the ground potential.

[0107] The first electric field shielding structure contact region 190 has a second conductive type, which is different from the first conductive type. In other words, the first electric field shielding structure contact region 190 is opposite to the conductive type of the semiconductor material layer 110, and is the same as the conductive type of the first electric field shielding structure 150, but has a higher ion doping concentration than the first electric field shielding structure 150. Exemplarily, the first electric field shielding structure contact region 190 is a P+ doped region; and is formed by heavily doping the surface layer of the first electric field shielding structure 150.

[0108] As an optional embodiment, the trench gate transistor further includes a third electric field shielding structure 180 located below the gate trench 120, and having an overlapping region with the first electric field shielding structure 150 and / or the second electric field shielding structure 170, through which the third electric field shielding structure 180 is in electrically conductive connection with the first electric field shielding structure 150 and / or the second electric field shielding structure 170.

[0109] The first electric field shielding structure 150, the second electric field shielding structure 170, and the third electric field shielding structure 180 are electric field shielding structures corresponding to the same gate trench 120.

[0110] The third electric field shielding structure 180 can be formed by a doping process, specifically, for example, an ion implantation process. Exemplarily, the third electric field shielding structure 180 can have a second conductive type, which is different from the first conductive type. In other words, the third electric field shielding structure 180 is not the same as the conductive type of the semiconductor material layer 110; in this way, it can play a role in attracting or depleting a part of the electric field. In actual applications, the third electric field shielding structure 180 can be P-type; the third electric field shielding structure 180 can also be referred to as a P shield structure.

[0111] The third electric field shielding structure 180 is used to protect the bottom of the gate dielectric layer 130, and does not affect the formation of the channel region, so that the protection effect of the gate dielectric layer 130 can be further enhanced. The third electric field shielding structure 180 is further arranged on the basis of the first electric field shielding structure 150 and the second electric field shielding structure 170, which is more conducive to taking into account the electric field shielding effect of the bottom of the gate dielectric layer 130 and the influence on the on-resistance of the trench gate transistor.

[0112] Further, the third electric field shielding structure 180 is connected to the ground potential through the first electric field shielding structure 150 and / or the second electric field shielding structure 170; in this way, the shielding effect can be better, so as to better weaken the electric field intensity at the bottom of the gate dielectric layer 130.

[0113] Next, please refer to FIG. 10 and FIG. 11. As an optional embodiment, the width W1 of the drift region 113 between adjacent second electric field shielding structures 170 increases from the direction close to the gate trench 120 to the direction away from the gate trench 120.

[0114] In the embodiment shown in FIG. 4, the distance between two adjacent second electric field shielding structures 170 is substantially constant, so that W1 remains unchanged in the direction from the direction close to the gate trench 120 to the direction away from the gate trench 120. It can be understood that the saturation current of the device of the embodiment shown in FIG. 10 and FIG. 11 is also reduced compared with the related art. In the case where W1 in the embodiment shown in FIG. 4 is equal to the minimum W1 in the embodiment shown in FIG. 10 and FIG. 11, the saturation current of the embodiment shown in FIG. 10 and FIG. 11 will be greater than that of the embodiment shown in FIG. 4, that is, the reduction effect of the saturation current is not as good as that of the embodiment shown in FIG. 4; however, the specific on-resistance Rsp will be better than that of the embodiment shown in FIG. 4. In this way, by increasing W1 from the direction close to the gate trench 120 to the direction away from the gate trench 120, the flexibility of adjusting Rsp and short-circuit performance can be further increased.

[0115] Further, please refer to FIG. 10. In some embodiments, the distance between the portions of the adjacent second electric field shielding structures 170 located below the gate trench 120 is equal.

[0116] Further, please refer to FIG. 11. In other embodiments, the distance between the portions of the adjacent second electric field shielding structures 170 located below the gate trench 120 decreases in the direction toward the center of the gate trench 120. It can be understood that, compared with the embodiment shown in FIG. 10, in the case where the minimum distance between the adjacent second electric field shielding structures 170 in the embodiment shown in FIG. 11 is equal to the distance between the portions of the adjacent second electric field shielding structures 170 located below the gate trench 120 in the embodiment shown in FIG. 10, the embodiment shown in FIG. 11 can obtain a greater saturation current and a smaller Rsp.

[0117] Next, please refer to FIG. 12 and FIG. 13. As an alternative embodiment, the trench gate transistor further comprises: a current diffusion layer 230, located in the JFET region 114 below the body region 160, the ion doping concentration of the current diffusion layer 230 is greater than the ion doping concentration of the drift region 113.

[0118] It can be understood that the electric field shielding structure not only protects the bottom of the gate dielectric layer 130, but also forms a JFET between the body region 160. The existence of the parasitic JFET will reduce the current density of the device. In this embodiment, by providing the current diffusion layer 230 in the JFET region 114, the parasitic resistance of the parasitic JFET can be reduced, thereby improving the conductivity of the device.

[0119] The current diffusion layer 230 can be formed by a doping process, for example, an ion implantation process. Exemplarily, the current diffusion layer 230 can have the first conductivity type; in other words, the current diffusion layer 230 has the same conductivity type as the semiconductor material layer 110, but the ion doping concentration of the current diffusion layer 230 is greater than the ion doping concentration of the semiconductor material layer 110.

[0120] Next, please refer to FIG. 14 to FIG. 17. As an alternative embodiment, the trench gate transistor further comprises: an interlayer dielectric layer 210, located in the gate trench 120 and above the gate 140; and a conductive layer 220, located on the semiconductor material layer 110, the conductive layer 220 is insulated and separated from the gate 140 by the interlayer dielectric layer 210.

[0121] It can be understood that the conductive layer 220 is used for electrically connecting with the source contact region 200, but needs to be insulated and separated from the gate 140. Please refer to FIG. 3 to FIG. 7, if the interlayer dielectric layer 210 is arranged on the semiconductor material layer 110, in order to ensure that the interlayer dielectric layer 210 can completely cover the gate 140, it is usually necessary to design the interlayer dielectric layer 210 to be slightly larger than the planar size of the gate 140, so that the arrangement space of the source conductive contact hole is limited. Due to the size limitation of the source conductive contact hole, it is difficult to further reduce the cell size, and it is difficult to continue to iteratively reduce the Rsp. In this embodiment, by arranging the interlayer dielectric layer 210 in the gate trench 120, not only the photolithography process for defining the position of the interlayer dielectric layer 210 is omitted, a self-alignment structure is realized, but also the source conductive contact hole can be avoided, thereby further reducing the cell size, which is conducive to reducing the Rsp.

[0122] The trench gate transistor can further comprise: a drain (not shown in the figure), located on one side of the lower surface 112 of the semiconductor material layer 110. Specifically, the drain is located on the side of the substrate 100 away from the epitaxial layer (semiconductor material layer 110). In actual devices, the drain can be a metal drain.

[0123] It should be noted that the technical features among the technical solutions recorded in the embodiments of the present application can be combined arbitrarily without conflict.

[0124] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes can also be made to the above embodiments without departing from the scope of the present disclosure. Similarly, various technical features of the above embodiments can be combined arbitrarily to form additional embodiments of the present application that can not have been explicitly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the protection scope of the patent of the present application.

Claims

1. A trench gate transistor, characterized by, Comprise: a semiconductor material layer; a gate trench extending from an upper surface of the semiconductor material layer to an interior, the gate trench comprising a sidewall and a bottom wall, the sidewall comprising at least two first portions arranged in intervals along an extending direction and a second portion between adjacent first portions, the extending direction being a direction in which the sidewall extends in a plane in which the upper surface of the semiconductor material layer lies; a first electric field shielding structure located outside the gate trench and adjacent to the first portions; a body region located outside the gate trench and adjacent to the second portion, a portion of the body region close to the gate trench being used to form a channel region; a drift region located below the channel region; a second electric field shielding structure located below the first electric field shielding structure and extending at least partially below the channel region, so that, along the extending direction, a width of the drift region between adjacent second electric field shielding structures is smaller than a width of the channel region.

2. The trench transistor of claim 1, wherein, a bottom of the first electric field shielding structure is farther away from the upper surface of the semiconductor material layer than a bottom of the body region, so that there is a gap between the second electric field shielding structure and the body region; along the extending direction, the width of the drift region between adjacent second electric field shielding structures is smaller than a width between adjacent first electric field shielding structures; and / or, the second electric field shielding structure is spaced apart from the body region by 0.25 μm to 1.2 μm.

3. The trench transistor of claim 1, wherein, an ion doping concentration of the second electric field shielding structure is greater than an ion doping concentration of the first electric field shielding structure.

4. The trench transistor according to claim 1 or 3, wherein an ion doping concentration of the body region is smaller than an ion doping concentration of the first electric field shielding structure and smaller than an ion doping concentration of the second electric field shielding structure.

5. The trench transistor of claim 1, wherein, the width of the drift region between adjacent second electric field shielding structures increases from a direction close to the gate trench to a direction away from the gate trench.

6. The trench transistor of claim 1, wherein, the second electric field shielding structure is adjacent to a bottom of the first electric field shielding structure; the second electric field shielding structure and the first electric field shielding structure are both connected to a ground potential.

7. The trench transistor of claim 1, wherein, the first electric field shielding structure surrounds two sides and the bottom wall of the gate trench.

8. The trench transistor of claim 1, wherein, Further comprise: a third electric field shielding structure located below the gate trench and overlapping with the first electric field shielding structure and / or the second electric field shielding structure, the third electric field shielding structure being conductively connected to the first electric field shielding structure and / or the second electric field shielding structure through the overlapping region.

9. The trench transistor of claim 1, wherein, Further comprise: a current diffusion layer located in a JFET region below the body region, an ion doping concentration of the current diffusion layer being greater than an ion doping concentration of the drift region.

10. The trench transistor of claim 1, wherein, Further comprise: a gate dielectric layer covering the sidewall and the bottom wall of the gate trench; a gate formed on the gate dielectric layer and filling the gate trench; an interlayer dielectric layer located in the gate trench and above the gate; a conductive layer located on the semiconductor material layer, the conductive layer being insulated and isolated from the gate through the interlayer dielectric layer.

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