Array substrate, manufacturing method therefor, motherboard, display panel and display device

Abstract

An array substrate (001), a manufacturing method for an array substrate (001), a motherboard, a display panel (PNL) and a display device. The array substrate (001) comprises: a base substrate (101), which comprises a display area (AA) and a non-display area (BB) surrounding the display area (AA); a plurality of sensing signal lines (102), which are located in the non-display area (BB); a plurality of transistors (103), which are located in the non-display area (BB) and are electrically connected to at least part of the sensing signal lines (102); and a plurality of first detection terminals (104), which are located in the non-display area (BB) and are used for detecting whether the plurality of sensing signal lines (102) and the plurality of transistors (103) are normal, wherein one first detection terminal (104) is arranged corresponding to at least one sensing signal line (102).

Description

Array substrate, manufacturing method thereof, mother board, display panel and display device

[0001] Cross-reference to Related Applications

[0002] This application claims priority to the Chinese Patent Application No. 202410885834.9, filed on July 2, 2024, and entitled "Array substrate, manufacturing method thereof, mother board, display panel and display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to an array substrate, a manufacturing method thereof, a mother board, a display panel and a display device. BACKGROUND

[0004] For decades, the development of the television industry has undergone earth-shattering changes as much as the mobile phone, from the bulky black and white television to the color TV, and now to the large-screen intelligentization. The innovation technology has never stopped changing. With the product update iteration and the higher requirements of the majority of users on display products, it is necessary to continuously break through traditional technology and innovate. In addition to the development in terms of low cost, high transmittance and high contrast, it is also proposed to set sensors on display products, such as adding light sensing and temperature sensing design, to improve the user experience through the setting of sensors. SUMMARY

[0005] The array substrate, the manufacturing method thereof, the mother board, the display panel and the display device provided by the present disclosure have the following specific solutions:

[0006] In one aspect, the present disclosure provides an array substrate, comprising:

[0007] a substrate, comprising a display area and a non-display area surrounding the display area;

[0008] a plurality of sensing signal lines located in the non-display area;

[0009] a plurality of transistors located in the non-display area, the plurality of transistors being electrically connected to at least part of the sensing signal lines;

[0010] a plurality of first detection terminals located in the non-display area, the plurality of first detection terminals being used for detecting whether the plurality of sensing signal lines and the plurality of transistors are normal, and one first detection terminal being provided corresponding to at least one sensing signal line.

[0011] In some embodiments, in the above array substrate provided by the present disclosure, two adjacent sensing signal lines correspond to different first detection terminals.

[0012] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the plurality of sensing signal lines comprises a plurality of first light sensing signal lines, different first light sensing signal lines are electrically connected to the first poles of different transistors;

[0013] An odd number of the first light sensing signal lines correspond to one of the first detection terminals, and an even number of the first light sensing signal lines correspond to another of the first detection terminals.

[0014] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the plurality of sensing signal lines further comprises second light sensing signal lines located on one side of the plurality of first light sensing signal lines, and the second light sensing signal lines are electrically connected to the second poles of the plurality of transistors;

[0015] The second light sensing signal lines correspond to different first detection terminals from the first light sensing signal lines.

[0016] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the plurality of sensing signal lines further comprises third light sensing signal lines located on the side of the second light sensing signal lines away from the plurality of first light sensing signal lines, and the third light sensing signal lines are electrically connected to the gate electrodes of the plurality of transistors;

[0017] The third light sensing signal lines, the second light sensing signal lines, and the first light sensing signal lines correspond to different first detection terminals.

[0018] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the plurality of sensing signal lines further comprises a temperature sensing signal line;

[0019] The temperature sensing signal line, the third light sensing signal line, the second light sensing signal line, and the first light sensing signal line correspond to different first detection terminals.

[0020] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the plurality of sensing signal lines further comprises second light sensing signal lines located on one side of the plurality of first light sensing signal lines, and the second light sensing signal lines are electrically connected to the second poles of the plurality of transistors;

[0021] The second light sensing signal lines correspond to the same first detection terminal as an even number of the first light sensing signal lines.

[0022] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, third light sensing signal lines located on the side of the second light sensing signal lines away from the plurality of first light sensing signal lines are electrically connected to the gate electrodes of the plurality of transistors;

[0023] The third light sensing signal line corresponds to the same first detection terminal as an odd number of the first light sensing signal lines.

[0024] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the plurality of sensing signal lines further include a temperature sensing signal line.

[0025] The temperature sensing signal line corresponds to the same first detection terminal as an even number of the first light sensing signal lines.

[0026] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a plurality of first connection lines are further included, one end of the plurality of first connection lines is integrally arranged on the same first detection terminal on a side away from the display area, and the other end of the plurality of first connection lines is disconnected from each other on different sensing signal lines on a side away from the display area.

[0027] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a plurality of second connection lines are further included, which are arranged in a layer different from the plurality of first connection lines.

[0028] One end of the plurality of second connection lines is integrally arranged on the same first detection terminal on a side away from the display area, and the other end of the plurality of second connection lines is disconnected from each other on different sensing signal lines on a side away from the display area.

[0029] The plurality of second connection lines correspond to different first detection terminals and different sensing signal lines from the plurality of first connection lines.

[0030] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the orthogonal projection of the first connection line on the substrate substrate is arranged alternately with the orthogonal projection of the second connection line on the substrate substrate.

[0031] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a plurality of third connection lines are further included, one end of different third connection lines is integrally arranged with different first detection terminals, and the other end of the plurality of third connection lines is disconnected from each other at the boundary of the array substrate.

[0032] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, different sensing signal lines are electrically connected to different first detection terminals.

[0033] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a plurality of fourth connection lines are further included, which are arranged in the same layer as the plurality of first detection terminals, and a plurality of fifth connection lines are further included, which are arranged in a layer different from the plurality of first detection terminals; wherein,

[0034] Different ends of the fourth connection lines are integrally arranged with different first detection terminals, different ends of the fifth connection lines are electrically connected with different first detection terminals, and the fourth connection lines and the fifth connection lines are alternately arranged with the first detection terminals corresponding thereto; the other ends of the fourth connection lines and the other ends of the fifth connection lines are disconnected with each other at the boundary of the array substrate.

[0035] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, a sixth connection line is further arranged in the same layer as the fourth connection lines, one end of the sixth connection line is integrally arranged with the first detection terminal not corresponding to the fourth connection lines and not corresponding to the fifth connection lines, and the other end of the sixth connection line is disconnected with the other ends of the fourth connection lines and the other ends of the fifth connection lines at the boundary of the array substrate.

[0036] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the non-display area includes a first non-display area where the plurality of detection terminals are located, a second non-display area opposite to the first non-display area, and two third non-display areas connecting the first non-display area and the second non-display area, and the plurality of transistors are located in the second non-display area and the third non-display area.

[0037] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the third non-display area further includes a gate drive circuit and a gate drive circuit signal line electrically connected with the gate drive circuit.

[0038] The plurality of sensing signal lines and the plurality of transistors are located on a side of the gate drive circuit and the gate drive circuit signal line away from the display area.

[0039] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, a sealant surrounding the display area is further included, and the sealant covers at least a connection position of the transistor and the sensing signal line.

[0040] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the gate drive circuit signal line includes a clock signal line located on a side of the gate drive circuit away from the display area, and the sealant further covers a connection position of the clock signal line and the gate drive circuit.

[0041] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the non-display area includes a first non-display area where the plurality of first detection terminals are located, and the first non-display area includes a plurality of fan-out areas.

[0042] The array substrate further comprises a common electrode line between the fan-out areas, the plurality of transistors are located between the fan-out areas and the common electrode line, and the plurality of transistors are arranged obliquely along the edges of the fan-out areas.

[0043] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the gates of the plurality of transistors are arranged approximately in steps along the edges of the fan-out areas, and the gates of the plurality of transistors are integrally provided with one of the sensing lines.

[0044] In another aspect, the embodiments of the present disclosure provide a mother substrate comprising the array substrate provided by the embodiments of the present disclosure, and a plurality of second detection terminals located at the periphery of the array substrate; wherein one of the second detection terminals is electrically connected with at least one of the first detection terminals.

[0045] In some embodiments, in the mother substrate provided by the embodiments of the present disclosure, the array substrate comprises a plurality of third connection lines, and different second detection terminals are electrically connected with different first detection terminals through different third connection lines.

[0046] In some embodiments, in the mother substrate provided by the embodiments of the present disclosure, the array substrate comprises a plurality of fourth connection lines, a sixth connection line provided in the same layer, and a plurality of fifth connection lines provided in a layer different from the plurality of fourth connection lines; wherein,

[0047] One end of different fourth connection lines is integrally provided with different first detection terminals, and the other end of the plurality of fourth connection lines converges at the periphery of the array substrate to be integrally provided with the same second detection terminal;

[0048] One end of different fifth connection lines is electrically connected with different first detection terminals, and the other end of the plurality of fifth connection lines converges at the periphery of the array substrate to be electrically connected with the same second detection terminal;

[0049] One end of the sixth connection line is integrally provided with one of the first detection terminals, and the other end of the sixth connection line is integrally provided with one of the second detection terminals at the periphery of the array substrate;

[0050] The plurality of fourth connection lines, the plurality of fifth connection lines, and the sixth connection line correspond to different first detection terminals and different second detection terminals;

[0051] The plurality of fourth connection lines and the plurality of fifth connection lines cross each other near the boundary of the array substrate;

[0052] The fourth connection line and the fifth connection line are alternately arranged on the substrate substrate in the cross position close to one side of the display area, and the first spacing is provided between the fourth connection line and the fifth connection line adjacent to the orthographic projection.

[0053] The second spacing and the third spacing are provided between the fourth connection line and the fifth connection line adjacent to the cross position away from the display area, and the second spacing, the third spacing and the first spacing are substantially the same.

[0054] In another aspect, the present disclosure provides a manufacturing method of the array substrate, comprising:

[0055] A substrate substrate is provided, and the substrate substrate comprises a plurality of array substrate areas, and each array substrate area comprises a display area and a non-display area surrounding the display area;

[0056] A plurality of sensing signal lines, a plurality of transistors and a plurality of first detection terminals are formed in the non-display area, and the plurality of transistors are electrically connected to at least part of the sensing signal lines, and one first detection terminal is electrically connected to at least one sensing signal line;

[0057] The array substrate areas are cut into a plurality of small plates;

[0058] The first detection terminal and the corresponding sensing signal line are disconnected to form the array substrate.

[0059] In some embodiments, in the manufacturing method provided by the present disclosure, one first detection terminal is electrically connected to at least one sensing signal line, which specifically comprises:

[0060] A plurality of first connection lines and a plurality of second connection lines are formed in different layers; one end of different first connection lines is integrally arranged with different sensing signal lines, the other end of the plurality of first connection lines converges to one first detection terminal; one end of different second connection lines is electrically connected to different sensing signal lines, the other end of the plurality of second connection lines converges to one first detection terminal; and the plurality of second connection lines and the plurality of first connection lines correspond to different first detection terminals and different sensing signal lines.

[0061] In some embodiments, in the manufacturing method provided by the present disclosure, the first detection terminal and the corresponding sensing signal line are disconnected, which specifically comprises:

[0062] The plurality of first connection lines and the plurality of second connection lines are removed to disconnect the first detection terminal and the corresponding sensing signal line; or,

[0063] disconnecting the plurality of first connection lines from the corresponding sensing signal lines, the plurality of first connection lines from the corresponding first detection terminals, the plurality of second connection lines from the corresponding sensing signal lines, the plurality of second connection lines from the corresponding first detection terminals, so that the first detection terminals are disconnected from the corresponding sensing signal lines.

[0064] In some embodiments, in the above manufacturing method provided by the embodiments of the present disclosure, in the forming of the plurality of sensing signal lines, the plurality of transistors and the plurality of first detection terminals in the non-display area and the electrically connecting of the plurality of transistors with at least part of the sensing signal lines and the electrically connecting of one of the first detection terminals with at least one of the sensing signal lines, the method further comprises:

[0065] forming a plurality of second detection terminals in the periphery of the array substrate area and electrically connecting one of the second detection terminals with at least one of the first detection terminals;

[0066] cutting the array substrate area into a plurality of small plates, and the method further comprises:

[0067] removing the plurality of second detection terminals and making each of the first detection terminals independent of each other at the end corresponding to the second detection terminals.

[0068] In some embodiments, in the above manufacturing method provided by the embodiments of the present disclosure, the electrically connecting of one of the second detection terminals with at least one of the first detection terminals specifically comprises:

[0069] forming a plurality of fourth connection lines, sixth connection lines in the same layer and a plurality of fifth connection lines in different layers from the plurality of fourth connection lines; and integrally arranging one end of each of the fourth connection lines with a different first detection terminal and the other end of each of the fourth connection lines to the same second detection terminal in the periphery of the array substrate; electrically connecting one end of each of the fifth connection lines with a different first detection terminal and the other end of each of the fifth connection lines to the same second detection terminal in the periphery of the array substrate; integrally arranging one end of the sixth connection line with one of the first detection terminals and the other end of the sixth connection line with one of the second detection terminals in the periphery of the array substrate; and the plurality of fourth connection lines, the plurality of fifth connection lines and the sixth connection line correspond to different first detection terminals and different second detection terminals.

[0070] removing the plurality of second detection terminals and making each of the first detection terminals independent of each other at the end corresponding to the second detection terminals, specifically comprising:

[0071] The plurality of second detection terminals are cut off, and the plurality of fourth connection lines, the plurality of fifth connection lines and the sixth connection line outside the periphery of the array substrate are cut off, so that the fourth connection line, the fifth connection line and the sixth connection line corresponding to each first detection terminal are disconnected from each other at the boundary of the array substrate.

[0072] In another aspect, the display panel provided by the embodiments of the present disclosure includes the array substrate provided by the embodiments of the present disclosure and an opposite substrate opposite to the array substrate.

[0073] In some embodiments, in the display panel provided by the embodiments of the present disclosure, the opposite substrate includes a black matrix covering part of the transistors and a color resistance covering the remaining transistors.

[0074] In another aspect, the display device provided by the embodiments of the present disclosure includes the display panel provided by the embodiments of the present disclosure and a backlight module located on the light-incident side of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0075] FIG. 1 is a structural schematic diagram of an array substrate provided by the embodiments of the present disclosure;

[0076] FIG. 2 is an enlarged structural schematic diagram of a Z1 region in FIG. 1;

[0077] FIG. 3 is an enlarged structural schematic diagram of a Z2 region in FIG. 1;

[0078] FIG. 4 is another enlarged structural schematic diagram of the Z2 region in FIG. 1;

[0079] FIG. 5 is another enlarged structural schematic diagram of the Z1 region in FIG. 1;

[0080] FIG. 6 is another enlarged structural schematic diagram of the Z2 region in FIG. 1;

[0081] FIG. 7 is another enlarged structural schematic diagram of the Z2 region in FIG. 1;

[0082] FIG. 8 is another structural schematic diagram of an array substrate provided by the embodiments of the present disclosure;

[0083] FIG. 9 is another structural schematic diagram of an array substrate provided by the embodiments of the present disclosure;

[0084] FIG. 10 is an enlarged structural schematic diagram of a Z3 region in FIG. 9;

[0085] FIG. 11 is an enlarged structural schematic diagram of a Z4 region in FIG. 10;

[0086] FIG. 12 is a structural schematic diagram of an array substrate and AT detection terminals in the periphery thereof in a motherboard provided by the embodiments of the present disclosure;

[0087] FIG. 13 is an enlarged structural schematic view of the Z5 region in FIG. 12;

[0088] FIG. 14 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure;

[0089] FIG. 15 is a structural schematic view of a display panel provided by an embodiment of the present disclosure;

[0090] FIG. 16 is a structural schematic view of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0091] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. It should be noted that, in the drawings, the thicknesses of layers, films, panels, regions and the like are exaggerated for clarity. In the present disclosure, example embodiments are described with reference to cross-sectional views that are schematic but are intended to be as realistic as possible. As such, the shapes of the figures shown in the drawings will be expected to deviate in some aspects from what is shown in the drawings as a consequence of, for example, manufacturing processes and / or tolerances. Thus, embodiments described in the present disclosure are not to be construed as being limited to the particular shapes of regions as illustrated in the drawings but are to include deviations in shapes that result from, for example, manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features; an illustrated sharp angle can be rounded, etc. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and do not reflect true scales, but are merely intended to schematically illustrate the present disclosure. Like or similar designations in the drawings indicate like or similar elements or elements with like or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of known functions and known components.

[0092] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning as is commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", and similar terms do not denote any order, quantity, or importance, but are used to distinguish one element from another, and the terms "comprises", "comprising", "includes", "including" and the like can be used herein and mean including but not limited to as set out herein. The terms "connected", "coupled", and the like, can be used herein and mean one or more elements or components connected or coupled at least indirectly together, whether connected or coupled directly together or connected or coupled indirectly together, via other elements or components. The terms "inner", "outer", "up", "down", and the like, can be used herein and mean relative positions for clarity only and can change according to different viewpoints or absolute positions of the described objects.

[0093] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on the other element or layer, directly connected to the other element or layer, or an intervening element or layer can be present. When an element or layer is referred to as being "on one side of" another element or layer, it can be directly on the side of the other element or layer, directly connected to the other element or layer, or an intervening element or layer can be present. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" another element or layer, there is no intervening element or layer. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0094] With the popularization of intelligent display, the light and temperature sensor design integrated in the display panel gradually appears in some large-size display panels. This design has higher accuracy and does not affect the size of the frame, and has obvious advantages compared with the existing products integrated on the circuit board or the outer frame.

[0095] In order to save cost and improve yield, the array section and the cell section of the light and temperature sensor integrated in the display panel need to be detected, and if there is a defect, the product needs to be graded. However, since the normal array section and cell section detection is a detection of whether the display function of the display panel is abnormal, the positions of the light and temperature sensor are all outside the display area, and are not related to the normal display function of the display panel. Therefore, the array section and cell section detection of the display panel for normal display cannot detect the light and temperature sensor.

[0096] To solve the above technical problems, the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 1 to FIG. 5, can include:

[0097] The substrate 101 includes a display area AA and a non-display area BB surrounding the display area AA. The non-display area BB includes a first non-display area BB1 provided with a binding area BD, a second non-display area BB2 opposite to the first non-display area BB1, and a third non-display area BB3 connecting the first non-display area BB1 and the second non-display area BB2. In some embodiments, the display area AA includes red sub-pixel areas, green sub-pixel areas, blue sub-pixel areas, etc. arranged in an array. The substrate 101 is a substrate allowing visible light to pass through, such as a glass, quartz, plastic, etc.

[0098] A plurality of sensing signal lines 102 and a plurality of transistors 103 are located in the non-display area BB. The plurality of transistors 103 are electrically connected to at least part of the sensing signal lines 102. Each transistor 103 can be composed of a plurality of (for example, 40-10) small-sized transistors in parallel. In some embodiments, FIG. 1 shows three light sensing components S1-S3 composed of the plurality of transistors 103. The first light sensing component S1 of the second non-display area BB2 includes a first transistor S1D covered by a black matrix, a second transistor S1R covered by a red color filter, a third transistor S1G covered by a green color filter, and a fourth transistor S1B covered by a blue color filter. The second light sensing component S2 of the left third non-display area BB3 includes a fifth transistor S2D covered by a black matrix and a sixth transistor S2G covered by a green color filter. The third light sensing component S3 of the right third non-display area BB3 includes a seventh transistor S3D covered by a black matrix and an eighth transistor S3G covered by a green color filter. The plurality of sensing signal lines 102 include a temperature sensing signal line TS, a plurality of first light sensing signal lines ASS electrically connected to the first poles of the different transistors 103, a second light sensing signal line ASD electrically connected to the second poles of all the transistors 103, and a third light sensing signal line ASG electrically connected to the gates of all the transistors 103.

[0099] The plurality of first detection terminals 104 are located in the non-display area BB, for example, the first detection terminals 104 are located in the binding area BD of the first non-display area BB1; the binding area BD can also be provided with data terminals D1, D2 (electrically connected with the data line DL) and common electrode terminals Com (electrically connected with the common electrode line CL) for detecting display functions; optionally, the plurality of first detection terminals 104 are used for detecting whether the plurality of sensing signal lines 102 and the plurality of transistors 103 are normal, and one first detection terminal 104 is arranged corresponding to at least one sensing signal line 102. It should be noted that in the present disclosure, “one first detection terminal 104 is arranged corresponding to at least one sensing signal line 102” can be understood as: in the Cell section, one first detection terminal 104 is electrically connected with the corresponding at least one sensing signal line 102, so that in the detection process, one first detection terminal 104 can load a detection signal for the corresponding at least one sensing signal line 102; after the detection is completed, the first detection terminal 104 is disconnected with the corresponding at least one sensing signal line 102, so as to ensure that the different sensing signal lines 102 are disconnected with each other, thereby avoiding crosstalk between the sensing signal lines 102. In addition, after the detection is completed, the operator can be reminded to judge the product function by a simple signal light alarm and the like. For example, a red signal light indicates that there is a defect, and a green signal light indicates that the product is qualified.

[0100] In the embodiments of the present disclosure, when the number of the first detection terminals 104 is sufficient, the sensing signal lines 102 can be connected one by one corresponding to the first detection terminals 104; when the number of the first detection terminals 104 is limited, two or more sensing signal lines 102 can share one first detection terminal 104; thereby realizing the sensing function detection of the sensing signal lines 102 and the transistors 103 electrically connected therewith. In some embodiments, the first detection terminals 104 can be idle terminals in the related detection terminal group (used for realizing display function detection), so that the structure of the detection terminal group does not need to be changed, the compatibility with related products is higher, and the cost can be effectively saved.

[0101] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIG. 1, the plurality of first detection terminals 104 are divided into two groups, i.e., a first detection assembly CT1 and a second detection assembly CT2. Optionally, the temperature sensing signal line TS, the second light sensing signal line ASD and the third light sensing signal line ASG are signal lines that are broken only in the first non-display area BB1 and surround the display area AA, and therefore, the corresponding first detection terminals 104 can be arranged on the first detection assembly CT1 and the second detection assembly CT2 to detect the disconnection failure of the temperature sensing signal line TS, the second light sensing signal line ASD and the third light sensing signal line ASG. The first light sensing signal line ASS is not a signal line that surrounds the screen, but a signal line that goes in the plane and does not come out, and therefore, the characteristics of the transistor 103 need to be detected in combination with the detection scheme, specifically, if the current of the transistor 103 can be normally detected, it means that the first light sensing signal line ASS has no disconnection; if the current cannot be detected, it means that the first light sensing signal line ASS is disconnected.

[0102] In some embodiments, the first detection assembly CT1 and the second detection assembly CT2 can correspond to half of the first light sensing signal lines ASS, for example, in FIG. 1, the first detection assembly CT1 and the second detection assembly CT2 correspond to 4 first light sensing signal lines ASS. In some embodiments, the more the transistors 103, the more the first light sensing signal lines ASS required, and the more the first light sensing signal lines ASS corresponding to the first detection assembly CT1 and the second detection assembly CT2. The present disclosure takes the first detection assembly CT1 and the second detection assembly CT2 corresponding to 4 first light sensing signal lines ASS as an example to illustrate the specific arrangement scheme of the first detection terminals 104 of a detection assembly (for example, CT1 or CT2) and the sensing signal lines 102.

[0103] In some embodiments, as shown in FIGS. 2 to 5, two adjacent sensing signal lines 102 can correspond to different first detection terminals 104, so as to facilitate the short circuit detection of the two adjacent sensing signal lines 102. If the resistance between the two adjacent signal lines 102 is small (for example, less than a preset value), it means that the two are short-circuited, otherwise, it means that there is no short circuit.

[0104] As can be seen from FIGS. 2 to 5, four first light sensing signal lines ASS, one second light sensing signal line ASD, one third light sensing signal line ASG and one temperature sensing signal line TS can be arranged in sequence from left to right, wherein the odd first light sensing signal lines ASS can correspond to the same first detection terminal 104, and the even first light sensing signal lines ASS can correspond to another first detection terminal 104.

[0105] Specifically, in FIG. 2, the number of first detection terminals 104 is sufficient, and four first light sensing signal lines ASS, one second light sensing signal line ASD, one third light sensing signal line ASG, and one temperature sensing signal line TS can be respectively arranged to correspond to one first detection terminal 104, so that not only the short circuit between adjacent sensing signal lines 102 and the short circuit between the source and the drain of the transistor 103 (i.e., channel bridge) can be detected, but also the open circuit of the single sensing signal line 103 and the conduction characteristics of the transistor 103 can be detected. The transistor 103 can be regarded as a fixed source-drain current Ids after a fixed gate voltage Vgs and a fixed source-drain voltage difference Vds are obtained. Therefore, after a fixed Vgs and Vds are given, whether the current size meets the standard can be used as a detection scheme for judging the characteristics of the transistor 103, that is, the test characteristic curve is simplified to a test single-point current value. However, if this detection is to be realized, each light sensing signal line ASS, ASD, and ASG needs to have a corresponding first detection terminal 104, and if the number of first detection terminals 104 is insufficient, the detection cannot be realized.

[0106] In FIG. 3, the first detection terminal 104 is 5, at this time, the temperature sensing signal line TS, the third light sensing signal line ASG, the second light sensing signal line ASD, the odd first light sensing signal line ASS, and the even first light sensing signal line ASS can be respectively arranged to correspond to one first detection terminal 104, so that the connection can detect the short circuit between adjacent sensing signal lines 102, the short circuit between the source and the drain of the transistor 103 (i.e., channel bridge), and the open circuit of the temperature sensing signal line TS, the third light sensing signal line ASG, and the second light sensing signal line ASD.

[0107] In FIG. 4, the first detection terminal 104 is 3, at this time, the second light sensing signal line ASD can be arranged to correspond to one first detection terminal 104, the third light sensing signal line ASG and the odd first light sensing signal line ASS can be commonly arranged to correspond to one first detection terminal 104, and the temperature sensing signal line TS and the even first light sensing signal line ASS can be commonly arranged to correspond to one first detection terminal 104, so that the short circuit between adjacent sensing signal lines 102, the short circuit between the source and the drain of the transistor 103 (i.e., channel bridge), and the open circuit of the temperature sensing signal line TS, the third light sensing signal line ASG, and the second light sensing signal line ASD can be detected.

[0108] In FIG. 5, the first detection terminal 104 is 2, at this time the third light sensing signal line ASG and the odd first light sensing signal line ASS correspond to a first detection terminal 104, the second light sensing signal line ASD and the temperature sensing signal line TS and the even first light sensing signal line ASS correspond to a first detection terminal 104, so that the connection can detect the short circuit between the adjacent sensing signal lines 102, and the temperature sensing signal line TS, the third light sensing signal line ASG and the second light sensing signal line ASD are disconnected.

[0109] In some embodiments, FIG. 6 and FIG. 7 are another enlarged structure diagram of the Z2 region in FIG. 1. As shown in FIG. 1, FIG. 6 and FIG. 7, in the array substrate provided in the embodiments of the present disclosure, a plurality of first connection lines 105 can also be included, one end of the plurality of first connection lines 105 is integrally arranged on the same first detection terminal 104 away from the display area AA, and the other end of the plurality of first connection lines 105 is disconnected from each other on different sensing signal lines 102 away from the display area AA. In the Cell section detection scheme, these first connection lines 105 can connect one first detection terminal 104 and a plurality of sensing signal lines 102, so that the detection signal of the first detection terminal 104 is transmitted to the plurality of sensing signal lines 102 for detection through the plurality of first connection lines 105. After detection is completed, the first connection line 105 needs to be disconnected from the first detection terminal 104 and the sensing signal line 102, which does not affect subsequent use. Of course, in some embodiments, the first connection line 105 can also be cut off to ensure that the plurality of sensing signal lines 102 and the corresponding first detection terminal 104 are disconnected from each other.

[0110] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIG. 1, FIG. 6 and FIG. 7, a plurality of second connection lines 106 can also be included, which are arranged in a layer different from the plurality of first connection lines 105. Optionally, the first connection line 105 is located in the gate metal layer (Gate), and the second connection line 106 is located in the source-drain metal layer (SD); one end of the plurality of second connection lines 106 is integrally arranged on the same first detection terminal 104 away from the display area AA, and the other end of the plurality of second connection lines 106 is disconnected from each other on different sensing signal lines 102 away from the display area AA; and the plurality of second connection lines 106 correspond to different first detection terminals 104 and different sensing signal lines 102 of the plurality of first connection lines 105.

[0111] In the cell segment detection scheme, the second connection lines 106 can connect the first detection terminal 104 and the plurality of sensing signal lines 102, so that the detection signal of the first detection terminal 104 is transmitted to the plurality of sensing signal lines 102 through the plurality of second connection lines 106 for detection. After the detection is completed, the second connection lines 106 need to be disconnected from the first detection terminal 104 and the sensing signal lines 102, without affecting the subsequent use. Of course, in some embodiments, the second connection lines 106 can also be cut off to ensure that the plurality of sensing signal lines 102 and the corresponding first detection terminal 104 are disconnected from each other.

[0112] In addition, compared with the first connection line 105 and the second connection line 106 arranged in the same layer, the first connection line 105 and the second connection line 106 arranged in different layers in the present disclosure can reduce the width of the first non-display area BB1, and realize the narrow frame design. Optionally, the orthogonal projection of the first connection line 105 on the substrate 101 and the orthogonal projection of the second connection line 106 on the substrate 101 are arranged alternately, which can increase the spacing of the wiring in the same layer, reduce the short-circuit probability of the wiring in the same layer, and avoid the coupling capacitance caused by the opposite arrangement of the wiring in different layers, and cause signal mutual interference.

[0113] In some embodiments, as shown in FIG. 7, the temperature sensing signal line TS can be arranged corresponding to a first detection terminal 104 through a wire TSL, and the wire TSL and the first connection line 105 are arranged in the same layer and the same material (for example, in the gate metal layer). In order to avoid the short circuit of the first connection line 105 and the wire TSL, the first connection line 105 can be arranged to be disconnected at the wire TSL, and the disconnected first connection line 105 is connected by a jumper JW. Optionally, the jumper JW and the second connection line 106 are arranged in the same layer and the same material (for example, in the source-drain metal layer).

[0114] In some embodiments, as shown in FIGS. 2 and 13, in the array segment, the first detection terminal 104 can also be connected to the sensing signal line 102 one by one through the seventh connection line 114; before the detection of the cell segment is completed, the first detection terminal 104 can still be connected to the sensing signal line 102 one by one through the seventh connection line 114; after the detection of the cell segment is completed, the seventh connection line 114 needs to be cut off, or the electrical connection relationship between the first connection line 114 and the first detection terminal 104 and the sensing signal line 102 is disconnected.

[0115] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 1, FIG. 3 to FIG. 5, a plurality of third connection lines 107 can also be included, one end of each of the third connection lines 107 is integrally arranged with a different first detection terminal 104, and the other end of each of the third connection lines 107 is disconnected from each other at the boundary of the array substrate. The third connection lines 107 can electrically connect the first detection terminals 104 with the detection terminals on the motherboard (i.e., array test pads located at the periphery of the array substrate), so that the sensing signal lines 102 and the transistors 103 are subjected to yield detection by loading the detection signal to the AT detection terminals on the motherboard. During the process of cutting the motherboard into a plurality of small boards, the AT detection terminals at the periphery of the array substrate and the local part of the plurality of third connection lines 107 at the periphery of the array substrate are cut off.

[0116] In some embodiments, in the case that the number of AT detection terminals is insufficient but the number of CT detection terminals (i.e., the first detection terminals 104) is sufficient, the scheme of reserving all the CT detection terminals (i.e., the first detection terminals 104) and short-circuiting the AT detection terminals in an odd-even manner can be adopted. Accordingly, as shown in FIG. 2, the array substrate can also include a plurality of fourth connection lines 108 arranged in the same layer as the plurality of first detection terminals 104, and a plurality of fifth connection lines 109 arranged in different layers from the plurality of first detection terminals 104; one end of each of the fourth connection lines 108 is integrally arranged with a different first detection terminal 104, one end of each of the fifth connection lines 109 is electrically connected with a different first detection terminal 104, and the corresponding first detection terminals 104 of the fourth connection lines 108 and the fifth connection lines 109 are arranged alternately; the other end of each of the fourth connection lines 108 and the other end of each of the fifth connection lines 109 are disconnected from each other at the boundary of the array substrate. In the array segment, the plurality of fourth connection lines 108 connect some of the first detection terminals 104 to the same AT detection terminal, and the plurality of fifth connection lines 109 connect some of the first detection terminals 104 to another AT detection terminal, so that a small number of AT detection terminals can be used to detect the sensing signal lines 102 and the transistors 103. Optionally, in order to reduce the short-circuiting probability of the wiring in the same layer and the coupling capacitance of the wiring in different layers, the orthogonal projection of the fourth connection lines 108 on the substrate 101 and the orthogonal projection of the fifth connection lines 109 on the substrate 101 can be arranged alternately inside the array board.

[0117] In some embodiments, as shown in FIG. 2, the array substrate provided by the present disclosure can further include a sixth connection line 110 arranged in the same layer as the plurality of fourth connection lines 108, one end of the sixth connection line 110 being integrally arranged with the first detection terminal 104 that does not correspond to the plurality of fourth connection lines 108 and the plurality of fifth connection lines 109, and the other end of the sixth connection line 110 being disconnected from the other end of the plurality of fourth connection lines 108 and the other end of the plurality of fifth connection lines 109 at the boundary of the array substrate. In this way, in the array section, the corresponding one first detection terminal 104 and one AT detection terminal can be connected by using the sixth connection line 110, so as to realize detection of the sensing signal line 102 and the transistor 103. In the cell section, the fourth connection line 108, the fifth connection line 109 and the sixth connection line 110 are disconnected, which does not affect the normal use of the sensing signal line 102.

[0118] In some embodiments, the transistor 103 and the sensing signal line 102 are located inside the gate driving circuit area GOA (provided with a gate driving circuit and a gate driving circuit signal line electrically connected with the gate driving circuit) and close to the AA area, which makes the output signal line Gout (electrically connected with the gate line GL) of the gate driving circuit overlap with the sensing signal line 102. If a short circuit occurs at the overlapping position, the GOA output will be affected, and the risk of quality problems will greatly increase. At the same time, the sensing signal line 102 overlaps with the Gout line more, and is more likely to generate electrostatic ESD, which can cause product problems.

[0119] In order to solve the above problems, FIG. 8 shows another structure diagram of the array substrate provided by the embodiment of the present disclosure. As shown in FIG. 8, in the third non-display area BB3, the light sensing assembly S2&S3 composed of the sensing signal line 102 and the plurality of transistors 103 are located on the side of the gate driving circuit area GOA away from the display area AA, so as to avoid the yield problem caused by the intersection of the sensing signal line 102 and the gate driving circuit signal line.

[0120] In some embodiments, the present disclosure can further include a sealant (Seal) surrounding the display area AA, the sealant (Seal) covering at least the connection position of the transistor 103 and the sensing signal line 102, so as to avoid water and oxygen corrosion of the via at the connection position. Optionally, the gate driving circuit signal line includes a clock signal line (CLK) located on the side of the gate driving circuit away from the display area AA, and the sealant (Seal) further covers the connection position of the clock signal line (CLK) and the gate driving circuit, so as to avoid water and oxygen corrosion of the via at the connection position.

[0121] In some embodiments, FIG. 9 shows another structural schematic diagram of an array substrate provided by the embodiments of the present disclosure, FIG. 10 is an enlarged structural schematic diagram of the Z3 region in FIG. 9, and FIG. 11 is an enlarged structural schematic diagram of the Z4 region in FIG. 10. As shown in FIGS. 9-11, the first non-display area BB1 can include a plurality of fan-out areas FA, and the adjacent two fan-out areas FA have a common electrode line 111 therebetween. The sensing signal line 102 and the transistor 103 can be located between the fan-out area FA (provided with a plurality of fan-out lines FL) and the common electrode line 111, so as to avoid the intersection of the sensing signal line 102 and the fan-out line FL, and the gate driving circuit signal line. Optionally, in order to save space, the transistor 103 can be arranged obliquely along the edge of the fan-out area FA. In some embodiments, the gates G of the plurality of transistors 103 are arranged approximately in steps along the edge of the fan-out area FA, and the gates G of the plurality of transistors are integrally provided through a sensing line (i.e., a third light sensing signal line ASG). In some embodiments, the gate G of the transistor 103 is in a rectangular shape, and the adjacent gates G are arranged staggeredly, with a sensing line (i.e., a third light sensing signal line ASG) connecting the adjacent gates G, and the staggered trend of the plurality of adjacent gates G is the same as the extending trend of the edge of the fan-out area FA. It should be noted that, in order to improve the detection accuracy, the transistor 103 can be simultaneously provided between the fan-out areas FA, and in the second non-display area BB2 and the third non-display area BB3.

[0122] In some embodiments, in order to improve the process uniformity, as shown in FIGS. 9-11, a dummy transistor 112 can be provided between the fan-out areas FA where no transistor 103 is provided, and between the transistors 103. The structure of the dummy transistor 112 can be the same as that of the transistor 103, for example, both can include a plurality of small-size separate transistors TFT as shown in FIG. 11, and the difference is that the first pole of the dummy transistor 112 is not connected to the first light sensing signal line ASS, and the second pole of the dummy transistor 112 is not connected to the second light sensing signal line ASD. Moreover, in the case where one transistor 103 is composed of a plurality of (for example, 40-100) small-size separate transistors TFT in parallel, the wiring space can be fully utilized, which is conducive to achieving a narrow frame effect.

[0123] In some embodiments, as shown in FIG. 3, FIG. 4, FIG. 6 and FIG. 7, the array substrate provided by the embodiments of the present disclosure can be configured to achieve the following purposes. In the array substrate, the sensing signal line 102 is connected to the driving circuit (for example, the circuit with the COF) through bonding, and the first detection terminal 104 is configured to receive the detection signal provided by the detection device. In the bonding area BD, the sensing signal line 102 and the first detection terminal 104 are respectively provided with corresponding switching electrodes 113. Optionally, the switching electrodes 113 are configured in the same layer and of the same material as the transparent electrodes (pixel electrodes and / or common electrodes) on the top layer of the array substrate. The sensing signal line 102 (which can be located in the gate metal layer) in the bonding area BD and the corresponding switching electrode 113 together serve as a bonding terminal, and the sensing signal line 102 and the corresponding switching electrode 113 in the bonding area BD are connected through a via. The first detection terminal 104 can be located in the gate metal layer, and the first detection terminal 104 and the corresponding switching electrode 113 together serve as a detection pad, and the first detection terminal 104 is electrically connected to the corresponding switching electrode 113 through a via. In addition, in order to improve the etching uniformity, dummy lines DY of the same layer and of the same material as the switching electrodes 113 and / or the sensing signal lines 102 can be arranged between the sensing signal lines 102 in the bonding area BD, between the first detection terminals 104, and in other large blank areas without effective patterns (for example, for achieving sensing function, display function, etc.). The other essential components in the array substrate should be understood by those skilled in the art, and are not described here in detail, and should not be regarded as a limitation on the present disclosure.

[0124] Based on the same inventive concept, the embodiments of the present disclosure provide a mother board, comprising a plurality of array substrates 001 provided by the above-mentioned embodiments of the present disclosure, and a plurality of second detection terminals 002 located at the periphery of the array substrate 001. One second detection terminal 002 is electrically connected to at least one first detection terminal 104, and the second detection terminal 002 can be used to detect the sensing signal line 102 and the transistor 103 in the array segment. Optionally, the periphery of the array substrate 001 is further provided with test terminals 1-16 for detecting display function.

[0125] FIG. 12 and FIG. 13 specifically show two groups of second detection terminals 002 outside the array substrate 001, each group of second detection terminals 002 includes three (i.e. three terminals marked as 17, 18, 19), one of the second detection terminals 002 is electrically connected to one first detection terminal 104 through the sixth connection line 110, another second detection terminal 002 is electrically connected to multiple first detection terminals 104 through multiple fifth connection lines 109, and the other second detection terminal 002 is electrically connected to multiple first detection terminals 104 through multiple fourth connection lines 108. Of course, in some embodiments, the second detection terminals 002 can also be electrically connected to the first detection terminals 104 one by one through the third connection lines 107, which is not limited in the present disclosure.

[0126] Continuing to refer to FIG. 12 and FIG. 13, it can be seen that the multiple fourth connection lines 108 and the multiple fifth connection lines 108 intersect each other near the boundary of the array substrate 001 (equivalent to the cutting line); and on one side of the intersection position CP close to the display area AA, the orthogonal projection of the fourth connection line 108 on the substrate 101 and the orthogonal projection of the fifth connection line 109 on the substrate 101 are arranged alternately, and the first interval is provided between the adjacent fourth connection line 108 and the fifth connection line 105; on the side of the intersection position CP away from the display area AA, the second interval is provided between the adjacent fourth connection lines 108, and the third interval is provided between the adjacent fifth connection lines 109, the second interval, the third interval and the first interval are substantially the same, so that the multiple fourth connection lines 108 converge to the corresponding second detection terminal 002, and the multiple fifth connection lines 109 converge to the corresponding second detection terminal 002.

[0127] It should be noted that in the embodiments provided in the present disclosure, due to the limitation of process conditions or the influence of other factors such as measurement, “substantially the same” may be completely identical, or there may be some deviation (for example, a deviation of ±5%), therefore, as long as the error is allowed, the relationship between the related features “substantially the same” belongs to the protection scope of the present disclosure.

[0128] Based on the same inventive concept, the present disclosure provides a manufacturing method of the above-mentioned array substrate, since the principle of the manufacturing method solving the problem is similar to the principle of the above-mentioned array substrate solving the problem, therefore, the implementation of the manufacturing method can refer to the embodiments of the above-mentioned array substrate, and the repeated parts will not be described herein.

[0129] In some embodiments, as shown in FIG. 14, the manufacturing method of the above-mentioned array substrate provided by the embodiments of the present disclosure can include the following steps:

[0130] S1401, providing a substrate, the substrate includes multiple array substrate areas, and each array substrate area includes a display area and a non-display area surrounding the display area.

[0131] S1402, a plurality of sensing signal lines, a plurality of transistors, and a plurality of first detection terminals are formed in the non-display area, and the plurality of transistors are electrically connected to at least part of the sensing signal lines, and one first detection terminal is electrically connected to at least one sensing signal line.

[0132] S1403, the array substrate area is cut into a plurality of small plates. At this time, the first detection terminal on each small plate is electrically connected to at least one sensing signal line, and the first detection terminal can be used to detect the sensing signal line and the transistor;

[0133] S1404, the first detection terminal is disconnected from the corresponding sensing signal line to form an array substrate. At this time, there is no signal crosstalk between different sensing signal lines.

[0134] In some embodiments, in the above manufacturing method provided by the embodiments of the present disclosure, one first detection terminal in the above step S1402 is electrically connected to at least one sensing signal line, which can be realized by the following way:

[0135] A plurality of first connection lines and a plurality of second connection lines are formed in different layers; one end of different first connection lines is integrally arranged with different sensing signal lines, the other end of the plurality of first connection lines converges to one first detection terminal; one end of different second connection lines is electrically connected to different sensing signal lines, the other end of the plurality of second connection lines converges to one first detection terminal; and the plurality of second connection lines and the plurality of first connection lines correspond to different first detection terminals and different sensing signal lines.

[0136] In some embodiments, in the above manufacturing method provided by the embodiments of the present disclosure, the above step S1404, disconnecting the first detection terminal from the corresponding sensing signal line, can be realized by the following way:

[0137] The plurality of first connection lines and the plurality of second connection lines are removed to disconnect the first detection terminal from the corresponding sensing signal line; or the plurality of first connection lines, the plurality of first connection lines and the corresponding first detection terminal, the plurality of second connection lines and the corresponding sensing signal line, and the plurality of second connection lines and the corresponding first detection terminal are disconnected to disconnect the first detection terminal from the corresponding sensing signal line.

[0138] In some embodiments, in the above manufacturing method provided by the embodiments of the present disclosure, while performing the above step S1402, a plurality of sensing signal lines, a plurality of transistors, and a plurality of first detection terminals are formed in the non-display area, and the plurality of transistors are electrically connected to at least part of the sensing signal lines, and one first detection terminal is electrically connected to at least one sensing signal line, the following steps can also be performed:

[0139] A plurality of second detection terminals are formed in the periphery of the array substrate region, and one second detection terminal is electrically connected to at least one first detection terminal;

[0140] Correspondingly, while performing the above step S1403, the array substrate region is divided into a plurality of small plates, the following step can also be performed:

[0141] The plurality of second detection terminals are removed, and one end of each first detection terminal corresponding to the second detection terminal is independent of each other.

[0142] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, the electrical connection of one second detection terminal to at least one first detection terminal can be achieved in the following way:

[0143] A plurality of fourth connection lines and sixth connection lines are formed in the same layer, and a plurality of fifth connection lines are formed in a different layer from the plurality of fourth connection lines; one end of each different fourth connection line is integrally arranged with a different first detection terminal, and the other end of the plurality of fourth connection lines converges to a same second detection terminal in the periphery of the array substrate; one end of each different fifth connection line is electrically connected to a different first detection terminal, and the other end of the plurality of fifth connection lines converges to a same second detection terminal in the periphery of the array substrate; one end of the sixth connection line is integrally arranged with a first detection terminal, and the other end of the sixth connection line is integrally arranged with a second detection terminal in the periphery of the array substrate; and the plurality of fourth connection lines, the plurality of fifth connection lines, and the sixth connection line correspond to different first detection terminals and different second detection terminals;

[0144] Correspondingly, the plurality of second detection terminals are removed, and one end of each first detection terminal corresponding to the second detection terminal is independent of each other, which can be achieved in the following way:

[0145] The plurality of second detection terminals are cut off, and the plurality of fourth connection lines, the plurality of fifth connection lines, and the sixth connection line in the periphery of the array substrate region are also cut off, so that the fourth connection line, the fifth connection line, and the sixth connection line corresponding to each first detection terminal are disconnected from each other at the boundary of the array substrate.

[0146] Based on the same inventive concept, the embodiments of the present disclosure provide a display panel, and FIG. 15 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure. As shown in FIG. 15, the display panel of the present disclosure includes the above array substrate 001 provided by the embodiments of the present disclosure, and a counter substrate 002 opposite to the array substrate 001. Since the problem-solving principle of the display panel is similar to that of the above array substrate, the implementation of the display panel can be referred to the embodiments of the array substrate, and the repeated parts will not be described here.

[0147] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the counter substrate 002 can include a black matrix BM and color resist CF (for example, including red color resist, green color resist, and blue color resist), wherein the black matrix BM covers part of the transistors 103, and the color resist CF covers the remaining transistors 103, so as to realize detection of ambient light brightness and color temperature by using the transistors 103 covered by the black matrix BM as a control group in combination with the transistors 103 covered by the color resist CF.

[0148] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 15, a liquid crystal layer 003 can also be arranged between the array substrate 001 and the counter substrate 002, a first polarizer 004 can be arranged on the side of the array substrate 001 away from the counter substrate 002, a second polarizer 005 can be arranged on the side of the counter substrate 002 away from the array substrate 001, and the polarization direction of the first polarizer 004 is perpendicular to the polarization direction of the second polarizer 005. Other essential components in the display panel should be understood by those skilled in the art, and will not be described here in detail, nor should they be regarded as a limitation on the present disclosure.

[0149] Based on the same inventive concept, the embodiments of the present disclosure provide a display device, as shown in FIG. 16, which includes the above-mentioned display panel PNL provided in the embodiments of the present disclosure, and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU can be a direct type backlight module or a side type backlight module. Optionally, the side type backlight module can include a lamp strip, a reflector arranged in a stacked manner, a light guide plate, a diffusion sheet, a prism group, etc., and the lamp strip is located on one side of the light guide plate in the thickness direction. The direct type backlight module can include a matrix light source, a reflector arranged in a stacked manner on the light-incident side of the matrix light source, a diffusion plate, a brightness enhancement film, etc., and the reflector includes an opening corresponding to the position of each lamp bead in the matrix light source. The lamp bead in the lamp strip and the lamp bead in the matrix light source can be a light emitting device (LED), for example, a quantum dot light emitting device.

[0150] In some embodiments, the lamp bead can also be a micro light emitting device (such as Mini LED, Micro LED), etc. The micro light emitting device of sub-millimeter level or even micron level is as self-luminous as the organic light emitting device (OLED). It has a series of advantages such as high brightness, ultra-low delay, and ultra-large viewing angle as the organic light emitting device. And because the inorganic light emitting device emits light based on the metal semiconductor with more stable properties and lower resistance, it has the advantages of lower power consumption, longer service life, and better resistance to high and low temperatures compared with the organic light emitting device based on organic matter. When the micro light emitting device is used as a backlight source, it can achieve more precise dynamic backlight effect, effectively improve the screen brightness and contrast, and solve the glare phenomenon caused by the traditional dynamic backlight between the screen light and dark areas, and optimize the visual experience.

[0151] In some embodiments, the display device provided by the embodiments of the present disclosure can be any product or component with display function, such as a display, a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, etc. Optionally, the display device provided by the embodiments of the present disclosure includes, but is not limited to, a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a control chip, and the like. Optionally, the control chip is a central processing unit, a digital signal processor, a system chip (SoC), etc. For example, the control chip can also include a memory, and can also include a power module, etc., and realizes the power supply and signal input and output functions through the additionally arranged wires, signal lines, etc. For example, the control chip can also include hardware circuit and computer executable code, etc. The hardware circuit can include conventional very large scale integration (VLSI) circuit or gate array, and existing semiconductors such as logic chips, transistors, and other discrete elements; the hardware circuit can also include field programmable gate array, programmable array logic, programmable logic device, etc. In addition, the above structure does not constitute a limitation on the display device provided by the embodiments of the present disclosure, in other words, the display device provided by the embodiments of the present disclosure can include more or less components, or combine certain components, or different component arrangements.

[0152] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, The application relates to a display substrate, which comprises a substrate, a display area and a non-display area surrounding the display area. A plurality of sensing signal lines are arranged in the non-display area. A plurality of transistors are arranged in the non-display area and electrically connected to at least part of the sensing signal lines. A plurality of first detection terminals are arranged in the non-display area and used for detecting whether the sensing signal lines and the transistors are normal, and one first detection terminal is arranged corresponding to at least one sensing signal line. Two adjacent sensing signal lines correspond to different first detection terminals.

2. The array substrate of claim 1, wherein, The plurality of sensing signal lines comprise a plurality of first light sensing signal lines, different first light sensing signal lines are electrically connected to the first poles of different transistors.

3. The array substrate of claim 2, wherein, An odd number of first light sensing signal lines correspond to the same first detection terminal, and an even number of first light sensing signal lines correspond to another first detection terminal. The plurality of sensing signal lines further comprise second light sensing signal lines arranged on one side of the plurality of first light sensing signal lines, and the second light sensing signal lines are electrically connected to the second poles of the transistors.

4. The array substrate of claim 3, wherein, The second light sensing signal lines correspond to different first detection terminals from the first light sensing signal lines. The plurality of sensing signal lines further comprise third light sensing signal lines arranged on the side of the second light sensing signal lines away from the plurality of first light sensing signal lines, and the third light sensing signal lines are electrically connected to the gate poles of the transistors.

5. The array substrate of claim 4, wherein, The third light sensing signal lines, the second light sensing signal lines and the first light sensing signal lines correspond to different first detection terminals. The plurality of sensing signal lines further comprise temperature sensing signal lines.

6. The array substrate of claim 5, wherein, The temperature sensing signal lines, the third light sensing signal lines, the second light sensing signal lines and the first light sensing signal lines correspond to different first detection terminals. The plurality of sensing signal lines further comprise second light sensing signal lines arranged on one side of the plurality of first light sensing signal lines, and the second light sensing signal lines are electrically connected to the second poles of the transistors.

7. The array substrate of claim 3, wherein, The second light sensing signal lines correspond to the same first detection terminal as an even number of first light sensing signal lines. Third light sensing signal lines are arranged on the side of the second light sensing signal lines away from the plurality of first light sensing signal lines, and the third light sensing signal lines are electrically connected to the gate poles of the transistors.

8. The array substrate of claim 4 or 7, wherein, The third light sensing signal lines correspond to the same first detection terminal as an odd number of first light sensing signal lines. The plurality of sensing signal lines further comprise temperature sensing signal lines.

9. The array substrate of claim 8, wherein, The temperature sensing signal lines correspond to the same first detection terminal as an even number of first light sensing signal lines. The application further comprises a plurality of first connecting lines, one end of the plurality of first connecting lines is integrally arranged on the side of the same first detection terminal away from the display area, and the other end of the plurality of first connecting lines is disconnected from each other on the side of different sensing signal lines away from the display area.

10. The array substrate according to any one of claims 1 to 9, wherein, The application further comprises a plurality of second connecting lines arranged in a layer different from the plurality of first connecting lines.

11. The array substrate of claim 10, wherein, ​ One end of the plurality of second connection lines is integrally arranged on the same first detection terminal away from the display area, and the other end of the plurality of second connection lines is disconnected from each other on different sensing signal lines away from the display area. The plurality of second connection lines correspond to different first detection terminals and different sensing signal lines from the plurality of first connection lines.

12. The array substrate of claim 11, wherein, The orthogonal projection of the first connection line on the substrate substrate is alternately arranged with the orthogonal projection of the second connection line on the substrate substrate.

13. The array substrate of any one of claims 1 to 12, wherein, Further comprising a plurality of third connection lines, one end of different third connection lines is integrally arranged with different first detection terminals, and the other end of the plurality of third connection lines is disconnected from each other at the boundary of the array substrate.

14. The array substrate of claim 2, wherein, Different sensing signal lines are electrically connected with different first detection terminals.

15. The array substrate of claim 14, wherein, Further comprising a plurality of fourth connection lines arranged in the same layer as the plurality of first detection terminals, and a plurality of fifth connection lines arranged in different layers from the plurality of first detection terminals; wherein, One end of different fourth connection lines is integrally arranged with different first detection terminals, one end of different fifth connection lines is electrically connected with different first detection terminals, and the first detection terminals corresponding to the fourth connection lines and the fifth connection lines are alternately arranged; the other end of the plurality of fourth connection lines and the other end of the plurality of fifth connection lines are disconnected from each other at the boundary of the array substrate.

16. The array substrate of claim 15, wherein, Further comprising a sixth connection line arranged in the same layer as the plurality of fourth connection lines, one end of the sixth connection line is integrally arranged with the first detection terminal not corresponding to the plurality of fourth connection lines and not corresponding to the plurality of fifth connection lines, and the other end of the sixth connection line is disconnected from the other end of the plurality of fourth connection lines and the other end of the plurality of fifth connection lines at the boundary of the array substrate.

17. The array substrate of any one of claims 1 to 16, wherein, The non-display area includes a first non-display area where the plurality of detection terminals are located, a second non-display area opposite to the first non-display area, and two third non-display areas connecting the first non-display area and the second non-display area, and the plurality of transistors are located in the second non-display area and the third non-display area.

18. The array substrate of claim 17, wherein, The third non-display area further comprises a gate drive circuit and a gate drive circuit signal line electrically connected with the gate drive circuit; The plurality of sensing signal lines and the plurality of transistors are located on the side of the gate drive circuit and the gate drive circuit signal line away from the display area.

19. The array substrate of claim 18, wherein, Further comprising a sealant surrounding the display area, the sealant covering at least the connection position of the transistor and the sensing signal line.

20. The array substrate of claim 19, wherein, The gate drive circuit signal line includes a clock signal line located on the side of the gate drive circuit away from the display area, and the sealant further covers the connection position of the clock signal line and the gate drive circuit.

21. The array substrate of any one of claims 1 to 16, wherein, The non-display area includes a first non-display area where the plurality of first detection terminals are located, and the first non-display area includes a plurality of fan-out areas; The array substrate further comprises a common electrode line between the fan-out areas, the plurality of transistors are between the fan-out areas and the common electrode line, and the plurality of transistors are arranged obliquely along the edges of the fan-out areas.

22. The array substrate of claim 21, wherein, The gates of the plurality of transistors are arranged approximately in steps along the edges of the fan-out areas, and the gates of the plurality of transistors are integrally provided with one of the sensing lines.

23. A motherboard, wherein, The array substrate comprises a plurality of array substrates as claimed in any one of claims 1 to 22, and a plurality of second detection terminals at the periphery of the array substrate; wherein one of the second detection terminals is electrically connected with at least one of the first detection terminals.

24. The female board of claim 23, wherein, The array substrate comprises a plurality of third connection lines, and different second detection terminals are electrically connected with different first detection terminals through different third connection lines.

25. The master as recited in claim 24, wherein, The array substrate comprises a plurality of fourth connection lines, a plurality of sixth connection lines which are provided in the same layer, and a plurality of fifth connection lines which are provided in a layer different from the plurality of fourth connection lines; wherein One end of each of the fourth connection lines is integrally provided with a different first detection terminal, and the other end of each of the fourth connection lines converges at the periphery of the array substrate to be integrally provided with a same second detection terminal; One end of each of the fifth connection lines is electrically connected with a different first detection terminal, and the other end of each of the fifth connection lines converges at the periphery of the array substrate to be electrically connected with a same second detection terminal; One end of the sixth connection line is integrally provided with one of the first detection terminals, and the other end of the sixth connection line is integrally provided with one of the second detection terminals at the periphery of the array substrate; The plurality of fourth connection lines, the plurality of fifth connection lines, and the sixth connection line correspond to different first detection terminals and different second detection terminals; The plurality of fourth connection lines and the plurality of fifth connection lines cross each other near the boundary of the array substrate; On the side of the intersection position close to the display area, the orthogonal projection of the fourth connection line on the substrate and the orthogonal projection of the fifth connection line on the substrate are alternately arranged, and the first spacing is provided between the adjacent fourth connection line and the adjacent fifth connection line in the orthogonal projection. On the side of the intersection position away from the display area, the second spacing is provided between the adjacent fourth connection lines, the third spacing is provided between the adjacent fifth connection lines, and the second spacing, the third spacing, and the first spacing are substantially the same.

26. A method of manufacturing the array substrate according to any one of claims 1 to 22, wherein, Providing a substrate, the substrate comprises a plurality of array substrate areas, the array substrate area comprises a display area and a non-display area surrounding the display area; forming a plurality of sensing signal lines, a plurality of transistors, and a plurality of first detection terminals in the non-display area, and electrically connecting the plurality of transistors with at least part of the sensing signal lines, and electrically connecting one of the first detection terminals with at least one of the sensing signal lines; cutting the array substrate area into a plurality of small plates; disconnecting the first detection terminal from the corresponding sensing signal line to form the array substrate. One of the first detection terminals is electrically connected with at least one of the sensing signal lines, specifically comprising:

27. The production method according to claim 26, wherein ​ forming a plurality of first connection lines and a plurality of second connection lines in different layers; and making one end of different first connection lines integral with different sensing signal lines, the other end of the plurality of first connection lines converging to one first detection terminal; one end of different second connection lines electrically connected with different sensing signal lines, the other end of the plurality of second connection lines converging to one first detection terminal; and the plurality of second connection lines corresponding to different first detection terminals and different sensing signal lines from the plurality of first connection lines.

28. The production method according to claim 27, wherein disconnecting the first detection terminal from the corresponding sensing signal line, specifically including: removing the plurality of first connection lines and the plurality of second connection lines, so that the first detection terminal is disconnected from the corresponding sensing signal line; or, disconnecting the plurality of first connection lines from the corresponding sensing signal line, the plurality of first connection lines from the corresponding first detection terminal, the plurality of second connection lines from the corresponding sensing signal line, and the plurality of second connection lines from the corresponding first detection terminal, so that the first detection terminal is disconnected from the corresponding sensing signal line.

29. The method of manufacturing according to any one of claims 26 to 28, wherein, forming a plurality of sensing signal lines, a plurality of transistors, and a plurality of first detection terminals in the non-display area, and making the plurality of transistors electrically connected with at least part of the sensing signal lines, one first detection terminal electrically connected with at least one sensing signal line, further including: forming a plurality of second detection terminals in the periphery of the array substrate area, and making one second detection terminal electrically connected with at least one first detection terminal; cutting into a plurality of small plates in units of the array substrate area, further including: removing the plurality of second detection terminals, and making each first detection terminal corresponding to one end of the second detection terminal independent of each other.

30. The production method according to claim 29, wherein making one second detection terminal electrically connected with at least one first detection terminal, specifically including: forming a plurality of fourth connection lines, sixth connection lines in the same layer, and a plurality of fifth connection lines in different layers from the plurality of fourth connection lines; and making one end of different fourth connection lines integral with different first detection terminals, the other end of the plurality of fourth connection lines converging to one second detection terminal integral with the same array substrate in the periphery; one end of different fifth connection lines electrically connected with different first detection terminals, the other end of the plurality of fifth connection lines electrically connected with the same second detection terminal in the periphery of the array substrate; one end of the sixth connection line integral with one first detection terminal, the other end of the sixth connection line integral with one second detection terminal in the periphery of the array substrate; and the plurality of fourth connection lines, the plurality of fifth connection lines, and the sixth connection line corresponding to different first detection terminals and different second detection terminals; removing the plurality of second detection terminals, and making each first detection terminal corresponding to one end of the second detection terminal independent of each other, specifically including: The second detecting terminals are cut off, and the fourth connecting lines, the fifth connecting lines and the sixth connecting lines in the periphery of the array substrate are cut off, so that the fourth connecting lines, the fifth connecting lines and the sixth connecting lines corresponding to each first detecting terminal are disconnected with each other at the boundary of the array substrate.

31. A display panel, wherein, The display panel comprises the array substrate as claimed in any one of claims 1 to 22, and an opposite substrate opposite to the array substrate.

32. The display panel of claim 31, wherein, The opposite substrate comprises a black matrix covering part of the transistors and color resist covering the rest of the transistors.

33. A display device comprising: The display panel comprises the display panel as claimed in claim 31 or 32, and a backlight module located at the light-in side of the display panel.

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