Display substrate and display device

Abstract

A display substrate (100) and a display device. The display substrate (100) comprises a plurality of data lines (D1 to Dn) extending in a first direction (X); a plurality of gate lines (S1 to Sm-1) extending in a second direction (Y), wherein the first direction (X) intersects with the second direction (Y), and the plurality of gate lines (S1 to Sm-1) intersect with the plurality of data lines (D1 to Dn) to define a plurality of sub-pixel (Pxij) regions; and a plurality of sub-pixels (Pxij), wherein a single sub-pixel (Pxij) is located within a single sub-pixel (Pxij) region. At least one of the plurality of sub-pixels (Pxij) comprises a driving circuit, a first electrode (51), and a second electrode (61) which are arranged on a substrate (10); the first electrode (51) at least partially overlaps the second electrode (61) in a direction away from the substrate (10); the driving circuit is separately electrically connected to one gate line (S), one data line (D) and the first electrode (51), and is configured to transmit an electrical signal of the data line (D) to the first electrode (51) under the control of the gate line (S); and the orthographic projection of the second electrode (61) on the substrate (10) covers the orthographic projection of the gate line (S) on the substrate (10).

Description

Display substrate and display device

[0001] The present application claims priority to the Chinese patent application No. 202410875168.0, filed on July 01, 2024, and entitled "Display substrate and display device", the contents of which are to be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] The present document relates to, but is not limited to, display technology, in particular to a display substrate and a display device. BACKGROUND

[0003] Liquid Crystal Display (LCD) has been rapidly developed due to its small size, low power consumption, and no radiation. The liquid crystal display panel includes a thin film transistor array (TFT) substrate and a color filter (CF) substrate in a cell. Liquid crystal (LC) molecules are arranged between the array substrate and the color filter substrate. By controlling the common electrode and the pixel electrode, an electric field is formed to drive the liquid crystal to deflect, thereby realizing gray scale display. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising: a plurality of data lines extending along a first direction; a plurality of gate lines extending along a second direction, the first direction and the second direction intersecting; a plurality of sub-pixel regions defined by the plurality of gate lines and the plurality of data lines intersecting; a plurality of sub-pixels, each of the sub-pixels being located in a corresponding one of the sub-pixel regions; at least one of the plurality of sub-pixels comprising a driving circuit, a first electrode and a second electrode disposed on a substrate, the first electrode and the second electrode at least partially overlapping in a direction away from the substrate; the driving circuit electrically connected to one of the gate lines, one of the data lines and the first electrode, respectively, and configured to transmit an electrical signal of the data line to the first electrode under control of the gate line; wherein a projection of the second electrode on the substrate covers a projection of the gate line on the substrate.

[0006] In an exemplary embodiment, the first electrode comprises a plurality of slits, at least two of the plurality of slits extending in the same direction.

[0007] In an exemplary embodiment, the slit comprises a middle portion, a first end portion and a second end portion connected to each other, and the first end portion and the second end portion are respectively located on both sides of the middle portion along the first direction.

[0008] In an exemplary embodiment, an included angle between an extension direction of the first end portion and the second direction is a first angle a1, and the first angle a1 is less than or equal to 55 degrees.

[0009] In an exemplary embodiment, a first length L1 of the first end portion is a maximum distance of the first end portion relative to both ends in the extension direction of the first end portion; and a first depth V1 of the first end portion is greater than or equal to 3.5 microns, V1 = L1*sin(a1).

[0010] In an exemplary embodiment, an included angle between an extension direction of the second end portion and the second direction is a second angle a2, and the second angle a2 is less than or equal to 55 degrees.

[0011] In an exemplary embodiment, a second length L2 of the second end portion is a maximum distance of the second end portion relative to both ends in the extension direction of the second end portion; and a second depth V2 of the second end portion is greater than or equal to 3.5 microns, V2 = L2*sin(a2).

[0012] In an exemplary embodiment, a plurality of the slits are arranged in sequence along the second direction; and first end portions of at least two of the slits away from one side edge of the middle portion are flush with each other along the second direction, and second end portions of the at least two of the slits away from the one side edge of the middle portion are flush with each other along the second direction.

[0013] In an exemplary embodiment, a plurality of the slits are arranged in sequence along the second direction; and first end portions of at least two of the slits away from one side edge of the middle portion are arranged in a stepped manner along the second direction, or second end portions of the at least two of the slits away from the one side edge of the middle portion are arranged in a stepped manner along the second direction.

[0014] In an exemplary embodiment, a plurality of the slits are arranged in sequence along the second direction; and first end portions of at least two of the slits away from one side edge of the middle portion are arranged in a stepped manner along the second direction, and second end portions of the at least two of the slits away from the one side edge of the middle portion are arranged in a stepped manner along the second direction.

[0015] In an exemplary embodiment, in the case that the first end portions of at least two of the slits adjacent in the second direction are arranged in a stepped manner away from the side edge of the middle portion, the distance between the first end portions of the adjacent slits is less than or equal to 6 microns; the distance between the first end portions of the adjacent slits is the distance of the first end portions of the adjacent slits away from the side edge of the middle portion in the first direction.

[0016] In an exemplary embodiment, in the case that the second end portions of at least two of the slits adjacent in the second direction are arranged in a stepped manner away from the side edge of the middle portion, the distance between the second end portions of the adjacent slits is less than or equal to 6 microns; the distance between the second end portions of the adjacent slits is the distance of the second end portions of the adjacent slits away from the side edge of the middle portion in the first direction.

[0017] In an exemplary embodiment, the driving circuit comprises a first transistor, the gate line is connected with the gate electrode of a plurality of the first transistors in the extending direction of the gate line, the first electrode of the first transistor is connected with the data line, and the second electrode of the first transistor is connected with the first electrode; the orthogonal projection of the second electrode on the substrate exposes the orthogonal projection of the gate electrode of the first transistor on the substrate.

[0018] In an exemplary embodiment, the sum of the overlapping areas of the orthogonal projection of the second electrode on the substrate and the orthogonal projection of the gate line and the gate electrode on the substrate is a first area, and the sum of the areas of the orthogonal projection of the gate line and the gate electrode on the substrate is a second area; the ratio of the first area to the second area is greater than or equal to 65% and less than or equal to 95%.

[0019] In an exemplary embodiment, the gate line and the gate electrode of the plurality of the first transistors in the extending direction of the gate line are an integral structure.

[0020] In an exemplary embodiment, the plurality of sub-pixels comprises a plurality of sub-pixel columns arranged in the first direction and a plurality of sub-pixel rows arranged in the second direction; two gate lines are distributed between two sub-pixel rows adjacent in the first direction, and the sub-pixels in a single sub-pixel row are respectively electrically connected with the two gate lines adjacent in the first direction.

[0021] In another aspect, the present disclosure provides a display device comprising the aforementioned display substrate, a counter substrate, and a liquid crystal layer disposed between the display substrate and the counter substrate.

[0022] In an exemplary embodiment, the dielectric constant of the liquid crystal material of the liquid crystal layer is less than or equal to 8; or the liquid crystal material of the liquid crystal layer is a negative liquid crystal.

[0023] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0024] Overview of the attached figures

[0025] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0026] Figure 1 is a schematic cross-sectional view of a display device;

[0027] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0028] Figure 3 is a plan view of a display substrate employing a dual-gate structure in an exemplary embodiment;

[0029] Figure 4 is a schematic diagram of the arrangement of liquid crystal molecules in a sub-pixel when scratch defects occur;

[0030] Figure 5 is an enlarged schematic diagram of the dashed area G in Figure 4 in some embodiments;

[0031] Figure 6 is an enlarged view of the first region G in Figure 4 in an exemplary embodiment of this disclosure;

[0032] Figure 7 is a top view of the pixel electrode of a sub-pixel in an exemplary embodiment;

[0033] Figure 8 is an enlarged view of the first region G in Figure 4 in yet another exemplary embodiment;

[0034] Figure 9 is a diagram showing the orthographic projection relationship between liquid crystal molecules and pixel electrodes on a display substrate in an exemplary embodiment;

[0035] Figure 10A is a schematic diagram of the sub-pixel structure in an exemplary embodiment;

[0036] Figure 10B is the optical path diagram of the sub-pixel in Figure 10A;

[0037] Figure 11A is a schematic diagram of the structure of a sub-pixel in yet another exemplary embodiment;

[0038] Figure 11B is the optical path diagram of the sub-pixel in Figure 11A;

[0039] Figure 12 is a top view of the pixel electrode of a sub-pixel in another exemplary embodiment;

[0040] Figure 13A is a top view of the pixel electrode of a sub-pixel in an exemplary embodiment;

[0041] Figure 13B is a top view of the pixel electrode of a sub-pixel in yet another exemplary embodiment;

[0042] FIG. 13C is a plan view of a pixel electrode of a sub-pixel in another exemplary embodiment;

[0043] FIG. 13D is a plan view of a pixel electrode of a sub-pixel in another exemplary embodiment;

[0044] FIG. 14 is a cross-sectional view of the display substrate of FIG. 2 along the CC direction in an exemplary embodiment.

[0045] DETAILED DESCRIPTION

[0046] Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. Embodiments can be implemented in a variety of different ways. It is readily apparent to one of ordinary skill in the art that the embodiments and the contents can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following embodiments. Embodiments in the present disclosure and features in the embodiments can be arbitrarily combined so long as there is no conflict.

[0047] In the drawings, the size, the thickness, or the region of one or more constituent elements can be exaggerated for clarity in some cases. Therefore, one embodiment of the present disclosure is not limited to what is described in the following embodiments and the drawings, and the shape, the relative size, and the like of one or more constituent elements illustrated in the drawings can be arbitrarily changed. In addition, the exemplary embodiments are schematically illustrated in the drawings, and the present disclosure is not limited to the shapes or values illustrated in the drawings. The ratio of the dimensions of the drawings in the present disclosure can be used as a reference for the actual process, but is not limited thereto. For example, the width-length ratio of a channel, the thickness and the interval of a film layer, and the width and the interval of a signal line can be adjusted as needed.

[0048] The ordinal numbers "first", "second", "third", and the like in the present specification are used to avoid confusion among constituent elements and are not intended to indicate or imply a relative importance of the constituent elements. "A plurality of" in the present disclosure means two or more.

[0049] In the present specification, the words "center", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like used to describe the positional relationship of the constituent elements with reference to the drawings are used for the convenience of explanation of the positional relationship of the constituent elements with reference to the drawings, and are used only to facilitate the description of the present specification and simplify the description, and thus cannot be understood as indicating or implying that the device or the element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of the constituent elements described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0050] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", "connected" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or internal communication of two elements. For those skilled in the art, the meaning of the above terms in this disclosure can be understood according to the circumstances. Among them, "electrically connected" includes the case where the constituent elements are connected together through an element having a certain electrical effect. "Element having a certain electrical effect" is not particularly limited as long as it can transmit electrical signals between the connected constituent elements. Examples of "element having a certain electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.

[0051] In this specification, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain) and a source electrode (a source electrode terminal, a source region, or a source), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to a region where current flows mainly.

[0052] In this specification, in order to distinguish two electrodes of a transistor other than the gate, one of the electrodes is referred to as a first electrode and the other is referred to as a second electrode. For example, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case where the direction of current flow is changed in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0053] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus also includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus also includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0054] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. There can be some small deformation due to tolerance, there can be an angle, an arc edge, and deformation, etc.

[0055] "About" in this specification means not strictly limited to the limit, allowing values within the range of process and measurement error.

[0056] In the present specification, A extends along a direction of B means that A can include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a bar-shaped body, the main part stretches along the direction of B, and the length of the main part stretching along the direction of B is greater than the length of the secondary part stretching along other directions. In the following description, A extending along the direction of B means that the main part of A extending along the direction of B.

[0057] In the present specification, A and B are arranged in the same layer means that A and B are formed at the same time by the same patterning process when the display substrate is prepared.

[0058] FIG. 1 is a schematic diagram of a cross-sectional structure of a display device. As shown in FIG. 1, the display device can include a display substrate 100 and a counter substrate 200 arranged opposite to each other, and a liquid crystal layer 300 arranged between the display substrate 100 and the counter substrate 200. The display substrate 100 can be referred to as an array substrate, and the counter substrate 200 can be referred to as a color film substrate. The display substrate 100 can include a first structure layer 102 arranged on a side of a first base 101 facing the counter substrate 200, and the counter substrate 200 can include a second structure layer 202 arranged on a side of a second base 201 facing the first substrate 100. LCDs can be classified into a twisted nematic (TN) display mode, an in plane switching (IPS) display mode, a fringe field switching (FFS) display mode, an advanced super dimension switch (ADS) display mode, and the like according to a display mode. For the ADS display mode, in an exemplary embodiment, the first structure layer 102 can include a gate line, a data line, a first transistor, a first electrode, and a second electrode. The first electrode can be a pixel electrode, and the second electrode can be a common electrode connected to a common voltage line. The first electrode and the second electrode are used to generate an electric field that controls the deflection of liquid crystal molecules in the liquid crystal layer, thereby realizing a specific gray scale display. The first transistor can be electrically connected to the first electrode, the data line, and the gate line, respectively. A scan signal transmitted by the gate line can control the on-off of the first transistor. After the first transistor is turned on, a pixel voltage transmitted by the data line can be output to the first electrode, thereby realizing picture display. The second structure layer 202 can include a black matrix and a filter unit.

[0059] FIG. 2 is a schematic diagram of a planar structure of a display substrate, which can be an array substrate. As shown in FIG. 2, in an exemplary embodiment, the display substrate 100 can include a display area AA and a non-display area, which can be disposed at least on one side of the display area AA. In an exemplary embodiment, the non-display area can be disposed around the display area AA. The non-display area can include a circuit area, which can include a first circuit area BB1 and a second circuit area BB2. The first circuit area BB1 can be located on one side of the display area AA along a second direction Y, and the second circuit area BB2 can be located on the opposite side of the display area AA along the second direction Y. The display area AA can include at least one first wire extending along the second direction Y, which can be a gate line for example, and at least one second wire extending along a first direction X, which can be a data line for example, and the second direction Y can be perpendicular to the first direction X, for example. A first scan driver can be disposed in the first circuit area BB1, and a second scan driver can be disposed in the second circuit area BB2, and the first scan driver and the second scan driver can provide scan signals to the gate lines in the display area AA. A data driver can provide data signals to the data lines in the display area AA.

[0060] In an exemplary embodiment, as shown in FIG. 2, a plurality of gate lines (S1 to S m-1 ) and a plurality of data lines (D1 to D n ) can cross to define a plurality of sub-pixel (Pxij) regions, and each sub-pixel region can be provided with a sub-pixel including a first electrode, a second electrode, and a driving circuit connected to the first electrode. The driving circuit can include at least one first transistor. Taking an oxide thin film transistor as an example, the drain electrode of the oxide thin film transistor can be electrically connected to the first electrode, the source electrode can be electrically connected to the data line, and the gate electrode can be electrically connected to the gate line. The first transistor can be controlled to turn on by a scan signal transmitted by the gate line to light up the corresponding sub-pixel on the display substrate.

[0061] In an exemplary embodiment, as shown in FIG. 2, a timing signal line, a common voltage line, a high-voltage power supply line, and a low-voltage power supply line, etc. (not shown in the figure) can be disposed on the side of the first scan driver away from the display area AA and on the side of the second scan driver away from the display area AA. The first scan driver and the second scan driver can control the sub-pixels in the display area AA to display according to the timing signal from the timing signal line, the high-voltage power supply line can provide a high-voltage signal, and the low-voltage power supply line can provide a low-voltage signal for the display device to normally display.

[0062] In an exemplary embodiment, as shown in FIG. 2, the plurality of sub-pixels within the display area AA can be arranged in an array, including a plurality of sub-pixel columns arranged along a first direction X and a plurality of sub-pixel rows arranged along a second direction Y. As shown in FIG. 2, a single gate line is provided between two adjacent sub-pixel rows.

[0063] FIG. 3 is a plan view of a display substrate employing a dual gate structure in an exemplary embodiment, showing the arrangement of four rows and six columns of sub-pixels and omitting other structures. As shown in FIG. 3, the display substrate 100 can employ a dual gate structure, in which two gate lines are provided between two adjacent sub-pixel rows, and each pixel row is adjacent to two gate lines along the first direction X. The sub-pixels in a single sub-pixel row can be connected to the two adjacent gate lines, respectively, and the sub-pixels connected to different gate lines in a single sub-pixel row can be arranged at intervals. Two adjacent sub-pixel columns can share a data line, and a plurality of common voltage lines Vcom can extend along the first direction X and be arranged at intervals in the second direction Y from the data lines. The common voltage lines Vcom can be electrically connected to the second electrodes of the sub-pixels (not shown in the figure) to provide a low voltage signal to the second electrodes of the sub-pixels. By employing the dual gate structure, the number of gate lines on the display substrate is doubled, which can reduce the number of data lines and source driving ICs, thereby reducing the cost of the display substrate 100.

[0064] FIG. 4 is a schematic diagram of the arrangement of liquid crystal molecules in a sub-pixel when trace mura occurs, illustrating the orthographic projection relationship between the liquid crystal molecules and the pixel electrode on the display substrate. For a liquid crystal display device, when a user's finger is swiped on the screen in the case of displaying a high gray scale (L255) picture, the electric field at the finger pressing position changes, which easily causes the arrangement of the liquid crystal molecules to be disordered, the screen brightness at the position swiped by the finger is reduced, a trace of local darkening is formed, and the trace cannot be recovered after 5 seconds of pressing, which is called trace mura. As shown in FIG. 4, the pixel electrode 51 includes a plurality of slits 510, the extension direction of the slits 510 intersects the first direction X, the plurality of slits 510 are arranged in sequence along the second direction Y, the slits 510 include a middle portion F1 located in the middle region of the sub-pixel and a first end portion F2 and a second end portion F3 away from the center of the sub-pixel, the first end portion F2 and the second end portion F3 can be located on both sides of the middle portion F1 along the first direction X respectively, the middle portion F1 can have different extension directions, forming a dual-domain or multi-domain structure, and FIG. 4 illustrates the case of dual-domain distribution of the liquid crystal molecules 301 by way of example, which is not limited in the present disclosure. The plurality of liquid crystal molecules 301 are distributed in multiple columns along the second direction Y, and the arrangement of the liquid crystal molecules in the leftmost column (i.e. in the dashed line region E) is disordered. In the case of displaying a high gray scale picture, the electric field at the first end portion F2 and the second end portion F3 away from the center of the sub-pixel is weak, while the electric field of the gate line S adjacent to the first end portion F2 and the second end portion F3 is strong, under the influence of the electric field of the gate line S, the arrangement of the liquid crystal molecules 301 at the first end portion F2 and the second end portion F3 of the slits 510 is easily disordered, after the finger is swiped on the screen, the change of the electric field caused by pressing makes the liquid crystal molecules 301 disordered at the first end portion F2 and the second end portion F3 drive the liquid crystal molecules 301 in the column where the liquid crystal molecules 301 are located to be disordered as well, resulting in the arrangement of the plurality of liquid crystal molecules 301 in the dashed line region E being disordered, and trace mura is formed. In the display substrate adopting a dual-gate structure, the number of gate lines is larger, the electric field interference on the liquid crystal molecules is stronger, and trace mura is more likely to occur.

[0065] FIG. 5 is an enlarged schematic diagram of the dashed line region G of FIG. 4 in some embodiments, illustrating the orthographic projection relationship between the gate line S, the data line D, the pixel electrode 51, the common electrode 61 and the liquid crystal molecules 301 on the display substrate. As shown in FIG. 5, the orthographic projection of the common electrode 61 on the display substrate covers the orthographic projection of the pixel electrode 51 on the display substrate, the orthographic projection of the common electrode 61 on the display substrate does not overlap the orthographic projection of the gate line S on the display substrate, and the electric field of the gate line S acts on the liquid crystal molecules 301 at the first end portion F2 of the slits 510, which easily causes the deflection angle of the liquid crystal molecules 301 at the first end portion F2 of the slits 510 to be abnormal, and trace mura is more likely to be formed when the finger is swiped on the screen.

[0066] The display substrate provided by the example embodiments of the present disclosure comprises: a substrate, and a plurality of gate lines and a plurality of data lines disposed on the substrate, the plurality of data lines extend along a first direction, the plurality of gate lines extend along a second direction, the plurality of gate lines and the plurality of data lines cross to define a plurality of sub-pixel regions, and one sub-pixel is disposed in each of the sub-pixel regions; at least one of the plurality of sub-pixels comprises a driving circuit, a first electrode, and a second electrode, the first electrode and the second electrode at least partially overlap in a direction away from the substrate, the driving circuit is electrically connected with one of the gate lines, one of the data lines, and the first electrode, and is configured to transmit an electrical signal of the data line to the first electrode under the control of the gate line; and a projection of the second electrode on the substrate covers a projection of the gate line on the substrate.

[0067] The display substrate provided by the example embodiments of the present disclosure makes the projection of the second electrode on the substrate cover the projection of the gate line on the substrate, so that the second electrode can shield the electric field of the gate line, avoid the electric field of the gate line affecting the arrangement of liquid crystal molecules, help to avoid scratch defects, and improve the display effect.

[0068] In the example embodiments, the first electrode comprises a plurality of slits, and at least two of the plurality of slits extend in the same direction.

[0069] In the example embodiments, the slit comprises a middle part, a first end part, and a second end part connected with each other, and the first end part and the second end part are respectively located on two sides of the middle part along the first direction.

[0070] In the example embodiments, an included angle between the extension direction of the first end part and the second direction is a first angle a1, and the first angle a1 is less than or equal to 55 degrees.

[0071] In the example embodiments, a first length L1 of the first end part is a maximum distance between opposite ends of the first end part in the extension direction of the first end part; and a first depth V1 of the first end part is greater than or equal to 3.5 microns, and V1 = L1*sin(a1).

[0072] In the example embodiments, an included angle between the extension direction of the second end part and the second direction is a second angle a2, and the second angle a2 is less than or equal to 55 degrees.

[0073] In the example embodiments, a second length L2 of the second end part is a maximum distance between opposite ends of the second end part in the extension direction of the second end part; and a second depth V2 of the second end part is greater than or equal to 3.5 microns, and V2 = L2*sin(a2).

[0074] In exemplary embodiments, a plurality of the slits are arranged in sequence along the second direction; in the second direction, first end portions of at least two of the slits away from one side edge of the middle portion are flush with each other, and / or, second end portions of at least two of the slits away from one side edge of the middle portion are flush with each other.

[0075] In exemplary embodiments, a plurality of the slits are arranged in sequence along the second direction; first end portions of at least two of the slits adjacent in the second direction away from one side edge of the middle portion are arranged in a stepped manner, and second end portions of at least two of the slits adjacent in the second direction away from one side edge of the middle portion are arranged in a stepped manner.

[0076] In exemplary embodiments, in the case where first end portions of at least two of the slits adjacent in the second direction away from one side edge of the middle portion are arranged in a stepped manner, a distance between the first end portions of the adjacent slits is less than or equal to 6 microns; the distance between the first end portions of the adjacent slits is a distance of the first end portions of the adjacent slits away from one side edge of the middle portion in the first direction.

[0077] In exemplary embodiments, in the case where second end portions of at least two of the slits adjacent in the second direction away from one side edge of the middle portion are arranged in a stepped manner, a distance between the second end portions of the adjacent slits is less than or equal to 6 microns; the distance between the second end portions of the adjacent slits is a distance of the second end portions of the adjacent slits away from one side edge of the middle portion in the first direction.

[0078] In exemplary embodiments, the driving circuit includes a first transistor, a gate electrode of the first transistor is connected with the gate line in the extending direction of the gate line, a first electrode of the first transistor is connected with the data line, and a second electrode of the first transistor is connected with the first electrode; a projection of the second electrode on the substrate exposes a projection of the gate electrode of the first transistor on the substrate.

[0079] In exemplary embodiments, a sum of overlapping areas of a projection of the second electrode on the substrate and projections of the gate line and the gate electrode on the substrate is a first area, and a sum of areas of the projections of the gate line and the gate electrode on the substrate is a second area; a ratio of the first area to the second area is greater than or equal to 65% and less than or equal to 95%.

[0080] In exemplary embodiments, the gate line and the gate electrode of the first transistor in the extending direction of the gate line are in one structure.

[0081] The display substrate of the present disclosure is illustrated below by some exemplary embodiments.

[0082] FIG. 6 is an enlarged view of the first area G of FIG. 4, illustrating the orthogonal projection relationship of the gate line S, the data line D, the pixel electrode 51, the common electrode 61 and the driving circuit on the display substrate, and other structures of the display substrate are omitted. As shown in FIG. 6, in a single sub-pixel, the first electrode can be the pixel electrode 51, and the second electrode can be the common electrode 61, which can be located on the side of the pixel electrode 51 away from the substrate (not shown). The driving circuit can include a first transistor, the gate electrode 22 of the first transistor can be connected with the corresponding gate line S, for example, can be an integrated structure, the first electrode 44 of the first transistor can be connected with the adjacent data line D, for example, can be an integrated structure, the first electrode 44 can be, for example, a source electrode, and the second electrode 45 of the first transistor can be connected with the pixel electrode 51, and the second electrode 45 can be, for example, a drain electrode. The orthogonal projection of the common electrode 61 on the substrate can cover the orthogonal projection of the gate line S on the substrate, and the orthogonal projection of the common electrode 61 on the substrate can expose the orthogonal projection of the gate electrode 22 of the first transistor on the substrate. In the case where the gate electrode 22 of the first transistor and the corresponding gate line S are an integrated structure, in the direction perpendicular to the substrate, the area where the gate line S overlaps with the active layer (not shown) of the first transistor serves as the gate electrode of the first transistor. The common electrode 61 can shield the electric field from the gate line S, so that there is no electric field of the gate line S near the end of the slit 510, the liquid crystal molecules at the corresponding position will not be abnormally deflected, the influence of the electric field at the edge of the sub-pixel on the liquid crystal molecules at the end of the slit 510 is reduced, the angle of deflection of the liquid crystal molecules at the corresponding position is smaller when the finger is drawn across the screen, the liquid crystal molecules can recover to normal arrangement in a short time, the ability of the liquid crystal molecules to recover to the deflected state after being disturbed by the electric field is improved, and scratch defects are avoided.

[0083] In an example embodiment, as shown in FIG. 6, the first electrode 44 of the first transistor can be in the shape of a “U”, and the opening direction of the “U” shape can be away from the data line D connected therewith. The second electrode 45 of the first transistor can be in the shape of a line, and the second electrode 45 of the first transistor can extend into the “U” shaped opening of the first electrode 44.

[0084] In an example embodiment, the orthogonal projection of the common electrode 61 on the substrate can overlap with the orthogonal projections of the gate line S and the gate electrode 22 on the substrate, and the sum of the overlapping areas of the orthogonal projection of the common electrode 61 on the substrate with the orthogonal projections of the gate line S and the gate electrode 22 on the substrate can be a first area. The sum of the areas of the orthogonal projections of the gate line S and the gate electrode 22 on the substrate can be a second area, and the ratio of the first area to the second area can be greater than or equal to 65% and less than or equal to 95%, for example, the ratio of the first area to the second area can be about 81%, and the sizes of the first area and the second area can be set as needed, which is not limited in the present disclosure.

[0085] In the example embodiment, the gate electrode 22 of the first transistor and the corresponding gate line S can be an integral structure.

[0086] In the example embodiment, in the structure shown in FIG. 4, the slits 510 of the pixel electrode 51 are in a strip shape, the extension direction of the first end portion F2 is the same as that of the connected middle portion F1, the extension direction of the second end portion F3 is the same as that of the connected middle portion F1, the extension direction of the slits 510 of the pixel electrode 51 has a certain influence on the deflection direction of the liquid crystal molecules, and the structure shown in FIG. 4 is in the case of displaying a high gray scale (L255) picture. In this case, the electric field of the first end portion F2 is perpendicular to that of the connected middle portion F1, the electric field of the second end portion F3 is perpendicular to that of the connected middle portion F1, the arrangement of the liquid crystal molecules 301 located at the first end portion F2 and the second end portion F3 is prone to abnormal deflection, when the user presses the screen with his finger, the liquid crystal molecules 301 are more prone to abnormal deflection under the action of the electric field, and the liquid crystal molecules 301 located on one side of the middle portion F1 are also prone to abnormal deflection, the arrangement of the liquid crystal molecules 301 in this column is disordered, and a scratch defect is formed.

[0087] Figure 7 is a top view of a pixel electrode of a sub-pixel in an example embodiment. As shown in Figure 7, the middle part of the slit 510 includes a first main part F11, a second main part F12, and a connecting part F13, the first main part F11 is connected with the first end part F2, the second main part F12 is connected with the second end part F3, and the connecting part F13 is used to connect the first main part F11 and the second main part F12. The extension direction of the first main part F11 and the extension direction of the second main part F12 can be different, the extension direction of the first main part F11 and the extension direction of the first end part F2 can be different, and the extension direction of the second main part F12 and the extension direction of the second end part F3 can be different. As shown in Figure 7, the angle between the extension direction of the first end part F2 of the slit 510 and the second direction Y is a first angle a1, the length of the first end part F2 of the slit 510 is a first length L1, the first length L1 can be the maximum distance of the first end part F2 relative to both ends in the extension direction thereof, the depth of the first end part F2 of the slit 510 is a first depth V1, V1 = L1*sin(a1), and the first depth V1 represents the distance between one end of the first end part F2 away from the connecting part F13 and one end of the first main part F11 away from the connecting part F13 along the first direction X. The angle between the extension direction of the second end part F3 of the slit 510 and the second direction Y is a second angle a2, the length of the second end part F3 of the slit 510 is a second length L2, the second length L2 can be the maximum distance of the second end part F3 relative to both ends in the extension direction thereof, the depth of the second end part F3 of the slit 510 is a second depth V2, V2 = L2*sin(a2), and the second depth V2 represents the distance between one end of the second end part F3 away from the connecting part F13 and one end of the second main part F12 away from the connecting part F13 along the first direction X. By forming corner structures such as the first end part F2 and the second end part F3 on the slit 510, the angle, length, depth, etc. of the first end part F2 and the second end part F3 can be set, the electric field direction at the first end part F2 and the second end part F3 can be changed, the influence of the electric field at the edge of the sub-pixel on the liquid crystal molecules at the end of the slit 510 can be reduced, the deflection angle of the liquid crystal molecules 301 located at the first end part F2 and the second end part F3 can be controlled, abnormal deflection of the liquid crystal molecules can be avoided, and after the finger is removed from the screen, the liquid crystal molecules can quickly recover to the deflection state to avoid forming a scratch defect.

[0088] In an example embodiment, the ADS display mode light transmittance formula is shown as formula (1):

[0089] In formula (1), T represents light transmittance, λ is the wavelength of incident light, Φ is the azimuth angle between the liquid crystal director and the applied electric field, △n is the liquid crystal birefringence, and d is the device cell gap.

[0090] According to formula (1), when the deflection angle of the liquid crystal is 45 degrees, the light transmittance reaches the maximum value under the condition that other conditions are unchanged. Considering the further deflection of the liquid crystal in the pressed state of the screen and the process fluctuation, the actual deflection angle Φ will deviate from the theoretical value by about 20 degrees. Accordingly, the extension direction and length dimension of the first end portion F2 and the second end portion F3 can be set.

[0091] In an example embodiment, the first angle a1 can be less than or equal to 55 degrees, for example, the first angle a1 can be less than or equal to 50 degrees, and the first depth V1 can be greater than or equal to 3.5 microns, for example, the first depth V1 can be greater than or equal to 4 microns. This size design of the first end portion F2 can effectively prevent abnormal deflection of the liquid crystal molecules located at the first end portion F2, and the size of the first angle and the first depth of the first end portion F2 can be set as needed, which is not limited in the present disclosure.

[0092] In an example embodiment, the second angle a2 can be less than or equal to 55 degrees, for example, the second angle a2 can be less than or equal to 50 degrees, and the second depth V2 can be greater than or equal to 3.5 microns, for example, the second depth V2 can be greater than or equal to 4 microns. This size design of the second end portion F3 can effectively prevent abnormal deflection of the liquid crystal molecules located at the second end portion F3, and the size of the second angle and the second depth of the second end portion F3 can be set as needed, which is not limited in the present disclosure.

[0093] In an example embodiment, the first angle a1 can be equal to the second angle a2, the first length L1 can be equal to the second length L2, the first depth V1 can be equal to the second depth V2, and the end size and angle of the plurality of slits 510 can be the same, which is not limited in the present disclosure.

[0094] FIG. 8 is an enlarged view of the first area G of FIG. 4 in another example embodiment, which illustrates the orthographic projection relationship of the gate line S, the data line D, the pixel electrode 51, the common electrode 61 and the driving circuit on the display substrate in the case of using the pixel electrode 51 with the structure shown in FIG. 7, and other structures of the display substrate are omitted. FIG. 9 is a diagram of the orthographic projection relationship of the liquid crystal molecules and the pixel electrode on the display substrate in an example embodiment, which illustrates the arrangement of the liquid crystal molecules at the first main body portion F11 and the first end portion F2 in the case of using the pixel electrode 51 with the structure shown in FIG. 7. As shown in FIGS. 8 and 9, by setting the corner structure of the slits 501 of the pixel electrode 51 away from at least one end (the first end portion F1 or the second end portion F2) of the middle portion, the direction of the electric field at the corner structure can be controlled, the influence of the electric field at the edge of the sub-pixel on the liquid crystal molecules at the end of the slit 510 can be reduced, the abnormal deflection of the liquid crystal molecules at the corner structure can be effectively prevented, the position of the liquid crystal molecules can be limited, and the scratch defect can be prevented.

[0095] FIG. 10A is a schematic diagram of a structure of a sub-pixel in an example embodiment, and FIG. 10B is a light path diagram of the sub-pixel in FIG. 10A. In the pixel electrode 51 shown in FIG. 10A, the second left slit (i.e., the slit circled by the dashed line region E1) is not provided with a corner structure, and the rest of the slits are provided with a corner structure. As shown in FIG. 10B, there is a scratch E2 on the screen, and the position of the scratch E2 corresponds to the second left slit in FIG. 10A. The scratch E2 seriously affects the normal display of the display panel and brings a poor user experience.

[0096] FIG. 11A is a schematic diagram of a structure of a sub-pixel in another example embodiment. The structure of FIG. 11A is similar to that of FIG. 10A, and the only difference is that the second left slit (i.e., the slit circled by the dashed line region E1) in FIG. 11A is provided with a corner structure. FIG. 11B is a light path diagram of the sub-pixel in FIG. 11A. As shown in FIG. 11B, after the second left slit is provided with a corner structure, there is no scratch on the screen. It can be seen that, by providing a corner structure on the slit, the abnormal deflection of liquid crystal molecules is well limited, the liquid crystal molecules are arranged in order, no scratch is formed on the screen, which is helpful for the normal display of the display panel and for improving the user experience.

[0097] FIG. 12 is a top view of a pixel electrode of a sub-pixel in another example embodiment. As shown in FIG. 12, a single pixel electrode 51 can include a plurality of slits 510, and the plurality of slits 510 can be arranged in sequence along the second direction Y. In the second direction Y, the first end F2 of the plurality of slits 510 away from one side edge of the middle F1 can be flush with each other, and the second end F3 of the plurality of slits 510 away from one side edge of the middle F1 can be flush with each other, as shown by the three slits 510 on the left side in FIG. 12. In other embodiments, in the first direction X, the first end F2 of the two adjacent slits 510 away from one side edge of the middle F1 can be arranged in a stepped manner, and the second end F3 of the two adjacent slits 510 away from one side edge of the middle F1 can be arranged in a stepped manner, as shown by the three slits 510 on the right side in FIG. 12. The stepped arrangement is helpful for increasing the light transmittance of the display substrate. The number and distribution of the slits 510 included in a single pixel electrode 51 can be set as needed, and the present disclosure does not limit this. In the case where the plurality of slits 510 of a single pixel electrode 51 include a stepped arrangement, the positions of the first end F2 and the second end F3 of different slits 510 are different, and the positions of the first end F2, the second end F3 and the main body are not marked in FIG. 8.

[0098] In the example embodiment, in the case of the stepped distribution of the adjacent slits 510, the electric field intensity of the middle part F1 of the slit 510 is different from that of the two side ends, and the influence on the arrangement of the liquid crystal molecules is also different. The present inventors have found through research that, in the second direction Y, when the distance between the second ends F3 of the adjacent slits 510 is greater than 6 microns, the electric field intensity of the middle part F1 of the slit 510 is less than that of the end part of the slit 510, and the liquid crystal molecules located near the middle part F1 are greatly affected, and after the finger is moved across the screen, a scratch defect is formed. Taking the case of the adjacent slit A and slit B as an example, the "distance between the second ends F3 of the adjacent slits 510" can be the distance between the side edge of the second end F3 of the slit A away from the middle part F1 and the side edge of the second end F3 of the slit B away from the middle part F1 in the first direction X. The case of the stepped distribution of the slit 510 at the first end F2 is similar to that at the second end F3, and will not be described here again.

[0099] In the example embodiment, in the case of the stepped distribution of the adjacent slits 510, in the second direction Y, the distance between the second ends F3 of the adjacent slits 510 is less than or equal to 6 microns, which can ensure that no scratch defect is formed. In the example embodiment, as shown in FIG. 12, the single pixel electrode 51 can include five slits 510, in order from left to right, the first slit, the second slit, the third slit, the fourth slit, and the fifth slit, the two ends of the first slit, the second slit, and the third slit are flush with each other in the second direction Y, the distance between the second end F3 of the fourth slit and the second end F3 of the third slit can be a first distance H1, and the distance between the second end F3 of the fifth slit and the second end F3 of the fourth slit can be a second distance H2. Through experiments, it has been found that, in the case where the first distance H1 and the second distance H2 are both less than or equal to 6 microns, after the finger is moved away from the screen for about 500 milliseconds, the dark trace on the screen disappears, and no scratch defect is formed.

[0100] The structures in the embodiments of the present disclosure can be combined with each other arbitrarily, and the present disclosure does not limit this.

[0101] FIGS. 13A to 13D are top views of pixel electrodes of sub-pixels in example embodiments, which show the setting of the plurality of slits 510 in different lengths, and the present inventors have conducted simulation experiments for each case. The difference between the display panels in FIGS. 13A to 13D is only the setting of the slits 510.

[0102] In FIG. 13A, the two ends of the first, second, and third slits are flush with each other along the second direction Y, the fourth and fifth slits are arranged in a stepped manner, the distance between the second end F3 of the third slit and the second end F3 of the fourth slit is about 11.6 microns, and the distance between the second end F3 of the fourth slit and the second end F3 of the fifth slit is about 7 microns. It is found through simulation that, since the first distance H1 and the second distance H2 are both greater than 6 microns, the display panel of the structure shown in FIG. 13A will have scratch defects near the fourth and fifth slits. In FIG. 13B, the two ends of the first and second slits are flush with each other along the second direction Y, the third, fourth, and fifth slits are arranged in a stepped manner, the distance between the second end F3 of the second slit and the second end F3 of the third slit is about 3.6 microns, the distance between the second end F3 of the third slit and the second end F3 of the fourth slit is about 8 microns, and the distance between the second end F3 of the fourth slit and the second end F3 of the fifth slit is about 5 microns. It is found through simulation that, since the distance between the second end F3 of the third slit and the second end F3 of the fourth slit is greater than 6 microns, the display panel of the structure shown in FIG. 13B will have scratch defects near the third slit. In FIG. 13C, the two ends of the first and second slits are flush with each other along the second direction Y, the third, fourth, and fifth slits are arranged in a stepped manner, the distance between the second end F3 of the second slit and the second end F3 of the third slit is about 5.6 microns, the distance between the second end F3 of the third slit and the second end F3 of the fourth slit is about 6 microns, and the distance between the second end F3 of the fourth slit and the second end F3 of the fifth slit is about 5 microns. It is found through simulation that, since the distance between the second end F3 of the third slit and the second end F3 of the fourth slit is less than 6 microns, the display panel of the structure shown in FIG. 13C will have the darkened trace on the screen disappear in about 700 milliseconds after the finger leaves the screen, and will not have scratch defects. In FIG. 13D, the two ends of the first, second, and third slits are flush with each other along the second direction Y, the fourth and fifth slits are arranged in a stepped manner, the distance between the second end F3 of the third slit and the second end F3 of the fourth slit is about 6 microns, and the distance between the second end F3 of the fourth slit and the second end F3 of the fifth slit is about 6 microns. It is found through simulation that, the display panel of the structure shown in FIG. 13D will have the darkened trace on the screen disappear in about 500 milliseconds after the finger leaves the screen, and will not have scratch defects.

[0103] FIG. 14 is a cross-sectional view of the display substrate of FIG. 2 along the CC direction in an exemplary embodiment. As shown in FIG. 14, the display substrate can include a substrate 10, a first transistor, a gate line S, and a data line D disposed on the substrate 10. In a direction away from the substrate 10, the display substrate can include a first conductive layer, a first insulating layer 11, a semiconductor layer, a first transparent conductive layer, a second conductive layer, a first organic layer 71, a second insulating layer 12, and a third conductive layer. The first insulating layer 11 and the second insulating layer 12 are inorganic insulating layers, the first insulating layer 11 can be referred to as a gate insulating (GI) layer, and the second insulating layer 12 can be referred to as a passivation layer (PVX). In an exemplary embodiment, the first conductive layer and the second conductive layer can employ a conductive material such as a metal material, and the first transparent conductive layer and the third conductive layer can employ a transparent conductive material.

[0104] In an example embodiment, as shown in FIG. 14, the first conductive layer at least includes: the gate electrode 22 of the first transistor and the gate line S. The gate electrode 22 of the first transistor and the corresponding gate line S can be arranged as an integrated structure. The semiconductor layer at least includes: the active layer 31 of the first transistor. The active layer 31 can include: a channel region, a first doped region and a second doped region. The channel region can not be doped with impurities and has semiconductor properties. The first doped region and the second doped region can be on both sides of the channel region and are doped with impurities and thus have electrical conductivity. The impurities can vary according to the type of transistor (e.g., N-type or P-type). The gate electrode 22 of the first transistor and the gate line S can be an integrated structure, and in a direction perpendicular to the substrate 10, the part where the gate line S and the active layer 31 overlap can be used as the gate electrode 22 of the first transistor. The first transparent conductive layer at least includes: the first electrode 51. The second conductive layer at least includes: the first electrode 44, the second electrode 45 of the first transistor and the data line D. The first electrode 44 of the first transistor overlaps and is directly connected to the first doped region of the active layer 31, and the second electrode 45 overlaps and is directly connected to the second doped region of the active layer 31. The first electrode 44 of the first transistor and the adjacent data line D can be an integrated structure, and the first electrode 44 can be, for example, a source electrode. The second electrode 45 of the first transistor has an orthogonal projection on the substrate 10 that overlaps the first electrode 51, and the second electrode 45 of the first transistor is directly connected to the first electrode 51, and the second electrode 45 can be, for example, a drain electrode. For example, the first electrode 51 can have a plurality of slits, and the extension direction of the plurality of slits can cross the first direction X, and the first electrode 51 can have slits of two different directions, thereby forming a dual-domain structure, however, the present embodiment is not limited thereto. For example, the first electrode 51 can form a single-domain or multi-domain structure. The third conductive layer at least includes: a plurality of second electrodes 61, and the second electrode 61 can be a sheet electrode, and the orthogonal projection of the second electrode 61 and the first electrode 51 on the substrate 10 can overlap each other, and the second electrodes 61 of different sub-pixels can be connected to each other. The second electrode 61 and the first electrode 51 are located in the sub-pixel region defined by the intersection of the data line 43 and the gate line 21. In other embodiments, the display substrate can adopt other forms of film layer arrangement, for example, the film layers where the first electrode 51 and the second electrode 61 are located can be exchanged with each other, and the present disclosure is not limited thereto.

[0105] The present disclosure also provides a display device, which includes the aforementioned display substrate, a counter substrate, and a liquid crystal layer arranged between the display substrate and the counter substrate. The display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, an LCD display, a notebook computer, a digital photo frame, a navigator, etc., and the present disclosure is not limited thereto.

[0106] In the example embodiment, the liquid crystal material of the liquid crystal layer is positive liquid crystal, and the dielectric constant is less than or equal to 8. The dielectric constant of the liquid crystal material is Δε = ε / / - ε⊥, where ε / / represents the dielectric coefficient in the direction parallel to the axis of the liquid crystal molecule, and ε⊥ represents the dielectric coefficient in the direction perpendicular to the axis of the liquid crystal molecule. The dielectric constant of the positive liquid crystal is greater than 0, the rotation direction is parallel to the electric field direction, and the angle of rotation under the electric field disturbance is large. In the example, the liquid crystal material with the dielectric constant less than or equal to 8 is selected, the driving voltage required for the rotation of the liquid crystal molecule is large, and the angle of rotation is small, which can effectively prevent the rotation angle of the liquid crystal molecule under the electric field disturbance, and is not prone to arrangement disorder, which is helpful to avoid scratch defects.

[0107] In the example embodiment, the liquid crystal material of the liquid crystal layer is negative liquid crystal. The dielectric constant of the negative liquid crystal is less than 0, the rigidity is strong, and the rotation direction is perpendicular to the electric field direction, which is not prone to be affected by the electric field disturbance, and is helpful to avoid scratch defects.

[0108] Although the embodiments disclosed in the present disclosure are as described above, the content described above is only the embodiments adopted for the purpose of facilitating the understanding of the embodiments of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined in the appended claims.

Claims

1. A display substrate, comprising: a plurality of data lines extending in a first direction; a plurality of gate lines extending in a second direction, the first direction and the second direction crossing each other; a plurality of the gate lines and a plurality of the data lines crossing to define a plurality of sub-pixel regions; a plurality of sub-pixels, each of the sub-pixels being located in one of the sub-pixel regions; at least one of the sub-pixels comprising a driving circuit, a first electrode and a second electrode disposed on a substrate, the first electrode and the second electrode at least partially overlapping in a direction away from the substrate; the driving circuit being electrically connected to one of the gate lines, one of the data lines and the first electrode respectively, and configured to transmit an electrical signal of the data line to the first electrode under control of the gate line; wherein a projection of the second electrode on the substrate covers a projection of the gate line on the substrate. 2.The display substrate of claim 1, wherein, the first electrode comprising a plurality of slits, at least two of the slits extending in the same direction. 3.The display substrate of claim 2, wherein, the slit comprising a middle portion, a first end portion and a second end portion connected to each other, the first end portion and the second end portion being located on two sides of the middle portion along the first direction respectively. 4.The display substrate of claim 3, wherein, an included angle between the extending direction of the first end portion and the second direction is a first angle a1, the first angle a1 being less than or equal to 55 degrees. 5.The display substrate of claim 4, wherein, a first length L1 of the first end portion is a maximum distance between opposite ends of the first end portion in the extending direction of the first end portion. a first depth V1 of the first end portion is greater than or equal to 3.5 microns, V1 = L1*sin(a1). 6.The display substrate of claim 3, wherein, an included angle between the extending direction of the second end portion and the second direction is a second angle a2, the second angle a2 being less than or equal to 55 degrees. 7.The display substrate of claim 6, wherein, a second length L2 of the second end portion is a maximum distance between opposite ends of the second end portion in the extending direction of the second end portion. a second depth V2 of the second end portion is greater than or equal to 3.5 microns, V2 = L2*sin(a2). 8.The display substrate of claim 3, wherein, the plurality of the slits are arranged in sequence along the second direction; in the second direction, first end portions of at least two of the slits away from one side edge of the middle portion are flush with each other, and second end portions of the at least two of the slits away from the one side edge of the middle portion are flush with each other. 9.The display substrate of claim 3, wherein, the plurality of the slits are arranged in sequence along the second direction; first end portions of at least two of the slits adjacent to each other in the second direction away from one side edge of the middle portion are arranged in a stepped manner, or second end portions of the at least two of the slits adjacent to each other in the second direction away from the one side edge of the middle portion are arranged in a stepped manner. 10.The display substrate of claim 3, wherein, the plurality of the slits are arranged in sequence along the second direction; first end portions of at least two of the slits adjacent to each other in the second direction away from one side edge of the middle portion are arranged in a stepped manner, and second end portions of the at least two of the slits adjacent to each other in the second direction away from the one side edge of the middle portion are arranged in a stepped manner. 11.The display substrate according to claim 9 or 10, wherein In a case where first end portions of at least two of the slits adjacent in the second direction are arranged in a stepped manner away from the side edge of the middle portion, a distance between the first end portions of the adjacent slits is less than or equal to 6 micrometers; the distance between the first end portions of the adjacent slits is a distance in the first direction of the first end portions of the adjacent slits away from the side edge of the middle portion. 12.The display substrate according to claim 9 or 10, wherein In a case where second end portions of at least two of the slits adjacent in the second direction are arranged in a stepped manner away from the side edge of the middle portion, a distance between the second end portions of the adjacent slits is less than or equal to 6 micrometers; the distance between the second end portions of the adjacent slits is a distance in the first direction of the second end portions of the adjacent slits away from the side edge of the middle portion. 13.The display substrate of claim 1, wherein, The driving circuit includes a first transistor, a gate electrode of the first transistor is connected with the gate line in the extending direction of the gate line, a first electrode of the first transistor is connected with the data line, and a second electrode of the first transistor is connected with the first electrode. A projection of the second electrode on the substrate exposes a projection of the gate electrode of the first transistor on the substrate. 14.The display substrate of claim 13, wherein, An overlapping area of the projection of the second electrode on the substrate and the projection of the gate line and the gate electrode on the substrate is a first area, and a sum of areas of the projection of the gate line and the gate electrode on the substrate is a second area. A ratio of the first area to the second area is greater than or equal to 65% and less than or equal to 95%. 15.The display substrate of claim 13, wherein, The gate line and the gate electrode of the first transistor in the extending direction of the gate line are in an integrated structure. 16.The display substrate of claim 1, wherein, The plurality of sub-pixels includes a plurality of sub-pixel columns arranged in the first direction and a plurality of sub-pixel rows arranged in the second direction. Two of the gate lines are distributed between two of the sub-pixel rows adjacent in the first direction, and the sub-pixels in a single one of the sub-pixel rows are respectively electrically connected with the two of the gate lines adjacent in the first direction.

17. A display device, comprising the display substrate according to any one of claims 1 to 16, an opposite substrate, and a liquid crystal layer disposed between the display substrate and the opposite substrate.

18. The display device of claim 17, wherein, A dielectric constant of a liquid crystal material of the liquid crystal layer is less than or equal to 8; or the liquid crystal material of the liquid crystal layer is a negative liquid crystal.

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