Pre-matching circuit and power amplifier

Abstract

Embodiments of the present invention provide a pre-matching circuit and a power amplifier. The pre-matching circuit comprises: an input matching circuit, an active die, and an output matching circuit. The input matching circuit comprises a plurality of groups of input matching units which are connected in parallel, wherein each group of input matching units comprise a first capacitor having a ground terminal, a first inductor, and a second inductor; the first inductor is connected in series to the second inductor; the first capacitor is connected to a connection point between the first inductor and the second inductor; the active die comprises a plurality of groups of cells which are connected in parallel, wherein the plurality of groups of cells which are connected in parallel are connected one by one to the plurality of groups of input matching units which are connected in parallel; and the output matching circuit is connected to the active die.

Description

A pre-matching circuit and a power amplifier

[0001] Cross Reference to Related Applications

[0002] The present application is based on Chinese Patent Application No. 202410873394.5, filed on July 1, 2024, entitled “A pre-matching circuit and a power amplifier”, and claims priority to the patent application, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Embodiments of the present disclosure relate to the field of communication technology, in particular to a pre-matching circuit and a power amplifier. BACKGROUND

[0004] Power amplifiers in wireless communication systems are usually used to amplify the power of radio frequency signals. With the rapid growth of requirements related to data rate, spectrum utilization and system capacity, modern wireless communication systems use more and more complex and high-order modulation methods and system architectures, and the signal bandwidth is wider and wider, and the performance requirements of power amplifiers are also higher and higher, and the performance of power amplifiers is mainly affected by the impedance matching circuit of the active die. In order to realize the miniaturization of the system, a part of the impedance matching circuit is packaged together with the active die inside the power amplifier, which is called a pre-matching circuit.

[0005] The active die is synthesized by a plurality of unit cells, and the higher the power requirement, the more unit cells the active die contains. In some cases, some unit cells will be coupled to other unit cells through structures such as matching circuits in the power amplifier, which will cause self-oscillation, especially for high-power power amplifiers, the number of unit cells is large, and the coupling between them is very complex, and it is very easy to cause self-oscillation. In addition, in the face of increasingly wide signal bandwidth, the possibility of power tube self-oscillation is also increasing, and once oscillation occurs inside the power amplifier, it is difficult to eliminate the oscillation according to the conventional pre-matching circuit while ensuring the basic performance of the power amplifier. SUMMARY

[0006] Embodiments of the present disclosure provide a pre-matching circuit and a power amplifier to at least solve the problem that the conventional pre-matching circuit is difficult to ensure the stability of the power amplifier while ensuring the good basic performance of the power amplifier for power amplifiers with high performance requirements in the related art.

[0007] According to one embodiment of the present disclosure, a pre-matching circuit is provided, comprising: an input matching circuit, an active die, and an output matching circuit; the input matching circuit comprises a plurality of groups of input matching units connected in parallel, wherein each group of input matching units comprises a first capacitor with a ground terminal, a first inductor, and a second inductor, the first inductor and the second inductor are connected in series, and the first capacitor is connected at the connection point of the first inductor and the second inductor; the active die comprises a plurality of groups of cells connected in parallel, wherein the plurality of groups of cells are connected one by one with the plurality of groups of input matching units; and the output matching circuit is connected with the active die.

[0008] According to another embodiment of the present disclosure, a power amplifier is provided, comprising: the pre-matching circuit in the above embodiment. BRIEF DESCRIPTION OF DRAWINGS

[0009] FIG. 1 is a schematic diagram of the internal structure of a power amplifier in the related art;

[0010] FIG. 2 is a schematic diagram of the internal structure of a power amplifier one according to an embodiment of the present disclosure;

[0011] FIG. 3 is a schematic diagram of the structure of the power amplifier one according to an embodiment of the present disclosure;

[0012] FIG. 4 is a schematic diagram of the structure of the power amplifier one according to an embodiment of the present disclosure;

[0013] FIG. 5 is a schematic diagram of the internal structure of a power amplifier two according to an embodiment of the present disclosure;

[0014] FIG. 6 is a schematic diagram of the structure of the power amplifier two according to an embodiment of the present disclosure;

[0015] FIG. 7 is a schematic diagram of the internal structure of a power amplifier three according to an embodiment of the present disclosure;

[0016] FIG. 8 is a schematic diagram of the structure of the power amplifier three according to an embodiment of the present disclosure;

[0017] FIG. 9 is a schematic diagram of the internal structure of a power amplifier four according to an embodiment of the present disclosure;

[0018] FIG. 10 is a schematic diagram of the structure of the power amplifier three according to an embodiment of the present disclosure;

[0019] FIG. 11 is a schematic diagram of the internal structure of a power amplifier five according to an embodiment of the present disclosure;

[0020] FIG. 12 is a schematic diagram of the structure of the power amplifier five according to an embodiment of the present disclosure;

[0021] FIG. 13 is a schematic diagram of the internal structure of a power amplifier six according to an embodiment of the present disclosure;

[0022] FIG. 14 is a structural schematic diagram of a power amplifier six according to an embodiment of the present disclosure;

[0023] FIG. 15 is a schematic diagram of a radio frequency loop in which feedback exists in a power amplifier in the related art;

[0024] FIG. 16 is a schematic diagram of a radio frequency loop before improvement based on a power amplifier one according to an embodiment of the present disclosure;

[0025] FIG. 17 is a schematic diagram of a radio frequency loop after improvement based on a power amplifier one according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0027] It should be noted that the terms "first", "second", and the like in the specification and claims of the present disclosure and the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence.

[0028] A power amplifier, abbreviated as a power amplifier tube, is used to amplify the power of a radio frequency signal. FIG. 1 is a schematic diagram of the internal structure of a power amplifier in the related art, as shown in FIG. 1, in order to realize system miniaturization, an impedance matching circuit and an active tube core are usually packaged together inside the power amplifier, which is called a pre-matching circuit.

[0029] As shown in FIG. 1, the impedance matching circuit in the pre-matching circuit includes an output matching circuit and an input matching circuit, including a bonding wire, a capacitor, a resistor, etc. The matching circuit outside the power amplifier is called a board-level matching circuit, which generally uses a microstrip line structure and a combination of discrete capacitors and discrete inductors.

[0030] The basic purpose of the pre-matching circuit is to match the active tube core to a suitable impedance, which facilitates the implementation of the board-level matching circuit, for example: the input matching circuit shown in FIG. 1 includes inductor L1 and inductor L2 and capacitor C'1, and the output matching circuit includes inductor L'1 and inductor L'2 and capacitor C'2. By adjusting the inductor value of each inductor and the capacitance value of the capacitor in the input matching circuit and / or the output matching circuit, the required impedance value can be obtained. In addition, harmonic control circuits and the like can also be added to the pre-matching circuit to control the performance of the power amplifier, such as efficiency. The implementation of the active tube core in the power amplifier includes but is not limited to GaN, LDMOS, GaAs, etc., which all have a certain power density, and different output powers are mainly obtained by changing the gate width.

[0031] The embodiment of the present disclosure provides a high-stability wideband high-power power amplifier tube pre-matching technology, which is based on the original matching circuit (i.e., FIG. 1), and the matching circuit network is reasonably split, that is, the input matching circuit is set as multiple groups of input matching units, and / or the output matching unit is set as multiple groups of output matching units, so that the coupling amount between different cells of the active tube core is changed, thereby suppressing the odd mode self-oscillation and improving the stability of the power amplifier.

[0032] In one embodiment, the input matching circuit includes multiple groups of parallel input matching units, wherein each group of input matching units includes: a first capacitor with a ground terminal, a first inductor and a second inductor, the first inductor and the second inductor are connected in series, and the first capacitor is connected at the connection point of the first inductor and the second inductor; an active tube core including multiple groups of parallel cells, wherein the multiple groups of parallel cells are connected one-to-one with the multiple groups of parallel input matching units; and an output matching circuit connected with the active tube core.

[0033] In the embodiment, the connection relationship between the structures inside the power amplifier at least includes: the connection relationship between the structures in the input matching unit, the connection relationship between the input matching unit and the corresponding cell, the connection relationship between the multiple groups of cells, the connection relationship between the multiple groups of cells and the output matching circuit, and the corresponding connection relationship of other structures.

[0034] FIG. 2 is a schematic diagram of the internal structure of a power amplifier according to an embodiment of the present disclosure, which shows the internal structure of the power amplifier, taking the example that the active tube core includes two groups (the mth group and the nth group) of cells, and two groups of input matching units are correspondingly set in the input matching circuit, as shown in FIG. 2, the power amplifier includes: an input pin, an input matching circuit, an active tube core, an output matching circuit, and an output pin. The input matching circuit is connected with the corresponding gate of the active tube core, and the output matching circuit is connected with the drain of the active tube core.

[0035] The connection relationship between the structures in the input matching unit includes the connection relationship between the structures in the mth group of input matching units and the connection relationship between the structures in the nth group of input matching units.

[0036] The connection relationship between the structures in the mth group of input matching units includes: the mth group of first inductors L m1 , which are connected in series between the input pin and the mth group of first capacitors C m1 ; the mth group of second inductors L m2 , which are connected in series between the gate of the field effect tube of the mth group of cells and the mth group of first capacitors C m1 ; the mth group of first capacitors C m1 , which are connected between the mth group of first inductors L m1 and the mth group of second inductors L m2The connection point connects the signal to ground in parallel;

[0037] The connection relationships between the structures in the nth group of input matching units include: the first inductor L in the nth group. n1 , connected in series with the input pin and the first capacitor C of the nth group n1 Between; the second inductor L of the nth group n2 The gate of the nth unit cell and the first capacitor C of the nth group are connected in series. n1 Between; the first capacitor C of the nth group n1 In the nth group, the first inductor L n1 and the second inductor L of the nth group n2 The connection point connects the signal to ground in parallel.

[0038] The first capacitor includes the m-th group of first capacitors C. m1 and the first capacitor C of the nth group n1 The first inductor includes the m-th group of first inductors L. m1 and the first inductor L of the nth group n1 The second inductor includes the m-th group of second inductors L. m2 and the second inductor L of the nth group n2 .

[0039] The connection relationship between the input matching unit and the corresponding unit cell includes: the first inductor L of the m-th group m1 Connect the gate of the field-effect transistor in the m-th group of unit cells, and the first inductor L in the n-th group. n1 Connect the gate of the field-effect transistor in the nth unit cell.

[0040] The connection relationships between multiple groups of unit cells include: the drain of the field effect transistor in the m-th group of unit cells is connected to the drain of the field effect transistor in the n-th group of unit cells; the source of the field effect transistor in the m-th group of unit cells is grounded, and the source of the field effect transistor in the n-th group of unit cells is grounded.

[0041] The connection relationship between multiple sets of unit cells and the output matching circuit includes: the output matching circuit is connected to the connection point between the drain of the field effect transistor in the m-th unit cell and the drain of the field effect transistor in the n-th unit cell. That is, as shown in Figure 2, after the drain of the field effect transistor in the m-th unit cell and the drain of the field effect transistor in the n-th unit cell are connected to one point, they are connected together to the output matching circuit.

[0042] The structural configuration of power amplifier one in practical application is shown in Figure 3. Figure 3 is a schematic diagram of the structure of power amplifier one according to an embodiment of the present disclosure, wherein the first inductor L of the m-th group in Figure 2 is... m1 Corresponding to the bonding line array L in Figure 3 11 The second inductor L in the m-th group in Figure 2 m2 Corresponding to the bonding wire array L in Figure 3 12; the mth group of first capacitors C in FIG. 2 m1 Corresponding to the capacitor C in FIG. 3 11 ; the nth group of first inductors L in FIG. 2 n1 Corresponding to the bonding wire array L in FIG. 3 21 ; the nth group of second inductors L in FIG. 2 n2 Corresponding to the bonding wire array L in FIG. 3 22 ; the nth group of first capacitors C in FIG. 2 n1 Corresponding to the capacitor C in FIG. 3 21 .

[0043] In actual applications, the mth group of first capacitors C m1 and the nth group of first capacitors C n1 may be two capacitors arranged on the same semiconductor substrate, and the pads thereof are not directly connected, as shown in FIG. 3; or as shown in FIG. 4, the two capacitors are located on different semiconductor substrates. In FIG. 4, the reference numerals of the structures are the same as those of the corresponding structures in FIG. 3, and therefore, the correspondence between the structures in FIG. 4 and the structures in FIG. 2 can be referred to the correspondence between the structures in FIG. 3 and the structures in FIG. 2, which will not be described herein again.

[0044] In one embodiment, the input matching circuit further comprises a third inductor (i.e., L3) and a second capacitor (i.e., C2) with a ground terminal, wherein the third inductor is connected in series with the plurality of groups of input matching units and the active die; and the second capacitor is connected between the plurality of groups of input matching units and the third inductor.

[0045] FIG. 5 is a schematic diagram of the internal structure of a power amplifier two according to an embodiment of the present disclosure. As shown in FIG. 5, the power amplifier two is additionally provided with a third inductor L3 and a second capacitor C2 in structure compared with the power amplifier one.

[0046] The connection relationship between the structures in the mth group of input matching units comprises: the mth group of first inductors L m1 connected in series between the input pin and the mth group of first capacitors C m1 ; the mth group of second inductors L m2 connected in series between the mth group of first capacitors C m1 and the second capacitor C2; the mth group of first capacitors C m1 connected in parallel to the ground at the connection point of the mth group of first inductors L m1 and the mth group of second inductors L m2 .

[0047] The connection relationship between the structures in the nth group of input matching units comprises: the nth group of first inductors L n1, the n th group of first inductors L n1 , the n th group of second inductors L n2 , the n th group of first inductors L n1 and the second capacitor C2; the n th group of first inductors L n1 , the n th group of first inductors L n1 and the n th group of second inductors L n2 in parallel to ground at the connection point of the n th group of first inductors L

[0048] As shown in FIG. 5, due to the arrangement of a third inductor L3 and a second capacitor C2, the power amplifier two further includes the following connection relationship:

[0049] The connection relationship corresponding to other structures includes: the second capacitor C2 is connected in parallel to ground at the connection point of the m th group of second inductors L m2 , the n th group of second inductors L n2 and the third inductor L3; the third inductor L3 is connected in series between the connection point of the plurality of single-cell field effect tube gates and the second capacitor C2. The connection point of the m th group of second inductors L m2 , the n th group of second inductors L n2 and the third inductor L3 is a point that simultaneously connects the m th group of second inductors L m2 , the n th group of second inductors L n2 and the third inductor L3; and the connection point of the plurality of single-cell field effect tube gates is a point that simultaneously connects the plurality of single-cell field effect tube gates.

[0050] The other connection relationship of the power amplifier two is the same as that of the power amplifier one, and the embodiment will not be described here.

[0051] The structure arrangement of the power amplifier two in actual application is shown in FIG. 6, which is a structure schematic diagram of the power amplifier two according to the embodiment of the present disclosure. In FIG. 6, the m th group of first inductors L m1 in FIG. 5 corresponds to the bonding wire array L 11 in the embodiment shown in FIG. 6; the m th group of second inductors L m2 in FIG. 5 corresponds to the bonding wire array L 12 in FIG. 6; the m th group of first inductors C m1 in FIG. 5 corresponds to the capacitor C 11 in FIG. 6; the n th group of first inductors L n1 in FIG. 5 corresponds to the bonding wire array L 21 in FIG. 6; and the n th group of second inductors L n2 in FIG. 5 corresponds to the bonding wire array L 22; the second capacitor C2 in FIG. 5 corresponds to the second capacitor C2 in FIG. 6; the third inductor L3 in FIG. 5 corresponds to the bonding wire array L3 in FIG. 6, and the nth group of first capacitors C n1 corresponds to the capacitor C in FIG. 6 21 .

[0052] In one embodiment, the input matching circuit further comprises: a fourth inductor (i.e., L4) and a third capacitor (i.e., C3) with a ground terminal, wherein the third capacitor is in series with the fourth inductor, the fourth inductor is in series between the third capacitor and the active die, and the fourth inductor is in parallel with each group of unit cells.

[0053] FIG. 7 is a schematic diagram of the internal structure of the third power amplifier according to an embodiment of the present disclosure. As shown in FIG. 7, the third power amplifier is additionally provided with a fourth inductor L4 and a third capacitor C3 in structure compared with the first power amplifier.

[0054] The connection relationship between the structures in the mth group of input matching units includes: the mth group of first inductors L m1 , which are in series between the input pin and the mth group of first capacitors C m1 ; the mth group of second inductors L m2 , which are in series between the mth group of first capacitors C m1 and the gate connection points of each group of unit cells; the mth group of first capacitors C m1 , which are in parallel between the connection points of the mth group of first inductors L m1 and the mth group of second inductors L m2 and ground.

[0055] The connection relationship between the structures in the nth group of input matching units includes: the nth group of first inductors L n1 , which are in series between the input pin and the nth group of first capacitors C n1 ; the nth group of second inductors L n2 , which are in series between the nth group of first capacitors C n1 and the gate connection points of each group of unit cells; the nth group of first capacitors C n1 , which are in parallel between the connection points of the nth group of first inductors L n1 and the nth group of second inductors L n2 and ground.

[0056] As shown in FIG. 7, due to the provision of a fourth inductor L4 and a third capacitor C3, the third power amplifier further includes the following connection relationship:

[0057] The connection relationship corresponding to other structures includes: the third capacitor C3 and the fourth inductor L4 are connected in series, and after the third capacitor C3 and the fourth inductor L4 are connected in series, the third capacitor C3 and the fourth inductor L4 are connected in parallel to the ground at the gate connection point of each group of unit cells as a whole, that is, the third capacitor C3 and the fourth inductor L4 are connected in parallel to each unit cell as a whole.

[0058] The other connection relationship of the third power amplifier is the same as that of the first power amplifier, and details are not repeated here.

[0059] The structure of the third power amplifier in actual application is shown in FIG. 8, which is a structural schematic diagram of the third power amplifier according to an embodiment of the present disclosure. In FIG. 8, the mth group of first inductors L m1 in FIG. 7 correspond to the bonding wire array L 11 in the embodiment shown in FIG. 8. m2 The mth group of second inductors L 12 in FIG. 7 correspond to the bonding wire array L m1 in FIG. 8. 11 The mth group of first capacitors C n1 in FIG. 7 correspond to the capacitors C 21 in FIG. 8. n2 The n th group of first inductors L 22 in FIG. 7 correspond to the bonding wire array L n1 in FIG. 8. 21 The n th group of second inductors L mn in FIG. 7 correspond to the bonding wire array L mn in FIG. 8. m1 The n th group of first capacitors C m2 in FIG. 7 correspond to the capacitors C m1 in FIG. 8. m1 The third capacitor C3 in FIG. 7 corresponds to the capacitor C3 in FIG. 8, and the fourth inductor L4 in FIG. 7 corresponds to the bonding wire array L4 in FIG. 8.

[0060] In one embodiment, the input matching circuit further includes: a resistor connected in parallel between the first capacitors of two adjacent groups of input matching units (i.e., R mn ).

[0061] FIG. 9 is a schematic diagram of the internal structure of a fourth power amplifier according to an embodiment of the present disclosure. As shown in FIG. 9, the fourth power amplifier is additionally provided with a resistor R mn in structure compared with the first power amplifier.

[0062] The connection relationship between the structures in the mth group of input matching units includes: the mth group of first inductors L m1 connected in series between the input pin and the mth group of first capacitors Cm1; the mth group of second inductors L m2 connected in series between the gate of the mth group of unit cells and the mth group of first capacitors C m1 ; the mth group of first capacitors C m1 connected in parallel between the mth group of first inductors L m1and the connection point of the mth group of second inductors L m2 parallelly connects the signal to the ground;

[0063] The connection relationship between the structures in the nth group of input matching units includes: the nth group of first inductors L n1 connected in series between the input pin and the nth group of first capacitors C n1 ; the nth group of second inductors L n2 connected in series between the gate of the nth group of unit cells and the nth group of first capacitors C n1 ; the nth group of first capacitors C n1 parallelly connecting the signal to the ground at the connection point of the nth group of first inductors L n1 and the nth group of second inductors L n2 .

[0064] As shown in FIG. 9, the power amplifier four further includes the following connection relationship because of the resistor R mn .

[0065] The connection relationship corresponding to other structures includes: the resistor R mn parallelly connected between the mth group of first capacitors C m1 and the nth group of first capacitors C n1 .

[0066] The other connection relationship of the power amplifier four is the same as that of the power amplifier one, and the embodiment will not be described here.

[0067] The structure setting of the power amplifier four in actual application is shown in FIG. 10, which is a structure schematic diagram of the power amplifier three according to the embodiment of the present disclosure, wherein the mth group of first inductors L m1 in FIG. 9 corresponds to the bonding wire array L 11 in FIG. 10; the mth group of second inductors L m2 in FIG. 9 corresponds to the bonding wire array L 12 in FIG. 10; the mth group of first capacitors C m1 in FIG. 9 corresponds to the capacitor C 11 in FIG. 10; the nth group of first inductors L n1 in FIG. 9 corresponds to the bonding wire array L 21 in FIG. 10; the nth group of second inductors L n2 in FIG. 9 corresponds to the bonding wire array L 22 in FIG. 10; the nth group of first capacitors C n1 in FIG. 9 corresponds to the capacitor C 21 in FIG. 10; and the resistor R mn in FIG. 9 corresponds to the thin-film resistor R 12 in FIG. 10.

[0068] In the embodiments of the present disclosure, the unit cells in the active die are not limited to two unit cells, and more unit cells can be arranged according to the performance requirements of the power amplifier tube. The input matching circuit is not limited to two input matching units, and a corresponding number of input matching units can be added according to the number of unit cells.

[0069] In one embodiment, the output matching circuit includes a plurality of groups of first output matching units; each group of first output matching units includes a fifth inductor, a sixth inductor, and a fourth capacitor with a ground terminal; the fifth inductor and the sixth inductor are connected in series, and the fourth capacitor is connected to the connection point of the fifth inductor and the sixth inductor.

[0070] In the present embodiment, the connection relationship between the structures inside the power amplifier includes at least: the connection relationship between the structures in the output matching unit, the connection relationship between the output matching unit and the corresponding unit cell, the connection relationship between the plurality of groups of unit cells, the connection relationship between the plurality of groups of unit cells and the input matching circuit, and the corresponding connection relationship of other structures.

[0071] FIG. 11 is a schematic diagram of the internal structure of a power amplifier five according to an embodiment of the present disclosure, which includes two groups (the mth group and the nth group) of unit cells in the active die, and two groups of first output matching units are arranged in the output matching circuit as an example, to illustrate the internal structure of the power amplifier.

[0072] The connection relationship between the structures in the output matching unit includes: the connection relationship between the structures in the mth group of first output matching units, and the connection relationship between the structures in the nth group of first output matching units.

[0073] The connection relationship between the structures in the mth group of first output matching units includes: the mth group of fifth inductors L m5 connected in series between the drain of the field effect tube of the mth group of unit cells and the mth group of fourth capacitors C m4 The mth group of second inductors L m6 are connected in series between the output pin and the mth group of first capacitors C m4 The mth group of fourth capacitors C m4 are connected in parallel between the connection point of the mth group of fifth inductors L m5 and the mth group of sixth inductors L m6 to ground.

[0074] The connection relationship between the structures in the nth group of first output matching units includes: the nth group of fifth inductors L n5 connected in series between the drain of the field effect tube of the nth group of unit cells and the nth group of fourth capacitors C n4 The nth group of sixth inductors L n6 are connected in series between the output pin and the nth group of fourth capacitors C n4 The nth group of fourth capacitors Cn4 the connecting point of the nth group of the fifth inductor L n5 and the nth group of the sixth inductor L n6 parallel the signal to the ground.

[0075] wherein the fourth capacitor comprises the mth group of the fourth capacitor C m4 and the nth group of the fourth capacitor C n4 ; the fifth inductor comprises the mth group of the fifth inductor L m5 and the nth group of the fifth inductor L n5 ; the sixth inductor comprises the mth group of the sixth inductor L m6 and the nth group of the sixth inductor L n6 .

[0076] The connection relationship between the output matching unit and the corresponding unit cell comprises: the mth group of the fifth inductor L m5 connecting the drain of the field effect tube in the mth group of unit cells, the nth group of the fifth inductor L n5 connecting the drain of the field effect tube in the nth group of unit cells.

[0077] The connection relationship between the multiple groups of unit cells comprises: the drain of the field effect tube in the mth group of unit cells is connected with the gate of the field effect tube in the nth group of unit cells; the source of the field effect tube in the mth group of unit cells is grounded, and the source of the field effect tube in the nth group of unit cells is grounded.

[0078] The connection relationship between the multiple groups of unit cells and the input matching circuit comprises: the input matching circuit is connected to the connecting point of the gate of the field effect tube in the mth group of unit cells and the gate of the field effect tube in the nth group of unit cells. That is, as shown in FIG. 11, after the gate of the field effect tube in the mth group of unit cells and the gate of the field effect tube in the nth group of unit cells are connected to a point, the input matching circuit is connected to the point.

[0079] The structure of the power amplifier five in actual application is shown in FIG. 12, which is a structure schematic diagram of the power amplifier five according to the embodiment of the present disclosure, wherein the mth group of the fifth inductor L m5 in FIG. 11 corresponds to the bonding wire array L 11 in FIG. 12; the mth group of the sixth inductor L m6 in FIG. 11 is in the bonding wire array L 12 in FIG. 12; the mth group of the fourth capacitor C m4 in FIG. 11 corresponds to the capacitor C 11 in FIG. 12; the nth group of the fifth inductor L n5 in FIG. 11 corresponds to the bonding wire array L 21 in FIG. 12; the nth group of the sixth inductor L n6 in FIG. 11 corresponds to the bonding wire array L 22 in FIG. 12; the nth group of the fourth capacitor C n4Corresponding to the capacitor C in FIG. 12 21 .

[0080] In one embodiment, the pre-matching circuit further comprises: wherein the output matching circuit comprises a plurality of groups of second output matching units and a seventh inductor; each group of second output matching units comprises: a fifth capacitor with a ground terminal and an eighth inductor, the eighth inductor is in series with the fifth capacitor; the seventh inductor is connected in series between the active die and the output pin of the pre-matching circuit.

[0081] FIG. 13 is a schematic diagram of the internal structure of the power amplifier six according to an embodiment of the present disclosure, which includes two groups (the mth group and the nth group) of unit cells in the active die, and two groups of input matching units are set in the input matching circuit as an example, to illustrate the internal structure of the power amplifier.

[0082] The connection relationship between the structures in the output matching unit includes: the connection relationship between the structures in the mth group of second output matching units, and the connection relationship between the structures in the nth group of second output matching units.

[0083] The connection relationship between the structures in the mth group of second output matching units includes: the mth group of eighth inductors L m8 , connected in series between the drain of the field effect tube of the mth group of unit cells and the mth group of fifth capacitors C m5 ; the mth group of fifth capacitors C m5 , are connected in parallel to the signal to ground at the mth group of eighth inductors L m8 .

[0084] The connection relationship between the structures in the nth group of second output matching units includes: the nth group of eighth inductors L n8 , connected in series between the drain of the field effect tube of the nth group of unit cells and the nth group of fifth capacitors C n5 ; the nth group of fifth capacitors C n5 , are connected in parallel to the signal to ground at the nth group of eighth inductors L n8 .

[0085] As shown in FIG. 13, in addition to setting multiple output matching units in the output matching circuit, the power amplifier six also additionally sets a seventh inductor L7, and the power amplifier six further includes the following connection relationship:

[0086] The corresponding connection relationship of other structures includes: the second inductor L7 is connected in series between the drain of the mth and nth group of unit cells and the output pin.

[0087] The structure setting of the power amplifier six in actual application is shown in FIG. 14, which is a structural schematic diagram of the power amplifier six according to an embodiment of the present disclosure, wherein the mth group of first inductors L m1Corresponding to the bonding wire array L in FIG. 14 11 ; the mth group of first capacitors C in FIG. 13 m1 Corresponding to the capacitor C in FIG. 14 11 ; the nth group of first inductors L in FIG. 13 n1 Corresponding to the bonding wire array L shown in FIG. 14 21 ; the nth group of first capacitors C in FIG. 13 n1 Corresponding to the capacitor C in FIG. 14 21 ; the second inductor L2 in FIG. 13 corresponds to the bonding wire array L2 in FIG. 14.

[0088] In the embodiments of the present disclosure, the output matching circuit is also not limited to being provided with two output matching units, and a corresponding number of input matching units can be added according to the number of unit cells.

[0089] In the embodiments of the present disclosure, any two or more of the power amplifiers one to six can be combined to obtain a new power amplifier. That is, except for the same parts, the other parts between the power amplifiers one to six can be combined with each other, for example, the third capacitor C3 and the fourth inductor L4 can also be connected according to the connection mode shown in FIG. 7 on the power amplifier two.

[0090] According to the above embodiments of the present disclosure, a plurality of groups of unit cells can be provided in the active die according to high performance requirements, and meanwhile, a plurality of groups of input matching units connected one by one with the plurality of groups of unit cells can be provided to reduce the coupling degree between different unit cells in the active die, and thus the generation of self-excited oscillation of the power amplifier can be suppressed. Therefore, the problem that the conventional pre-matching circuit cannot guarantee good basic performance of the power amplifier while taking into account the stability of the power amplifier for the power amplifier with high performance requirements in the related art can be solved, so that the effect of suppressing odd mode oscillation and improving the stability of the power amplifier can be achieved.

[0091] In the embodiments of the present disclosure, when the input circuit is split, in order to ensure that the impedance conditions matched by the gates of each group of unit cells are consistent, the split pre-matching circuit of the embodiments of the present disclosure follows the principle of symmetry and equality, that is, each capacitor split from the same capacitor should have the same capacitance, and each inductor split from the same inductor should have the same inductance, so as to avoid odd mode oscillation caused by asymmetry.

[0092] That is, the capacitance of the first capacitor of each group of input matching units is the same, the inductance of the first inductor of each group of input matching units is the same, and the inductance of the second inductor of each group of input matching units is the same.

[0093] The capacitance of the fourth capacitor of each group of output matching units is the same, the inductance of the fifth inductor of each group of output matching units is the same, and the inductance of the sixth inductor of each group of output matching units is the same.

[0094] For example, in FIG. 2, the inductance of the mth group of first inductors L m1 is equal to the inductance of the nth group of first inductors L n1 ; the inductance of the mth group of second inductors L m2 is equal to the inductance of the nth group of second inductors L n2 ; the capacitance of the mth group of first capacitors C m1 is equal to the capacitance of the nth group of first capacitors C n1 .

[0095] In the embodiments of the present disclosure, the implementation of the capacitor includes but is not limited to ceramic capacitor, Integrated Passive Device (IPD), and the implementation of the inductor includes but is not limited to bonding wire, IPD, etc.

[0096] In the embodiments of the present disclosure, the input matching circuit is provided with multiple input matching units or the output matching circuit is provided with multiple output matching units, including: splitting the inductors and / or capacitors in the existing input matching circuit or the existing output matching circuit, and the number of splitting is one or more. For example, the capacitor in the pre-matching circuit is split, and the splitting mode can be as shown in FIG. 3, that is, the same capacitor on the same semiconductor substrate is split into different capacitors; or as shown in FIG. 4, that is, the same capacitor on the same semiconductor is split into different capacitors on different semiconductor substrates. The splitting can be complete splitting as described above, or incomplete splitting as shown in FIG. 10, that is, an isolation resistor is added between the split capacitor pads. Correspondingly, the inductors connected to the related capacitors will also be split accordingly. In order to ensure that the impedance conditions matched by each group of unit cell gates are consistent, the splitting should follow the principle of symmetry and equality, that is, each capacitor split from the same capacitor should have the same capacitance, and each inductor split from the same inductor should have the same inductance, so as to avoid possible odd mode self-oscillation caused by asymmetry. The splitting mode includes but is not limited to the structures shown in FIGS. 2, 5, 7, 9, 11, and 13 and their mutual combinations. By different splitting modes, each group of unit cells will have different coupling amounts, and selecting a suitable splitting mode can suppress the oscillation caused by abnormal coupling between each group of unit cells.

[0097] The following is a description of the working principle of the pre-set matching circuit in the embodiments of the present disclosure, which can suppress self-oscillation caused by abnormal coupling between each group of unit cells:

[0098] As shown in FIG. 15, FIG. 15 is a schematic diagram of a radio frequency loop with feedback in a power amplifier in the related art, in which an input voltage is v i , a feedback loop signal is v f , a transfer function of the amplifier is A(jω), a transfer function of the feedback loop is β(jω), an input voltage of the amplifier can be represented as v d = v i + v f , an output voltage can be represented as v o =A(jω)v d , and a feedback voltage can be represented as v f =β(jω)v o . Then a closed loop gain can be represented as:

[0099] In the absence of an input v i , if the amplifier still has a non-zero output v o , the amplifier is self-excited, and at this time, there is a condition 1-β(jω)A(jω)=0, that is, β(jω)A(jω)=1, which is a boundary condition for oscillation occurrence, wherein β(jω)A(jω) is also referred to as a loop gain. When the power is turned on, if the loop gain is greater than 1, the thermal noise generated by the resistor and the transistor is amplified via the amplifier, and oscillation occurs.

[0100] Therefore, in a broadband high-power power amplifier, the active die scale is large, the number of unit cells is large, the coupling relationship between them is very complex, the loop gain of a group or multiple groups of unit cells is easily greater than 1, and then oscillation occurs, so that the stability of the power amplifier is greatly reduced.

[0101] In the embodiments of the present disclosure, the capacitor C1 in the input matching circuit shown in FIG. 16 is split into C m1 and C n1 in FIG. 17, and the capacitor C2 in the output matching circuit shown in FIG. 16 is split into C m2 and C n2 in FIG. 17. At this time, the feedback path through the capacitors C1 and C2 is cut off, the isolation degree between different groups of unit cells is improved, the transfer function β(jω) of the overall feedback loop is also changed, and then the loop gain β(jω)A(jω) is less than 1, achieving the effect of improving the stability of the power amplifier. The mth group of unit cells in FIG. 16 and FIG. 17 can be regarded as the power amplifier in FIG. 15, and the other groups of unit cells, the input matching circuit, the output matching circuit, and the like can be regarded as the feedback loop.

[0102] By splitting and combining the pre-matching circuit network, the coupling amount between different unit cells of the active die is changed, so as to suppress odd mode oscillation and improve the stability of the power amplifier.

[0103] In the present embodiment, a power amplifier is also provided for implementing the above-mentioned embodiments and preferred embodiments, which have been described above and will not be repeated here.

[0104] The above only provides preferred embodiments of the present disclosure and is not intended to limit the present disclosure. The present disclosure can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A pre-matching circuit, comprising: An input matching circuit, an active die, and an output matching circuit; The input matching circuit comprises a plurality of groups of input matching units connected in parallel, wherein each group of input matching units comprises a first capacitor with a ground terminal, a first inductor, and a second inductor, the first inductor and the second inductor are connected in series, and the first capacitor is connected to the connection point of the first inductor and the second inductor; The active die comprises a plurality of groups of cells connected in parallel, wherein the plurality of groups of cells are connected one by one with the plurality of groups of input matching units connected in parallel. The output matching circuit is connected with the active die.

2. The pre-matching circuit of claim 1, wherein, The input matching circuit further comprises a third inductor and a second capacitor with a ground terminal, wherein the third inductor is connected in series with the plurality of groups of input matching units connected in parallel and the active die respectively; and the second capacitor is connected to the connection point of the plurality of groups of input matching units connected in parallel and the third inductor.

3. The pre-matching circuit of claim 2, wherein, The input matching circuit further comprises a fourth inductor and a third capacitor with a ground terminal, wherein the third capacitor is connected in series with the fourth inductor, the fourth inductor is connected in series between the third capacitor and the active die, and the fourth inductor is connected in parallel with each group of cells.

4. The pre-matching circuit of claim 1, wherein, The input matching circuit further comprises a fourth inductor and a third capacitor with a ground terminal, wherein the third capacitor is connected in series with the fourth inductor, the fourth inductor is connected in series between the third capacitor and the active die, and the fourth inductor is connected in parallel with each group of cells.

5. A pre-matching circuit as claimed in any one of claims 1-4, wherein, The input matching circuit further comprises a resistor connected in parallel between the first capacitors of adjacent two groups of input matching units.

6. The pre-matching circuit of claim 1, wherein, The output matching circuit comprises a plurality of groups of first output matching units; Each group of first output matching units comprises a fifth inductor, a sixth inductor, and a fourth capacitor with a ground terminal; The fifth inductor and the sixth inductor are connected in series, and the fourth capacitor is connected to the connection point of the fifth inductor and the sixth inductor.

7. The pre-matching circuit of claim 1 or 6, wherein, The output matching circuit comprises a plurality of groups of second output matching units and a seventh inductor; Each group of second output matching units comprises a fifth capacitor with a ground terminal and an eighth inductor connected in series with the fifth capacitor; The seventh inductor is connected in series between the active die and the output pin of the pre-matching circuit.

8. The pre-matching circuit of claim 1, wherein, The capacitance of the first capacitors of each group of input matching units is the same, the inductance of the first inductors of each group of input matching units is the same, and the inductance of the second inductors of each group of input matching units is the same.

9. The pre-matching circuit of claim 6, wherein, The capacitance of the fourth capacitors of each group of output matching units is the same, the inductance of the fifth inductors of each group of output matching units is the same, and the inductance of the sixth inductors of each group of output matching units is the same.

10. A power amplifier comprising the pre-matching circuit of any one of claims 1-9.

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