Semiconductor device and power conversion device

Abstract

This semiconductor device (101) comprises: a board having a first surface (10A) and a second surface (10B) located on the opposite side from the first surface; and an electronic circuit mounted on the first surface and the second surface. The electronic circuit includes a plurality of semiconductor elements (20) arranged adjacently on the first surface; a first interconnection layer (30) disposed on the first surface; a second interconnection layer (40) disposed on the second surface; and a third interconnection layer (50) disposed so as to be spaced apart from the first interconnection layer in a first direction that intersects the first surface.

Description

Semiconductor device and power conversion device

[0001] The present disclosure relates to a semiconductor device and a power conversion device.

[0002] Semiconductor devices including modules incorporating multiple semiconductor elements are known. Japanese Patent Application Laid-Open Publication No. 2018-152591 (Patent Document 1) describes a power overlay (POL) submodule incorporating multiple power semiconductor elements. The semiconductor device described in Patent Document 1 includes a heat sink on one side of the multiple power semiconductor elements that is thermally connected to the multiple power semiconductor elements via conductive shims. Furthermore, the semiconductor device includes metal wiring electrically connected to the contact pads of each of the multiple power semiconductor elements and solder balls electrically connected to the contact pads via the metal wiring on the other side of the multiple power semiconductor elements.

[0003] Japanese Patent Application Laid-Open No. 2018-152591

[0004] In the semiconductor device described in Patent Document 1, metal wiring is provided only on the other side of the multiple power semiconductor elements. When the structure and function of such a semiconductor device are made more complex (for example, when the semiconductor device includes a 6-in-1 module capable of three-phase output), multiple metal wirings arranged side by side with an insulating distance between them are required, and the semiconductor device becomes larger in the in-plane direction.

[0005] A primary object of the present disclosure is to provide a technology that can suppress an increase in size of a semiconductor device in an in-plane direction. Another object of the present disclosure is to provide a technology that can suppress an increase in size of a power conversion device.

[0006] The semiconductor device according to the present disclosure includes a substrate having a first surface and a second surface located on the opposite side to the first surface, and an electronic circuit mounted on the first surface and the second surface. The electronic circuit includes a plurality of semiconductor elements arranged side by side on the first surface, a first wiring layer arranged on the first surface, a second wiring layer arranged on the second surface, and a third wiring layer arranged at a distance from the first wiring layer in a first direction intersecting the first surface.

[0007] According to the present disclosure, it is possible to prevent the semiconductor device and the power conversion device from increasing in size.

[0008] 11 is a cross-sectional view of a semiconductor device according to a first embodiment; FIG. 12 is a perspective view of a first surface side of the semiconductor device shown in FIG. 1; FIG. 13 is a cross-sectional view of a semiconductor device according to a second embodiment; FIG. 14 is a partially enlarged plan view for explaining the positional relationship between a semiconductor element and a third wiring layer in the semiconductor device shown in FIG. 3; FIG. 15 is a cross-sectional view of a semiconductor device according to a third embodiment; FIG. 16 is a partially enlarged plan view for explaining the positional relationship between a semiconductor element and a third wiring layer in the semiconductor device shown in FIG. 5; FIG. 17 is a cross-sectional view of a semiconductor device according to a fourth embodiment; FIG. 18 is a cross-sectional view of the semiconductor device shown in FIG. 7, different from FIG. 7; FIG. 19 is a partially enlarged plan view for explaining the positional relationship between a semiconductor element and a first wiring layer in the semiconductor device shown in FIGS. 7 and 8; FIG. 19 is a partially enlarged plan view for explaining the positional relationship between a semiconductor element and a third wiring layer in the semiconductor device shown in FIGS. 7 to 9;

[0009] Embodiments of the present disclosure will be described below with reference to the drawings. A semiconductor device according to an embodiment of the present disclosure includes a substrate having a first surface and an electronic circuit mounted on the substrate. The electronic circuit includes a plurality of semiconductor elements arranged side by side on the first surface, and a first wiring layer, a second wiring layer, and a third wiring layer stacked at intervals in a first direction perpendicular to the first surface. In this disclosure, a wiring layer refers to a structure including a plurality of wiring patterns arranged at intervals on a plane. Each of the plurality of wiring patterns constitutes a part of the electronic circuit together with the plurality of semiconductor elements. As an example, the plurality of wiring patterns are formed by patterning one or more conductive films using photolithography. As another example, the plurality of wiring patterns are conductive wires or conductive ribbons.

[0010] The semiconductor device according to the present embodiment includes, as an example, a 6-in-1 module having six semiconductor elements. In the semiconductor device according to the present embodiment, the six semiconductor elements are, for example, switching elements constituting upper and lower arms of three phases in a main conversion circuit of a power conversion device. The number and types of semiconductor elements included in the semiconductor device according to the present embodiment can be set arbitrarily. The semiconductor device according to the present embodiment includes, for example, multiple semiconductor elements included in the main conversion circuit of the power conversion device. The semiconductor device according to the present embodiment may further include at least one semiconductor element included in a control circuit of the power conversion device.

[0011] First Embodiment <Configuration of Semiconductor Device> Figure 1 is a cross-sectional view showing an example of a semiconductor device 101 according to the first embodiment. As shown in Figure 1, the semiconductor device 101 according to the first embodiment mainly includes a substrate 10, a plurality of semiconductor elements 20, 25, first wiring layers 30A, 30B, a second wiring layer 40, a third wiring layer 50, a plurality of connection terminals 60, and a first insulating film 70. The plurality of semiconductor elements 20, 25, the first wiring layers 30A, 30B, the second wiring layer 40, the third wiring layer 50, and the plurality of connection terminals 60 are components that constitute an electronic circuit mounted on the substrate 10.

[0012] The substrate 10 is electrically insulating. The substrate 10 has a first surface 10A and a second surface 10B located on the opposite side of the first surface 10A. The second surface 10B is, for example, parallel to the first surface 10A. The substrate 10 has a plurality of vias (not shown) that penetrate between the first surface 10A and the second surface 10B. The plurality of vias includes first vias and second vias.

[0013] Hereinafter, a direction perpendicular to the first surface 10A will be referred to as a first direction DR1. A direction along the first surface 10A will be referred to as an in-plane direction. Two in-plane directions along the first surface 10A and perpendicular to each other will be referred to as a second direction DR2 and a third direction DR3. FIG. 2 is a perspective view of the first surface 10A side of the semiconductor device 101 shown in FIG. 1. Note that FIG. 2 omits illustration of the third wiring layer 50, the first insulating film 70, and structures on the second surface 10B.

[0014] 2, the plurality of semiconductor elements 20, 25 are arranged side by side on the first surface 10A of the substrate 10. The plurality of semiconductor elements 20, 25 are arranged side by side on the first wiring layer 30. Each of the plurality of semiconductor elements 20, 25 is mounted on the first wiring layer 30 by a bonding member such as solder.

[0015] The plurality of semiconductor elements 20, 25 include a plurality of power semiconductor elements 20 and a plurality of IC (Integrated Circuit) elements 25. Each of the plurality of power semiconductor elements 20 is included in a main conversion circuit of the power conversion device according to this embodiment. Each of the plurality of IC elements 25 is included in a control circuit of the power conversion device according to this embodiment. The number of the plurality of power semiconductor elements 20 is, for example, six or more. The number of power semiconductor elements 20 may be any number equal to or greater than two. The number of the plurality of power semiconductor elements 20 may be four or eight.

[0016] The multiple power semiconductor elements 20 are arranged side by side at intervals in the second direction DR2. Each of the multiple power semiconductor elements 20 has a first electrode facing the first surface 10A and electrically connected to the first wiring layer 30, and a second electrode located on the opposite side to the first electrode and electrically connected to the third wiring layer 50. The first electrode faces the first surface 10A in the first direction DR1 and has a surface in contact with the first wiring layer 30. The second electrode faces the side opposite to the first surface 10A in the first direction DR1 and has a surface in contact with the third wiring layer 50.

[0017] Each of the multiple power semiconductor elements 20 is, for example, an IGBT (Insulated Gate Bipolar Transistor). Each power semiconductor element 20 has a third surface 20A and a fourth surface 20B located opposite the third surface 20A. Each power semiconductor element 20 further has a gate electrode and an emitter electrode formed on the third surface 20A at an interval from each other, and a collector electrode formed on the fourth surface 20B. The collector electrode is disposed, for example, over the entire fourth surface 20B. The surface area of ​​the collector electrode is larger than the surface area of ​​each of the gate electrode and the emitter electrode.

[0018] There are no particular limitations on the type of each of the plurality of power semiconductor elements 20. Each of the plurality of power semiconductor elements 20 may be a metal-oxide-semiconductor field-effect transistor (MOSFET) or a bipolar transistor.

[0019] In the semiconductor device 101, the collector electrode 21 of each power semiconductor element 20 is electrically connected to the first wiring layer 30. The gate electrode and emitter electrode 22 of each power semiconductor element 20 are electrically connected to each of the plurality of conductive members 51 included in the third wiring layer 50.

[0020] 2 , the multiple IC elements 25 are arranged side by side at intervals from one another in the second direction DR2. The multiple IC elements 25 are arranged, for example, at intervals from each of the multiple power semiconductor elements 20 in the third direction DR3. Each of the multiple IC elements 25 has a third electrode facing the first surface 10A and electrically connected to the first wiring layer 30, and a fourth electrode located on the opposite side to the third electrode and electrically connected to the third wiring layer 50.

[0021] The first wiring layer 30 is disposed on the first surface 10A of the substrate 10. The first wiring layer 30 is formed, for example, by patterning one or more conductor films formed on the first surface 10A using photolithography. The first wiring layer 30 has a plurality of patterns disposed at intervals from each other in the in-plane direction.

[0022] The first wiring layer 30 includes, for example, a plurality of first patterns 31 and a plurality of second patterns 32. Each of the plurality of first patterns 31 is electrically connected to a first electrode of each of the plurality of power semiconductor elements 20. Each of the plurality of second patterns 32 is electrically connected to a third electrode of each of the plurality of power semiconductor elements 20.

[0023] The second wiring layer 40 is disposed on the second surface 10B of the substrate 10. The second wiring layer 40 is formed, for example, by patterning one or more conductor films formed on the second surface 10B using photolithography. The second wiring layer 40 has a plurality of third patterns 41 disposed at intervals from one another in the in-plane direction.

[0024] The second wiring layer 40 includes, for example, a plurality of third patterns 41 and a plurality of fourth patterns (not shown). Each of the third patterns 41 is electrically connected to each of the first patterns 31 of the first wiring layer 30 via a first via provided in the substrate 10. Each of the fourth patterns is electrically connected to each of the second patterns 32 of the first wiring layer 30 via a second via provided in the substrate 10.

[0025] The third wiring layer 50 is disposed on the plurality of semiconductor elements 20, 25, and is disposed at a distance from the first wiring layer 30 in the first direction DR1. The third wiring layer 50 includes a plurality of conductive members 51. Each of the plurality of conductive members 51 is, for example, a conductive wire or a conductive ribbon. The plurality of conductive members 51 are disposed at a distance from one another in the in-plane direction.

[0026] The third wiring layer 50 includes, for example, a plurality of conductive members 51 electrically connected to the emitter electrodes 22 of each of the plurality of power semiconductor elements 20, a plurality of conductive members electrically connected to the gate electrodes of each of the plurality of power semiconductor elements 20, and a plurality of conductive members electrically connected to the fourth electrodes of each of the plurality of IC elements 25.

[0027] The material constituting each of the first wiring layer 30, the second wiring layer 40, and the third wiring layer 50 includes at least one selected from the group consisting of aluminum (Al), copper (Cu), gold (Au), silver (Ag), platinum (Pt), nickel (Ni), and palladium (Pd).

[0028] The spacing between the multiple first patterns 31 in the first wiring layer 30, the spacing between the multiple third patterns 41 in the second wiring layer 40, and the spacing between the multiple conductive members 51 in the third wiring layer 50 are each equal to or greater than the required insulation distance.

[0029] The multiple connection terminals 60 are connection terminals for electrically connecting the semiconductor device 101 to an external device. The multiple connection terminals 60 are electrically connected to the second wiring layer 40. Each of the multiple connection terminals 60 is, for example, a solder ball or a metal ball. Each of the multiple connection terminals 60 is arranged on a part of the second wiring layer 40. Each of the multiple connection terminals 60 is arranged at intervals from each other in the in-plane direction. Note that each of the multiple connection terminals 60 may have any structure as long as it can electrically connect the semiconductor device 101 to an external device.

[0030] The first insulating film 70 is disposed on the first surface 10A and covers the first surface 10A, the first wiring layer 30, the plurality of semiconductor elements 20 and 25, and the third wiring layer 50. The material constituting the first insulating film 70 has electrical insulation properties. Preferably, the thermal conductivity of the first insulating film 70 is higher than the thermal conductivity of the substrate 10.

[0031] The first insulating film 70 has a fifth surface 70A located on the first surface 10A. The fifth surface 70A is a surface that is thermally connected to a heat sink or other heat radiator (not shown). The first insulating film 70 is composed of, for example, a plurality of insulating films stacked on top of each other in the first direction DR1.

[0032] 1, the semiconductor device 101 has an outer surface 101O. The outer surface 101O is made of only an electrically insulating material. The first wiring layer 30, the second wiring layer 40, the third wiring layer 50, and other conductive components are not exposed on the outer surface 101O. The outer surface 101O is made up of, for example, the outer surface of the substrate 10 and the outer surface of the first insulating film 70.

[0033] As shown in FIG. 2 , the semiconductor device 101 has a first region R1 and a second region R2 in a plan view. A first circuit portion including a plurality of power semiconductor elements 20, a plurality of first patterns 31, and a plurality of third patterns 41 is mounted in the first region R1. A second circuit portion including a plurality of IC elements 25, a plurality of second patterns 32, and a plurality of fourth patterns is mounted in the second region R2. The first region R1 is, for example, a region in which at least a portion of a main conversion circuit that converts and outputs power input to the power conversion device is formed. The second region R2 is, for example, a region in which at least a portion of a control circuit that outputs a control signal to the main conversion circuit in the power conversion device is formed. The first region R1 and the second region R2 are arranged side by side in an in-plane direction. The first region R1 and the second region R2 are arranged side by side in, for example, a third direction DR3.

[0034] <Effects> Next, the effects of the semiconductor device 101 will be described.

[0035] As described above, in the semiconductor device including the POL submodule described in Patent Document 1, when the structure and function of the semiconductor device are complicated, such as when the semiconductor device includes a 6-in-1 module, multiple metal wirings arranged side by side with an insulating distance between them must be arranged side by side in the in-plane direction. As a result, when the structure and function of the semiconductor device are complicated, it is difficult to prevent the size of the semiconductor device from increasing in the in-plane direction.

[0036] In contrast, in the semiconductor device 101, the electronic circuit mounted on the substrate 10 includes multiple semiconductor elements 20 and 25, a first wiring layer 30, a second wiring layer 40, and a third wiring layer 50. Therefore, even when the structure and function of the semiconductor device 101 are complicated, the semiconductor device 101 can be prevented from increasing in size in the in-plane direction compared to the semiconductor device including the POL submodule described in Patent Document 1. Therefore, the semiconductor device 101 is suitable for semiconductor devices with more complicated structures and functions than the semiconductor device described in Patent Document 1. The semiconductor device 101 is suitable for a power conversion device including, for example, a 6-in-1 module capable of three-phase output. An example configuration of the power conversion device will be described later.

[0037] Furthermore, in the semiconductor device 101, heat generated in the multiple power semiconductor elements 20 can be dissipated through the third wiring layer 50 and the first insulating film 70 to a heat sink or other heat sink connected to the fifth surface 70A of the first insulating film 70. Therefore, in the semiconductor device 101, the heat can be dissipated more efficiently than in a semiconductor device that includes a substrate in the heat dissipation path between the power semiconductor elements and the heat sink.

[0038] In addition, in the semiconductor device described in Patent Document 1, since the metal wiring is exposed on the outer surface of the semiconductor device, the placement of the semiconductor device relative to the external device may be restricted in order to ensure an insulating distance between the metal wiring and the external device. In contrast, in the semiconductor device 101, the outer surface 101O is made only of an electrically insulating material, so the degree of freedom in the placement of the semiconductor device 101 relative to the external device is increased compared to the semiconductor device described in Patent Document 1.

[0039] <Modification> The semiconductor device 101 may further include a second insulating film disposed on the second surface 10B and covering a part of the second wiring layer 40 .

[0040] 3 and 4, unless otherwise specified, semiconductor device 102 according to embodiment 2 has the same configuration and effects as those of embodiment 1. Therefore, the same components as those of embodiment 1 are denoted by the same reference numerals, and description thereof will not be repeated.

[0041] 4 is a partially enlarged plan view illustrating the positional relationship between the power semiconductor elements 20 and the third wiring layer 50 in the semiconductor device 102. As shown in FIG. 4 , in the power semiconductor element 20, the emitter electrode 22 and the gate electrode 23 are arranged at an interval from each other. The emitter electrode 22 and the gate electrode 23 are arranged side by side in, for example, the third direction DR3. The third wiring layer 50 includes a plurality of first plate-shaped members 52 and a plurality of second plate-shaped members 53. Each of the plurality of first plate-shaped members 52 is electrically connected to at least a portion of the emitter electrode 22 of each of the plurality of power semiconductor elements 20. Each of the plurality of second plate-shaped members 53 is electrically connected to at least a portion of the gate electrode 23 of each of the plurality of power semiconductor elements 20.

[0042] The third wiring layer 50, which includes a plurality of first plate-shaped members 52 and a plurality of second plate-shaped members 53, is formed, for example, by patterning one or more conductive films using photolithography. The third wiring layer 50 can be formed, for example, by patterning a conductive film formed on an interlayer insulating film that exposes a portion of the emitter electrode 22 using photolithography. In this case, the thickness TA of the first plate-shaped member 52 in the first direction DR1 is equal to the thickness of the second plate-shaped member 53 in the first direction DR1. The third wiring layer 50 may be formed by bonding a conductive member that has been formed into a plate shape in advance to the emitter electrode 22, etc. The thickness T of the first plate-shaped member 52 in the first direction DR1 １ may be different from the thickness of the second plate-shaped member 53 in the first direction DR1.

[0043] 3 and 4, each of the first plate-shaped member 52 and the second plate-shaped member 53 extends along the in-plane direction. In a plan view, each of the first plate-shaped member 52 and the second plate-shaped member 53 has, for example, a longitudinal direction and a lateral direction. The lateral direction of the first plate-shaped member 52 is, for example, along the second direction DR2. The lateral direction of the second plate-shaped member 53 is, for example, along the third direction DR3. In this specification, a plan view refers to a viewpoint seen from the first direction DR1.

[0044] The width W of each of the first plate-shaped member 52 and the second plate-shaped member 53 in the short side direction in a plan view Ａ , WＢ is the thickness T in the first direction DR1 of each of the first plate-shaped member 52 and the second plate-shaped member 53. １ The width W of the first plate-shaped member 52 in the short direction of the first plate-shaped member 52 is larger than Ａ is, for example, the width W of the emitter electrode 22 (second electrode) of each of the plurality of power semiconductor elements 20. １ Narrower than.

[0045] The width W of the second plate-shaped member 53 in the short direction of the second plate-shaped member 53 Ｂ is, for example, the width W of the gate electrode 23 of each of the plurality of power semiconductor elements 20 ２ The width W of the second plate-shaped member 53 is wider than Ｂ is the width W of the gate electrode 23 of each of the plurality of power semiconductor elements 20 ２ The width W of the second plate-like member 53 may be equal to or narrower than the width W of the second plate-like member 53. Ｂ is the width W of the first plate-shaped member 52 Ａ The width W of the second plate-shaped member 53 may be equal to Ｂ is the width W of the first plate-shaped member 52 Ａ It may be narrower or wider than that.

[0046] 4 , in a plan view, the power semiconductor element 20 has a plurality of corners 24. In a plan view, the first plate-shaped member 52 and the second plate-shaped member 53 are disposed inside the plurality of corners 24.

[0047] The thickness T of the first plate-shaped member 52 in the first direction DR1 １ is the thickness T in the first direction DR1 of the emitter electrode 22 (second electrode) of each of the plurality of power semiconductor elements 20. ０ Thicker than.

[0048] <Effects> Next, the effects of the semiconductor device 102 will be described.

[0049] The third wiring layer 50 is closer to the fifth surface 70A than the first wiring layer 30 and the second wiring layer 40. Therefore, the contribution of the third wiring layer 50 to the heat dissipation performance of the semiconductor device 102 is higher than that of the first wiring layer 30 and the second wiring layer 40.

[0050] In the semiconductor device 102, the third wiring layer 50 includes a plurality of first plate-like members 52, and each of the plurality of first plate-like members 52 has a width W Ａ is the thickness T １ Therefore, in the semiconductor device 102, the width W Ａ is the thickness T １ , the heat generated in each of the plurality of power semiconductor elements 20 can be more efficiently dissipated to the plurality of first plate-shaped members 52. The heat dissipated to the third wiring layer 50 is efficiently transferred to the heat sink in contact with the fifth surface 70A via the first insulating film 70. Therefore, the heat dissipation performance of the semiconductor device 102 is improved when the width W Ａ is the thickness T １ This is higher than when it is smaller than

[0051] The third wiring layer 50 further includes a plurality of second plate-like members 53, and each of the second plate-like members 53 has a width W Ｂ is the thickness T １ If it is larger than the width W Ｂ is the thickness T １ In this case, the heat generated in each of the plurality of power semiconductor elements 20 can be more efficiently released to the plurality of second plate-shaped members 53 than when the distance between the first and second plate-shaped members 53 is smaller than the distance between the first and second plate-shaped members 53 .

[0052] In the semiconductor device 102, the thickness T １ is the thickness T in the first direction DR1 of the emitter electrode 22 (second electrode) of each of the plurality of power semiconductor elements 20. ０ Therefore, in the semiconductor device 102, the thickness T １ is the thickness T ０ In comparison with a case where the thickness is equal to or thinner than that, the heat generated in each power semiconductor element 20 can be dissipated to the first plate-shaped member 52 more efficiently.

[0053] In a cross section perpendicular to the longitudinal direction, the cross-sectional area of ​​each of the plurality of first plate-shaped members 52 is preferably larger than the cross-sectional area of ​​each of the emitter electrodes 22 (second electrodes) of the plurality of power semiconductor elements 20. In this way, heat generated in each power semiconductor element 20 can be more efficiently released to the first plate-shaped member 52 than in a case where the cross-sectional area of ​​each of the plurality of first plate-shaped members 52 is smaller than the cross-sectional area of ​​each emitter electrode 22.

[0054] <Modifications> In the semiconductor device 102, the third wiring layer 50 only needs to include at least the first plate-shaped member 52. The semiconductor device 102 may include a conductive member 51 instead of the second plate-shaped member 53. The semiconductor device 102 may be modified in the same manner as the semiconductor device 101.

[0055] 5 and 6, unless otherwise specified, semiconductor device 103 according to embodiment 3 has the same configuration and effects as those of embodiment 2. Therefore, the same components as those of embodiment 2 are denoted by the same reference numerals, and description thereof will not be repeated.

[0056] As shown in FIGS. 5 and 6, in the semiconductor device 103, the width W of the first plate-shaped member 52 in the second direction DR2, which is the short-side direction of the first plate-shaped member 52, is Ａ is the width W of the emitter electrode 22 (second electrode) of each power semiconductor element 20 to which the first plate-shaped member 52 is connected. １ It is wider than.

[0057] As shown in FIG. 5, in a cross section perpendicular to the longitudinal direction of the first plate-shaped member 52, the cross-sectional area of ​​the first plate-shaped member 52 is larger than the cross-sectional area of ​​each emitter electrode 22 to which the first plate-shaped member 52 is connected.

[0058] 6 , in a plan view, each of the first plate-shaped member 52 and the second plate-shaped member 53 of the third wiring layer 50 has a portion that extends outward beyond at least one of the multiple corners 24 of each of the multiple power semiconductor elements 20. In a plan view, each of the first plate-shaped member 52 and the second plate-shaped member 53 is arranged so as to overlap at least one corner 24 of the power semiconductor element 20.

[0059] Preferably, in a plan view, each of the first plate-shaped member 52 and the second plate-shaped member 53 of the third wiring layer 50 has a portion that extends outward beyond the two corners 24 of each of the plurality of power semiconductor elements 20. Preferably, in a plan view, each of the first plate-shaped member 52 and the second plate-shaped member 53 is arranged so as to overlap the two corners 24 of the power semiconductor elements 20.

[0060] <Effects> In the semiconductor device 103, the width W of the first plate-shaped member 52 in the second direction DR2, which is the short-side direction of the first plate-shaped member 52, is Ａ The width W of the emitter electrode 22 (second electrode) of each of the plurality of power semiconductor elements 20 １ Therefore, in the semiconductor device 103, the width W Ａ However, the above width W １ In comparison with the semiconductor device 102 having a smaller width, the heat generated in each power semiconductor element 20 can be dissipated to the first plate-shaped member 52 more efficiently.

[0061] In the semiconductor device 103, in a cross section perpendicular to the longitudinal direction of the first plate-shaped member 52, the cross-sectional area of ​​the first plate-shaped member 52 is larger than the cross-sectional area of ​​each emitter electrode 22 (second electrode) of the plurality of power semiconductor elements 20. Therefore, in the semiconductor device 103, the cross-sectional area of ​​the first plate-shaped member 52 is larger than the cross-sectional area of ​​each emitter electrode 22 (second electrode) Ａ However, the above width W １ In comparison with the semiconductor device 102 having a smaller width, the heat generated in each power semiconductor element 20 can be dissipated to the first plate-shaped member 52 more efficiently.

[0062] In the semiconductor device 103, in a plan view, each of the first plate-shaped member 52 and the second plate-shaped member 53 of the third wiring layer 50 has a portion that extends outward beyond the multiple corners 24 of each of the multiple power semiconductor elements 20. Therefore, in the semiconductor device 103, heat generated in each power semiconductor element 20 can be more efficiently released by the first plate-shaped member 52 than in a case where the first plate-shaped member 52 and the second plate-shaped member 53 are arranged inside the multiple corners 24 in a plan view.

[0063] In the semiconductor device 103, only one of the first plate-shaped member 52 and the second plate-shaped member 53 of the third wiring layer 50 may have a portion that extends outward beyond the multiple corners 24 of each of the multiple power semiconductor elements 20. The semiconductor device 103 may be modified in the same manner as the semiconductor device 101 or the semiconductor device 102.

[0064] 7 and 8, unless otherwise specified, a semiconductor device 104 according to embodiment 4 has the same configuration and effects as those of embodiment 2. Therefore, the same components as those of embodiment 2 are denoted by the same reference numerals, and description thereof will not be repeated.

[0065] 7 and 8 , in the semiconductor device 104, at least some of the power semiconductor elements 20 are inverted in the first direction DR1 compared to the semiconductor devices 101 to 103. At least some of the power semiconductor elements 20 are arranged such that the fourth surfaces 20B of the power semiconductor elements 20 face the first surface 10A. The emitter electrodes 22 and gate electrodes 23 of the power semiconductor elements 20 are electrically connected to the first wiring layer 30. The collector electrodes 21 (second electrodes) of the power semiconductor elements 20 are electrically connected to the third wiring layer 50.

[0066] The first wiring layer 30 has a plurality of fifth patterns 35, a plurality of sixth patterns 36, and a plurality of seventh patterns 37. Each of the plurality of fifth patterns 35 is electrically connected to the emitter electrode 22 (first electrode) of each of the plurality of power semiconductor elements 20. Each of the plurality of sixth patterns 36 is electrically connected to the gate electrode 23 (third electrode) of each of the plurality of power semiconductor elements 20. Each of the plurality of seventh patterns 37 is electrically connected to the collector electrode 21 (second electrode) of each of the plurality of power semiconductor elements 20 via the third wiring layer 50.

[0067] The third wiring layer 50 has a plurality of third plate-shaped members 54. Each of the plurality of third plate-shaped members 54 electrically connects the collector electrode 21 (second electrode) of each of the plurality of power semiconductor elements 20 to each of the plurality of seventh patterns 37 of the first wiring layer 30. Each third plate-shaped member 54 has a first portion 54A arranged to overlap the collector electrode 21 in the first direction DR1, a second portion 54B arranged to overlap the seventh pattern 37 in the first direction DR1, and a third portion 54C extending between the first portion 54A and the second portion 54B. The third portion 54C has, for example, a bent portion bent relative to each of the first portion 54A and the second portion 54B.

[0068] The second portion 54B of each third plate-shaped member 54 is electrically connected to the seventh pattern 37, for example, via a conductive member 27. The dimension of the conductive member 27 in the first direction DR1 is smaller than the dimension of the power semiconductor element 20 in the first direction DR1.

[0069] The second portion 54B of each third plate-shaped member 54 may be connected directly to the seventh pattern 37 without the conductive member 27 therebetween.

[0070] The third portion 54C does not have to have a bent portion. In this case, the dimension of the conductive member 27 in the first direction DR1 may be equal to the dimension of the power semiconductor element 20 in the first direction DR1.

[0071] 9 is a partially enlarged bottom view illustrating the positional relationship between the power semiconductor element 20 and the first wiring layer 30 in the semiconductor device 104. FIG. 10 is a partially enlarged plan view illustrating the positional relationship between the power semiconductor element 20 and the third wiring layer 50 in the semiconductor device 104.

[0072] 9 , in a plan view (bottom view), each of the fifth pattern 35 and the sixth pattern 36 of the first wiring layer 30 has a portion that extends outward beyond the multiple corners 24 of each of the multiple power semiconductor elements 20. In a plan view, each of the multiple corners 24 of the power semiconductor element 20 is arranged to overlap with the fifth pattern 35 or the sixth pattern 36. The area of ​​the contact surface between the fifth pattern 35 and the emitter electrode 22 is equal to the surface area of ​​the emitter electrode 22. The area of ​​the contact surface between the sixth pattern 36 and the gate electrode 23 is equal to the surface area of ​​the gate electrode 23.

[0073] 10 , in a plan view, the third plate-shaped member 54 of the third wiring layer 50 has a portion that extends outward beyond the multiple corners 24 of each of the multiple power semiconductor elements 20. In a plan view, each of the multiple corners 24 of the power semiconductor elements 20 is arranged to overlap the third plate-shaped member 54. The area of ​​the contact surface between the third plate-shaped member 54 and the collector electrode 21 is equal to or smaller than the surface area of ​​the collector electrode 21. The surface area of ​​the collector electrode 21 is larger than the surface area of ​​each of the emitter electrode 22 and the gate electrode 23.

[0074] In the semiconductor device 104, the contact area between the third wiring layer 50 and the collector electrode 21 (second electrode) is larger than the contact area between the first wiring layer 30 and the emitter electrode 22 (first electrode) and the gate electrode 23.

[0075] <Effects> In the semiconductor device 104, the area of ​​the contact surface between the third wiring layer 50 and the collector electrode 21 (second electrode) is larger than the area of ​​the contact surface between the first wiring layer 30 and the emitter electrode 22 (first electrode) and the gate electrode 23. Therefore, heat generated in each power semiconductor element 20 is efficiently dissipated to the heat sink in contact with the fifth surface 70A via the third wiring layer 50 and the first insulating film 70. Therefore, the heat dissipation performance of the semiconductor device 104 is improved compared to the semiconductor devices 101 to 103.

[0076] <Modifications> In the semiconductor device 104, all of the multiple power semiconductor elements 20 may be inverted in the first direction DR1 compared to the semiconductor devices 101 to 103. The semiconductor device 104 may be modified in the same manner as the semiconductor devices 101 to 103.

[0077] 11 , unless otherwise specified, a semiconductor device 105 according to embodiment 5 has the same configuration and effects as those of embodiment 1. Therefore, the same components as those of embodiment 1 are denoted by the same reference numerals, and description thereof will not be repeated.

[0078] 11 illustrates a plurality of third patterns 41 and a plurality of fourth patterns 42 included in the second wiring layer 40. As described above, the plurality of third patterns 41 are formed in the first region R1. The plurality of fourth patterns 42 are formed in the second region R2. The second wiring layer 40 may further include an eighth pattern 43 that connects the third pattern 41 and the fourth pattern 42.

[0079] 11, the minimum spacing L1 of the third patterns 41 on the first region R1 is longer than the minimum spacing L2 of the fourth patterns 42 on the second region R2. The density of the third patterns 41 on the first region R1 is lower than the density of the fourth patterns 42 on the second region R2.

[0080] As shown in FIG. 11 , the semiconductor device 104 is disposed on the second surface 10B of the substrate 10 and further includes a second insulating film 80 that covers the second surface 10B and the second wiring layer 40 .

[0081] The second insulating film 80 has a plurality of openings 81 formed therein, which expose only a portion of each of the second wiring layers 40. The exposed surfaces 45 of the second wiring layer 40 exposed from each opening 81 have, for example, a circular shape. The plurality of openings 81 are formed, for example, only in regions close to the outer edge of the second surface 10B. The plurality of openings 81 are not formed, for example, in the central portion of the second surface 10B. In each of the first region R1 and the second region R2, the second wiring layer 40 has exposed surfaces 45 only in regions close to the outer edge on the second surface 10B.

[0082] The material constituting the second insulating film 80 has electrical insulating properties. The thermal conductivity of the first insulating film 70 is, for example, higher than the thermal conductivity of the second insulating film 80. The material constituting the second insulating film 80 may include a resist.

[0083] 12 is a partially enlarged cross-sectional view illustrating the second wiring layer 40 and the second insulating film 80. As shown in Fig. 12, an exposed surface 45 of the second wiring layer 40 is bonded to a connection terminal 60 such as a solder ball. The thickness T2 of the second insulating film 80 in the first direction DR1 is smaller than the thickness of the second wiring layer 40 in the first direction DR1.

[0084] The structure on the first surface 10A of the semiconductor device 105 is the same as the structure on the first surface 10A of the semiconductor device 101, for example.

[0085] <Effects> In the semiconductor device 105, the minimum spacing L1 of the third patterns 41 on the first region R1 is longer than the minimum spacing L2 of the fourth patterns 42 on the second region R2. Therefore, electrical insulation between the third patterns 41 can be ensured.

[0086] Furthermore, in the semiconductor device 105, the second insulating film 80 is provided so as to cover the second wiring layer 40. Therefore, electrical insulation between the third patterns 41 and electrical insulation between the fourth patterns 42 can be ensured.

[0087] 13 is a bottom view showing a modification of the semiconductor device 105. As shown in FIG. 13, in the semiconductor device 105, the distance L between the second wiring layer 40 and the outer edge 10E of the second surface 10B is ３ , L ４ is larger than the thickness T2 of the second insulating film 80. The distance L between the third pattern 41 and the outer edge 10E of the second surface 10B ３ and the distance L between the third pattern 41 and the outer edge 10E of the second surface 10B. ４ is greater than the thickness T2 of the second insulating film 80. ３ is the distance L ４ It may be equal to or different from L ３ , L ４ In this way, electrical insulation between the second wiring layer 40 and the external device can be easily ensured.

[0088] The structure on the first surface 10A of the semiconductor device 105 may be the same as the structure on the first surface 10A of any of the semiconductor devices 102 to 104. The semiconductor device 105 can be modified in the same manner as the semiconductor devices 101 to 104.

[0089] Sixth Embodiment In this embodiment, the semiconductor device according to any one of the above-described first to fifth embodiments is applied to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, the following will describe, as the sixth embodiment, a case in which the present disclosure is applied to a three-phase inverter.

[0090] FIG. 14 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0091] The power conversion system shown in Fig. 14 is composed of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be composed of various components, such as a DC system, a solar cell, or a storage battery, or it may be composed of a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 100 may also be composed of a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0092] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, and converts DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. As shown in Fig. 14 , the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.

[0093] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0094] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheel diodes (not shown). The switching elements convert DC power supplied from the power source 100 into AC power, which is supplied to the load 300. While the main conversion circuit 201 can have a variety of specific circuit configurations, the main conversion circuit 201 according to this embodiment is a two-level, three-phase full-bridge circuit that can be configured with six switching elements and six freewheel diodes connected in anti-parallel to each switching element. At least one of the switching elements and freewheel diodes of the main conversion circuit 201 is a switching element or freewheel diode included in a semiconductor device 202 corresponding to any of the semiconductor devices according to any of the first to fifth embodiments described above. Two of the six switching elements are connected in series to form upper and lower arms, which constitute each phase (U phase, V phase, and W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0095] The main conversion circuit 201 also includes a drive circuit (not shown) that drives each switching element. However, the drive circuit may be built into the semiconductor device 202, or may be provided separately from the semiconductor device 202. The drive circuit generates drive signals that drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or greater than the threshold voltage of the switching element. When maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or less than the threshold voltage of the switching element.

[0096] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 203 then outputs a control command (control signal) to a drive circuit included in the main conversion circuit 201 so that an on signal is output to a switching element that should be in the on state at each time point, and an off signal is output to a switching element that should be in the off state at each time point. In accordance with this control signal, the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0097] In the power conversion device of this embodiment, a semiconductor device according to any one of embodiments 1 to 5 is applied as the semiconductor device 202 constituting the main conversion circuit 201, and therefore, compared to a power conversion device including a POL submodule described in Patent Document 1, it is possible to suppress enlargement in the in-plane direction.

[0098] In the present embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used. In addition, when supplying power to a single-phase load, the present disclosure may also be applied to a single-phase inverter. Furthermore, when supplying power to a DC load, etc., the present disclosure may also be applied to a DC / DC converter or an AC / DC converter.

[0099] 15 , in the power conversion device according to the present embodiment, a heat sink 90 is attached to the fifth surface 70A of each of the semiconductor devices 101 to 105. The heat sink 90 may have any configuration as long as it can discharge the heat conducted to the fifth surface 70A to the outside of the semiconductor device.

[0100] Furthermore, the power conversion device to which the present disclosure is applied is not limited to cases in which the above-mentioned load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0101] 10 Substrate, 10A First surface, 10B Second surface, 10E Outer edge, 20 Semiconductor element, 20A Third surface, 20B Fourth surface, 21 Collector electrode, 22 Emitter electrode, 23 Gate electrode, 24 Corner portion, 25 IC element, 27, 51 Conductive member, 30, 30A, 30B First wiring layer, 31 First pattern, 32 Second pattern, 35 Fifth pattern, 36 Sixth pattern, 37 Seventh pattern, 40 Second wiring layer, 41 Third pattern, 42 Fourth pattern, 43 Eighth pattern, 45 Exposed surface, 50 Third wiring layer, 52 First plate-shaped member, 53 Second plate-shaped member, 54 Third plate-shaped member, 54A First portion, 54B Second portion, 54C Third portion, 60 Connection terminal, 70 First insulating film, 70A Fifth surface, 80 Second insulating film, 81 Opening, 90 Heat sink, 100 power supply, 101, 102, 103, 104, 105, 202 semiconductor device, 101O outer surface, 200 power conversion device, 201 main conversion circuit, 203 control circuit, 300 load.

Claims

1. A semiconductor device comprising: a substrate having a first surface and a second surface located opposite the first surface; and an electronic circuit mounted on the first surface and the second surface, wherein the electronic circuit includes a plurality of semiconductor elements arranged side by side on the first surface, a first wiring layer arranged on the first surface, a second wiring layer arranged on the second surface, and a third wiring layer arranged at a distance from the first wiring layer in a first direction intersecting the first surface.

2. The semiconductor device according to claim 1, wherein the third wiring layer includes a plurality of plate-shaped members, and the width of each of the plurality of plate-shaped members in a planar view is greater than the thickness of each of the plurality of plate-shaped members in the first direction.

3. The semiconductor device described in claim 2, wherein each of the plurality of semiconductor elements has a first electrode electrically connected to the first wiring layer and a second electrode arranged on the opposite side of the first electrode and electrically connected to the third wiring layer, and the thickness in the first direction of each of the plurality of plate-like members is thicker than the thickness in the first direction of the second electrode.

4. The semiconductor device described in claim 3, wherein, in a plan view, each of the plurality of plate-like members has a longitudinal direction and a lateral direction, and in a cross section perpendicular to the longitudinal direction, the cross-sectional area of ​​each of the plurality of plate-like members is larger than the cross-sectional area of ​​the second electrode of each of the plurality of semiconductor elements.

5. The semiconductor device according to claim 3 or 4, wherein the area of ​​the contact surface between said third wiring layer and said second electrode is larger than the area of ​​the contact surface between said first wiring layer and said first electrode.

6. A semiconductor device according to any one of claims 2 to 5, wherein, in a plan view, each of the plurality of semiconductor elements has a plurality of corners, and, in a plan view, each of the plurality of plate-like members has a portion that extends outward beyond the plurality of corners of each of the plurality of semiconductor elements.

7. The semiconductor device according to claim 6, wherein, in plan view, each of said third wiring layers extends outward beyond the entire outer edge of each of said plurality of semiconductor elements.

8. The semiconductor device according to any one of claims 1 to 7, further comprising a first insulating film disposed on said first surface and covering said first surface, said first wiring layer, said plurality of semiconductor elements, and said third wiring layer, wherein the thermal conductivity of said first insulating film is higher than the thermal conductivity of said substrate.

9. The semiconductor device according to claim 8, further comprising a second insulating film disposed on said second surface and covering said second wiring layer, said second insulating film having a plurality of openings formed therein exposing only a portion of said second wiring layer, and a plurality of connection terminals joined to said portion of said second wiring layer exposed from each of said plurality of openings.

10. The semiconductor device according to claim 9, wherein the distance between said second wiring layer and the outer edge of said second surface is greater than the film thickness of said second insulating film.

11. The semiconductor device according to any one of claims 1 to 10, having an outer surface, said outer surface being made of only an electrically insulating material.

12. The semiconductor device according to any one of claims 1 to 11, wherein the plurality of semiconductor elements include a power semiconductor element and an IC element, the second wiring layer has a plurality of third wiring patterns and a plurality of fourth wiring patterns that are arranged at intervals from each other in a planar view, and the semiconductor device has, in a planar view, a first region in which a first circuit portion including the power semiconductor element and the plurality of third wiring patterns is mounted, and a second region in which a second circuit portion including the IC element and the plurality of fourth wiring patterns is mounted, and the spacing between the plurality of third wiring patterns in the first region is larger than the spacing between the plurality of fourth wiring patterns in the second region.

13. A power conversion device comprising a semiconductor device according to any one of claims 1 to 11, a main conversion circuit that converts input power and outputs it, and a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit.

14. A power conversion device having the semiconductor device according to claim 12, comprising: a main conversion circuit that converts input power and outputs it; and a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit, wherein the first circuit portion is included in the main conversion circuit, and the second circuit portion is included in the control circuit.

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