Power converter

Abstract

The purpose of the present invention is to suppress any rise in temperature due to heat generated by a switching element without adding a cooling structure to a multilayer substrate, and to reduce the size and cost of the multilayer substrate. A layer (L3) is formed between a layer (L1) in which a positive electrode pattern (201) connected to a positive electrode terminal (103d) of a switching element is positioned and a layer (L4) in which a negative electrode pattern (202) connected to a negative electrode terminal (103s) is positioned, a floating pattern (204) that is not electrically connected to the other patterns is positioned in said layer (L3). The positive electrode pattern (201) and the floating pattern (204) at least partially overlap when viewed perpendicularly with respect to the substrate, and the negative electrode pattern (202) and the floating pattern (204) at least partially overlap when viewed perpendicularly with respect to the substrate.

Description

Power Conversion Device

[0001] The present disclosure relates to a power conversion device.

[0002] A power conversion device used in an electric powertrain that generates motive power for a vehicle is equipped with a power supply circuit for driving the power conversion device. For example, the power conversion device is an inverter, and the auxiliary power supply circuit for driving this inverter is composed of an isolated power supply that uses a high-voltage battery as a supply source and generates power for the drive system using a low-voltage battery such as a lead battery as a reference. The traction motor is driven by power supplied from the high-voltage battery via this auxiliary power supply circuit.

[0003] Furthermore, miniaturization and cost reduction of power conversion devices are required to expand the vehicle interior space for electric powertrains. However, heat generation from components and patterns on multilayer printed circuit boards (PCBs) that mount power circuits can be a problem. This heat can exceed the glass transition temperature of the board or the heat resistance temperature of the electronic components mounted on the board, reducing the reliability of the components, patterns, and via connections mounted on the board and shortening the product lifespan.

[0004] Therefore, it is necessary to reduce the wiring layer loss by increasing the thickness of the copper foil on the board or by increasing the number of wiring layers to reduce the impedance of the pattern, or to suppress the temperature rise of the board by adding a structure to cool the board.However, these measures increase the size and cost, which are contrary to what is required.

[0005] For example, a technology that can suppress temperature rises in electronic components arranged on a substrate is known, as described in Patent Document 1. That is, an electronic circuit device includes a substrate on which multiple circuit layers are stacked with insulating layers interposed therebetween, electronic components that are arranged on the surface of the substrate and have positive terminals and ground terminals, a case that houses the substrate, and a fixing member that fixes the substrate to the case through fixing holes formed in the substrate.

[0006] The surface of the substrate is provided with a circuit layer having a positive circuit pattern connected to the positive terminal of the electronic component and a ground circuit pattern connected to the ground terminal of the electronic component. The interior of the substrate is provided with a circuit layer having a positive solid pattern connected to the positive circuit pattern via a positive via, and a circuit layer having a ground solid pattern connected to the ground circuit pattern via a ground via. The positive solid pattern and the ground solid pattern are adjacent to each other via an insulating layer. That is, no other circuit layer is interposed between the positive solid pattern and the ground solid pattern. The positive solid pattern and the ground solid pattern are each thermally connected to a fixing member through the inner surface of a fixing hole, thereby dissipating heat.

[0007] Patent No. 6794757

[0008] However, in the device described in Patent Document 1, positive solid patterns and ground solid patterns connected to the switching elements are arranged alternately on adjacent circuit layers, and these positive solid patterns and ground solid patterns form parasitic capacitance, which increases the parasitic capacitance and worsens the switching loss of the switching elements.

[0009] In this way, the heat dissipation performance of the board is improved, but the tradeoff is that the amount of heat generated by the switching elements increases due to increased switching losses, causing the switching elements to exceed their heat resistance temperature. Alternatively, the increased heat generated by the switching elements is transferred to the board on which they are mounted, causing the board temperature to rise further and exceed the board's heat resistance temperature. To address these issues, adding cooling components such as heat sinks to the switching elements to suppress the heat generated by the switching elements, which are the heat source, results in problems such as larger size and higher costs.

[0010] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a power conversion device that can be made smaller and less expensive by suppressing the temperature rise of components without adding cooling structural components such as heat sinks.

[0011] The power conversion device of the present disclosure comprises a multilayer substrate in which a plurality of layers are stacked with insulating layers interposed therebetween; a switching element disposed on a surface of the multilayer substrate and having a positive terminal and a negative terminal; a first layer on which a positive electrode pattern electrically and thermally connected to the positive electrode terminal is disposed; a second layer on which a floating pattern not electrically connected to the first layer is disposed; and a third layer on which a negative electrode pattern electrically and thermally connected to the negative electrode terminal is disposed, wherein the floating pattern partially overlaps with the positive electrode pattern and the negative electrode pattern when viewed from a normal direction to the substrate surface of the multilayer substrate, and the heat generated by the switching element is transmitted in the order of the positive electrode pattern, the floating pattern, and the negative electrode pattern.

[0012] The power conversion device of the present disclosure reduces switching loss, thereby suppressing temperature increases due to heat generated by components mounted on the board and the board patterns connecting the components, without the need to add a cooling structure such as a heat sink to the board. As a result, the power conversion device can be made smaller and less expensive.

[0013] FIG. 1 is a circuit diagram showing an example of a power supply circuit of a power conversion device according to embodiment 1. FIG. 2 is a diagram showing an example of a cross section of a multilayer substrate on which the power supply circuit of the power conversion device according to embodiment 1 is arranged. FIG. 3 is a configuration diagram of each layer of the multilayer substrate of the power conversion device according to embodiment 1. FIG. 4 is a diagram showing an example of a cross section of a multilayer substrate on which the power supply circuit of the power conversion device according to embodiment 1 is arranged. FIG. 5 is a diagram showing an example of a cross section of a multilayer substrate on which the power supply circuit of the power conversion device according to embodiment 1 is arranged. FIG. 6 is a circuit diagram showing an example of a power supply circuit of a power conversion device according to embodiment 2. FIG. 7 is a diagram showing an example of a cross section of a multilayer substrate on which the power supply circuit of the power conversion device according to embodiment 2 is arranged. FIG. 8 is a configuration diagram of each layer of the multilayer substrate of the power conversion device according to embodiment 2.

[0014] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a power conversion device according to the present invention will now be described with reference to the accompanying drawings. The same components and corresponding parts are designated by the same reference numerals, and detailed description thereof will be omitted.

[0015] First Embodiment. Fig. 1 is a circuit diagram showing an example of a power supply circuit used in a power conversion device according to a first embodiment. The circuit of Fig. 1 is an isolated flyback power supply, isolated by a transformer 101. A DC power supply 102 is connected to a primary winding 101a of the transformer 101. The input voltage from the DC power supply 102 is stored in the primary winding 101a while a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 103 is on. When the MOSFET 103 is switched off, the stored power is output to the secondary winding 101b using the back electromotive force of the transformer 101. Since this power is an AC voltage that repeatedly switches on and off, it is rectified by a diode 104 and converted to a DC voltage. Since the converted DC voltage has ripple, the ripple is reduced by a capacitor 105.

[0016] Furthermore, the MOSFET 103 has a drain-source capacitance 107. A parasitic capacitance 108 between a positive electrode pattern and a negative electrode pattern of the substrate, which will be described later, is connected in parallel to the drain-source capacitance 107.

[0017] The parallel connection of the parasitic capacitance 108 increases the drain-source capacitance 107. As a result, when the gate is turned off, a current due to the drain-source capacitance 107 flows, increasing the time it takes for the MOSFET 103 to turn off. Therefore, the increase in the time it takes for the MOSFET 103 to complete switching also increases loss, and the increased loss becomes heat, further increasing the temperature of the components mounted on the board and the board pattern connected to the components. To suppress this temperature increase, it is necessary to reduce the parasitic capacitance 108.

[0018] Fig. 2 is a diagram showing a portion of a cross section of a substrate on which the circuit of Fig. 1 is arranged. The substrate is a multilayer substrate, in which a plurality of layers, from a first layer L1 to a sixth layer L6, are stacked with insulating layers 203 interposed therebetween. Note that although the multilayer substrate of this embodiment is configured with six layers, this is not limiting, and the number of layers is not particularly limited.

[0019] Figure 3 is a diagram showing the structure of each layer of the substrate, and Figures 3(a) to 3(f) show the structure of each layer as seen from above the substrate in Figure 2. The cross section of the substrate in Figure 2 is a cross section taken along line A-A in Figure 3(a).

[0020] As shown in FIG. 3(a), a switching element, MOSFET 103, is disposed on the surface of the first layer L1 of the substrate. A positive electrode pattern 201 electrically and thermally connected to the drain terminal 103d, which is the positive electrode terminal of MOSFET 103, is disposed on the first layer L1 and the second layer L2. The positive electrode pattern 201 disposed on the first layer L1 and the positive electrode pattern 201 disposed on the second layer L2 shown in FIG. 3(b) at least partially overlap when viewed in the normal direction of the substrate, and the respective positive electrode patterns 201 are electrically and thermally connected by vias 201a. A negative electrode pattern 202 is disposed on the first layer L1 so as not to overlap with the positive electrode pattern 201 when viewed in the normal direction of the substrate. The negative electrode pattern 202 on the first layer L1 is electrically and thermally connected to the source terminal 103s of the MOSFET. The negative electrode patterns 202 on the first layer L1 to the sixth layer L6 are electrically and thermally connected by vias 202a. Furthermore, the floating pattern 204 of the third layer L3 and the negative electrode pattern 202 of the fourth layer L4 (described later) are disposed so as to overlap at least partially when viewed in the normal direction of the substrate.

[0021] 3(c) is arranged a floating pattern 204 that is not physically connected to other patterns, including the positive electrode pattern 201 and the negative electrode pattern 202. That is, the floating pattern 204 is not electrically connected to the positive electrode pattern 201 and the negative electrode pattern 202. The positive electrode pattern 201 of the second layer L2 and the floating pattern 204 of the third layer L3 are arranged so as to at least partially overlap when viewed from the normal direction of the substrate.

[0022] 3(d), (e), and (f), negative electrode patterns 202 having the same potential as the ground 106 in FIG. 1 are arranged on the fourth layer L4 to the sixth layer L6. The negative electrode patterns 202 on the fourth layer L4 to the sixth layer L6 are arranged so as to overlap at least partially when viewed in the normal direction of the substrate. In addition, to connect the negative electrode patterns 202 to the source terminal 103s of the MOSFET, the negative electrode patterns 202 on the first layer L1 to the third layer L3 are arranged so as not to overlap with the positive electrode patterns 201 when viewed in the normal direction of the substrate, and the floating pattern 204 on the third layer L3 and the negative electrode pattern 202 on the fourth layer L4 are arranged so as to overlap at least partially when viewed in the normal direction of the substrate.

[0023] When patterns of different potentials overlap when viewed in the normal direction of the substrate as shown in Figure 2, a parasitic capacitance occurs, and the capacitance value can be calculated using the following formula (1): where C [F], ε, ε0 [F / m], and S [m 2 ], and the pattern distance is d [m].

[0024]

[0025] As shown in formula (1), the larger the pattern overlap area S or the shorter the inter-pattern distance d, the larger the parasitic capacitance C. Therefore, the larger the overlapping area of ​​the positive electrode pattern 201 and the negative electrode pattern 202, or the more layers there are overlapping, the larger the parasitic capacitance C becomes.

[0026] By disposing the floating pattern 204 between the second layer L2 on which the positive electrode pattern 201 is disposed and the fourth layer L4 on which the negative electrode pattern 202 is disposed, a parasitic capacitance 205 is formed between the positive electrode pattern 201 and the floating pattern 204, and a parasitic capacitance 206 is formed between the floating pattern 204 and the negative electrode pattern 202, as shown in FIG. 2 .

[0027] Parasitic capacitance C between the positive electrode pattern 201 of the second layer L2 and the negative electrode pattern 202 of the fourth layer L4 108 is a parasitic capacitance 205 between the positive electrode pattern 201 of the second layer L2 and the floating pattern 204 of the third layer L3. 205, the parasitic capacitance 206 between the floating pattern 204 of the third layer L3 and the negative electrode pattern 202 of the fourth layer L4 is C 206 In this case, it is expressed by the following equation.

[0028]

[0029] From equation (2), the parasitic capacitance C between the positive electrode pattern 201 and the negative electrode pattern 202 is 108 is the parasitic capacitance C due to the positive electrode pattern 201 and the floating pattern 204 205 , a parasitic capacitance C formed by the floating pattern 204 and the negative electrode pattern 202 206 The capacitance is smaller than either of the above.

[0030] On the other hand, the thermal resistance R seen in the normal direction of the substrate can be expressed by equation (3), where R is the thermal resistance [m2 K / W], d is the thickness [m], and λ is the thermal conductivity [W / (m K)].

[0031]

[0032] From equation (3), the thicker the layer thickness d and the lower the thermal conductivity λ, the higher the thermal resistance R. Therefore, assuming that the thermal resistance of the insulating layer 203 in Figure 2 is 207, the thermal resistance of the floating pattern 204 is 208, and the thermal resistance of the insulating layer 203 is 209, the thermal resistance from the positive electrode pattern 201 of the second layer L2 to the negative electrode pattern 202 of the fourth layer L4 is the sum of the thermal resistances 207 to 209.

[0033] Since thermal resistors 207 and 209 are both insulating layers, their thermal conductivity is approximately 0.3 W / (m·K). On the other hand, thermal resistor 208 of floating pattern 204 has a thermal conductivity of approximately 400 W / (m·K) because the material of the pattern is copper. The distance from positive electrode pattern 201 of the second layer to negative electrode pattern 202 of the fourth layer is the same regardless of whether floating pattern 204 is present or not.

[0034] Copper has a higher thermal conductivity than insulating materials, so by placing the floating pattern 204 without leaving any gap between the layers, the thermal conductivity between the positive electrode pattern 201 and the negative electrode pattern 202 is improved and increased compared to a configuration without the floating pattern 204. Therefore, more heat is dissipated from the MOSFET 103, which is a heat-generating component, to the positive electrode pattern 201, and more heat is dissipated from the positive electrode pattern 201 via the insulating layer 203 to the floating pattern 204, and further from the floating pattern 204 to the negative electrode pattern 202 via the insulating layer 203, thereby suppressing a temperature rise due to heat generation in the MOSFET 103.

[0035] In addition, in a configuration in which the substrate is fixed to a conductive case 210 made of metal or the like that houses the substrate using a fixing member, the negative electrode pattern 202 may be electrically and thermally connected to the case 210. This configuration ensures a heat dissipation path to the case 210, thereby further suppressing the temperature rise of the MOSFET 103 and the substrate.

[0036] 4, the positive electrode pattern 201 and the floating pattern 204 may be arranged to overlap in the normal direction of the substrate, and the floating pattern 204 and the negative electrode pattern 202 may be arranged to overlap, with no overlap between the positive electrode pattern 201 and the negative electrode pattern 202. This configuration ensures a heat dissipation path while reducing the pattern overlap, thereby reducing parasitic capacitance and further improving switching loss.

[0037] Alternatively, the area of ​​the floating pattern 204 may be larger than that of the drain terminal 103d, which serves as the heat dissipation surface of the MOSFET 103, and the area of ​​the negative electrode pattern 202 may be larger than that of the floating pattern 204. With this configuration, heat generated by the MOSFET 103 is more easily dissipated to the floating pattern 204 and the negative electrode pattern 202, thereby suppressing the temperatures of the MOSFET 103 and the substrate.

[0038] 5, the negative electrode pattern 202 may be disposed as a solid pattern on the surface of the sixth layer L6, which is the outermost layer, different from the surface that comes into contact with air of the first layer L1 on which the MOSFET 103 is mounted. By configuring it in this way, the surface area that comes into contact with air of the negative electrode pattern 202 increases, and the temperature rise of the MOSFET 103 and the substrate can be further suppressed.

[0039] 5, the floating pattern 204 disposed between the positive electrode pattern 201 and the negative electrode pattern 202 may be configured to be disposed in two layers, a third layer L3 and a fourth layer L4. By configuring in this manner, the parasitic capacitance can be further reduced, and switching loss can be improved. Note that the number of layers is not limited to two, and the floating patterns 204 may be disposed in multiple layers. In this case, the multiple floating patterns 204 are electrically insulated from each other.

[0040] The MOSFET 103 is not limited to a self-arc-suppressing semiconductor switching element such as a Si (Silicon)-MOSFET, but may also be a wide bandgap semiconductor such as SiC (Silicon Carbide) or GaN (Gallium Nitride). Wide bandgap semiconductors can achieve high switching speeds and low losses, thereby further realizing miniaturization of the device.

[0041] 6 is a circuit diagram showing an example of a power supply circuit used in a power conversion device according to embodiment 2. Parasitic capacitances 109 and 110 formed by a substrate pattern, a case ground 111, and a control IC (Integrated Circuit) 112 that controls a gate terminal 103g of a MOSFET 103 are added to the circuit of FIG. 1 described in embodiment 1.

[0042] Parasitic capacitance 109 is the parasitic capacitance between drain terminal 103d of MOSFET 103 and case ground 111, and parasitic capacitance 110 is the parasitic capacitance between source terminal 103s of MOSFET 103 and case ground 111. Drain terminal 103d is connected to source terminal 103s via parasitic capacitances 109 and 110. Therefore, the parasitic capacitance formed by connecting parasitic capacitances 109 and 110 in series is connected in parallel to drain-source capacitance 107. Therefore, it is necessary to reduce at least one of parasitic capacitances 109 and 110.

[0043] Fig. 7 is a cross-sectional view of the substrate in embodiment 2. Fig. 8 is a configuration diagram of each layer of the substrate in embodiment 2. The cross section in Fig. 7 is taken along line B-B in Fig. 8, but the control IC 112 is not included in the cross section and is therefore indicated by a dotted line.

[0044] The MOSFET 103 and the control IC 112 are arranged on the first layer L1 of the substrate, and a positive electrode pattern 201 is arranged on the first layer L1 and the second layer L2, and is electrically and thermally connected to the drain terminal 103d of the MOSFET 103. The positive electrode pattern 201 arranged on the first layer L1 and the positive electrode pattern 201 arranged on the second layer L2 at least partially overlap when viewed in the normal direction of the substrate, and are connected by vias 201a that electrically and thermally connect the positive electrode patterns 201.

[0045] A negative electrode pattern 202 connected to the source terminal 103s is disposed on the first layer L1 of the substrate. The negative electrode pattern 202 and the control IC 112 are at least partially overlapped when viewed in the normal direction of the substrate. As shown in FIG. 8A, the gate terminal 103g and the control IC 112 are electrically and thermally connected on the first layer L1.

[0046] 8B, in addition to the positive electrode pattern 201, a ground pattern 212 is arranged on the second layer L2 of the substrate. The ground pattern 212 at least partially overlaps with the negative electrode pattern 202 on the first layer L1 when viewed in the normal direction of the substrate.

[0047] As shown in Figure 8(c), a floating pattern 204 that is not physically connected to other patterns is arranged on the third layer L3. That is, the floating pattern 204 is not electrically connected to the positive electrode pattern 201, the negative electrode pattern 202, or the ground pattern 212. The positive electrode pattern 201 on the second layer L2 and the floating pattern 204 on the third layer L3 are arranged so that they at least partially overlap when viewed in the normal direction of the substrate. In addition, a ground pattern 212 is arranged on the third layer L3, and at least partially overlaps the ground pattern 212 arranged on the second layer L2 when viewed in the normal direction of the substrate, and is connected by vias 212a.

[0048] 8(d), (e), and (f), ground patterns 212 having the same potential as the case ground 111 are arranged on the fourth layer L4 to the sixth layer L6. The ground patterns 212 on the second layer L2 to the sixth layer L6 are arranged so that the ground patterns on adjacent layers at least partially overlap when viewed in the normal direction of the board.

[0049] The ground patterns 212 on the first layer L1 to the sixth layer L6 are electrically and thermally connected by vias 212a. The floating pattern 204 on the third layer L3 and the ground pattern 212 on the fourth layer L4 are arranged so that they at least partially overlap when viewed in the normal direction of the substrate. The source terminal 103s is electrically and thermally connected to the ground 106.

[0050] 7 and 8, the substrate is fixed to a case 210 that houses the substrate using fixing members 211 in mounting holes 213. The fixing members 211 and the case 210 that houses the substrate are made of a conductive material such as metal.

[0051] The parasitic capacitance 109 in Fig. 6 is a series connection of the parasitic capacitances 214 and 215 shown in Fig. 7 , and the parasitic capacitance 110 in Fig. 6 is represented by the parasitic capacitance 216 in Fig. 7 . As in the first embodiment, the parasitic capacitance 109 is reduced by forming the third layer L3 on which the floating pattern 204 is disposed between the second layer L2 on which the positive electrode pattern 201 is disposed and the fourth layer L4 on which the ground pattern 212 is disposed. However, in order to reduce the parasitic capacitance 110, a layer on which the floating pattern 204 is disposed may be formed between the layer on which the negative electrode pattern 202 is disposed and the layer on which the ground pattern 212 is disposed. Furthermore, in order to reduce both the parasitic capacitances 109 and 110, both of the above-described two floating patterns 204 may be applied.

[0052] In order to reduce thermal resistance, a floating pattern made of copper is placed without any gap between the layers, thereby improving the thermal conductivity between the positive electrode pattern 201 and the ground pattern 212. Therefore, heat is dissipated from the MOSFET 103, which is a heat-generating component, to the positive electrode pattern 201, from the positive electrode pattern 201 to the floating pattern 204 via the insulating layer 203, and further from the floating pattern 204 to the negative electrode pattern 202 via the insulating layer 203, thereby suppressing the temperature rise due to heat generation of the MOSFET 103. Furthermore, if a layer in which the floating pattern 204 is placed is formed between the layer in which the negative electrode pattern 202 is placed and the layer in which the ground pattern 212 is placed in order to reduce the parasitic capacitance 110, heat is dissipated from the MOSFET 103, which is a heat-generating component, to the negative electrode pattern 202, from the negative electrode pattern 202 to the floating pattern 204 via the insulating layer 203, and further from the floating pattern 204 to the ground pattern 212 via the insulating layer 203.

[0053] Alternatively, the area of ​​floating pattern 204 may be larger than drain terminal 103d, which serves as the heat dissipation surface of MOSFET 103, and the area of ​​ground pattern 212 may be larger than floating pattern 204. With this configuration, heat generated by MOSFET 103 is more easily dissipated to floating pattern 204 and ground pattern 212, thereby suppressing the temperatures of MOSFET 103 and the substrate.

[0054] Furthermore, by arranging the negative electrode pattern 202 directly below the control IC 112 and placing the pattern without leaving any gap between layers, the thermal conductivity between the negative electrode pattern 202 and the ground pattern 212 is also improved. Heat from the control IC 112 is dissipated to the negative electrode pattern 202 and then conducted to the ground pattern 212 via the insulating layer 203, thereby suppressing a temperature rise due to heat generation from the control IC 112.

[0055] The first layer L1 or sixth layer L6 of the ground pattern 212, or both layers, and the case 210 that houses the board are attached so as to be electrically and thermally connected directly or via fixing members 211. The connection between the ground pattern 212 and the case 210 forms a heat dissipation path and increases the heat capacity, thereby further suppressing temperature increases due to heat generated by components mounted on the board.

[0056] Alternatively, the positive electrode pattern 201 and the floating pattern 204 may be arranged to overlap, the floating pattern 204 and the ground pattern 212 may be arranged to overlap, and the positive electrode pattern 201 and the negative electrode pattern 202 may be arranged so as not to overlap. Furthermore, by configuring the same as in FIG. 5 shown in the first embodiment, a heat dissipation path can be ensured, while reducing the overlap between different patterns to reduce parasitic capacitance, thereby improving switching loss. For example, the positive electrode pattern and the ground pattern, or the negative electrode pattern and the ground pattern, may not overlap when viewed from the normal direction of the substrate surface.

[0057] The ground pattern 212 may also be configured to be disposed as a solid pattern on the surface of the sixth layer L6, which is the outermost layer, different from the surface of the first layer L1 on which the MOSFET 103 is mounted. By configuring it in this way, the surface that comes into contact with the air is expanded, thereby promoting heat dissipation.

[0058] Although various exemplary embodiments and examples are described in this application, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless variations not illustrated are contemplated within the scope of the technology disclosed in this specification. For example, this includes cases where at least one component is modified, added, or omitted, or where at least one component is extracted and combined with components of another embodiment.

[0059] 101: transformer, 101a: primary winding, 101b: secondary winding, 103: MOSFET, 103d: drain terminal, 103s: source terminal, 104: diode, 105: capacitor, 106: ground, 107: drain-source capacitance, 108: parasitic capacitance, 109, 110: parasitic capacitance, 111: case ground, 112: control IC, 201: positive electrode pattern, 201a: via, 202: negative electrode pattern, 202a: via, 203: insulating layer, 204: floating pattern, 205, 206: parasitic capacitance, 207, 208, 209: thermal resistance, 210: case, 211: fixing member, 212: ground pattern, 212a: via, 213: mounting hole, 214, 215, 216: parasitic capacitance.

Claims

1. A power conversion device comprising: a multilayer substrate in which multiple layers are stacked with insulating layers interposed between them; a switching element disposed on the surface of the multilayer substrate and having a positive terminal and a negative terminal; a first layer on which a positive electrode pattern is disposed that is electrically and thermally connected to the positive electrode terminal; a second layer on which a floating pattern that is not electrically connected to the first layer is disposed; and a third layer on which a negative electrode pattern that is electrically and thermally connected to the negative electrode terminal is disposed, wherein the floating pattern partially overlaps with the positive electrode pattern and the negative electrode pattern when viewed from the normal direction of the substrate surface of the multilayer substrate, and wherein heat generated by the switching element is transmitted in the order of the positive electrode pattern, the floating pattern, and the negative electrode pattern.

2. The power conversion device according to claim 1, further comprising a case for accommodating the substrate, said case and said negative electrode pattern being electrically connected.

3. The power conversion device according to claim 1 or 2, wherein the second layer is formed between the first layer and the third layer.

4. A power conversion device comprising: a multilayer substrate in which multiple layers are stacked with insulating layers interposed therebetween; a switching element disposed on the surface of the multilayer substrate and having a positive terminal and a negative terminal; a first layer on which a positive pattern electrically and thermally connected to the positive terminal is disposed; a second layer on which a floating pattern not electrically connected to the first layer is disposed; a third layer on which a negative pattern electrically and thermally connected to the negative terminal is disposed; and a fourth layer on which a ground pattern is disposed; wherein the floating pattern partially overlaps with the positive pattern and the ground pattern when viewed from the normal direction to the surface of the multilayer substrate, and wherein heat generated by the switching element is transmitted in the order of the positive pattern, the floating pattern, and the ground pattern.

5. The power conversion device according to claim 4, wherein the second layer is formed between the first layer and the fourth layer.

6. The power conversion device according to claim 4, wherein the second layer is formed between the second layer and the fourth layer.

7. A power conversion device comprising: a multilayer substrate formed by stacking multiple layers with insulating layers interposed therebetween; a switching element disposed on a surface of the multilayer substrate and having a positive terminal and a negative terminal; a case for accommodating the multilayer substrate; a fixing member for fixing the multilayer substrate to the case through a fixing hole formed in the multilayer substrate; a first layer on which a positive pattern electrically and thermally connected to the positive terminal is disposed; a second layer on which a floating pattern not electrically connected to the first layer is disposed; a third layer on which a negative pattern electrically and thermally connected to the negative terminal is disposed; and a fourth layer on which a ground pattern electrically and thermally connected to the case is disposed, wherein the floating pattern partially overlaps with the positive pattern and the negative pattern, or partially overlaps with the positive pattern and the ground pattern, when viewed from the normal direction to the surface of the multilayer substrate, and wherein heat generated by the switching element is transmitted in the order of the positive pattern, the floating pattern, and the negative pattern, or the positive pattern, the floating pattern, the ground pattern, and the case.

8. The power conversion device according to any one of claims 1 to 7, wherein the positive electrode pattern and the negative electrode pattern do not overlap when viewed in the normal direction of the substrate surface.

9. A power conversion device as described in any one of claims 1 to 8, characterized in that the area of ​​the floating pattern is larger than the positive terminal which serves as the heat dissipation surface of the switching element, and the area of ​​the negative pattern is larger than the floating pattern.

10. A power conversion device as described in any one of claims 1 to 3, characterized in that the negative electrode pattern is arranged as a solid pattern on the outermost layer opposite the first layer on which the switching elements of the multilayer substrate are arranged.

11. The power conversion device according to any one of claims 4 to 7, wherein the positive electrode pattern and the ground pattern, or the negative electrode pattern and the ground pattern, do not overlap when viewed in the normal direction to the substrate surface.

12. A power conversion device as claimed in any one of claims 4 to 7 and 11, characterized in that the area of ​​the floating pattern is larger than the positive terminal which serves as the heat dissipation surface of the switching element, and the area of ​​the ground pattern is larger than the floating pattern.

13. A power conversion device according to any one of claims 4 to 7, 11 and 12, characterized in that the ground pattern is arranged as a solid pattern on the outermost layer opposite the first layer on which the switching elements of the multilayer substrate are arranged.

14. The power conversion device according to any one of claims 1 to 13, wherein the floating patterns are arranged in a plurality of adjacent layers and are electrically insulated.

15. A power conversion device according to any one of claims 1 to 14, wherein the switching element is an element made using a wide band gap semiconductor.

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