Co-packaged optics structure having optical port protection and manufacturing method therefor

Abstract

The present invention relates to a co-packaged optics structure having optical port protection and a manufacturing method therefor. Said manufacturing method comprises: performing primary molding on an optical chip module, the optical chip module comprising a first optical chip and a second optical chip, a first surface of the first optical chip and a first surface of the second optical chip respectively comprising a first optical port and a second optical port, the first optical port and the second optical port sharing one trench, and the first surface of the first optical chip and the first surface of the second optical chip being coplanar with a first surface of a first molding compound; thinning a second surface of the first molding compound, and exposing a second surface of the optical chip module; forming within the first molding compound a conductive through molding via (TMV) and forming on the second surfaces of the first molding compound and the optical chip module a redistribution layer (RDL); mounting electronic chips onto the redistribution layer (RDL) and performing secondary molding; forming protrusions on the first surfaces of the optical chip module and the first molding compound; and performing wafer dicing along the trench shared by the first chip and the second chip, so as to obtain a single packaged module.

Description

A photoelectric sealing structure with optical port protection and its manufacturing method Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an optoelectronic encapsulation structure with optical port protection and its manufacturing method. Background Technology

[0002] With the continued growth of data communication and processing services, hybrid packaging of optical and electrical chips has become a mainstream development trend. To achieve higher bandwidth, higher speed, and lower power consumption information transmission, optical chips are no longer satisfied with simple WB packaging processes. More and more customers are beginning to try bump and through-hole (BHM) processes on optical chips to achieve 2.5D / 3D packaging, meeting more and higher application requirements. Optoelectronic hybrid packaging has become the mainstream packaging form. Compared with electrical chip packaging, the biggest problem with optical chip packaging lies in the protection of the optical port. The injection molding process during packaging encapsulates both the optical and electrical chips in molding compound, which can contaminate the optical port. Optical port contamination can lead to reduced chip performance or even failure.

[0003] Chinese patent CN 115775843A discloses a method for fabricating an optoelectronic encapsulation structure. Specifically, the method includes: providing a carrier board and an optical chip, with at least one optical interface on one side of the optical chip; providing at least one electrical chip disposed on the upper surface of the optical chip; providing at least one protective structure, which is a cap-like structure with an internal cavity and at least one through-hole on its surface; attaching the protective structure to the upper surface of the optical chip corresponding to the optical interface, so that the optical interface is completely located within the cavity; providing a fluid colloid, filling the through-hole with the colloid, and depressurizing the external environment of the cavity; when the external pressure of the cavity decreases, the gas inside the cavity is discharged through the gap between the uncured colloid and the through-hole until the gas pressure inside the cavity is at a low-pressure environment; then curing the colloid, so that the colloid completely blocks the through-hole; forming a plastic encapsulation. This method achieves protection of the optical port by forming a separate protective structure for the optical port.

[0004] International patent WO2023 / 087323A1 discloses another optoelectronic component. The optoelectronic component includes an electronic integrated circuit, a molding compound, and a photonic integrated circuit. The molding compound encapsulates the electronic integrated circuit and has one or more through-holes. A first redistribution layer and a second redistribution layer are formed on both the top and bottom surfaces of the molding compound. The photonic integrated circuit is electrically coupled to multiple second bumps on the second redistribution layer via multiple first solder balls. During the manufacturing process of this component, to avoid the molding compound blocking the optical port, the optical chip is mounted last, and the molding compound only encapsulates the electronic chip, leaving the optical chip exposed.

[0005] In existing optoelectronic encapsulation processes, to prevent molding compound from contaminating the optical port, one approach is to incorporate a protective structure at the optical interface; another is to mount the optical chip at the end of the process, interconnecting it via WB (Weight-by-Board) or flip-chip bonding without further molding. The first approach, requiring a separate protective structure, leads to complex processes and high costs. The second approach, with the optical chip exposed, cannot provide effective encapsulation protection. Therefore, how to protect the optical port within the package is a pressing issue that needs to be addressed. Summary of the Invention

[0006] To address some or all of the problems in the prior art, the present invention provides a method for manufacturing an optoelectronic sealing structure, characterized by comprising:

[0007] The optical chip module is first encapsulated, the optical chip module including a first optical chip and a second optical chip; the first side of the first optical chip and the second optical chip respectively includes a first optical port and a second optical port, the first optical port and the second optical port share a groove, and the first side of the first optical chip and the second optical chip are coplanar with the first side of the first encapsulating material.

[0008] The second side of the first molding compound is thinned to expose the second side of the optical chip module;

[0009] A conductive through-hole (TMV) is formed within the first molding compound, and a redistribution layer (RDL) is formed on the second surface of the first molding compound and the optical chip module.

[0010] The electrical chip is mounted on the redistribution layer RDL and then subjected to a second molding process.

[0011] A protrusion is formed on the first surface of the optical chip module and the first molding compound; and

[0012] The wafer is diced along the common trench of the first and second chips to obtain a single package module.

[0013] In one embodiment of the present invention, during the process of encapsulating the optical chip module, the optical port is blocked by a film.

[0014] In one embodiment of the present invention, thinning the second side of the first molding compound to expose the second side of the optical chip module includes:

[0015] The optical chip module and the first side of the first molding compound are fixed on the bonding carrier by a temporary bonding layer. Then, the second side of the first molding compound is thinned by a grinding process, and the second side of the optical chip module is exposed.

[0016] In one embodiment of the present invention, mounting the electrical chip on the redistribution layer RDL and performing a second molding process includes:

[0017] The chip bumps are aligned and mounted on the bottom redistribution layer. After the layout is completed, bonding is performed by reflow soldering or thermoforming. After the interconnect is formed, underfill is applied around the chip. The underfill filler fills the gap between the chip and the redistribution layer through capillary action. After filling, the assembly is placed in a curing oven to cure the underfill.

[0018] In one embodiment of the present invention, forming a protrusion on the first surface of the optical chip module and the first molding compound includes:

[0019] Remove temporary bonded substrate;

[0020] A UBM layer is formed at the raised position, then solder is formed on the UBM layer, and finally the wafer is reflowed to form smooth spherical C4 solder bumps under the action of surface tension.

[0021] In one embodiment of the present invention, an optoelectronic sealing structure is provided, comprising:

[0022] Optical chip and one or more electrical chips;

[0023] The first surface of the optical chip is coplanar with the first surface of the first molding compound, and the second surface of the optical chip is coplanar with the second surface of the first molding compound. The first and second surfaces of the optical chip are two opposing main planes of the optical chip. The optical port is located on the first surface of the optical chip, and the trench is located on the chip edge on one side of the optical port.

[0024] The first molding compound encapsulates the optical chip, but the first side, the second side, and the side where the trench is located are not covered by the first molding compound. One or more conductive through-holes (TMVs) are provided in the first molding compound. The first side of the optical chip and the first side of the first molding compound have multiple protrusions.

[0025] A redistribution layer (RDL) is formed on the second surface of a first molding compound and an optical chip. One or more electrical chips are mounted on the redistribution layer (RDL), and a second molding compound encapsulates the electrical chips and the redistribution layer.

[0026] In one embodiment of the invention, a UBM layer is provided beneath the plurality of protrusions.

[0027] In one embodiment of the present invention, the protrusion is formed on a pad on a first surface of the optical chip module and on a conductive through-hole (TMV) of a first molding compound.

[0028] In one embodiment of the present invention, the redistribution layer RDL includes one or more conductive line layers and an insulating medium disposed between the conductive line layers.

[0029] In one embodiment of the present invention, the electrical chip is a flip chip.

[0030] The optoelectronic encapsulation structure and manufacturing method provided by this invention enable the encapsulation of optical and electrical chips, protecting and securing the chips while providing electrical connections. This solves the problems associated with exposed chips, such as susceptibility to damage, contamination, difficulty in storage, and difficulty in connection, thereby ensuring chip reliability and stability and extending chip lifespan. Furthermore, the optoelectronic encapsulation structure and manufacturing method provided by this invention eliminate the need for a separate protective structure for the optical port, simplifying the process and reducing manufacturing costs. Attached Figure Description

[0031] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0032] Figure 1 shows a top view and a cross-sectional view of an optical chip 200 according to an embodiment of the present invention.

[0033] Figure 2 shows a top view of an optical chip module 101 according to an embodiment of the present invention.

[0034] Figure 3 shows a flowchart of an optoelectronic sealing process according to an embodiment of the present invention.

[0035] Figures 4 to 9 show cross-sectional views of the optoelectronic encapsulation manufacturing process according to an embodiment of the present invention.

[0036] Figure 10 shows a cross-sectional schematic diagram of the photoelectric sealing structure according to an embodiment of the present invention. Detailed Implementation

[0037] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0038] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0039] In this specification, unless otherwise specified, "arranged on," "arranged above," and "arranged on top of" do not exclude the possibility of an intermediate element between them. Furthermore, "arranged on or above" merely indicates the relative positional relationship between two components, and in certain cases, such as when the product orientation is reversed, it can also be converted to "arranged below or under," and vice versa.

[0040] In this specification, unless otherwise specified, "first surface" and "second surface" are used only to describe surfaces that distinguish the same component. Furthermore, "first," "second," and "third" are used only for distinguishing descriptions and do not imply differences in size.

[0041] In this specification, unless otherwise specified, the quantifiers “one” and “a” do not exclude scenarios involving multiple elements.

[0042] It should be noted that the embodiments of the present invention describe the method steps in a specific order; however, this is only for illustrating the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.

[0043] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0044] Figure 1 shows a top view and a cross-sectional view of an optical chip 200 according to an embodiment of the present invention. As shown in Figure 1, to facilitate the reception of optical signals, the optical chip has an optical port 210 located at the edge of the chip, and a groove 330 is designed within the dicing channel. That is, the optical chip receives optical signals from the side. In existing optoelectronic encapsulation, to avoid the molding compound blocking the optical port, the optical chip is usually placed at the end of the process and interconnected via WB process, or it is not encapsulated after FC flip-chip bonding. To achieve full encapsulation of the optical chip, the present invention provides an optoelectronic encapsulation structure with an optical port protection design, which can avoid the problem of molding compound blocking the optical port, and at the same time eliminates the need for an additional optical port protection structure.

[0045] Figure 2 shows a top view of an optical chip module 101 according to an embodiment of the present invention. The optical chip module 101 includes a first optical chip 310 and a second optical chip 320. The first optical chip 310 and the second optical chip 320 each have a first optical port 311 and a second optical port 321 on their first surfaces, and the first optical port 311 and the second optical port 321 share a trench 330. The trench 330 is not designed within the dicing track. In subsequent packaging, the first optical chip 310 and the second optical chip 320 are used as a module, and after the wafer of the optical chip module is diced, the trench 330 is not interconnected with the dicing track.

[0046] Figure 3 shows a flowchart of an optoelectronic sealing process according to an embodiment of the present invention.

[0047] First, in step 401, the optical chip module is encapsulated. During the encapsulation process, the optical port is shielded by a film to prevent contamination by the encapsulating material, forming the packaging structure shown in Figure 4, where the optical chip module 101 has the structure shown in Figure 2. Specifically, the silicon photonics wafer is first diced into optical chip modules 101 and arranged in an array, then flip-mounted onto a heat-release film. Wafer-level encapsulation is completed using a first encapsulating material. Since the trenches 330 and the dicing tracks are not interconnected, no encapsulating material is squeezed into the trenches during the encapsulation process, thus preventing contamination of the optical port. Except for the first surface containing the optical port, all other surfaces of the optical chip module 101 are covered by the first encapsulating material 102. The first surface of the optical chip module 101 and the first surface of the first encapsulating material 102 are coplanar.

[0048] Next, in step 402, the second side of the first molding compound 102 is thinned to expose the second side of the optical chip module 101. Specifically, as shown in Figure 5, the optical chip module 101 and the first side of the first molding compound 102 are first fixed to the bonding carrier 103 by a temporary bonding layer 104. Then, the second side of the first molding compound 102 is thinned by a grinding process to expose the second side of the optical chip module 101. The temporary bonding layer 104 can be a thermoplastic or thermosetting organic material, or an inorganic material containing Cu, Ni, Cr, Co, etc. The temporary bonding layer 104 can be removed by heating, mechanical, chemical, laser, freezing, or other methods.

[0049] In step 403, a conductive through-hole (TMV) 105 is formed within the first molding compound 102, and a redistribution layer (RDL) 106 is formed on the second surface of the first molding compound 102 and the optical chip module 101, as shown in FIG6. In an embodiment of the present invention, the through-hole can be prepared in the first molding compound 102 by laser drilling, and then conductive material is filled into the through-hole by processes such as sputtering and electroplating to form the conductive through-hole (TMV) 105. In an embodiment of the present invention, the redistribution layer (RDL) 106 can be formed on the second surface by processes such as photolithography and electroplating. The redistribution layer (RDL) 106 may include one or more conductive circuit layers and an insulating medium disposed between the conductive circuit layers. Pads or bumps are provided on the top surface of the redistribution layer (RDL) 106.

[0050] In step 404, the electrical chip 107 is mounted on the redistribution layer RDL 106 and encapsulated, as shown in FIG7. In an embodiment of the present invention, multiple electrical chips 107 can be soldered onto the redistribution layer RDL 106 using a flip-chip process, followed by underfilling. Specifically, the electrical chip bumps are aligned and mounted on the bottom redistribution layer; after layout, bonding is performed using reflow soldering or thermoforming bonding processes; after interconnection is formed, underfill is drop-coated around the chip, and the underfill filler fills the gap between the chip and the redistribution layer through capillary action; after filling, the assembly is placed in a curing oven for curing of the underfill. Then, encapsulation is performed using a second encapsulating material 108. Optionally, the second encapsulating material 108 can be thinned to expose the back side of the electrical chip 107.

[0051] In step 405, the temporary bonding substrate 103 is removed, and a protrusion 109 is formed on the first surface of the optical chip module 101 and the first molding compound 102, as shown in FIG8. In embodiments of the present invention, the temporary bonding layer 104 can be removed by means of heating, mechanical, chemical, laser, freezing, etc. The protrusion 109 can be formed on the pads on the first surface of the optical chip module and on the conductive through-hole (TMV) 105 of the first molding compound 102.

[0052] In one embodiment of the present invention, the bump 109 is a C4 bump, which can be formed by processes such as vapor deposition, screen printing, electrochemical deposition, or electroplating. Specifically, a UBM layer is first formed at the location of the bump 109, then solder is formed on the UBM layer, and finally the wafer is reflowed to form a smooth spherical C4 solder bump under the action of surface tension.

[0053] In step 410, wafer dicing is performed along the common trench 330 of the first chip and the second chip to obtain a single package module, as shown in Figure 9.

[0054] Figure 10 shows a cross-sectional schematic diagram of an optoelectronic encapsulation structure according to an embodiment of the present invention. As shown in Figure 10, the optoelectronic encapsulation structure includes: an optical chip 1110 and one or more electrical chips 107. A first surface of the optical chip 1110 is coplanar with a first surface of a first molding compound 102, and a second surface of the optical chip 1110 is coplanar with a second surface of the first molding compound 102. The first and second surfaces of the optical chip 1110 are two opposing main planes of the optical chip 1110. An optical aperture is located on the first surface of the optical chip 1110, and a trench is located on the chip edge on one side of the optical aperture. The first molding compound 102 encapsulates the optical chip 1110, but the first surface, the second surface, and the side where the trench is located are not covered by the first molding compound 102. One or more conductive through-holes (TMVs) 105 are provided in the first molding compound 102. Multiple protrusions are present on the first surface of both the optical chip 1110 and the first surface of the first molding compound 102. The bumps can be formed on the pads on the first surface of the optical chip module and on the conductive through-hole (TMV) of the first molding compound.

[0055] A redistribution layer RDL 106 is formed on the second surface of the first molding compound 102 and the optical chip 1110. One or more electrical chips 107 are mounted on the redistribution layer RDL 106. A second molding compound 108 encapsulates the electrical chips 107 and the redistribution layer RDL 106.

[0056] The first molding compound and the second molding compound can be the same material or different materials.

[0057] The optoelectronic encapsulation structure and manufacturing method provided by this invention enable the encapsulation of optical and electrical chips, protecting and securing the chips while providing electrical connections. This solves the problems associated with exposed chips, such as susceptibility to damage, contamination, difficulty in storage, and difficulty in connection, thereby ensuring chip reliability and stability and extending chip lifespan. Furthermore, the optoelectronic encapsulation structure and manufacturing method provided by this invention eliminate the need for a separate protective structure for the optical port, simplifying the process and reducing manufacturing costs.

[0058] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A method for manufacturing a photoelectric sealing structure, characterized in that, include: The optical chip module is first encapsulated, the optical chip module including a first optical chip and a second optical chip; the first side of the first optical chip and the second optical chip respectively includes a first optical port and a second optical port, the first optical port and the second optical port share a groove, and the first side of the first optical chip and the second optical chip are coplanar with the first side of the first encapsulating material. The second side of the first molding compound is thinned to expose the second side of the optical chip module; A conductive through-hole (TMV) is formed within the first molding compound, and a redistribution layer (RDL) is formed on the second surface of the first molding compound and the optical chip module. The electrical chip is mounted on the redistribution layer RDL and then subjected to a second molding process. A protrusion is formed on the first surface of the optical chip module and the first molding compound; as well as The wafer is diced along the common trench of the first and second chips to obtain a single package module.

2. The manufacturing method of the optoelectronic sealing structure according to claim 1, characterized in that, Molding the optical chip module includes: The silicon photonics wafer is diced into photonic chip modules and arranged in an array, then flipped onto a heat-release film. Wafer-level molding is completed using the first molding compound. Since the trenches and dicing tracks are not interconnected, no molding compound is squeezed into the trenches during the molding process.

3. The manufacturing method of the optoelectronic sealing structure according to claim 1, characterized in that, Thinning the second side of the first molding compound to expose the second side of the optical chip module includes: The optical chip module and the first side of the first molding compound are fixed on the bonding carrier by a temporary bonding layer. Then, the second side of the first molding compound is thinned by a grinding process, and the second side of the optical chip module is exposed.

4. The manufacturing method of the optoelectronic sealing structure according to claim 1, characterized in that, Mounting the electrical chip onto the redistribution layer RDL and performing a second molding process includes: The chip bumps are aligned and mounted on the bottom redistribution layer. After the layout is completed, bonding is performed by reflow soldering or thermoforming. After the interconnect is formed, underfill is applied around the chip. The underfill filler fills the gap between the chip and the redistribution layer through capillary action. After filling, the assembly is placed in a curing oven to cure the underfill.

5. The manufacturing method of the optoelectronic sealing structure according to claim 1, characterized in that, The protrusion formed on the first surface of the optical chip module and the first molding compound includes: Remove temporary bonded substrate; A UBM layer is formed at the raised position, then solder is formed on the UBM layer, and finally the wafer is reflowed to form smooth spherical C4 solder bumps under the action of surface tension.

6. A photoelectric sealing structure formed by the manufacturing method of any one of claims 1 to 5, comprising: Optical chip and one or more electrical chips; The first surface of the optical chip is coplanar with the first surface of the first molding compound, and the second surface of the optical chip is coplanar with the second surface of the first molding compound. The first and second surfaces of the optical chip are two opposing main planes of the optical chip. The optical port is located on the first surface of the optical chip, and the trench is located on the chip edge on one side of the optical port. The first molding compound encapsulates the optical chip, but the first side, the second side, and the side where the trench is located are not covered by the first molding compound. One or more conductive through-holes (TMVs) are provided in the first molding compound. The first side of the optical chip and the first side of the first molding compound have multiple protrusions. A redistribution layer (RDL) is formed on the second surface of a first molding compound and an optical chip. One or more electrical chips are mounted on the redistribution layer (RDL), and a second molding compound encapsulates the electrical chips and the redistribution layer.

7. The optoelectronic sealing structure according to claim 6, characterized in that, The plurality of protrusions are under a UBM layer.

8. The optoelectronic sealing structure according to claim 6, characterized in that, The protrusions are formed on the pads on the first surface of the optical chip module and on the conductive through-hole (TMV) of the first molding compound.

9. The photoelectric sealing structure according to claim 6, characterized in that, The redistribution layer (RDL) includes one or more conductive lines and an insulating medium disposed between the conductive lines.

10. The optoelectronic sealing structure according to claim 6, characterized in that, The electronic chip is a flip chip.

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