Power amplifier and method for limiting gain of power amplifier

Abstract

The present invention provides a power amplifier. The power amplifier comprises a power amplification circuit, a bias circuit, and a power detection control circuit. The power detection control circuit collects and detects an input signal of the power amplification circuit. When the power of the input signal of the power amplification circuit is greater than set threshold power, the power detection control circuit draws the current of the bias circuit, the bias current output by the bias circuit is pulled down, and the gain of the power amplification circuit is reduced; and when the power of the input signal of the power amplification circuit is less than or equal to the set threshold power, the bias current output by the bias circuit remains unchanged. In this way, when the power of the input signal of the power amplification circuit is excessively high, the power amplifier can enter a low gain mode or a sleep mode, thereby effectively preventing the power amplifier from outputting higher power, and further effectively preventing the power amplifier from burning out. The present invention also provides a method for limiting the gain of a power amplifier.

Description

Power amplifiers and methods for limiting power amplifier gain Technical Field

[0001] This invention relates to the field of radio frequency technology, and in particular to a power amplifier and a method for limiting the gain of the power amplifier. Background Technology

[0002] Radio frequency (RF) power amplifiers are widely used in wireless communication devices such as mobile phones. In the pre-amplifier circuit of a transmitter, the RF signal generated by the modulation oscillator circuit has very low power and needs to be amplified by the RF power amplifier to obtain sufficient RF power before it can be fed to the antenna for radiation. The RF power amplifier is the last stage of the transmitter and is the highest power component in the transmitter. It is also susceptible to damage from factors such as excessive transmitter output power, antenna mismatch, and unstable power supply voltage, making it prone to burnout. Excessive transmitter output power often stems from inaccurate output power calibration, which can be caused by various factors, such as antenna mismatch, coupler coupling coefficient deviation, and production deviations in output power. Therefore, preventing power amplifier burnout is a crucial issue that needs to be addressed. Summary of the Invention

[0003] This invention provides a power amplifier and a method for limiting the gain of the power amplifier. When the transmitter transmits excessive power, the gain of the power amplifier can be automatically reduced or turned off, effectively preventing the power amplifier from outputting more power and effectively preventing the power amplifier from burning out.

[0004] To achieve the above objectives, the present invention provides a power amplifier. The power amplifier includes a power amplification circuit, a bias circuit, and a power detection and control circuit. The bias circuit outputs a bias current, which controls the output of the power amplification circuit. The power detection and control circuit adjusts the bias current output by the bias circuit based on the input signal of the power amplification circuit. Specifically, the power detection and control circuit acquires and detects the input signal of the power amplification circuit. When the power of the input signal is greater than a set threshold power, the power detection and control circuit draws current from the bias circuit, pulling down the bias current output by the bias circuit and reducing the gain of the power amplification circuit. When the power of the input signal is less than or equal to the set threshold power, the bias current output by the bias circuit remains unchanged.

[0005] Optionally, after acquiring the input signal of the power amplifier circuit, the power detection and control circuit performs DC shaping on the input signal to obtain a control voltage; when the control voltage is greater than the set threshold voltage, the power detection and control circuit draws current from the bias circuit, and the bias current output by the bias circuit is pulled low; when the control voltage is less than or equal to the set threshold voltage, the bias current output by the bias circuit remains unchanged.

[0006] Optionally, the power detection and control circuit includes a power detector and a current extractor; the power detector outputs a control voltage based on the input signal of the power amplifier circuit; the current extractor receives the control voltage, and when the control voltage is greater than a set threshold voltage, the current extractor extracts current from the bias circuit to pull down the bias current of the bias circuit; when the control voltage is less than or equal to the set threshold voltage, the current extractor does not operate.

[0007] Optionally, the power detection and control circuit further includes an attenuator; the attenuator receives the input signal from the power amplifier circuit and attenuates the input signal before outputting it to the power detector.

[0008] Optionally, the attenuator includes a fourth capacitor and a ninth resistor, one end of the ninth resistor is connected to the RF input terminal of the power amplifier circuit and the other end is connected to the first terminal of the fourth capacitor, and the second terminal of the fourth capacitor serves as the output terminal of the attenuator.

[0009] Optionally, the power detection and control circuit includes a power detector and an attenuator; the power detector includes a ninth transistor, an eighth transistor, a seventh transistor, an eighth resistor, a seventh resistor, a sixth resistor, a fifth resistor, a fourth resistor, and a third capacitor; one end of the eighth resistor and the base of the ninth transistor are connected to the output terminal of the attenuator, the other end of the eighth resistor is connected to one end of the sixth resistor, one end of the seventh resistor, and the collector of the ninth transistor, the other end of the sixth resistor is connected to a first power supply, the other end of the seventh resistor is connected to the base of the eighth transistor and one end of the third capacitor, the collector of the eighth transistor and the base of the seventh transistor are both connected to one end of the fifth resistor, the other end of the fifth resistor and the collector of the seventh transistor are both connected to the first power supply, the emitter of the seventh transistor is connected to one end of the fourth resistor, and the other end of the fourth resistor, the emitter of the ninth transistor, the other end of the third capacitor, and the emitter of the eighth transistor are grounded; the emitter of the seventh transistor serves as the output terminal of the power detector.

[0010] Optionally, the power detection and control circuit includes a power detector and a current extractor; the current extractor includes a third resistor, a sixth transistor, and a fifth transistor; the third resistor is connected to the output terminal of the power detector, and the other end of the third resistor is connected to the collector, base, and base of the sixth transistor; the emitters of the sixth and fifth transistors are grounded, and the collector of the fifth transistor is connected to the bias circuit; the collector of the fifth transistor serves as the output terminal of the current extractor.

[0011] Optionally, the power detection and control circuit includes at least one current extractor, the bias circuit includes at least one bias unit, and the number of current extractors and the number of bias units are equal, with one current extractor correspondingly connected to one bias unit.

[0012] Optionally, the number of current extractors is two or more, and the threshold voltages of the current extractors may be the same or different.

[0013] Optionally, the bias circuit includes a fourth transistor, a third transistor, a second transistor, a second resistor, a first resistor, and a second capacitor; the base of the third transistor, the collector of the third transistor, the base of the second transistor, one end of the second capacitor, and one end of the second resistor are all connected to the output terminal of the power detection and control circuit; the other end of the second resistor is connected to a second power supply; the collector of the second transistor is connected to a third power supply; the emitter of the third transistor is connected to the base and collector of the fourth transistor; the emitter of the fourth transistor and the other end of the second capacitor are grounded; the emitter of the second transistor is connected to one end of the first resistor; and the other end of the first resistor is connected to the power amplifier circuit.

[0014] Optionally, the power amplifier circuit includes a first capacitor and a first transistor. One end of the first capacitor is connected to the radio frequency input terminal of the power amplifier circuit, and the other end of the first capacitor is connected to the base of the first transistor and the output terminal of the bias circuit. The emitter of the first transistor is grounded.

[0015] Optionally, the power amplifier circuit includes at least one amplification unit, the number of which is equal to the number of bias units in the bias circuit, and one bias unit is connected to one amplification unit.

[0016] Optionally, the power detection and control circuit includes a first current extractor and a second current extractor; the bias circuit includes a first bias unit and a second bias unit; the power amplification circuit includes a first amplification unit and a second amplification unit; the first current extractor is connected to the first bias unit and can extract the current of the first bias unit; the first bias unit is also connected to the first amplification unit and controls the output of the first amplification unit; the second current extractor is connected to the second bias unit and can extract the current of the second bias unit; the second bias unit is also connected to the second amplification unit and controls the output of the second amplification unit.

[0017] Another aspect of the present invention provides a method for limiting the gain of a power amplifier. The power amplifier includes a power amplification circuit and a bias circuit, wherein the bias current output by the bias circuit controls the output of the power amplification circuit. The method for limiting the gain of the power amplifier includes: embedding a power detection and control circuit between the RF input terminal of the power amplification circuit and the bias circuit; the power detection and control circuit adjusts the bias current output by the bias circuit based on the input signal of the power amplification circuit; wherein the power detection and control circuit acquires and detects the input signal of the power amplification circuit; when the power of the input signal of the power amplification circuit is greater than a set threshold power, the power detection and control circuit draws current from the bias circuit, the bias current output by the bias circuit is pulled down, and the gain of the power amplification circuit decreases; when the power of the input signal of the power amplification circuit is less than or equal to the set threshold power, the power detection and control circuit does not draw current from the bias circuit, and the bias current output by the bias circuit remains unchanged.

[0018] The power amplifier and the method for limiting the gain of the power amplifier provided by this invention include a power amplifier circuit, a bias circuit, and a power detection and control circuit. The bias circuit outputs a bias current, and the bias current controls the output of the power amplifier circuit. The power detection and control circuit adjusts the bias current output by the bias circuit based on the input signal of the power amplifier circuit. Specifically, the power detection and control circuit acquires the input signal of the power amplifier circuit. When the power of the input signal of the power amplifier circuit exceeds a set threshold power, the power detection and control circuit draws current from the bias circuit, pulling down the bias current output by the bias circuit. This reduces the gain of the power amplifier, causing it to enter a low-gain mode or a sleep mode. This effectively prevents the power amplifier from outputting higher power and effectively prevents it from burning out, thus protecting the power amplifier. Attached Figure Description

[0019] Figure 1 is a schematic diagram of a power amplifier module provided in an embodiment of the present invention.

[0020] Figure 2 is a schematic diagram of the structure of a power amplifier provided in an embodiment of the present invention.

[0021] Figure 3 is a circuit diagram of the power detection and control circuit of a power amplifier provided in an embodiment of the present invention.

[0022] Figure 4 is a circuit diagram of a power amplifier provided in an embodiment of the present invention.

[0023] Figure 5 is a graph showing the change of control voltage of the power detection and control circuit as a function of the input power of the power amplifier according to an embodiment of the present invention.

[0024] Figure 6 is a graph showing the output gain of a power amplifier as a function of output power according to an embodiment of the present invention.

[0025] Explanation of reference numerals in the attached figures: 101-Power amplifier circuit; 102-Bias circuit; 103-Power detection and control circuit; 10-Input matching unit; 11-Attenuator; 12-Power detector; 13a-First current extractor; 13b-Second current extractor; 14a-First bias unit; 14b-Second bias unit; 15a-First amplification unit; 15b-Second amplification unit; 20-Output matching unit. Detailed Implementation

[0026] The power amplifier and the method for limiting the gain of the power amplifier proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0027] As used in this invention, the singular forms "a" and "the" include plural objects; the term "or" is generally used to include the meaning of "and / or"; and the term "at least two" is generally used to include the meaning of "two or more". The terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or at least two of that feature; the terms "one end" and "the other end" generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "joined" should be interpreted broadly, for example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two elements or the interaction between two elements.

[0028] In order to automatically reduce or shut down the gain of the power amplifier when the transmitter transmits excessive power, and to prevent the power amplifier from burning out, the present invention provides a power amplifier and a method for limiting the gain of the power amplifier.

[0029] Figure 1 is a schematic diagram of a power amplifier module provided according to an embodiment of the present invention. Referring to Figure 1, the power amplifier provided by the present invention includes a power amplifier circuit 101, a bias circuit 102, and a power detection and control circuit 103. The bias circuit 102 is used to output a bias current, which controls the output of the power amplifier circuit 101; the power detection and control circuit 103 is used to adjust the bias current output by the bias circuit 102 based on the input signal of the power amplifier circuit 101. Specifically, the power detection and control circuit 103 acquires and detects the input signal of the power amplifier circuit 101. When the power of the input signal of the power amplifier circuit 101 is greater than a set threshold power, the power detection and control circuit 103 draws current from the bias circuit 102, the bias current output by the bias circuit 102 is pulled down, and the gain of the power amplifier circuit 101 decreases; when the power of the input signal of the power amplifier circuit 101 is less than or equal to the set threshold power, the bias current output by the bias circuit 102 remains unchanged.

[0030] In this embodiment, the input signal of the power amplifier circuit 101 is a radio frequency input signal. After the power detection and control circuit 103 acquires the input signal of the power amplifier circuit 101, it performs DC shaping on the input signal to obtain a control voltage. When the control voltage is greater than a set threshold voltage, the power detection and control circuit 103 draws current from the bias circuit 102, and the bias current output by the bias circuit 102 is pulled low. When the control voltage is less than or equal to the set threshold voltage, the power detection and control circuit 103 does not draw current from the bias circuit 102, and the bias current output by the bias circuit 102 remains unchanged. It should be noted that the control voltage is related to the power of the input signal of the power amplifier circuit 101.

[0031] Figure 2 is a schematic diagram of the structure of a power amplifier provided in an embodiment of the present invention.

[0032] Specifically, referring to Figure 2, the power detection and control circuit includes a power detector 12 and a current extractor. The power detector 12 outputs a control voltage based on the input signal of the power amplifier circuit 101. The current extractor receives the control voltage. When the control voltage is greater than a set threshold voltage, the current extractor turns on, that is, the current extractor extracts the current of the bias circuit 102 to lower the bias current of the bias circuit 102. The bias circuit 102 enters a low current or even no current mode, and finally the gain of the power amplifier circuit 101, or the power amplifier, is reduced or even turned off. When the control voltage is less than or equal to the set threshold voltage, the current extractor turns off, that is, the current extractor does not extract the current of the bias circuit 102, so the working state of the bias circuit 102 remains unchanged, and the power amplifier circuit 101 works normally.

[0033] In this embodiment, as shown in FIG2, the power detection and control circuit 103 further includes an attenuator 11. The attenuator 11 receives the input signal from the power amplifier circuit 101 and attenuates the input signal before outputting it to the power detector 12. The power detector 12 processes the attenuated input signal to obtain the corresponding control voltage.

[0034] In this embodiment, referring to FIG2, the power detection and control circuit 103 has an input terminal and an output terminal. The input terminal of the power detection and control circuit 103 is connected to the RF input terminal of the power amplifier circuit 101, and the output terminal of the power detection and control circuit 103 is connected to the bias circuit 102. The output terminal of the bias circuit 102 is connected to the power amplifier circuit 101. In this embodiment, the input terminal of the attenuator 11 is used as the input terminal of the power detection and control circuit 103, and the output terminal of the current extractor is used as the output terminal of the power detection and control circuit 103.

[0035] As shown in Figure 2, the power amplifier circuit 101 may include an input matching unit 10, an amplification unit, and an output matching unit 20 connected in sequence.

[0036] The input matching unit 10 can be used to match the input impedance of the power amplifier and the impedance of the input signal source to ensure maximum power delivery. For example, the input matching unit 10 includes a transformer and a common-cathode amplifier. In this embodiment, both the attenuator 11 and the input matching unit 10 are connected to the RF input terminal. This structure reduces the impact on the input matching of the power amplifier compared to ordinary capacitive coupling.

[0037] The output matching unit 20 can be used to match the output impedance of the power amplifier with the impedance of the load to ensure maximum power delivery. For example, the output matching unit 20 includes an output transformer and a common-cathode amplifier, etc.

[0038] In this embodiment, the power amplifier circuit 101 includes at least one amplification unit, that is, the power amplifier circuit 101 is at least a first-stage amplification circuit. Correspondingly, the power detection and control circuit 103 includes at least one current extractor, and the bias circuit 102 includes at least one bias unit. The number of current extractors, the number of bias units, and the number of amplification units are equal. One current extractor is connected to one bias unit, and one bias unit is connected to one amplification unit.

[0039] For example, as shown in FIG2, the power detection and control circuit 103 includes two current extractors, namely a first current extractor 13a and a second current extractor 13b; the bias circuit 102 includes two bias units, namely a first bias unit 14a and a second bias unit 14b; the power amplifier circuit 101 includes two amplification units, namely a first amplification unit 15a and a second amplification unit 15b. The first current extractor 13a is connected to the first bias unit 14a and can extract the current of the first bias unit 14a. The first bias unit 14a is also connected to the first amplification unit 15a and controls the output of the first amplification unit 15a. The second current extractor 13b is connected to the second bias unit 14b and can extract the current of the second bias unit 14b. The second bias unit 14b is also connected to the second amplification unit 15b and controls the output of the second amplification unit 15b.

[0040] It should be noted that in Figure 2, the number of current extractors, bias units, and amplification units is two, but this is not a limitation. In other embodiments, the number of current extractors, bias units, and amplification units can be one or three, etc. When the power amplifier circuit 101 includes two or more amplification units, the power amplifier circuit 101 is a multi-stage radio frequency power amplifier circuit, and the power amplifier is a multi-stage radio frequency power amplifier.

[0041] In this application, all current extractors may receive the same control voltage. The following explanation assumes there are two or more current extractors. In some embodiments, the threshold voltages of the current extractors may be the same. When the power of the input signal to the power amplifier circuit 101 exceeds a set threshold power, the control voltage output by the power detector 12 exceeds the threshold voltage of the current extractor (i.e., the set threshold voltage), and all current extractors are turned on. When the power of the input signal to the power amplifier circuit 101 is less than or equal to the set threshold power, the control voltage output by the power detector 12 is less than or equal to the threshold voltage of the current extractor, and all current extractors are turned off. In some embodiments, the threshold voltages of the current extractors may be different. When multiple current extractors receive the same control voltage, the control voltage may be greater than the threshold voltage of some current extractors but less than the threshold voltage of others. This allows some current extractors to turn on and extract current from the corresponding bias unit, while others remain off.

[0042] Figure 3 is a circuit diagram of the power detection and control circuit of a power amplifier provided in an embodiment of the present invention.

[0043] For example, referring to Figures 2 and 3, the attenuator 11 may include a fourth capacitor C4 and a ninth resistor R9 connected in series. One end of the ninth resistor R9 is connected to the RF input terminal of the power amplifier circuit 101, and the other end is connected to the first end of the fourth capacitor C4. In this embodiment, one end of the ninth resistor R9 serves as the input terminal of the attenuator 11, and the second end of the fourth capacitor C4 serves as the output terminal of the attenuator 11.

[0044] The power detector 12 may include a ninth transistor T9, an eighth transistor T8, a seventh transistor T7, an eighth resistor R8, a seventh resistor R7, a sixth resistor R6, a fifth resistor R5, a fourth resistor R4, and a third capacitor C3. One end of the eighth resistor R8 and the base of the ninth transistor T9 are connected to the output terminal of the attenuator (i.e., the second end of the fourth capacitor C4). The other end of the eighth resistor R8 is connected to one end of the sixth resistor R6, one end of the seventh resistor R7, and the collector of the ninth transistor T9. The other end of the sixth resistor R6 is connected to the first power supply V_O. The DP connection is established. The other end of the seventh resistor R7 is connected to the base of the eighth transistor T8 and one end of the third capacitor C3. The collector of the eighth transistor T8 and the base of the seventh transistor T7 are both connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 and the collector of the seventh transistor T7 are both connected to the first power supply V_ODP. The emitter of the seventh transistor T7 is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4, the emitter of the ninth transistor T9, the other end of the third capacitor C3, and the emitter of the eighth transistor T8 are grounded.

[0045] In this embodiment, the emitter of the seventh transistor T7 serves as the output terminal of the power detector. The fourth resistor R4 is the bias resistor for the seventh transistor T7. The fifth resistor R5 is the bias resistor for the eighth transistor T8.

[0046] Referring to Figures 2 and 3, the current extractor may include a third resistor R3, a sixth transistor T6, and a fifth transistor T5. The third resistor R3 is connected to the output terminal of the power detector 12 (i.e., the emitter of the seventh transistor T7). The other end of the third resistor R3 is connected to the collector, base, and base of the sixth transistor T6 and the fifth transistor T5. The emitters of the sixth transistor T6 and the fifth transistor T5 are grounded. The collector of the fifth transistor T5 is connected to the bias circuit 102. In this embodiment, the collector of the fifth transistor T5 serves as the output terminal of the current extractor, which is also the output terminal of the power detection and control circuit. It should be noted that Figure 3 shows a current extractor for the power detection and control circuit, which may include a third resistor R3, a sixth transistor T6, and a fifth transistor T5.

[0047] Figure 4 is a circuit diagram of a power amplifier provided in an embodiment of the present invention. Referring to Figure 4, the bias circuit may include a fourth transistor T4, a third transistor T3, a second transistor T2, a second resistor R2, a first resistor R1, and a second capacitor C2; the base and collector of the third transistor T3, the base of the second transistor T2, one end of the second capacitor C2, and one end of the second resistor R2 are all connected to the output terminal of the current extractor (i.e., the collector of the fifth transistor T5); the other end of the second resistor R2 is connected to the second power supply V_ref; the collector of the second transistor T2 is connected to the third power supply Vbatt; the emitter of the third transistor T3 is connected to the base and collector of the fourth transistor T4; the emitter of the fourth transistor T4 and the other end of the second capacitor C2 are grounded; the emitter of the second transistor T2 is connected to one end of the first resistor R1; and the other end of the first resistor R1 is connected to the power amplifier circuit 101. In Figure 4, the bias circuit 102 shows only one bias unit. This bias unit may include a fourth transistor T4, a third transistor T3, a second transistor T2, a second resistor R2, a first resistor R1, and a second capacitor C2. The other end of the first resistor R1 serves as the output terminal of the bias circuit 102.

[0048] Referring to Figure 4, the power amplifier circuit 101 may include a first capacitor C1 and a first transistor T1. One end of the first capacitor C1 is connected to the RF input terminal of the power amplifier circuit, and the other end of the first capacitor C1 is connected to the base of the first transistor T1 and the output terminal of the bias circuit 102. The emitter of the first transistor T1 is grounded. Figure 4 only shows one amplification unit of the power amplifier circuit 101, and one amplification unit includes one first transistor T1. In this embodiment, the RF output terminal of the power amplifier circuit 101 can be led out from the collector of the first transistor T1.

[0049] It should be noted that Figure 4 only shows one example of the circuit structure of the bias circuit 102 and the power amplifier circuit 101. Figure 4 only shows the most classic circuit structure of the bias circuit 102 and the power amplifier circuit 101. In other embodiments, the circuit structure of the bias circuit 102 and the power amplifier circuit 101 may be different from that in Figure 4.

[0050] In this embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can all be any one of a heterojunction transistor, a high electron mobility transistor, a pseudo-high electron mobility transistor, or a bipolar junction transistor.

[0051] Referring to Figure 4, the input signal of the power amplifier circuit 101 is input from the RF input terminal, attenuated by the ninth resistor R9 and the fourth capacitor C4, and then reaches the ninth transistor T9. The diode effect from the base to the emitter of the ninth transistor T9 is used to DC-shape the input signal. After filtering by the seventh resistor R7 and the third capacitor C3, the first voltage V1 is obtained. The first voltage V1 is further input to the base of the eighth transistor T8, which shifts the first voltage V1 upwards to obtain the second voltage V2. The seventh transistor T7, acting as a source follower, shifts the second voltage V2 downwards to obtain the control voltage V3. The control voltage V3 is applied to the series connection of the third resistor R3 and the sixth transistor T6. The base and collector of the sixth transistor T6 are connected together, providing a bias voltage V4 to the base of the fifth transistor T5.

[0052] When the bias voltage V4 exceeds the startup threshold voltage of the fifth transistor T5, the fifth transistor T5 will draw current from the bias circuit 102, causing the current in the bias circuit 102 to be pulled low. Specifically, the fifth transistor T5 will draw current from the third transistor T3 and the fourth transistor T4 in the bias circuit 102, causing the base potential V5 of the second transistor T2 to be pulled down. V5 decreases until the bias current output by the second transistor T2 is turned off, and the bias circuit 102 enters a low-current or even no-current mode. Ultimately, the gain of the power amplifier circuit 101, or the power amplifier, is reduced until it is turned off.

[0053] Figure 5 is a graph showing the change of control voltage of the power detection and control circuit as a function of the input power of the power amplifier according to an embodiment of the present invention. As shown in Figure 5, curve 111 reflects the change of control voltage V3 of the power detection and control circuit as a function of input power, and curve 112 is the threshold voltage for the current extractor to start. Referring to curve 111, when the power of the input signal of the power amplifier (i.e., the input power of the power amplifier) ​​is low, the control voltage V3 obtained by the DC shaping of the power detection and control circuit 103 is low, approximately 1.1V, which cannot start the sixth transistor T6 and the fifth transistor T5, and therefore cannot change the operating state of the bias circuit 102. When the input signal power increases to 8dBm, the control voltage V3 obtained by the DC shaping of the power detection and control circuit 103 reaches 1.3V, exceeding the threshold voltage range for the sixth transistor T6 to start. The sixth transistor T6 and the fifth transistor T5 turn on and draw current from the bias circuit 102, reducing or turning off the bias current output by the bias circuit 102. This lowers the static bias current of the power amplifier circuit 101, causing it to enter a low-gain mode or a sleep mode, thus protecting the power amplifier. When the input signal power further increases, the control voltage V3 obtained by the DC shaping of the power detection and control circuit 103 reaches a maximum of 1.6V, which keeps the bias current output by the bias circuit 102 off, lowering the static bias current of the power amplifier circuit 101 and keeping it in sleep mode, thus protecting the power amplifier.

[0054] Figure 6 is a graph showing the output gain of a power amplifier as a function of output power according to an embodiment of the present invention. As shown in Figure 6, curve 211 (a flat solid line with a dashed line) is a graph showing the gain of a conventional power amplifier as a function of output power. Referring to curve 211, when the input power is low, the output gain of the power amplifier does not change with the input power, and therefore does not change with the output power. When the input power increases further, that is, when the output power increases, for example, exceeding 30 dBm, although the output gain decreases at this time, the output power still increases, which leads to the risk of the power amplifier being burned out.

[0055] Curve 212 (all solid lines) in Figure 6 is a graph showing the output gain of the power amplifier of this application as a function of output power. The difference between curve 212 and curve 211 occurs when the output power of the power amplifier exceeds 30 dBm. At this point, the power detection and control circuit 103 of the power amplifier of this application starts up, the bias circuit 102 reduces the output current, and the gain of the power amplifier circuit 101 drops rapidly. Consequently, the output power also decreases, resulting in curve 212 bending to the left (in the direction of lower output power). This effectively prevents the power amplifier from outputting even higher power, thus protecting the power amplifier.

[0056] This application also provides a method for limiting the gain of a power amplifier. The power amplifier of this application can perform the method for limiting the gain of the power amplifier.

[0057] Referring to Figures 1, 2 and 4, the power amplifier includes a power amplifier circuit 101 and a bias circuit 102, and the bias current output by the bias circuit 102 controls the output of the power amplifier circuit 101. The method for limiting the gain of the power amplifier includes: embedding a power detection and control circuit 103 between the RF input terminal of the power amplifier circuit 101 and the bias circuit 102; the power detection and control circuit 103 adjusting the bias current output by the bias circuit 102 based on the input signal of the power amplifier circuit 101; wherein, the power detection and control circuit 103 acquires and detects the input signal of the power amplifier circuit 101; when the power of the input signal of the power amplifier circuit 101 is greater than a set threshold power, the power detection and control circuit 103 draws current from the bias circuit 102, the bias current output by the bias circuit 102 is pulled down, and the gain of the power amplifier circuit 101 is reduced; when the power of the input signal of the power amplifier circuit 101 is less than or equal to the set threshold power, the power detection and control circuit 103 does not draw current from the bias circuit 102, and the bias current output by the bias circuit 102 remains unchanged.

[0058] Specifically, after the power detection and control circuit 103 acquires the input signal of the power amplifier circuit 101, it performs DC shaping on the input signal to obtain a control voltage. When the control voltage is greater than the set threshold voltage, the power detection and control circuit 103 draws current from the bias circuit 102, and the bias current output by the bias circuit 102 is pulled low. When the control voltage is less than or equal to the set threshold voltage, the power detection and control circuit 103 does not draw current from the bias circuit 102, and the bias current output by the bias circuit remains unchanged.

[0059] Referring to Figure 2, the power detection and control circuit 103 includes an attenuator 11, a power detector 12, and a current extractor.

[0060] The attenuator 11 receives the input signal from the power amplifier circuit 101 and attenuates the input signal before outputting it to the power detector 12. The power detector 12 outputs a control voltage based on the attenuated input signal. The current extractor receives the control voltage. When the control voltage is greater than a set threshold voltage, the current extractor extracts current from the bias circuit 102 to lower the bias current of the bias circuit 102. When the control voltage is less than or equal to the set threshold voltage, the current extractor does not operate.

[0061] It should be noted that in this application, when the power of the input signal of the power amplifier is less than the set threshold power, the gain of the power amplifier is basically a constant that does not change with the input power; when the power of the input signal is greater than the set threshold power, the gain of the power amplifier decreases monotonically and smoothly with the increase of the input power, thereby effectively preventing the power amplifier from burning out.

[0062] The power amplifier and the method for limiting the gain of the power amplifier provided by the present invention include a power amplifier circuit 101, a bias circuit 102, and a power detection and control circuit 103. The bias circuit 102 is used to output a bias current, and the bias current controls the output of the power amplifier circuit 101. The power detection and control circuit 103 is used to adjust the bias current output by the bias circuit 102 based on the input signal of the power amplifier circuit. The power detection and control circuit 103 acquires the input signal of the power amplifier circuit 101. When the power of the input signal of the power amplifier circuit 101 is greater than a set threshold power, the power detection and control circuit 103 draws current from the bias circuit 102, the bias current output by the bias circuit 102 is pulled down, and the gain of the power amplifier circuit is reduced, thereby causing the power amplifier to enter a low-gain mode or a sleep mode. This effectively prevents the power amplifier from outputting higher power and effectively prevents the power amplifier from burning out, thus protecting the power amplifier.

[0063] It should be noted that this manual uses a progressive approach. The methods for limiting the gain of the power amplifier described later focus on the differences from the power amplifiers described earlier. For similarities and similarities between the different parts, please refer to each other.

[0064] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A power amplifier, characterized in that, This includes power amplifier circuits, bias circuits, and power detection and control circuits; The bias circuit is used to output a bias current, and the bias current controls the output of the power amplifier circuit. The power detection and control circuit is used to adjust the bias current output by the bias circuit based on the input signal of the power amplifier circuit. The power detection and control circuit acquires and detects the input signal of the power amplifier circuit. When the power of the input signal of the power amplifier circuit is greater than a set threshold power, the power detection and control circuit draws current from the bias circuit, the bias current output by the bias circuit is pulled down, and the gain of the power amplifier circuit is reduced. When the power of the input signal of the power amplifier circuit is less than or equal to the set threshold power, the bias current output by the bias circuit remains unchanged.

2. The power amplifier as described in claim 1, characterized in that, After acquiring the input signal of the power amplifier circuit, the power detection and control circuit performs DC shaping on the input signal to obtain a control voltage; when the control voltage is greater than the set threshold voltage, the power detection and control circuit draws the current of the bias circuit, and the bias current output by the bias circuit is pulled down. When the control voltage is less than or equal to the set threshold voltage, the bias current output by the bias circuit remains unchanged.

3. The power amplifier as described in claim 1, characterized in that, The power detection and control circuit includes a power detector and a current extractor; the power detector outputs a control voltage based on the input signal of the power amplifier circuit; the current extractor receives the control voltage, and when the control voltage is greater than a set threshold voltage, the current extractor extracts the current of the bias circuit to pull down the bias current of the bias circuit; when the control voltage is less than or equal to the set threshold voltage, the current extractor does not work.

4. The power amplifier as described in claim 3, characterized in that, The power detection and control circuit further includes an attenuator; the attenuator receives the input signal from the power amplifier circuit and attenuates the input signal before outputting it to the power detector.

5. The power amplifier as described in claim 4, characterized in that, The attenuator includes a fourth capacitor and a ninth resistor. One end of the ninth resistor is connected to the RF input terminal of the power amplifier circuit and the other end is connected to the first terminal of the fourth capacitor. The second terminal of the fourth capacitor serves as the output terminal of the attenuator.

6. The power amplifier as described in claim 1, characterized in that, The power detection and control circuit includes a power detector and an attenuator. The power detector includes a ninth transistor, an eighth transistor, a seventh transistor, an eighth resistor, a seventh resistor, a sixth resistor, a fifth resistor, a fourth resistor, and a third capacitor. One end of the eighth resistor and the base of the ninth transistor are connected to the output terminal of the attenuator. The other end of the eighth resistor is connected to one end of the sixth resistor, one end of the seventh resistor, and the collector of the ninth transistor. The other end of the sixth resistor is connected to a first power supply. The other end of the seventh resistor is connected to the base of the eighth transistor and one end of the third capacitor. The collector of the eighth transistor and the base of the seventh transistor are both connected to one end of the fifth resistor. The other end of the fifth resistor and the collector of the seventh transistor are both connected to the first power supply. The emitter of the seventh transistor is connected to one end of the fourth resistor. The other end of the fourth resistor, the emitter of the ninth transistor, the other end of the third capacitor, and the emitter of the eighth transistor are grounded. The emitter of the seventh transistor serves as the output terminal of the power detector.

7. The power amplifier as claimed in claim 1, characterized in that, The power detection and control circuit includes a power detector and a current extractor; the current extractor includes a third resistor, a sixth transistor, and a fifth transistor; the third resistor is connected to the output terminal of the power detector, and the other end of the third resistor is connected to the collector, base, and base of the sixth transistor; the emitters of the sixth and fifth transistors are grounded, and the collector of the fifth transistor is connected to the bias circuit; the collector of the fifth transistor serves as the output terminal of the current extractor.

8. The power amplifier as described in claim 3, characterized in that, The power detection and control circuit includes at least one current extractor, and the bias circuit includes at least one bias unit. The number of current extractors and the number of bias units are equal, and one current extractor is connected to one bias unit.

9. The power amplifier as described in claim 8, characterized in that, The number of current extractors is two or more, and the threshold voltage of the current extractors is the same.

10. The power amplifier as claimed in claim 8, characterized in that, The number of current extractors is two or more, and the threshold voltages of the current extractors are different.

11. The power amplifier as claimed in claim 1, characterized in that, The bias circuit includes a fourth transistor, a third transistor, a second transistor, a second resistor, a first resistor, and a second capacitor. The base of the third transistor, the collector of the third transistor, the base of the second transistor, one end of the second capacitor, and one end of the second resistor are all connected to the output terminal of the power detection and control circuit. The other end of the second resistor is connected to a second power supply. The collector of the second transistor is connected to a third power supply. The emitter of the third transistor is connected to the base and collector of the fourth transistor. The emitter of the fourth transistor and the other end of the second capacitor are grounded. The emitter of the second transistor is connected to one end of the first resistor. The other end of the first resistor is connected to the power amplifier circuit.

12. The power amplifier as claimed in claim 1, characterized in that, The power amplifier circuit includes a first capacitor and a first transistor. One end of the first capacitor is connected to the radio frequency input terminal of the power amplifier circuit, and the other end of the first capacitor is connected to the base of the first transistor and the output terminal of the bias circuit. The emitter of the first transistor is grounded.

13. The power amplifier as claimed in claim 1, characterized in that, The power amplifier circuit includes at least one amplification unit, the number of which is equal to the number of bias units in the bias circuit, and one bias unit is connected to one amplification unit.

14. The power amplifier as claimed in claim 1, characterized in that, The power detection and control circuit includes a first current extractor and a second current extractor; the bias circuit includes a first bias unit and a second bias unit; the power amplifier circuit includes a first amplification unit and a second amplification unit; the first current extractor is connected to the first bias unit and can extract the current of the first bias unit; the first bias unit is also connected to the first amplification unit and controls the output of the first amplification unit; the second current extractor is connected to the second bias unit and can extract the current of the second bias unit; the second bias unit is also connected to the second amplification unit and controls the output of the second amplification unit.

15. A method for limiting the gain of a power amplifier, wherein the method for limiting the gain of a power amplifier is performed using a power amplifier as described in any one of claims 1 to 14, the power amplifier comprising a power amplification circuit and a bias circuit, wherein a bias current output by the bias circuit controls the output of the power amplification circuit, characterized in that, A power detection and control circuit is embedded between the RF input terminal of the power amplifier circuit and the bias circuit. The power detection and control circuit adjusts the bias current output by the bias circuit based on the input signal of the power amplifier circuit. Specifically, the power detection and control circuit acquires and detects the input signal of the power amplifier circuit. When the power of the input signal of the power amplifier circuit is greater than a set threshold power, the power detection and control circuit draws current from the bias circuit, the bias current output by the bias circuit is pulled down, and the gain of the power amplifier circuit is reduced. When the power of the input signal of the power amplifier circuit is less than or equal to the set threshold power, the power detection and control circuit does not draw current from the bias circuit, and the bias current output by the bias circuit remains unchanged.

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