Semiconductor process chamber and semiconductor process apparatus

Abstract

The present application discloses a semiconductor process chamber and a semiconductor process apparatus. The disclosed semiconductor process chamber comprises a chamber body, a shielding member, and a bearing device, wherein the shielding member and the bearing device are movably arranged in the chamber body; when the shielding member is located at a first position and the bearing device is located at a third position, the shielding member is opposite to the bearing device, and the shielding member, the chamber body, and the bearing device define a pre-cleaning space; and when the shielding member is located at a second position and the bearing device is located at a fourth position, the shielding member and the bearing device are distributed in a staggered manner, and the bearing device and the chamber body define a coating space. The solution can solve the problem in the related art that semiconductor process apparatuses have poor coating quality.

Description

Semiconductor process chambers and semiconductor process equipment Technical Field

[0001] This application belongs to the field of semiconductor technology, specifically relating to a semiconductor process chamber and semiconductor process equipment. Background Technology

[0002] To ensure coating quality, wafers typically undergo a pre-cleaning process before the coating process. The pre-cleaning process removes impurities such as oxides and nitrides from the wafer surface through etching. After the pre-cleaning process, the wafer is relatively clean and is then transported to the coating process chamber (such as a sputtering process chamber) for the coating process.

[0003] The semiconductor process equipment involved in the related technologies includes a pre-cleaning process chamber, a coating process chamber, and a transfer chamber. In the specific process, a wafer robot transports the wafer between the pre-cleaning and coating process chambers. Due to the lower vacuum level in the transfer chamber, slight oxidation and nitriding occur during the transfer of the wafer from the pre-cleaning chamber to the coating process chamber. Furthermore, the wafer is easily recontaminated during transport, resulting in unsatisfactory cleanliness of the wafers delivered to the coating process chamber. For this reason, the semiconductor process chambers designed in these technologies cannot improve the cleanliness of the wafers before coating, thus still resulting in poor coating quality.

[0004] To avoid this problem, related technologies have attempted to prevent secondary contamination of the wafer by improving the cleanliness of the environment in which the wafer transport path is located, but with little success. Summary of the Invention

[0005] This application discloses a semiconductor process chamber and semiconductor process equipment to solve the problem of poor coating quality in semiconductor process equipment involved in related technologies.

[0006] To solve the above-mentioned technical problems, this application provides the following technical solution:

[0007] In a first aspect, embodiments of this application disclose a semiconductor process chamber. The disclosed semiconductor process chamber includes a chamber body, a shielding member, and a support device. The shielding member is movably disposed within the chamber body to switch between a first position and a second position. The support device is movably disposed within the chamber body to switch between a third position and a fourth position.

[0008] When the shielding member is in the first position and the supporting device is in the third position, the shielding member is opposite to the supporting device, and the shielding member, the chamber body and the supporting device form a pre-cleaning space;

[0009] When the shielding member is in the second position and the supporting device is in the fourth position, the shielding member and the supporting device are misaligned, and the supporting device and the chamber body form a coating space.

[0010] Secondly, embodiments of this application disclose a semiconductor process apparatus, which includes the semiconductor process chamber described in the first aspect.

[0011] The technical solution adopted in this application can achieve the following technical effects:

[0012] The semiconductor process chamber disclosed in this application, by adjusting the positions of the shielding member and the carrier device, allows the shielding member and the carrier device to be positioned so that, when the shielding member is in a first position and the carrier device is in a third position, the shielding member and the carrier device are opposite each other, and the shielding member, the carrier device, and the chamber body cooperate to form a pre-cleaning space, thereby enabling the pre-cleaning process. Simultaneously, by adjusting the positions of the shielding member and the carrier device, the shielding member can also be positioned in a second position and the carrier device in a fourth position. In this case, the shielding member and the carrier device are staggered, and the carrier device and the chamber body form a coating space. Therefore, the semiconductor process chamber disclosed in this application can form both a pre-cleaning space and a coating space, allowing both the pre-cleaning process and the coating process to be performed within the same semiconductor process chamber. Compared to related technologies that require separate configuration of pre-cleaning process chambers and coating process chambers, resulting in the wafer being oxidized, nitrided, and contaminated again during transfer between them, the semiconductor process chamber disclosed in this application does not require the transfer of wafers between chambers. This avoids contamination, oxidation, and nitriding caused by the transfer of wafers between the pre-cleaning process chamber and the coating process chamber, thus making the wafer cleaner before the coating process, which in turn helps to improve the coating quality of the coating process after the pre-cleaning process.

[0013] Meanwhile, since the semiconductor process chamber disclosed in this application can realize both the pre-cleaning process and the coating process, the semiconductor process equipment does not need to be configured with a single-function pre-cleaning process chamber and a coating process chamber. This allows for more coating processes to be performed with the same number of chambers, thereby increasing the coating capacity of the semiconductor process equipment. Attached Figure Description

[0014] Figure 1 is a structural diagram of the semiconductor process chamber disclosed in the embodiment of this application when it is first connected to the wafer;

[0015] Figure 2 is a structural diagram of the semiconductor process chamber disclosed in the embodiment of this application when the shielding member is in the junction position;

[0016] Figure 3 is a structural diagram of the semiconductor process chamber disclosed in the embodiment of this application when the shielding member is supported by the first strut;

[0017] Figure 4 is a structural diagram of the semiconductor process chamber forming a pre-cleaning space according to an embodiment of this application;

[0018] Figure 5 is a structural diagram of the semiconductor process chamber forming a coating space as disclosed in the embodiments of this application;

[0019] Figure 6 is a cross-sectional view of the second sub-liner disclosed in an embodiment of this application;

[0020] Figure 7 is a schematic diagram of the structure of the insulating cylinder disclosed in the embodiment of this application;

[0021] Figure 8 is a schematic diagram of the structure of the covering ring disclosed in an embodiment of this application;

[0022] Figure 9 is a schematic diagram of the structure of the deposition ring disclosed in an embodiment of this application;

[0023] Figure 10 is a schematic diagram of the structure of the shielding component disclosed in the embodiment of this application;

[0024] Figure 11 is a sectional view along line AA of Figure 10;

[0025] Figure 12 is a schematic diagram of the structure of the semiconductor process equipment disclosed in the embodiments of this application;

[0026] Explanation of reference numerals in the attached drawings: 10-Cavity body, 11-Cavity shell, 111-Upper adapter, 1111-First air inlet, 1112-First cooling channel, 1113-Second air inlet, 112-Target material, 113-Lower adapter, 1131-Second cooling channel, 1141-Magnetic shielding cylinder, 1142-Insulating cylinder, 115-Insulating ring, 1161-First power supply, 1162-Magnetron drive unit, 1163-Upper electrode, 1164-Magnetron, 1165-Sealing device, 117-Bias magnetic field coil, 1181-Second power supply, 1182-First matching device, 1183-Third power supply, 1184-Second matching device, 119-Shell body, 1191-Transfer hole, 12-Top liner, 121-First sub-liner, 122-Second sub-liner, 1221-First annular protrusion, 1222-Second annular groove, 1223-First cylindrical body, 13-Covering ring, 131-Second annular protrusion, 132-Third annular groove, 14-Bottom liner, 141-Third annular protrusion, 15-First RF coil, 16-Annular gap, 17-First air intake channel, 18-Second air intake channel, 20-Shielding component, 21-Supporting protrusion, 22-Positioning groove, 23-First annular groove, 30-Bearing device, 301-First clearance hole, 302-Second clearance hole, 31-Extension cylinder, 32-Bearing body, 321-Bearing surface, 33-Deposition ring, 40-Wafer, 51-First support rod, 52-Second support rod, 53-Support rod seat, 61-Storage section, 62-Rotation drive mechanism, 01-Pre-cleaning space, 02-Coating space, 03-Upper space, 70-First lifting mechanism, 71-First lifting shaft, 72-First bellows, 80-Second lifting mechanism, 81-Second lifting shaft, 82-Second bellows, 91-Vacuum pump, 92-Vacuum gauge, 001-Loading and unloading chamber, 002-Baking chamber, 003-First process chamber, 004-Second process chamber, 005-Transfer chamber, 051-Wafer robot. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0028] The technical solutions disclosed in the various embodiments of this application will be described in detail below with reference to Figures 1 to 11.

[0029] Please refer to Figures 1 to 5. This application discloses a semiconductor process chamber. The disclosed semiconductor process chamber is part of a semiconductor process apparatus and includes a chamber body 10, a shielding member 20, and a support device 30.

[0030] The chamber body 10 is the main structure of the semiconductor process chamber and the main structure that encloses some spaces of the semiconductor process chamber. At the same time, the chamber body 10 is also the mounting base for other components of the semiconductor process chamber. Other components of the semiconductor process chamber can be directly or indirectly mounted on the chamber body 10.

[0031] The shielding member 20 is a component that performs an isolation function. The shielding member 20 can be a thin plate-like structure, a disc-shaped structure, a polygonal structure, etc. The specific structure of the shielding member 20 is not limited in this application embodiment. In this application embodiment, the shielding member 20 is movably disposed within the cavity body 10, thereby enabling movement within the cavity body 10. Through movement within the cavity body 10, the shielding member 20 can switch between a first position and a second position.

[0032] In some embodiments of this application, the shielding member 20 can be rotatably disposed within the cavity body 10 to achieve switching between a first position and a second position. However, this is not limiting. In other embodiments of this application, the shielding member 20 can also be movably disposed within the cavity body 10 to achieve switching between a first position and a second position. The embodiments of this application do not limit the specific movement mode of the shielding member 20 within the cavity body 10.

[0033] The carrier device 30 is used to carry the wafer 40. The carrier device 30 is movably disposed within the chamber body 10, thereby enabling movement within the chamber body 10. Similarly, by moving within the chamber body 10, the carrier device 30 can switch between a third position and a fourth position. In this embodiment, the carrier device 30 is vertically and vertically disposed within the chamber body 10, thereby achieving switching between the third and fourth positions through vertical movement relative to the chamber body 10.

[0034] Since both the shielding member 20 and the supporting device 30 can move within the chamber body 10, the shielding member 20 and the supporting device 30 disclosed in this application embodiment have multiple ways of cooperating within the chamber body 10.

[0035] When the shielding member 20 is in the first position and the carrier device 30 is in the third position, the shielding member 20 is opposite to the carrier device 30, and the shielding member 20 can be located directly above the carrier device 30. The shielding member 20, the chamber body 10, and the carrier device 30 can form a pre-cleaning space 01. The pre-cleaning space 01 is the space where the pre-cleaning process takes place, used for pre-cleaning the wafer 40. The pre-cleaning process is essentially an etching process that can remove impurities such as oxide layers, nitride layers, and contaminants from the surface of the wafer 40, thereby enabling the wafer 40 to be coated more cleanly in subsequent coating processes, which is beneficial to improving the coating quality in subsequent coating processes. It should be noted that the shielding member 20 being opposite to the carrier device 30 means that the shielding member 20 will cover the carrier device 30. In other words, the projection of the shielding member 20 in the direction perpendicular to the carrier surface 321 of the carrier device 30 will coincide with the carrier device 30.

[0036] When the shielding member 20 is in the second position and the supporting device 30 is in the fourth position, the shielding member 20 and the supporting device 30 are staggered, and the supporting device 30 and the chamber body 10 enclose a coating space 02. The coating space 02 is the space where the coating process takes place, used for coating on the wafer 40. In the embodiments of this application, the coating process can be a chemical vapor deposition coating process or a physical vapor deposition coating process, such as a magnetron sputtering coating process. The embodiments of this application do not limit the specific type of coating process. It should be noted that the staggered distribution of the shielding member 20 and the supporting device 30 means that the shielding member 20 does not cover the supporting device 30. In other words, the projection of the shielding member 20 in the direction perpendicular to the supporting surface 321 of the supporting device 30 does not overlap with the supporting device 30.

[0037] The working process of the semiconductor process chamber disclosed in this application embodiment is as follows: The wafer 40 is transported into the chamber body 10. By controlling the shielding member 20 to be in the first position and the carrier device 30 to be in the third position, the shielding member 20, the chamber body 10 and the carrier device 30 form a pre-cleaning space 01, thereby performing pre-cleaning on the wafer 40 carried on the carrier device 30, thereby removing impurities such as oxides, nitrides and contaminants from the surface of the wafer 40. After the pre-cleaning process is completed, the shielding member 20 is controlled to be in the second position and the carrier device 30 is in the fourth position, thereby making the carrier device 30 and the chamber body 10 form a coating space 02, and then the wafer 40 on the carrier device 30 is subjected to a coating process.

[0038] As can be seen from the above working process, the semiconductor process chamber disclosed in this application, by adjusting the positions of the shielding member 20 and the carrier device 30, allows the shielding member 20 to be in the first position and the carrier device 30 to be in the third position. The shielding member 20 and the carrier device 30, together with the chamber body 10, form a pre-cleaning space 01, thereby enabling the pre-cleaning process. Simultaneously, by adjusting the positions of the shielding member 20 and the carrier device 30, the shielding member 20 can also be in the second position and the carrier device 30 in the fourth position. In this case, the shielding member 20 and the carrier device 30 are staggered, and the carrier device 30 and the chamber body 10 form a coating space 02. Therefore, the semiconductor process chamber disclosed in this application can form a pre-cleaning space 01 and a coating space 02, allowing the pre-cleaning process and the coating process to be performed sequentially within the same semiconductor process chamber. Compared to related technologies that require separate pre-cleaning and coating process chambers, leading to secondary oxidation, nitriding, and contamination of the wafer during transfer between them, the semiconductor process chamber disclosed in this application forms a pre-cleaning space 01 and a coating space 02 through spatial changes within the semiconductor process chamber. There are no traditional pre-cleaning and coating process chambers. Therefore, there is no need to transfer the wafer between the pre-cleaning and coating process chambers, thus avoiding contamination, oxidation, and nitriding caused by wafer transfer between them. This results in a cleaner wafer 40 before the coating process, which in turn improves the coating quality after the pre-cleaning process.

[0039] Meanwhile, since the semiconductor process chamber disclosed in this application can realize both the pre-cleaning process and the coating process, the semiconductor process equipment does not need to be configured with a single-function pre-cleaning process chamber and a coating process chamber. This allows for more coating processes to be performed with the same number of chambers, thereby increasing the coating capacity of the semiconductor process equipment.

[0040] When the semiconductor process chamber disclosed in this application forms a coating space 02, the coating process performed in the coating space 02 can be either a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process. When the coating process is a PVD process, the PVD process can be a magnetron sputtering deposition process. This application does not limit the specific type of PVD process.

[0041] When the coating process is a physical vapor deposition process, a target material 112 is placed in the semiconductor process chamber. When the target material 112 is replaced, a target blasting process is performed to remove the oxide layer, foreign matter, etc., from the surface of the target material 112. In this case, during the target blasting process, the shielding member 20 is transferred to the carrier device 30 to replace the wafer 40 in receiving the impurities removed during the target blasting process. At this time, the shielding member 20 and the chamber body 10 can form a target blasting process space, with the shielding member 20 facing the target material 112. When the coating process is a physical vapor deposition process, the semiconductor process chamber disclosed in this application can not only form a target blasting process space with the shielding member 20 and the chamber body 10, but also receive the impurities removed during the target blasting process. In addition, the shielding member 20 required for the target blasting process can be fully utilized to assist in forming a pre-cleaning space 01, thereby realizing the multi-purpose use of the shielding member 20 and achieving the purpose of simplifying the semiconductor process chamber structure.

[0042] It should be noted that when the pre-cleaning space 01 is formed, the shielding member 20 is located directly above the supporting device 30, but is spaced apart from the supporting device 30. The pre-cleaning space 01 is located between the shielding member 20 and the supporting device 30, and the shielding member 20 can be supported by the first support rod 51 mentioned later. When the target firing process space is formed, the shielding member 20 is also located directly above the supporting device 30, but the shielding member 20 is in contact with and directly supported by the supporting device 30. It can be considered that the two are in direct contact, not spaced apart. Specifically, in the optional embodiment mentioned later, the lifting and lowering of the supporting device 30 can realize the transfer of the shielding member 20 between the supporting device 30 and the first support rod 51. After the supporting device 30 receives the shielding member 20, it will also drive the shielding member 20 to rise to the first position, so that the shielding member 20 and the chamber body 10 form the target firing process space. Of course, at this time, the supporting device 30 is not located in the third position.

[0043] In one alternative design, the pre-cleaning space 01 and the coating space 02 are different subspaces within the chamber body 10. The pre-cleaning space 01 and the coating space 02 may not overlap, thus avoiding interference between the pre-cleaning process and the coating process. In other words, the component surfaces surrounding the pre-cleaning space 01 and the component surfaces surrounding the coating space 02 are different surfaces, and there will be no mutual interference due to byproducts formed on the component surfaces during the process.

[0044] As described above, there are various ways to achieve the movement of the shielding member 20. In one embodiment, the semiconductor process chamber disclosed in this application may further include a plurality of first support rods 51, which serve to support the shielding member 20. Specifically, the plurality of first support rods 51 are vertically and flexibly disposed within the chamber body 10.

[0045] The supporting device 30 is provided with a first clearance hole 301, which slides in cooperation with the plurality of first support rods 51. Specifically, there are multiple first clearance holes 301, each slidingly cooperating with a plurality of first support rods 51. The plurality of first support rods 51 are used to pass through the corresponding first clearance holes 301 to support the shielding member 20, and to move the shielding member 20 to or from the first position when supporting it. In this structure, the plurality of first support rods 51 adjust the position of the shielding member 20 by raising and lowering it when supporting it, which has the advantage of simple structure. At the same time, the first support rods 51 can pass through the supporting device 30 through the cooperation with the first clearance holes 301, so as not to affect the raising and lowering position adjustment of the supporting device 30. The plurality of first support rods 51 achieve multi-point support for the shielding member 20, ensuring stable support while allowing the use of thin rods, thereby avoiding the components that drive the position adjustment of the shielding member 20 from occupying a large space and affecting the size of the pre-cleaning space 01. In a more specific example, multiple first clearance holes 301 and multiple first struts 51 can slide in a one-to-one correspondence.

[0046] As described above, the carrier device 30 is used not only to form the pre-cleaning space 01 in the third position, but also to form the coating space 02 in the fourth position. When the carrier device 30 has multiple first clearance holes 301, in order to prevent impurities removed during the pre-cleaning process or particles to be deposited during the coating process from contaminating other spaces outside the pre-cleaning space 01 or coating space 02 through the first clearance holes 301, in one solution, the carrier device 30 may also include multiple extension cylinders 31. The multiple extension cylinders 31 are respectively disposed at the openings of the first clearance holes 301 facing away from the bearing surface 321 of the carrier device 30, and the cylinder cavities of the extension cylinders 31 communicate with the corresponding first clearance holes 301. Each first support rod 51 passes sequentially through the corresponding extension cylinder 31 and the first clearance hole 301, and slides in cooperation with the corresponding extension cylinder 31 and the first clearance hole 301.

[0047] In this embodiment, the extension tube 31 can further slide and engage with the corresponding first support rod 51, improving the stability of the sliding of the first support rod 51 without affecting its lifting and lowering. Simultaneously, the extension tube 31 essentially extends the length of the corresponding first clearance hole 301, resulting in a longer new hole structure formed by the connection between the first clearance hole 301 and the cavity of the extension tube 31. This has a larger depth-to-width ratio, mitigating the problem of impurities removed during the pre-cleaning process or particles to be deposited during the coating process contaminating other spaces outside the pre-cleaning space 01 or coating space 02 through the first clearance hole 301. This, in turn, can prevent contamination of other spaces in the semiconductor process chamber connected to the pre-cleaning space 01 or coating space 02 through the first clearance hole 301 to a certain extent. Specifically, the depth-to-width ratio of the hole structure formed by the connection between the first clearance hole 301 and the cavity of the extension tube 31 should be greater than 1:1.

[0048] In one embodiment, the opening of the bearing surface 321 of the bearing device 30 facing away from each first clearance hole 301 can be connected to an extension tube 31. Of course, in other embodiments, the opening of the bearing surface 321 of the bearing device 30 facing away from each first clearance hole 301 can be connected to multiple extension tubes 31 in sequence, thereby extending the length of the first clearance hole 301 to a greater extent.

[0049] In this embodiment, the extension tube 31 can be fixed to the opening of the corresponding first clearance hole 301 by welding, bonding, snap-fitting, etc. This embodiment does not limit the specific connection method between the extension tube 31 and the opening of the first clearance hole 301.

[0050] It should be noted that the bearing surface 321 of the carrier device 30 is the area where the carrier device 30 directly supports the wafer 40. When the carrier device 30 and other corresponding components of the semiconductor process chamber enclose a pre-cleaning space 01, the bearing surface 321 faces the pre-cleaning space 01. When the carrier device 30 and other corresponding components of the semiconductor process chamber enclose a coating space 02, the bearing surface 321 faces the coating space 02.

[0051] In this embodiment, the carrier device 30 may further include a carrier body 32 and a deposition ring 33. The carrier body 32 is the main body of the carrier device 30 and has the aforementioned carrier surface 321. The deposition ring 33 is connected to the carrier body 32 and is distributed around the carrier surface 321. The plurality of first clearance holes 301 may be formed on the deposition ring 33 and are spaced apart along the circumferential direction of the deposition ring 33. The deposition ring 33 can play a shielding role, preventing deposits from being deposited on the carrier body 32 and contaminating the carrier body 32. Of course, the deposition ring 33 can also prevent the carrier body 32 from being directly etched during the pre-cleaning process, which could easily damage the carrier body 32. Specifically, the deposition ring 33 cooperates with the wafer 40 placed on the carrier surface 321 to achieve full coverage of the carrier body 32. More specifically, the plurality of first clearance holes 301 may be evenly distributed, for example, the plurality of first clearance holes 301 may be evenly arranged on the deposition ring 33 along the circumferential direction of the deposition ring 33. The deposition ring 33 is detachably connected to the support body 32, which facilitates the periodic replacement or cleaning of the deposition ring 33. For example, the deposition ring 33 overlaps the edge of the support body 32.

[0052] The carrier body 32 has an annular concave surface surrounding the carrier surface 321. The deposition ring 33 covers the annular concave surface and overlaps with it, thereby achieving installation on the carrier body 32. Of course, the deposition ring 33 and the carrier body 32 can also be assembled in other ways, and the embodiments of this application do not limit their specific assembly methods.

[0053] In this embodiment, the plurality of first clearance holes 301 can be formed on the carrier body 32 or in the deposition ring 33, and this embodiment does not impose any limitation. In this embodiment, the carrier device 30 not only carries the wafer 40, but also involves other functions, such as cooling and connecting to a bias power supply (e.g., the third power supply 1183 mentioned later). When the carrier device 30 is an electrostatic carrier device, it also has an electrostatic adsorption structure, etc. When the carrier device 30 includes a carrier body 32, these additional functional structures are designed on the carrier body 32, while the structure of the deposition ring 33 is relatively simple. Therefore, in order to avoid the impact of the openings on the more functional parts of the carrier device 30 and to reduce the difficulty of opening the openings, it is recommended that the plurality of first clearance holes 301 be formed on the deposition ring 33.

[0054] Since the deposition ring 33 has relatively few functions, it does not need to be designed to be thick. In the embodiment where multiple first clearance holes 301 are formed in the deposition ring 33, the depth of the first clearance holes 301 is small, which makes it easier for impurities cleaned up by the pre-cleaning process or particles to be deposited by the coating process to pass through the first clearance holes 301 and contaminate other spaces outside the pre-cleaning space 01 or coating space 02. Therefore, the multiple extension tubes 31 mentioned above are more targeted when set on the deposition ring 33.

[0055] It should be emphasized that, regardless of the location of the first clearance hole 301 in the support device 30, and regardless of the length of the first clearance hole 301, the addition of the extension tube 31 can prevent impurities cleaned up by the pre-cleaning process or particles to be deposited by the coating process from passing through the first clearance hole 301 and contaminating other spaces outside the pre-cleaning space 01 or the coating space 02.

[0056] As described above, the carrier body 32 has multiple functions. In one example, the carrier body 32 may include a cooling layer and a heating layer and an electrostatic adsorption layer stacked sequentially on the cooling layer. Of course, in other embodiments, when the carrier device 30 is a non-electrostatic adsorption structure, the carrier body 32 may not include the electrostatic adsorption layer, and may be replaced by other structures capable of fixing the wafer 40.

[0057] As described above, when supporting the wafer 40, the multiple first support rods 51 can move the wafer 40 to change position by lifting and lowering it. To improve the stability of the support, in one embodiment, the shielding member 20 can be provided with multiple positioning slots 22, which are used to position and insert into the support ends of the multiple first support rods 51 one by one. This structure can prevent the wafer 40 from shifting laterally during lifting and lowering, ensuring the stability of the wafer 40's position during movement.

[0058] In a further embodiment, a plurality of positioning grooves 22 are evenly distributed on the shielding member 20. For example, there are three positioning grooves 22, which are distributed on the shielding member 20 at an angle of 120°. Of course, correspondingly, there can be three first support rods 51, which are positioned and engaged with the positioning grooves 22 one by one.

[0059] In this application embodiment, the positioning groove 22 can have various structures. In order to make it easier for the first support rod 51 to be inserted, in a more specific embodiment, the positioning groove 22 can be a conical structure, so that the opening of the positioning groove 22 is larger, which is conducive to the insertion of the first support rod 51.

[0060] In this embodiment, the shielding member 20 is used to enclose the pre-cleaning space 01, while the coating space 02 does not require the shielding member 20 to enclose it. When the shielding member 20 is in the second position and the supporting device 30 is in the fourth position, the shielding member 20 can be positioned in a position that does not affect the coating process. To store the shielding member 20, the semiconductor process chamber disclosed in this embodiment may further include a storage section 61, which is movably disposed in the chamber body 10 and can move relative to the chamber body 10. The storage section 61 switches between an intersection position and a clearance position through its movement relative to the chamber body 10.

[0061] When the storage section 61 is in the handover position, the storage section 61 is above the support device 30. The storage section 61 is used to receive the shield 20 when the first support rod 51 descends or to hand over the shield 20 when the first support rod 51 rises.

[0062] When the storage section 61 is in the avoidance position, it is offset from the support device 30, thereby avoiding interference with the wafer 40 on the support device 30 for coating. It should be noted that, in this embodiment, the offset distribution of the storage section 61 from the support device 30 means that the storage section 61 is not directly above the support surface 321 of the support device 30, or in other words, the projection of the storage section 61 in the direction perpendicular to the support surface 321 does not overlap with the support device 30.

[0063] When the shielding member 20 is in the second position, the shielding member 20 is supported on the storage part 61 in the avoidance position, and is also offset from the support device 30, so that the shielding member 20 is not directly above the support surface 321 of the support device 30.

[0064] The storage unit 61 can not only store the shielding member 20 when it is not needed, but also change the position of the shielding member 20 by its own movement so that the shielding member 20 does not affect the coating process carried out in the coating space 02.

[0065] As described above, the shielding member 20 is received by the storage portion 61 and stored on the storage portion 61. In one embodiment, the shielding member 20 can make surface-to-surface contact with the storage portion 61 to achieve a supporting fit. In other embodiments, the shielding member 20 or the storage portion 61 may include multiple support protrusions 21. When the shielding member 20 is supported on the storage portion 61, the storage portion 61 can contact the shielding member 20 through the multiple support protrusions 21. In this structure, the shielding member 20 and the storage portion 61 achieve point-to-surface contact, thereby avoiding contamination of the shielding member 20 by foreign objects that may exist on the storage portion 61 due to the large contact area between the shielding member 20 and the storage portion 61.

[0066] In a preferred embodiment, multiple support protrusions 21 are provided on the shielding member 20. As mentioned above, in the target firing process, the shielding member 20 is supported on the supporting device 30. In embodiments where the shielding member 20 includes multiple support protrusions 21, the shielding member 20 can also be supported on the supporting device 30 through the multiple support protrusions 21, thereby achieving point-to-surface contact with the supporting device 30. This can alleviate the contamination of the supporting device 30 by foreign objects that may be present on the shielding member 20.

[0067] To reduce stress, the support protrusion 21 can be a hemispherical protrusion, or it can be a protrusion of other shapes. This application embodiment does not limit the specific shape.

[0068] The storage unit 61 disclosed in this application supports the shielding member 20, which is stored on the storage unit 61 under its own gravity. The storage unit 61 achieves the transfer of the shielding member 20 by raising and lowering the first support rod 51, offering advantages such as simple structure and easy transfer. As described above, the storage unit 61 is movably disposed within the chamber body 10. Specifically, the storage unit 61 can move within the chamber body 10, thereby switching between a transfer position and a clearance position. In embodiments where the shielding member 20 is stored on the storage unit 61 under its own gravity, the storage unit 61 can switch positions by horizontal movement, vertical raising and lowering, or a combination of horizontal and vertical movement.

[0069] In other embodiments, the storage unit 61 can also support the shielding member 20 through vacuum adsorption or clamping, and drive the shielding member 20 to move and switch positions. In this case, the storage unit 61 can be firmly grasped, thereby enabling movement. Specifically, the storage unit 61 can rotate or move to drive the shielding member 20, thereby adjusting the position of the shielding member 20 and the storage unit 61. The embodiments of this application do not limit the specific movement mode of the storage unit 61 and the shielding member 20.

[0070] In one embodiment, the semiconductor process chamber disclosed in this application may further include a rotation drive mechanism 62. The rotation drive mechanism 62 is at least partially disposed within the chamber body 10 and connected to the storage section 61. The rotation drive mechanism 62 drives the storage section 61 to move by rotation, thereby enabling the storage section 61 to switch between the intersection position and the avoidance position.

[0071] The semiconductor process chamber disclosed in this application embodiment may further include a plurality of second support rods 52, which may be disposed within the chamber body 10. The carrier device 30 is provided with second clearance holes 302 that slidably engage with the plurality of second support rods 52. The carrier device 30 is vertically and elliptically disposed within the chamber body 10. The carrier device 30 is used to transfer the wafer 40 between the carrier device 30 and the plurality of second support rods 52 through lifting and lowering; that is, to transfer the wafer 40 from the plurality of second support rods 52 to the carrier device 30 or to transfer the wafer 40 from the carrier device 30 to the plurality of second support rods 52. In a more specific example, the plurality of second support rods 52 and the second clearance holes 302 are matched one-to-one.

[0072] Specifically, when the end faces of the supporting ends of the multiple second support rods 52 protrude beyond the bearing surface 321 of the carrier device 30, the wafer 40 transferred to the semiconductor process chamber can be supported by the multiple second support rods 52; when the end faces of the supporting ends of the multiple second support rods 52 do not protrude (i.e., are not higher than) the bearing surface 321 of the carrier device 30, the supporting ends of the multiple second support rods 52 are recessed into or flush with the bearing surface 321 (i.e., coplanar), and the wafer 40 can be supported by the bearing surface 321. In the actual operation, the raising and lowering of the carrier device 30 can change the positional relationship between the end faces of the supporting ends of the second support rods 52 and the bearing surface 321, thereby realizing the transfer of the wafer 40.

[0073] In a more specific embodiment, the semiconductor process chamber disclosed in this application may further include a strut base 53. The strut base 53 is vertically and flexibly disposed within the chamber body 10. The plurality of first struts 51 and the plurality of second struts 52 described above can all be fixed to the strut base 53 and can move synchronously up and down within the chamber body 10 along with the strut base 53. It should be noted that the connecting ends of the plurality of first struts 51 and the connecting ends of the plurality of second struts 52 are fixed to the strut base 53. The connecting ends and supporting ends of the first struts 51 are opposite ends of the first struts 51. Similarly, the connecting ends and supporting ends of the second struts 52 are opposite ends of the second struts 52.

[0074] The supporting end of the first support rod 51 is higher than the supporting end of the second support rod 52, so that when the shielding member 20 is raised to the first position and the supporting device 30 is raised to the third position, the end face of the supporting end of the second support rod 52 is not higher than the supporting surface 321 of the supporting device 30. In this case, the wafer 40 supported on the supporting surface 321 can be coated in the formed coating space 02 without being suspended above the supporting surface 321, ensuring the stability of the wafer 40 during the coating process. It should be noted that "the supporting end of the first support rod 51 is higher than the supporting end of the second support rod 52" means that the end face of the supporting end of the first support rod 51 is higher than the end face of the supporting end of the second support rod 52.

[0075] In this embodiment, the first support rod 51 and the second support rod 52 are fixed to the support rod seat 53, so that the first support rod 51 and the second support rod 52 share the support rod seat 53. This facilitates the sharing of the same set of drive mechanisms for driving the support rod seat 53 to rise and fall. The shared drive mechanism for the rising and falling of the first support rod 51 and the second support rod 52 can reduce the number of drive mechanisms that need to be installed in the semiconductor process chamber, thereby simplifying the semiconductor process chamber and avoiding the problem of complex design due to the need for a large number of drive mechanisms.

[0076] As described above, the support device 30 can move up and down within the chamber body 10. Based on this, the semiconductor process chamber disclosed in this application embodiment may include a first lifting mechanism 70. The first lifting mechanism 70 is connected to the support device 30 and is used to drive the support device 30 to move up and down within the chamber body 10. The first lifting mechanism 70 may be a lead screw drive mechanism, a linear motor, a hydraulic telescopic drive mechanism, or a pneumatic telescopic drive mechanism. This application embodiment does not limit the specific type of the first lifting mechanism 70.

[0077] In one embodiment, the first lifting mechanism 70 may include a first lifting shaft 71 and a first bellows 72. A first end of the first lifting shaft 71 is connected to the supporting device 30. A second end of the first lifting shaft 71 extends outside the chamber body 10. Specifically, the chamber body 10 may have a first through hole, through which the second end of the first lifting shaft 71 extends outside the chamber body 10. The first bellows 72 is located inside the chamber body 10 and is fitted around the first lifting shaft 71.

[0078] The first port of the first bellows 72 is sealed to the support device 30, and the second port of the first bellows 72 is sealed to the inner wall of the chamber body 10. Specifically, the edge of the second port of the first bellows 72 is arranged around the first perforation and sealed to the area where the first perforation is located, thereby enabling the first bellows 72 to communicate with the external environment of the chamber body 10 and isolate it from other areas within the chamber body 10, thus ensuring the preset environment within the chamber body 10, such as a vacuum environment. The first lifting shaft 71 (driven by a power source located outside the chamber body 10) moves up and down, driving the support device 30 to move up and down, achieving the purpose of driving the support device 30 to move up and down. At the same time, the first bellows 72 will extend and retract with the movement of the first lifting shaft 71, adapting to the movement of the first lifting shaft 71 while ensuring the stability of the sealed connection at all times.

[0079] In this embodiment, multiple first support rods 51 and multiple second support rods 52 can be distributed around the first bellows 72. The support rod seat 53 can be provided with a clearance space for the first bellows 72 to pass through. In this case, the first lifting shaft 71 and the first bellows 72 are located in the clearance space, so that the lifting drive of the first lifting mechanism 70 on the bearing device 30 is not interfered with by the support rod seat 53. The clearance space can be a clearance hole or a clearance notch. This embodiment does not limit the specific shape of the clearance space.

[0080] As described above, the strut seat 53 is also vertically mounted within the chamber body 10. Based on this, the semiconductor process chamber disclosed in this application embodiment may further include a second lifting mechanism 80. The second lifting mechanism 80 is connected to the strut seat 53 and is used to drive the strut seat 53 to synchronously lift the first strut 51 and the second strut 52. Similarly, the second lifting mechanism 80 may be a lead screw drive mechanism, a linear motor, a hydraulic telescopic drive mechanism, a pneumatic telescopic drive mechanism, etc. This application embodiment does not limit the specific type of the second lifting mechanism 80.

[0081] In one embodiment, the second lifting mechanism 80 may include a second lifting shaft 81 and a second bellows 82. The first end of the second lifting shaft 81 is connected to the strut seat 53. The second end of the second lifting shaft 81 extends outside the chamber body 10. Specifically, the chamber body 10 may have a second through hole, through which the second end of the second lifting shaft 81 can extend outside the chamber body 10. The second bellows 82 is located inside the chamber body 10 and is fitted around the second lifting shaft 81.

[0082] The first port of the second bellows 82 is sealed to the strut seat 53, and the second port of the second bellows 82 is sealed to the inner wall of the chamber body 10. Specifically, the edge of the second port of the second bellows 82 is arranged around the second perforation and sealed to the area where the second perforation is located, thereby enabling the second bellows 82 to communicate with the external environment of the chamber body 10 and isolate it from other areas within the chamber body 10, thus ensuring the preset environment within the chamber body 10, such as a vacuum environment. The second lifting shaft 81 (driven by a power source located outside the chamber body 10 for the second lifting mechanism 80) moves up and down, driving the strut seat 53 to move up and down, achieving the purpose of driving the strut seat 53 to move up and down. At the same time, the second bellows 82 will extend and retract with the movement of the second lifting shaft 81, adapting to the movement of the second lifting shaft 81 while ensuring the stability of the sealed connection at all times.

[0083] It should be noted that in other embodiments of this application, the first support rod 51 and the second support rod 52 can also be set independently and do not share the support rod base 53. The semiconductor process chamber can be equipped with corresponding driving devices for the first support rod 51 and the second support rod 52 respectively. The driving device configured independently for the first support rod 51 can drive the first support rod 51 to rise and fall independently, and the driving device configured independently for the second support rod 52 can drive the second support rod 52 to rise and fall independently. This scheme can achieve independent driving, and it is only necessary to control the moving distance of the first support rod 51 or the second support rod 52 driven by the corresponding driving device. The height of the supporting end of the first support rod 51 and the supporting end of the second support rod 52 can be flexibly adjusted.

[0084] In this embodiment, when the shielding member 20 is in the second position and the supporting device 30 is in the fourth position to form a coating space 02, the shielding member 20 can be located within the coating space 02, as long as it does not affect the coating process of depositing the wafer 40 on the supporting device 30. However, this would also result in coating on the shielding member 20, which is undesirable. Moreover, the shielding member 20 being located within the coating space 02 makes it easier to affect the process environment within the coating space 02. Therefore, in one embodiment, when the shielding member 20 is in the second position and the supporting device 30 is in the fourth position, the shielding member 20 can be located outside the coating space 02.

[0085] In this embodiment, the chamber body 10 may be provided with a wafer transfer hole 1191. The wafer transfer hole 1191 is used to allow the wafer 40 to pass through when transferring the wafer 40, so that the wafer 40 can enter and exit the chamber body 10. Specifically, as described below, in an embodiment where the chamber body 10 includes a shell body 119, the wafer transfer hole 1191 may be formed on the shell body 119.

[0086] To better understand the formation process of the pre-cleaning space 01 and the coating space 02, the following detailed description uses the partial structures shown in Figures 1 to 5 as a specific embodiment.

[0087] As shown in Figure 1, the support device 30, the first support rod 51, the second support rod 52, and the support rod seat 53 are all in a lower position (i.e., the initial position) in the chamber body 10. The second support rod 52 passes through the corresponding second clearance hole 302 and protrudes from the support surface 321 of the support device 30. The wafer 40 is transferred into the chamber body 10 by the wafer robot 051 and handed over to the second support rod 52 in the state shown in Figure 1, so that the wafer 40 is supported by the second support rod 52.

[0088] As shown in Figure 2, the carrier device 30 then rises under the drive of the first lifting mechanism 70, thereby completing the transfer of the wafer 40 from the second support rod 52 to the carrier device 30. The storage part 61 (which can be driven by the rotation drive mechanism 62) moves from the clearance position to the transfer position, thereby moving the shielding member 20 above the carrier device 30. Referring to Figure 3, the support rod seat 53 then drives the first support rod 51 to rise, causing the storage part 61 to hand over the shielding member 20. After handing over the shielding member 20, the storage part 61 returns to the clearance position. In addition, the carrier device 30 also rises, eventually causing the shielding member 20 to rise to the first position and the carrier device 30 to rise to the third position. This allows the shielding member 20, the chamber body 10, and the carrier device 30 to form a pre-cleaning space 01. The wafer 40, which is carried on the support surface 321 of the carrier device 30, is then in the pre-cleaning space 01, thus preparing for the pre-cleaning process in the pre-cleaning space 01.

[0089] During the process of the strut seat 53 driving the first strut 51 to rise, the second strut 52 will also rise, and the bearing device 30 will also rise. Moreover, the height of the support end of the second strut 52 is lower than the height of the first strut 51. Ultimately, during the process of forming the pre-cleaning space 01, the end face of the support end of the second strut 52 will never be higher than the bearing surface 321, ensuring that the wafer 40 is stably supported by the bearing surface 321.

[0090] After the pre-cleaning process is completed, the strut base 53 drives the first strut 51 and the second strut 52 to descend. Simultaneously, the supporting device 30 also descends, and the storage section 61 moves to the junction position. As the strut base 53 descends, it receives the shielding member 20. After receiving the shielding member 20, the storage section 61 moves to a clearance position, where the shielding member 20 is stored on the storage section 61 in the clearance position. At this point, the shielding member 20 is in the second position. The descent of the supporting device 30 is to clear the storage section 61, ensuring that the storage section 61 can move to the junction position. After the shielding member 20 is received, the supporting device 30 continues to rise, moving to the fourth position. Since the shielding member 20 is already in the second position, when the supporting device 30 moves to the fourth position, it achieves the purpose of the supporting device 30 and the chamber body 10 forming the coating space 02, thus completing part of the preparatory work for the coating process.

[0091] After the coating process is completed, the carrier device 30 lowers the wafer 40. At this time, the support rod seat 53 has lowered the first support rod 51 and the second support rod 52 to their initial positions. The continued descent of the carrier device 30 will cause the supporting end of the second support rod 52 to pass through the second clearance hole 302 again and protrude from the carrier surface 321, thus completing the transfer of the wafer 40 from the carrier surface 321 to the second support rod 52. The wafer robot 051 will extend into the chamber body 10 through the wafer transfer hole 1191 and pick up the wafer 40 supported on the second support rod 52. The above process can be repeated when pre-cleaning and coating the next wafer 40.

[0092] Here, the applicant needs to emphasize that the above-described working process is merely an example of the embodiment illustrated in the accompanying drawings to explain the formation of the pre-cleaning space 01 and the coating space 02. This is based on the premise that the first support rod 51 and the second support rod 52 share the support rod seat 53, and that the storage part 61 moves, among other specific structures. In other embodiments, the formation of the pre-cleaning space 01 and the coating space 02 depends on the structural design of other embodiments and is not limited to the above-described movement process.

[0093] In this embodiment, the chamber body 10 is also used to cooperate with other components of the semiconductor process chamber to form a pre-cleaning space 01 or a coating space 02. The structure of the chamber body 10 can be varied, and the specific structure of the chamber body 10 is not limited in this embodiment.

[0094] As the peripheral structure of the semiconductor process chamber, the chamber body 10 disclosed in this application embodiment includes at least a chamber shell 11. In this case, the chamber shell 11 can form a pre-cleaning space 01 with the shielding member 20 and the carrier device 30, and the chamber shell 11 can also form a coating space 02 with the carrier device 30.

[0095] During the pre-cleaning or coating process, the inner wall of the chamber shell 11 is easily contaminated, and the chamber shell 11 is difficult to clean. Therefore, in a more specific embodiment, the chamber body 10 disclosed in this application may further include a top liner 12, which is disposed within the chamber shell 11. The top liner 12 has a cylindrical structure and is used to cover part of the inner wall of the chamber shell 11 to form the coating space 02 or the pre-cleaning space 01. The top liner 12 can provide targeted protection for part of the inner wall of the chamber shell 11, avoiding contamination of the chamber shell 11 during the pre-cleaning or coating process.

[0096] When the shielding member 20 is in the first position and the carrier device 30 is in the third position, at least the shielding member 20, the chamber housing 11, the top liner 12, and the carrier device 30 enclose a pre-cleaning space 01. Simultaneously, the top liner 12, the shielding member 20, and the chamber housing 11 also enclose an upper space 03. The upper space 03 is located above the pre-cleaning space 01 and is isolated from it, thereby allowing the semiconductor process chamber to partially enclose the pre-cleaning space 01, while the upper space 03 is isolated from the pre-cleaning space 01, thus preventing the pre-cleaning process from affecting a large area and causing unnecessary adverse effects. When the coating process is a physical vapor deposition process, the target material 112 can be formed in the upper space 03. This formation of an upper space 03 isolated from the pre-cleaning space 01 can prevent etching of the target material 112 during the pre-cleaning process.

[0097] When the shielding member 20 is in the second position and the supporting device 30 is in the fourth position, the shielding member 20, the top liner 12 and the chamber shell 11 form a coating space 02.

[0098] In this embodiment, the top liner 12 not only protects a portion of the chamber shell 11, but also works in conjunction with other components to form a pre-cleaning space 01 or a coating space 02, achieving a multi-purpose effect.

[0099] In this embodiment, one of the shielding member 20 and the top liner 12 may include a first annular protrusion 1221, and the other may be provided with a first annular groove 23. When the shielding member 20 is in the first position and the supporting device 30 is in the third position, the first annular protrusion 1221 extends into the first annular groove 23 and forms a first sealing and isolation structure with the first annular groove 23. This allows the mating point between the shielding member 20 and the top liner 12 to have a better isolation effect, preventing the pre-cleaning process gas (i.e., the first process gas) or byproducts generated by the pre-cleaning process from overflowing from the mating point between the shielding member 20 and the top liner 12 during the pre-cleaning process in the pre-cleaning space 01. This effectively prevents adverse effects on other areas outside the pre-cleaning space 01.

[0100] In one embodiment, the top liner 12 may include a first annular protrusion 1221, and the shielding member 20 may have a first annular groove 23, as shown in FIG4. In another embodiment, the top liner 12 may have a first annular groove 23, and correspondingly, the shielding member 20 may include the first annular protrusion 1221.

[0101] The semiconductor process chamber disclosed in this application embodiment may further include a shielding ring 13. The shielding ring 13 is disposed around the support device 30 and covers the edge of the support device to move up and down with the support device 30. One of the shielding ring 13 and the top liner 12 may include a second annular protrusion 131, and the other may have a second annular groove 1222. When the shielding member 20 is in the second position and the support device 30 is in the fourth position, the second annular protrusion 131 extends into the second annular groove 1222 and forms a second labyrinth isolation structure with the second annular groove 1222. This embodiment improves the structure of the shielding ring 13 so that the shielding ring 13 can form a second labyrinth isolation structure with the top liner 12 when the coating space 02 is formed in the semiconductor process chamber. The second labyrinth isolation structure ensures that when the shielding member 20, the top liner 12, and the chamber shell 11 enclose the coating space 02, the shielding ring 13 can form a second labyrinth isolation structure at the mating point with the top liner 12. This prevents deposits from overflowing from the mating point between the shielding ring 13 and the top liner 12 during the coating process in the coating space 02, thereby preventing adverse effects on other areas outside the coating space 02.

[0102] Referring to Figure 5, in one embodiment, the cover ring 13 includes a second annular protrusion 131, and the top liner 12 is provided with a second annular groove 1222. In another embodiment, the cover ring 13 may be provided with a second annular groove 1222, and correspondingly, the top liner 12 may include a second annular protrusion 131. In this embodiment, and in a further embodiment where the top liner 12 is provided with both a first annular groove 23 and a second annular groove 1222, the second annular groove 1222 may be the same annular groove as the first annular groove 23. This structure simplifies the structure of the top liner 12.

[0103] In this application embodiment, the top liner 12 can have various structures. In one embodiment, the top liner 12 may include a first cylindrical body 1223 and a first annular protrusion 1221. The first cylindrical body 1223 is the part of the top liner 12 used to protect the chamber shell 11. Specifically, the first cylindrical body 1223 is disposed inside the chamber shell 11 to cover part of the inner wall of the chamber shell 11, thereby achieving the purpose of protection. The first annular protrusion 1221 is disposed on the inner wall of the first cylindrical body 1223 and extends around the central axis of the first cylindrical body 1223. The first annular protrusion 1221 and the first cylindrical body 1223 can form a second annular groove 1222. In the top liner 12 of this structure, the first annular protrusion 1221 can not only form a first labyrinth isolation structure with the first annular groove 23, but also cooperate with the first cylindrical body 1223 to form a second annular groove 1222. This allows the top liner 12 to form the first annular protrusion 1221 and the second annular groove 1222 with fewer components, which helps to simplify the structure of the top liner 12.

[0104] As described above, the top liner 12 can have various structures. For example, in one embodiment, the top liner 12 is an integral cylindrical component. In other embodiments, as shown in Figures 1 to 5, the top liner 12 may include a first sub-liner 121 and a second sub-liner 122, with adjacent ends of the first sub-liner 121 and the second sub-liner 122 nested together. The first sub-liner 121 and the second sub-liner 122 may be distributed vertically, and the second sub-liner 122 may include a first cylindrical body 1223 and a first annular protrusion 1221. The first sub-liner 121 and the second sub-liner 122 can be detachably installed within the chamber shell 11 in various ways. This application does not limit the installation method of the first sub-liner 121 and the second sub-liner 122 within the chamber shell 11. As shown in Figure 1, both the first sub-liner 121 and the second sub-liner 122 may include overlapping flanges, and the first sub-liner 121 and the second sub-liner 122 can overlap the protrusions or support surfaces of the inner wall of the chamber shell 11 through their respective overlapping flanges. This method allows for the installation of the first sub-liner 121 and the second sub-liner 122, while also facilitating the removal and cleaning of the first sub-liner 121 and the second sub-liner 122 by operators.

[0105] In this embodiment, the chamber outer shell 11 may have a first air inlet 1111, and the nested portion of the first sub-liner 121 and the second sub-liner 122 may form an annular first air inlet channel 17, with the first air inlet 1111 communicating with the first air inlet channel 17. When the semiconductor process chamber forms the coating space 02, the first air inlet 1111 communicates with the coating space 02 through the first air inlet channel 17, as shown in FIG. 5. In this case, the first air inlet 1111 is used to introduce the second process gas used in the coating process into the coating space 02 through the first air inlet channel 17.

[0106] The chamber outer shell 11 may have a second air inlet 1113, and an annular second air inlet channel 18 may be formed between the second sub-liner 122 and the chamber outer shell 11. The second air inlet 1113 communicates with the second air inlet channel 18. When the semiconductor process chamber forms a pre-cleaning space 01, the second air inlet 1113 communicates with the pre-cleaning space 01 through the second air inlet channel 18, as shown in Figure 4. In this case, the first air inlet 1111 is used to introduce the first process gas used in the pre-cleaning process into the pre-cleaning space 01 through the second air inlet channel 18.

[0107] The semiconductor process chamber disclosed in this application may further include a bottom liner 14, which is disposed within the chamber housing 11 to protect part of the inner wall of the chamber housing 11. The bottom liner 14 can be detachably installed within the chamber housing 11 in various ways, and this application does not limit the specific connection method between the bottom liner 14 and the chamber housing 11. Optionally, the bottom liner 14 may have an overlapping flange, and the inner wall of the chamber housing 11 corresponding to the bottom liner 14 may have a protrusion or a support surface. The bottom liner 14 can be installed within the chamber housing 11 by overlapping the flange and engaging with the protrusion or support surface. This method allows the bottom liner 14 to be installed within the chamber housing 11 while also facilitating removal by operators for cleaning.

[0108] In an embodiment where the semiconductor process chamber includes a bottom liner 14, when the shielding member 20 is in a first position and the carrier 30 is in a third position, the carrier 30, the shielding ring 13, the bottom liner 14, the chamber housing 11, the top liner 12, and the shielding member 20 form a pre-cleaning space 01.

[0109] In a further embodiment, one of the bottom liner 14 and the cover ring 13 may include a third annular protrusion 141, and the other may have a third annular groove 132. When the shielding member 20 is in the first position and the supporting device 30 is in the third position, the third annular protrusion 141 may be disposed in the third annular groove 132, forming a third labyrinth isolation structure with the third annular groove 132. This structure enables the semiconductor process to have a better isolation effect at the mating point of the bottom liner 14 and the cover ring 13 when forming the pre-cleaning space 01, preventing the pre-cleaning process gas (i.e., the first process gas) or byproducts generated by the pre-cleaning process from overflowing from the mating point of the bottom liner 14 and the cover ring 13 during the pre-cleaning process in the pre-cleaning space 01, thereby better preventing adverse effects on other areas outside the pre-cleaning space 01.

[0110] Similarly, in one embodiment, the bottom liner 14 includes a third annular protrusion 141, and correspondingly, the cover ring 13 has a third annular groove 132. In another embodiment, the bottom liner 14 has a third annular groove 132, and correspondingly, the cover ring 13 includes a third annular protrusion 141. In the embodiment where the cover ring 13 has a third annular groove 132 and includes a second annular protrusion 131, the third annular groove 132 and the third annular protrusion 141 are respectively distributed on opposite sides of the cover ring 13.

[0111] During the pre-cleaning process, the first process gas needs to be ionized into plasma. Therefore, in this embodiment, a first radio frequency coil 15 is embedded in the portion of the chamber shell 11 that encloses the pre-cleaning space 01. The first radio frequency coil 15 is distributed around the pre-cleaning space 01, thereby ionizing the first process gas in the pre-cleaning space 01 into plasma to etch and remove impurities such as oxide layers from the surface of the wafer 40.

[0112] As described above, in the embodiment of the chamber body 10 disclosed in this application, which includes a top liner 12 and a bottom liner 14, the top liner 12 and the bottom liner 14 can be spaced apart to form an annular gap 16, with the first radio frequency coil 15 opposite to the annular gap 16. In this case, the radio frequency power of the first radio frequency coil 15 can be unobstructed by the top liner 12 or the bottom liner 14, thereby enabling more efficient coupling into the pre-cleaning space 01, ultimately improving the pre-cleaning effect.

[0113] The chamber housing 11 disclosed in this application embodiment may include an insulating cylinder 1142. The insulating cylinder 1142 may be disposed around the pre-cleaning space 01, and the first radio frequency coil 15 may be disposed around the insulating cylinder 1142. The inner wall surface of the insulating cylinder 1142 is used to form part of the inner wall of the chamber housing 11, and can directly participate in forming the pre-cleaning space 01. The insulating cylinder 1142 can receive by-products formed during the etching process during the pre-cleaning process. The insulating cylinder 1142 is detachable and installable, thereby facilitating periodic removal for cleaning.

[0114] The insulating cylinder 1142 is made of insulating material. For example, the insulating cylinder 1142 can be a ceramic cylinder made of ceramic material. The embodiments of this application do not limit the specific material of the insulating cylinder 1142.

[0115] In one embodiment, the inner wall surface of the insulating cylinder 1142 can be a regular cylindrical surface. In other embodiments, to enhance the ability of the insulating cylinder 1142 to collect by-products and reduce cleaning frequency, the inner wall surface of the insulating cylinder 1142 can be a convex-concave surface. The convex-concave surface increases the area of ​​the inner wall surface of the insulating cylinder 1142, allowing it to collect more impurities without frequent disassembly and cleaning. This also reduces downtime caused by disassembly and cleaning of the insulating cylinder 1142, thereby improving the throughput of the semiconductor process chamber.

[0116] In this embodiment, the structure of the chamber shell 11 can be varied. Referring to Figure 1, in one embodiment, the chamber shell 11 may include a shell body 119, a lower adapter 113, a magnetic shielding cylinder 1141, an insulating ring 115, an upper adapter 111, and an upper electrode 1163. The lower adapter 113, the magnetic shielding cylinder 1141, the upper adapter 111, and the insulating ring 115 are all annular structures and are stacked sequentially on the opening of the shell body 119. The upper electrode 1163 covers the insulating ring 115, thereby forming the chamber shell 11 of the chamber body 10.

[0117] The semiconductor process chamber disclosed in this application embodiment can be a magnetron sputtering process chamber. In this case, the semiconductor process chamber disclosed in this application embodiment may further include a first power supply 1161, a magnetron 1164, a magnetron drive unit 1162, and a target 112. The first power supply 1161 is electrically connected to the upper electrode 1163. The upper electrode 1163 is insulated and isolated from the upper adapter 111 by an insulating ring 115 to prevent the power of the first power supply 1161 from being transmitted to the upper adapter 111, the lower adapter 113, the magnetic shielding cylinder 1141, and the housing body 119. The target 112 is attached to the insulating ring 115, and the target 112 and the upper electrode 1163 form a closed space. The magnetron 1164 is disposed in the closed space. The first power supply 1161 can be a DC power supply or a radio frequency power supply. The first power source 1161 transmits power to the target material 112 through the upper electrode 1163, thereby charging the target material 112, which facilitates the adsorption of the second process gas during the target hitting process or coating process to impact the target material 112 and generate sputtered particles.

[0118] The magnetron drive unit 1162 is driven and connected to the magnetron 1164, thereby driving the magnetron 1164 to rotate in the enclosed space to achieve uniform magnetic control. The magnetron drive unit 1162 is located outside the enclosed space and can be driven and connected to the magnetron 1164 through a transmission mechanism passing through the upper electrode 1163. A sealing device 1165 can be provided at the point where the transmission mechanism passes through the upper electrode 1163 to ensure the airtightness of the enclosed space.

[0119] In one embodiment, the first air inlet 1111 and the second air inlet 1113 described above can be formed on the upper adapter 111. To cool the upper adapter 111, a first cooling channel 1112 can be provided. Similarly, to cool the lower adapter 113, a second cooling channel 1131 can be provided. In a specific process, a first cooling medium can be introduced into the first cooling channel 1112, and a second cooling medium can be introduced into the second cooling channel 1131. The first and second cooling media can be water, cooling gas, etc., and the embodiments of this application do not limit the specific types of the first and second cooling media.

[0120] In the semiconductor process chamber disclosed in this application embodiment, the chamber shell 11 simultaneously includes a magnetic shielding cylinder 1141 and an insulating cylinder 1142. The magnetic shielding cylinder 1141 is sleeved outside the insulating cylinder 1142. The magnetic shielding cylinder 1141 and the insulating cylinder 1142 are supported between the lower adapter 113 and the upper adapter 111. The magnetic shielding cylinder 1141, the insulating cylinder 1142, the upper adapter 111, and the lower adapter 113 form an annular space. The first radio frequency coil 15 is accommodated in the annular space and wound along the circumference of the annular space. This structure can effectively protect the first radio frequency coil 15. At the same time, it can also shield and prevent the electromagnetic field generated by the first radio frequency coil 15 from adversely affecting the external environment of the semiconductor process chamber. The semiconductor process chamber disclosed in this application embodiment also includes a second power supply 1181 and a first matching unit 1182. The second power supply 1181 is a radio frequency power supply. The second power supply 1181 is electrically connected to the first radio frequency coil 15 through the first matching unit 1182, thereby supplying power to the first radio frequency coil 15.

[0121] The semiconductor process chamber disclosed in this application embodiment further includes a third power supply 1183 and a second matching device 1184. The third power supply 1183 is electrically connected to the carrier device 30 through the second matching device 1184, thereby forming a bias electric field. This bias electric field then drives the coating particles to move towards the wafer 40 during the coating process. Of course, in the pre-cleaning process, the bias electric field can drive plasma formed in the pre-cleaning space to bombard the surface of the wafer 40, thereby achieving the purpose of purifying the wafer 40. The third power supply 1183 can be a radio frequency power supply.

[0122] The semiconductor process chamber disclosed in this application embodiment may further include a bias magnetic field coil 117, which is arranged around the circumference of the chamber shell 11. The bias magnetic field coil 117 generates a bias magnetic field, thereby improving the uniformity of the coating.

[0123] The semiconductor process chamber disclosed in this application embodiment may further include a vacuum pump 91, which is disposed on the chamber housing 11, for example, on the housing body 119. The vacuum pump 91 can ensure a vacuum environment in the semiconductor process chamber.

[0124] The semiconductor process chamber disclosed in this application embodiment may also include a vacuum gauge 92, which is mounted on the chamber housing 11. For example, the vacuum gauge 92 may be disposed on the housing body 119. The vacuum gauge 92 is used to monitor the vacuum level in the semiconductor process chamber.

[0125] Based on the semiconductor process chamber disclosed in the embodiments of this application, the embodiments of this application further disclose a semiconductor process apparatus, which includes the semiconductor process chamber described in the above embodiments.

[0126] Referring to Figure 12, in one related technology, a semiconductor process apparatus may include a loading / unloading chamber 001, a baking chamber 002, a first process chamber 003, a second process chamber 004, and a transfer chamber 005. The loading / unloading chamber 001 is used for loading and unloading the wafer 40. The baking chamber 002 is used to bake the wafer 40 to remove moisture adhering to it, so as to better facilitate the corresponding processes in the first process chamber 003 and the second process chamber 004. The transfer chamber 005 is equipped with the aforementioned wafer robot 051. The wafer robot 051 is used to transfer the wafer 40 between different chambers.

[0127] The first process chamber 003 is a pre-cleaning process chamber, and the second process chamber 004 is a coating process chamber. By employing the semiconductor process chambers disclosed in this application, since the semiconductor process chambers disclosed in this application can perform pre-cleaning and coating processes sequentially, both the first process chamber 003 and the second process chamber 004 in the semiconductor process equipment can be the semiconductor process chambers disclosed in this application. This facilitates the use of more process chambers for coating processes, ultimately improving the throughput of the coating process.

[0128] The above embodiments of this application focus on describing the differences between the various embodiments. As long as the different optimization features of the various embodiments are not contradictory, they can be combined to form a better embodiment. For the sake of brevity, they will not be described in detail here.

[0129] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A semiconductor process chamber, characterized in that, The device includes a chamber body, a shielding member, and a supporting device. The shielding member is movably disposed within the chamber body to switch between a first position and a second position. The supporting device is movably disposed within the chamber body to switch between a third position and a fourth position. When the shielding member is in the first position and the supporting device is in the third position, the shielding member is opposite to the supporting device, and the shielding member, the chamber body and the supporting device form a pre-cleaning space; When the shielding member is in the second position and the supporting device is in the fourth position, the shielding member and the supporting device are misaligned, and the supporting device and the chamber body form a coating space.

2. The semiconductor process chamber according to claim 1, characterized in that, The semiconductor process chamber also includes a plurality of first support rods, which are vertically and flexibly disposed within the chamber body; The supporting device is provided with a first clearance hole that slides with the plurality of first support rods. The plurality of first support rods are used to pass through the corresponding first clearance holes to support the shielding member, and when supporting the shielding member, they drive the shielding member to move to the first position or move it away from the first position.

3. The semiconductor process chamber according to claim 2, characterized in that, The bearing device includes multiple extension cylinders, which are respectively disposed at the openings of the first clearance hole facing away from the bearing surface of the bearing device, and the cylinder cavities of the extension cylinders are connected to the corresponding first clearance holes.

4. The semiconductor process chamber according to claim 2 or 3, characterized in that, The support device further includes a support body and a deposition ring. The support body has a support surface. The deposition ring is connected to the support body and is distributed around the support surface. There are multiple first clearance holes, which are opened on the deposition ring and are spaced apart along the circumferential direction of the deposition ring.

5. The semiconductor process chamber according to claim 2, characterized in that, The shielding component has multiple positioning slots, which are used to position and engage with the support ends of the multiple first support rods one by one.

6. The semiconductor process chamber according to claim 2, characterized in that, The semiconductor process chamber also includes a storage section, which is movably disposed within the chamber body to switch between an intersection position and a clearance position; When the storage part is in the handover position, the storage part is above the bearing device, and the storage part is used to receive the shield when the first support rod descends or to hand over the shield when the first support rod rises; When the storage section is in the avoidance position, the storage section and the supporting device are misaligned. When the shielding member is in the second position, the shielding member is supported on the storage part which is in the avoidance position.

7. The semiconductor process chamber according to claim 6, characterized in that, The shielding member or the storage part includes a plurality of support protrusions. When the shielding member is supported on the storage part, the storage part contacts the shielding member through the plurality of support protrusions.

8. The semiconductor process chamber according to claim 2, characterized in that, The semiconductor process chamber also includes a plurality of second support rods, which are disposed within the chamber body; The support device is provided with a second clearance hole that slides with the plurality of second support rods. The support device is vertically and vertically disposed within the cavity body. The support device is used to transfer the wafer between the support device and the plurality of second support rods by lifting and lowering.

9. The semiconductor process chamber according to claim 8, characterized in that, The semiconductor process chamber also includes a strut base, which is vertically and elliptically disposed within the chamber body. The plurality of first struts and the plurality of second struts are all fixed to the strut base, and the plurality of first struts and the plurality of second struts can move up and down synchronously with the strut base within the chamber body. The support end of the first support rod is higher than the support end of the second support rod, so that when the shielding member is raised to the first position and the bearing device is raised to the third position, the end face of the support end of the second support rod is not higher than the bearing surface of the bearing device.

10. The semiconductor process chamber according to claim 1, characterized in that, The chamber body includes a chamber shell and a top liner and / or a bottom liner disposed within the chamber shell; the top liner and the bottom liner are cylindrical structures and cover part of the inner wall of the chamber shell to form the coating space or the pre-cleaning space.

11. The semiconductor process chamber according to claim 10, characterized in that, The top liner includes a first annular protrusion, and the shielding member is provided with a first annular groove. When the shielding member is in the first position and the supporting device is in the third position, the first annular protrusion extends into the first annular groove and forms a first labyrinth isolation structure with the first annular groove.

12. The semiconductor process chamber according to claim 10, characterized in that, The semiconductor process chamber further includes a shielding ring, which surrounds the carrier and covers the edge of the carrier to move up and down with the carrier. The shielding ring includes a second annular protrusion, and the top liner is provided with a second annular groove. When the shielding member is in the second position and the carrier is in the fourth position, the second annular protrusion extends into the second annular groove and forms a second labyrinth isolation structure with the second annular groove.

13. The semiconductor process chamber according to claim 12, characterized in that, One of the bottom liner and the cover ring includes a third annular protrusion, and the other has a third annular groove. When the cover is in the first position and the support device is in the third position, the third annular protrusion extends into the third annular groove and forms a third labyrinth isolation structure with the third annular groove.

14. The semiconductor process chamber according to claim 10, characterized in that, The chamber shell has a first radio frequency coil embedded in the portion that encloses the pre-cleaning space, and the first radio frequency coil is distributed around the pre-cleaning space; the chamber shell includes an insulating cylinder, the insulating cylinder is arranged around the pre-cleaning space, the first radio frequency coil is arranged around the insulating cylinder, and the inner wall surface of the insulating cylinder is convex and concave.

15. The semiconductor process chamber according to claim 14, characterized in that, The top liner and the bottom liner are spaced apart to form an annular gap, and the first radio frequency coil is opposite to the annular gap.

16. A semiconductor process apparatus, characterized in that, Includes the semiconductor process chamber according to any one of claims 1 to 15.

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