Source electrode voltage compensation circuit and method for driving display panel, and display apparatus

Abstract

The present invention relates to the technical field of display, and provides a source electrode voltage compensation circuit and method for driving a display panel, and a display apparatus, which are used for reducing the risk of displaying vertical-line mura. A data line is electrically connected to a first sub-pixel and a second sub-pixel; a first gate line is electrically connected to the first sub-pixel, while a second gate line is electrically connected to the second sub-pixel; the turn-on time of the first gate line overlaps the turn-on time of the second gate line; within the scanning time of one image frame, the first gate line is turned on before the second gate line is; within the charging times of the first sub-pixel and the second sub-pixel, the source electrode voltage compensation circuit provides a first voltage V1 and a second voltage V2, separately, to the data line, wherein V1=V2-ΔV; and ΔV＝ΔV1-ΔV2, ΔV1 being a first feed-through voltage applied to the first sub-pixel and caused by a signal transition of the first gate line and the second gate line, and ΔV2 being a second feed-through voltage applied to the second sub-pixel and caused by the signal transition of the first gate line and the second gate line.

Description

Source voltage compensation circuit and method for driving display panels, and display device.

[0001] This invention claims priority to Chinese Patent Application No. 202410912148.6, filed with the State Intellectual Property Office of China on July 8, 2024, entitled “Source Voltage Compensation Circuit and Method for Driving a Display Panel, and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of display technology, and more specifically to a source voltage compensation circuit and method for driving a display panel, and a display device. Background Technology

[0003] Thin Film Transistor Liquid Crystal Display (TFT-LCD) features small size, low power consumption, high image quality, no radiation, and portability. It has developed rapidly in recent years and has been widely used in products of various sizes, covering almost all major electronic products in today's information society.

[0004] Currently, LCD panels suffer from uneven display. Summary of the Invention

[0005] In view of this, the present invention provides a source voltage compensation circuit and method for driving a display panel, and a display device, so as to improve the display uniformity of the display panel and reduce the risk of vertical lines appearing on the display.

[0006] In a first aspect, embodiments of the present invention provide a source voltage compensation circuit for driving a display panel, the display panel comprising:

[0007] Multiple rows of pixels arranged along a first direction, each row of pixels including multiple sub-pixels arranged along a second direction; the multiple sub-pixels include a first sub-pixel and a second sub-pixel.

[0008] Multiple data lines, which are electrically connected to the first sub-pixel and the second sub-pixel respectively;

[0009] Multiple grid line groups, each grid line group including a first grid line and a second grid line, the first grid line and the second grid line are located on opposite sides of the same pixel row; the first grid line is electrically connected to a first sub-pixel, and the second grid line is electrically connected to a second sub-pixel; the on-time of the first grid line and the on-time of the second grid line overlap; wherein, within the scanning time of one image frame, the first grid line is turned on before the second grid line.

[0010] A source voltage compensation circuit is used to provide a first voltage V1 to the data line during the charging time of the first sub-pixel, and to provide a second voltage V2 to the data line during the charging time of the second sub-pixel, wherein the first voltage V1 and the second voltage V2 satisfy V1 = V2 - ΔV; ΔV = ΔV1 - ΔV2, where ΔV1 is the first feedthrough voltage experienced by the first sub-pixel caused by the signal transition between the first gate line and the second gate line, and ΔV2 is the second feedthrough voltage experienced by the second sub-pixel caused by the signal transition between the first gate line and the second gate line.

[0011] Secondly, embodiments of the present invention provide a source voltage compensation method for driving a display panel, the display panel comprising:

[0012] Multiple rows of pixels arranged along a first direction, each row of pixels including multiple sub-pixels arranged along a second direction; the multiple sub-pixels include a first sub-pixel and a second sub-pixel.

[0013] Multiple data lines, which are electrically connected to the first sub-pixel and the second sub-pixel respectively;

[0014] Multiple grid line groups, each grid line group including a first grid line and a second grid line, the first grid line and the second grid line are located on opposite sides of the same pixel row; the first grid line is electrically connected to a first sub-pixel, and the second grid line is electrically connected to a second sub-pixel; the on-time of the first grid line and the on-time of the second grid line overlap; wherein, within the scanning time of one image frame, the first grid line is turned on before the second grid line.

[0015] Source voltage compensation methods include:

[0016] During the charging time of the first sub-pixel, a first voltage V1 is provided to the data line, and,

[0017] During the charging time of the second sub-pixel, a second voltage V2 is provided to the data line, wherein,

[0018] The first voltage V1 and the second voltage V2 satisfy V1 = V2 - ΔV; ΔV = ΔV1 - ΔV2, where ΔV1 is the first feedthrough voltage experienced by the first sub-pixel due to the signal transition between the first and second gate lines, and ΔV2 is the second feedthrough voltage experienced by the second sub-pixel due to the signal transition between the first and second gate lines.

[0019] Thirdly, embodiments of the present invention provide a display device, including the aforementioned source voltage compensation circuit for driving a display panel.

[0020] The source voltage compensation circuit and method for driving a display panel provided in this invention, and the display device, provide a first voltage V1 to the data line during the charging time of the first sub-pixel and a second voltage V2 to the data line during the charging time of the second sub-pixel, where V1 = V2 - ΔV and ΔV = ΔV1 - ΔV2. Here, ΔV1 is the first feedthrough voltage experienced by the first sub-pixel due to the signal transition between the first and second gate lines, and ΔV2 is the second feedthrough voltage experienced by the second sub-pixel due to the signal transition between the first and second gate lines. This reduces the impact of the feedthrough voltage difference on the brightness of the first and second sub-pixels, weakens or even avoids the display unevenness problem caused by the brightness difference between the first and second sub-pixels, and is beneficial to improving the brightness consistency of the display panel. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 is a schematic diagram of a display panel provided in an embodiment of the present invention;

[0023] Figure 2 is a signal timing diagram of a gate line provided in an embodiment of the present invention;

[0024] Figure 3 is an equivalent circuit diagram of a first sub-pixel provided in an embodiment of the present invention;

[0025] Figure 4 is an equivalent circuit diagram of a second sub-pixel provided in an embodiment of the present invention;

[0026] Figure 5 is a schematic diagram of the signal change principle of the pixel electrode of a first sub-pixel provided in an embodiment of the present invention;

[0027] Figure 6 is a schematic diagram of the signal change principle of a pixel electrode of a second sub-pixel provided in an embodiment of the present invention;

[0028] Figure 7 is a schematic diagram of a source voltage compensation circuit provided in an embodiment of the present invention;

[0029] Figure 8 is a schematic diagram of a data driving circuit provided in an embodiment of the present invention;

[0030] Figure 9 is a schematic diagram of another source voltage compensation circuit provided in an embodiment of the present invention;

[0031] Figure 10 is a schematic diagram of the polarity of each sub-pixel in a display panel provided by an embodiment of the present invention;

[0032] Figure 11 is a schematic diagram of a source voltage compensation method provided in an embodiment of the present invention;

[0033] Figure 12 is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0034] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0036] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0037] This invention provides a source voltage compensation circuit for driving a display panel. For example, the display panel provided in this invention includes a liquid crystal display panel.

[0038] As shown in Figure 1, which is a schematic diagram of a display panel according to an embodiment of the present invention, the display panel 1 includes multiple pixel rows 10 arranged along a first direction h1, multiple data lines 11, and multiple gate lines. The gate lines and data lines 11 are insulated from each other and cross each other. Each pixel row 10 includes multiple sub-pixels arranged along a second direction h2, where the first direction h1 intersects the second direction h2. Each sub-pixel includes a pixel electrode, a common electrode, a liquid crystal layer, and a thin-film transistor (TFT). The gate of the TFT is electrically connected to the gate line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the pixel electrode. One of the first electrode and the second electrode is the source electrode, and the other is the drain electrode. Under the action of the voltage difference between the pixel electrode and the common electrode, the liquid crystal molecules in the liquid crystal layer are deflected. By adjusting the deflection angle of the liquid crystal molecules, the transmittance of light passing through the liquid crystal molecules can be changed, thereby allowing the sub-pixels to exhibit different brightness levels.

[0039] In this embodiment of the invention, as shown in FIG1, the plurality of sub-pixels in pixel row 10 include a first sub-pixel 101 and a second sub-pixel 102, and the first sub-pixel 101 and the second sub-pixel 102 are electrically connected to the same data line 11. The plurality of gate lines are configured to include a plurality of gate line groups 12, and the gate line group 12 includes a first gate line 121 and a second gate line 122. As shown in FIG1, the first gate line 121 and the second gate line 122 are located on opposite sides of the same pixel row 10 in a first direction h1; the first gate line 121 is electrically connected to the first sub-pixel 101, and the second gate line 122 is electrically connected to the second sub-pixel 102.

[0040] Compared to a method where multiple sub-pixels in a pixel row 10 are connected to different data lines 11, this embodiment of the invention reduces the number of data lines 11 required to drive the display panel 1 by electrically connecting one data line 11 to at least two sub-pixels in the same pixel row 10. This reduces the number of output channels of the data driving circuit (Source IC) providing the data voltage. Given a fixed number of output channels for the data driving circuit, this embodiment reduces the number of required data driving circuits, decreases the width of the non-display area occupied by the data driving circuits, and facilitates narrower bezels, thus improving the narrow bezel design of the display panel 1. Furthermore, data driving circuits are typically expensive; by reducing the number of required data driving circuits, this embodiment reduces costs and enhances product competitiveness. This advantage is particularly pronounced when the display panel is applied to medium-sized products with higher resolution and more data lines.

[0041] In this embodiment of the invention, the turn-on time of the first gate line 121 and the turn-on time of the second gate line 122 overlap. The turn-on time of the gate line refers to the time during which the signal transmitted by the gate line controls the corresponding thin-film transistor to conduct. When the thin-film transistor is conducting, the voltage on the data line 11 can be written to the pixel electrode through the conducting thin-film transistor, thereby charging the corresponding sub-pixel. As shown in Figure 2, which is a signal timing diagram of a gate line provided in this embodiment of the invention, within the scanning time of one image frame, the first gate line 121 turns on before the second gate line 122 located in the same gate line group 12 as the first gate line 121. Figures 1 and 2 illustrate five pixel rows and five gate line groups electrically connected to the five pixel rows, respectively labeled as 12_1, 12_2, 12_3, 12_4, and 12_5. Figure 2 illustrates the gate line turn-on voltage as a positive voltage.

[0042] In this embodiment of the invention, the on-time of the first gate line 121 overlaps with the on-time of the second gate line 122. During the overlap period, the thin-film transistor in the first sub-pixel 101, which is electrically connected to the first gate line 121, is turned on, and the thin-film transistor in the second sub-pixel 102, which is electrically connected to the second gate line 122, is also turned on. The second sub-pixel 102 can be pre-charged with the data voltage required by the first sub-pixel 101. Based on this configuration, compared to the method where one data line 11 connects only one sub-pixel in one pixel row 10, and one gate line connects all sub-pixels in one pixel row 10, the scanning time of one frame can be increased without increasing the time, and it can ensure that all sub-pixels electrically connected to each gate line have sufficient charging time to avoid the problem of insufficient charging.

[0043] In this embodiment of the invention, the source voltage compensation circuit 2 is used to provide a first voltage V1 to the data line 11 during the charging time of the first sub-pixel 101, i.e., when the first gate line 121 is turned on, and to provide a second voltage V2 to the data line 11 during the charging time of the second sub-pixel 102, i.e., when the second gate line 122 is turned on. The first voltage V1 and the second voltage V2 satisfy V1 = V2 - ΔV; ΔV = ΔV1 - ΔV2, where ΔV1 is the first feedthrough voltage received by the first sub-pixel 101 caused by the signal transition between the first gate line 121 and the second gate line 122; and ΔV2 is the second feedthrough voltage received by the second sub-pixel 102 caused by the signal transition between the first gate line 121 and the second gate line 122. The first gate line 121 and the second gate line 122 belong to the same gate line group corresponding to the first sub-pixel 101.

[0044] As shown in Figure 2, during display panel operation, multiple gate lines are sequentially activated according to the scanning sequence of the display panel to charge the sub-pixels connected to the gate lines. Due to parasitic capacitance between the pixel electrodes and the gate lines, when the pixel electrode is in the maintenance phase after charging, a voltage jump occurs in the voltage transmitted by the gate lines, causing a corresponding change in the voltage on the pixel electrode due to capacitive coupling. This voltage change on the pixel electrode is the feedthrough voltage to the pixel electrode potential caused by the gate line voltage being turned off. The feedthrough voltage affects the accuracy of grayscale display.

[0045] In this embodiment of the invention, a first coupling capacitance exists between the pixel electrode and the gate line electrically connected to the pixel electrode via a thin-film transistor, and a second coupling capacitance exists between the pixel electrode and another gate line, which is a gate line belonging to the same gate line group as the gate line electrically connected to the pixel electrode. Since the pixel electrode is far from the gate lines in other gate line groups, the signal transitions of the gate lines in other gate line groups have a relatively small and negligible impact on the voltage of the pixel electrode.

[0046] As shown in Figures 3 and 4, Figure 3 is an equivalent circuit diagram of a first sub-pixel provided in an embodiment of the present invention, and Figure 4 is an equivalent circuit diagram of a second sub-pixel provided in an embodiment of the present invention. In these figures, Cst1 is the storage capacitance between the common electrode Com and the pixel electrode of the first sub-pixel 101; Clc1 is the equivalent capacitance of the liquid crystal molecules of the first sub-pixel 101; Cpg1 is the first coupling capacitance between the first gate line 121 and the pixel electrode of the first sub-pixel 101; Cpg1' is the second coupling capacitance between the second gate line 122 and the pixel electrode of the first sub-pixel 101; Cst2 is the storage capacitance between the common electrode Com and the pixel electrode of the second sub-pixel 102; Clc2 is the equivalent capacitance of the liquid crystal molecules of the second sub-pixel 102; Cpg2 is the first coupling capacitance between the second gate line 122 and the pixel electrode of the second sub-pixel 102; and Cpg1' is the second coupling capacitance between the first gate line 121 and the pixel electrode of the second sub-pixel 102.

[0047] Since the first gate line 121 is turned on before the second gate line 122, and their turn-on times overlap, when the first gate line 121 switches from an active level to an inactive level, the second gate line 122 is still in the active state, the TFT in the second sub-pixel 102 is turned on, and the signal on the data line 11 is still written to the pixel electrode of the second sub-pixel 102 through the active TFT. Therefore, the voltage of the pixel electrode in the second sub-pixel 102 is not affected by the signal transition of the first gate line 121.

[0048] As shown in Figure 5, Figure 5 is a schematic diagram of the signal change principle of the pixel electrode of a first sub-pixel according to an embodiment of the present invention. The second gate line 122 in the i-th gate line group 12_i and the first gate line 121 and second gate line 122 in the (i+1)-th gate line group 12_(i+1) are used as examples. The voltage of the pixel electrode of the first sub-pixel 101 in the (i+1)-th pixel row is affected by two feedthrough voltages. That is, ΔV1 = ΔV11 + ΔV12; where ΔV11 is the feedthrough voltage of the pixel electrode of the first sub-pixel 101 corresponding to the voltage transition of the first gate line 121, and ΔV12 is the feedthrough voltage of the pixel electrode of the first sub-pixel 101 corresponding to the voltage transition of the second gate line 122.

[0049] As shown in Figure 6, Figure 6 is a schematic diagram of the signal change principle of the pixel electrode of the second sub-pixel provided in an embodiment of the present invention. The first gate line 121 and the second gate line 122 in the (i+1)th gate line group 12_(i+1) are used as examples. The voltage of the pixel electrode of the second sub-pixel 102 in the (i+1)th pixel row will only be affected by the feedthrough voltage once.

[0050] It can be seen that the influence of the feedthrough voltage on the first sub-pixel 101 is greater than that on the second sub-pixel 102. When driving the display panel, this embodiment of the invention can compensate for the different influences of the feedthrough voltages on the first sub-pixel 101 and the second sub-pixel 102 by setting V1 = V2 - ΔV. Specifically, when the first sub-pixel 101 is charging, the source voltage compensation circuit 2 provides a first voltage V1 to the first sub-pixel 101. When the first gate line 121 switches from the turn-on voltage to the turn-off voltage, the voltage of the pixel electrode of the first sub-pixel 101 switches to V1 + ΔV11 through the coupling of the first gate line 121. When the second gate line 122 switches from the turn-on voltage to the turn-off voltage, the voltage of the pixel electrode of the first sub-pixel 101 switches to V1 + ΔV11 + ΔV12 through the coupling of the second gate line 122. That is, after two couplings, the voltage of the pixel electrode of the first sub-pixel 101 is V1 + ΔV1.

[0051] When the second sub-pixel 102 is charging, the source voltage compensation circuit 2 provides the second voltage V2 to the second sub-pixel 102. The signal transition of the first gate line 121 will not affect the pixel voltage of the second sub-pixel 102. When the second gate line 122 transitions from the turn-on voltage to the turn-off voltage, the voltage of the pixel electrode of the second sub-pixel 102 transitions to V2+ΔV2 through the coupling of the second gate line 122.

[0052] Since V1 = V2 - ΔV and ΔV = ΔV1 - ΔV2, it can be seen that after coupling, the voltage of the pixel electrode of the first sub-pixel 101 is equal to the voltage of the pixel electrode of the second sub-pixel 102.

[0053] In summary, by adopting the setting method provided in the embodiments of the present invention, the impact of the difference in feedthrough voltage on the brightness of the first sub-pixel 101 and the second sub-pixel 102 can be reduced, the uneven display problem caused by the difference in brightness between the first sub-pixel 101 and the second sub-pixel 102 can be weakened or even avoided, which is beneficial to improving the brightness consistency of the display panel.

[0054] Furthermore, based on the above configuration, when the first sub-pixel 101 and the second sub-pixel 102 are charged, as shown in Figures 3 and 4, the common voltage transmitted by the common electrode Com can be made equal. That is, without the need for differentiated design of the common voltage, the voltage difference between the two sides of the liquid crystal layer in the first sub-pixel 101 and the voltage difference between the two sides of the liquid crystal layer in the second sub-pixel 102 can be guaranteed to be equal, thereby enabling the first sub-pixel 101 and the second sub-pixel 102 to have the same brightness.

[0055] Optionally, pixel row 10 includes alternating red, green, and blue sub-pixels. Multiple sub-pixels of the same color are arranged along a first direction h1. In this embodiment, the first sub-pixel 101 and the second sub-pixel 102 are different colors; that is, the first sub-pixel 101 and the second sub-pixel 102 can be two of a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. As shown in FIG1, pixel row 10 may include multiple first sub-pixels 101 and second sub-pixels 102 electrically connected to different data lines 11.

[0056] For example, as shown in FIG1, the pixel row 10 further includes a first virtual pixel 201 and a second virtual pixel 202. The first virtual pixel 201 and the second virtual pixel 202 are located on the side of the pixel row 10 near the edge of the display panel 1. The positions of the first virtual pixel 201 and the second virtual pixel 202 in the display panel do not emit light. The setting of the first virtual pixel 201 and the second virtual pixel 202 can improve the etching uniformity of the display pixels located at the edge of the display area.

[0057] For example, the first voltage V1 mentioned above includes the standard data voltage V0 corresponding to the image data of the first sub-pixel 101 and the second sub-pixel 102 in the current frame; or, the second voltage V2 includes the standard data voltage V0 corresponding to the image data of the first sub-pixel 101 and the second sub-pixel 102 in the current frame. The standard data voltage can change as the image data is refreshed; for example, the standard data voltage in a black screen is different from the standard data voltage in a white screen. It should be noted that in this embodiment of the invention, the standard data voltage corresponding to the image data of the first sub-pixel 101 in the current frame and the standard data voltage corresponding to the image data of the second sub-pixel 102 in the current frame are equal, that is, the required brightness for both is the same.

[0058] As shown in Figure 7, which is a schematic diagram of a source voltage compensation circuit according to an embodiment of the present invention, the source voltage compensation circuit 2 includes a calculation circuit 21 and a source voltage driving circuit 22. The source voltage driving circuit 22 is electrically connected to the calculation circuit 21 and the data line 11. The source voltage driving circuit 22 is used to provide the aforementioned standard data voltage V0 to the data line 11 and the calculation circuit 21 according to the received image data of the current frame. The calculation circuit 21 is used to provide the data line 11 with one of the aforementioned first voltage V1 and second voltage V2 that does not include the standard data voltage V0, based on the difference ΔV between the aforementioned standard data voltage V0, the first feedthrough voltage ΔV1, and the second feedthrough voltage ΔV2. Wherein, the difference ΔV = ΔV1 - ΔV2.

[0059] For example, in an embodiment of the present invention, the second voltage V2 can include the standard data voltage V0 corresponding to the image data of the first sub-pixel 101 and the second sub-pixel 102 in the current frame. The source voltage driving circuit 22 can provide the standard data voltage V0 to the data line 11 and the calculation circuit 21 according to the received image data of the current frame during the charging time of the second sub-pixel. That is, during the charging time of the second sub-pixel 102, the source driving circuit 22 can directly use the standard data voltage V0 corresponding to the image data of the second sub-pixel 102 in the current frame to charge the second sub-pixel 102.

[0060] The calculation circuit 21 is used to provide the data line 11 with the first actual voltage required by the first sub-pixel 101 based on the difference ΔV between the standard data voltage V0, the first feedthrough voltage ΔV1, and the second feedthrough voltage ΔV2 during the charging time of the first sub-pixel 101. This first actual voltage is the first voltage V1. Wherein, V1 = V2 - ΔV = V0 - ΔV.

[0061] Alternatively, in this embodiment of the invention, the first voltage V1 may include the standard data voltage V0 corresponding to the image data of the first sub-pixel 101 and the second sub-pixel 102 in the current frame. That is, during the charging time of the first sub-pixel 101, the source driving circuit 22 can directly use the standard data voltage V0 corresponding to the image data of the first sub-pixel 101 in the current frame to charge the first sub-pixel 101.

[0062] The calculation circuit 21 is used to provide the data line 11 with the second actual voltage required by the second sub-pixel 102 based on the difference ΔV between the standard data voltage V0, the first feedthrough voltage ΔV1, and the second feedthrough voltage ΔV2 during the charging time of the second sub-pixel 102. This second actual voltage is the second voltage V2 mentioned above. Wherein, V2 = V1 + ΔV = V0 + ΔV.

[0063] In this embodiment of the invention, by making one of the first voltage V1 and the second voltage V2 include the standard data voltage V0 corresponding to the image data of the first sub-pixel 101 and the second sub-pixel 102 in the current frame, the first sub-pixel 101 or the second sub-pixel 102 can be directly charged using the standard data voltage V0 provided by the source driving circuit 22. The calculation circuit 21 can calculate the other of the first voltage and the second voltage that meets the brightness uniformity requirement based on the above-mentioned standard data voltage V0, the first feedthrough voltage ΔV1 and the second feedthrough voltage ΔV2. The operation is simple and easy to implement.

[0064] As exemplarily shown in FIG7, the computing circuit 21 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is electrically connected to the source voltage driving circuit 22; the second input terminal receives the difference ΔV between the first feedthrough voltage ΔV1 and the second feedthrough voltage ΔV2. The computing circuit 21 is used to output the aforementioned first voltage V1 or second voltage V2 to the output terminal according to the signals from the first input terminal and the second input terminal, and the output terminal provides the other of the first voltage V1 and the second voltage V2 to the data line 11.

[0065] As exemplarily shown in FIG7, the source voltage compensation circuit 2 further includes a compensation value acquisition unit 23, which is used to acquire the above-mentioned difference ΔV and provide the difference ΔV to the calculation circuit 21.

[0066] Optionally, the computing circuit 21 described above includes an operational amplifier.

[0067] For example, the source voltage compensation circuit 2 provided in this embodiment of the invention can be integrated into the data driving circuit for driving the display panel 1. As shown in FIG8, FIG8 is a schematic diagram of a data driving circuit provided in this embodiment of the invention. The data driving circuit includes a latch 31, an output gating circuit (MUX) 32, a level shifter 33, a digital-to-analog converter (DAC) 34, and an output buffer. The operational amplifier 210 used as the computing circuit 21 can be reused as the operational amplifier in the output buffer. With this configuration, there is no need to increase the number of modules in the data driving circuit 3, which helps to simplify the structure of the data driving circuit 3.

[0068] Optionally, as shown in Figure 8, the source drive circuit 22 can be implemented by the aforementioned latch 31, output gating circuit (MUX) 32, level shifter 33, and digital-to-analog converter (DAC) 34.

[0069] For example, the second voltage V2 mentioned above includes the standard data voltage V0 corresponding to the image data of the first sub-pixel 101 and the second sub-pixel 102 in the current frame, as shown in FIG9. FIG9 is a schematic diagram of another source voltage compensation circuit provided in an embodiment of the present invention. The calculation circuit 21 includes a subtractor 211.

[0070] As exemplarily shown in Figure 9, the subtractor 211 includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The first end of the first resistor R1 is electrically connected to the compensation value acquisition unit 23. The second end of the first resistor R2 is electrically connected to both the inverting input terminal of the subtractor 211 and the first end of the fourth resistor R4. The first end of the second resistor R2 is electrically connected to the source voltage drive circuit 22. The second end of the second resistor R2 is also electrically connected to both the non-inverting input terminal of the subtractor 211 and the first end of the third resistor R3. The second end of the third resistor R3 is electrically connected to ground (GND). The second end of the fourth resistor R4 is electrically connected to the output terminal OUT of the subtractor 211.

[0071] For example, in this embodiment of the invention, the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor can be made equal. Based on the difference ΔV provided by the compensation value acquisition unit 23 and the standard data voltage V0 provided by the source voltage driving circuit 22, the subtractor 211 can output V0-ΔV after calculation. When the first sub-pixel 101 is charging, the subtractor 211 can provide V0-ΔV to the data line 11. Moreover, when the effective level of the gate line is high, the first feedthrough voltage ΔV1, the second feedthrough voltage ΔV2, and the difference ΔV between the first feedthrough voltage ΔV1 and the second feedthrough voltage ΔV2 are all negative. When the standard data voltage V0 is positive, the subtractor 211 can make the first voltage V1 provided to the first sub-pixel 101 greater than V0. After the influence of the gate line voltage, this helps to ensure that the first sub-pixel 101 has a higher brightness.

[0072] Alternatively, the aforementioned first voltage V1 may include the standard data voltage V0 corresponding to the image data of the first sub-pixel 101 and the second sub-pixel 102 in the current frame, and the calculation circuit 21 may include an adder. Based on the difference ΔV provided by the compensation value acquisition unit 23 and the standard data voltage V0 provided by the source voltage driving circuit 22, the adder may output V0+ΔV through calculation. When the second sub-pixel 102 is charging, the adder may provide V0+ΔV to the data line 11.

[0073] Optionally, as shown in Figure 9, the source voltage compensation circuit 2 further includes a first switch 231 and a second switch 232. The first switch 231 is electrically connected to the output terminal of the computing circuit 21 and the data line 11. The first switch 231 is used to turn on during the charging time of the first sub-pixel 101. During the charging time of the first sub-pixel 101, the first switch 231 is turned on, and the first voltage V1 output by the computing circuit 21 is written into the data line 11 through the first switch 231 to charge the first sub-pixel 101. The second switch 232 is electrically connected to the source voltage driving circuit 22 and the data line 11. The second switch 232 is used to turn on during the charging time of the second sub-pixel 102. During the charging time of the second sub-pixel 102, the second switch 232 is turned on, and the standard data voltage V0 output by the source voltage driving circuit 22 can be used as the second voltage V2 and written into the data line 11 through the second switch 232 to charge the second sub-pixel 102.

[0074] As shown in Figure 9, the source voltage compensation circuit 2 also includes a control line 24, which is electrically connected to the control terminal of the first switch 231 and the control terminal of the second switch 232. The control line 24 is used to control the first switch 231 to be turned on during the charging time of the first sub-pixel 101 and to control the second switch 232 to be turned on during the charging time of the second sub-pixel 102.

[0075] Optionally, in this embodiment of the invention, one of the first switch 231 and the second switch 232 is a P-type transistor, and the other is an N-type transistor. Figure 9 illustrates this with the first switch 231 comprising a P-type transistor and the second switch 232 comprising an N-type transistor. Based on this arrangement, the control terminals of the first switch 231 and the second switch 232 can be connected to the same control line 24, which helps to reduce the number of control lines 24.

[0076] Alternatively, in this embodiment of the invention, the first switch 231 and the second switch 232 may include transistors of the same type. In this case, the embodiment of the invention may provide different control lines connected to the control terminals of the two switches respectively.

[0077] Optionally, as shown in Figure 9, the source voltage compensation circuit 2 further includes a control circuit 240, which is electrically connected to the control line 24. The control circuit 240 is used to provide control signals for controlling the first switch 231 and the second switch 232 to be turned on in a time-division manner.

[0078] For example, the source voltage compensation circuit 2 is also used to make the sub-pixels driven by the same data line 11 have opposite polarities in two adjacent frames, so as to avoid the voltage on both sides of the liquid crystal molecules being fixed at a certain value for a long time, and to avoid the problem that the characteristics of the liquid crystal molecules are destroyed and they can no longer rotate according to the change of electric field.

[0079] Optionally, as shown in Figures 1 and 10, Figure 10 is a polarity diagram of each sub-pixel in a display panel provided by an embodiment of the present invention. In two adjacent pixel rows 10, four sub-pixels electrically connected to the same data line 11 are staggered in the first direction h1.

[0080] For example, the source voltage compensation circuit 2 is also used to provide data voltages of opposite polarity to two adjacent data lines 11 to reduce flicker and improve display performance. Figure 10 illustrates four data lines, which are labeled 11_1, 11_2, 11_3 and 11_4 respectively.

[0081] For example, as shown in Figures 1 and 10, the first sub-pixel 101 and the second sub-pixel 102 are arranged adjacent to each other. Based on the connection relationship between the data line and the sub-pixels provided by the present invention, it is not necessary to frequently switch the polarity of the signal on the data line 11 when charging two adjacent pixel rows 10, thus achieving the effect of row two-point reversal. Here, row two-point reversal refers to reversing the positive and negative polarities in each pixel row 10 in units of two sub-pixels. While improving the display effect, it is also beneficial to reduce the power consumption of the source voltage compensation circuit 2.

[0082] Optionally, as shown in Figures 1 and 10, the data line 11 is located on the same side of the first sub-pixel 101 and the second sub-pixel 102 to which it is connected. This arrangement allows the data line 11 to be located between the first sub-pixel 101 and the second sub-pixel 102 that are electrically connected to it in two adjacent pixel rows 10, thereby shortening the length of the connection line between the data line 11 and the first sub-pixel 101 and the second sub-pixel 102, which helps to simplify the structure of the display panel.

[0083] This invention also provides a source voltage compensation method for driving a display panel 1. As shown in FIG1, the display panel 1 includes: a plurality of pixel rows 10 arranged along a first direction h1, the pixel rows 10 including a plurality of sub-pixels arranged along a second direction h2; the plurality of sub-pixels including a first sub-pixel 101 and a second sub-pixel 102; a plurality of data lines 11, the data lines 11 being electrically connected to the first sub-pixel 101 and the second sub-pixel 102 respectively; a plurality of gate line groups 12, the gate line groups 12 including a first gate line 121 and a second gate line 122, the first gate line 121 and the second gate line 122 being located on both sides of the same pixel row 10; the first gate line 121 being electrically connected to the first sub-pixel 101, and the second gate line 122 being electrically connected to the second sub-pixel 102; the turn-on time of the first gate line 121 and the turn-on time of the second gate line 122 overlap; wherein, within the scanning time of one image frame, the first gate line 121 turns on before the second gate line 122.

[0084] As shown in Figure 11, Figure 11 is a schematic diagram of a source voltage compensation method provided by an embodiment of the present invention. The source voltage compensation method includes:

[0085] During the charging time of the first sub-pixel 101, a first voltage V1 is provided to the data line 11, and,

[0086] During the charging time of the second sub-pixel 102, a second voltage V2 is provided to the data line 11, wherein,

[0087] The first voltage V1 and the second voltage V2 satisfy V1 = V2 - ΔV; ΔV = ΔV1 - ΔV2, where ΔV1 is the first feedthrough voltage received by the first sub-pixel 101 caused by the signal transition between the first gate line 121 and the second gate line 122, and ΔV2 is the second feedthrough voltage received by the second sub-pixel 102 caused by the signal transition between the first gate line 121 and the second gate line 122.

[0088] By adopting the setting method provided in the embodiments of the present invention, the influence of the difference in feedthrough voltage on the brightness of the first sub-pixel 101 and the second sub-pixel 102 can be reduced, weakening or even avoiding the display unevenness problem caused by the brightness difference between the first sub-pixel 101 and the second sub-pixel 102, which is beneficial to improving the brightness consistency of the display panel 1.

[0089] For example, as shown in FIG10, the source voltage compensation method provided in this embodiment of the invention further includes: providing data voltages of opposite polarity to two adjacent data lines 11 to reduce flicker and improve display effect.

[0090] This invention also provides a display device, as shown in FIG12. FIG12 is a schematic diagram of a display device provided by an embodiment of the present invention. The display device includes a display panel 1 and the aforementioned source voltage compensation circuit 2, which is electrically connected to the data lines in the display panel 1. The specific structure of the source voltage compensation circuit 2 has been described in detail in the above embodiments and will not be repeated here. Of course, the display device shown in FIG12 is merely illustrative, and the display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, car or motorcycle dashboard, e-reader, or television.

[0091] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A source voltage compensation circuit for driving a display panel, characterized in that, The display panel includes: Multiple rows of pixels arranged along a first direction, each row of pixels including multiple sub-pixels arranged along a second direction; the multiple sub-pixels including a first sub-pixel and a second sub-pixel; Multiple data lines, each of which is electrically connected to the first sub-pixel and the second sub-pixel respectively; Multiple gate line groups, each gate line group including a first gate line and a second gate line, the first gate line and the second gate line being located on opposite sides of the same pixel row; the first gate line being electrically connected to a first sub-pixel, and the second gate line being electrically connected to a second sub-pixel; the activation time of the first gate line and the activation time of the second gate line overlap; wherein, within the scanning time of one image frame, the first gate line is activated before the second gate line; The source voltage compensation circuit is used to provide a first voltage V1 to the data line during the charging time of the first sub-pixel, and to provide a second voltage V2 to the data line during the charging time of the second sub-pixel, wherein the first voltage V1 and the second voltage V2 satisfy V1 = V2 - ΔV; ΔV = ΔV1 - ΔV2, where ΔV1 is the first feedthrough voltage experienced by the first sub-pixel caused by the signal transition between the first gate line and the second gate line, and ΔV2 is the second feedthrough voltage experienced by the second sub-pixel caused by the signal transition between the first gate line and the second gate line.

2. The source voltage compensation circuit according to claim 1, characterized in that, The source voltage compensation circuit includes a calculation circuit and a source voltage driving circuit, wherein the source voltage driving circuit is electrically connected to the calculation circuit and the data line, respectively. One of the first voltage and the second voltage includes the standard data voltage corresponding to the image data of the first sub-pixel and the second sub-pixel in the current frame; The source voltage driving circuit is used to provide the standard data voltage to the data line and the computing circuit according to the received image data; The computing circuit is used to provide the data line with the other of the first voltage and the second voltage based on the difference between the standard data voltage, the first feedthrough voltage, and the second feedthrough voltage.

3. The source voltage compensation circuit according to claim 2, characterized in that, The computing circuit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is electrically connected to the source voltage drive circuit; The second input terminal receives the difference between the first feedthrough voltage and the second feedthrough voltage; The output terminal is used to output the other of the first voltage and the second voltage based on the signals from the first input terminal and the second input terminal.

4. The source voltage compensation circuit according to claim 2, characterized in that, The computing circuit includes an operational amplifier.

5. The source voltage compensation circuit according to claim 2, characterized in that, The second voltage includes the standard data voltage corresponding to the image data of the first sub-pixel and the second sub-pixel in the current frame; The computing circuit includes a subtractor.

6. The source voltage compensation circuit according to claim 5, characterized in that, It also includes a first switch and a second switch; The first switch is electrically connected to the output terminal of the computing circuit and the data line, and the first switch is used to turn on during the charging time of the first sub-pixel; The second switch is electrically connected to the source voltage driving circuit and the data line, and the second switch is used to turn on during the charging time of the second sub-pixel.

7. The source voltage compensation circuit according to claim 6, characterized in that, One of the first switch and the second switch is a P-type transistor, and the other is an N-type transistor; The source voltage compensation circuit further includes a control line, which is electrically connected to the control terminal of the first switch and the control terminal of the second switch. The control line is used to control the first switch to be turned on during the charging time of the first sub-pixel, and to control the second switch to be turned on during the charging time of the second sub-pixel.

8. The source voltage compensation circuit according to claim 2, characterized in that, The first voltage includes the standard data voltage corresponding to the image data of the first sub-pixel and the second sub-pixel in the current frame; The computing circuit includes an adder.

9. The source voltage compensation circuit according to claim 1, characterized in that, The source voltage compensation circuit is also used to provide data voltages of opposite polarity to two adjacent data lines.

10. The source voltage compensation circuit according to claim 1, characterized in that, The first sub-pixel and the second sub-pixel are arranged adjacent to each other.

11. The source voltage compensation circuit according to claim 1, characterized in that, In two adjacent pixel rows, the four sub-pixels electrically connected to the same data line are staggered in the first direction.

12. The source voltage compensation circuit according to claim 1, characterized in that, The data line is located on the same side of the first sub-pixel and the second sub-pixel.

13. A source voltage compensation method for driving a display panel, characterized in that, The display panel includes: Multiple rows of pixels arranged along a first direction, each row of pixels including multiple sub-pixels arranged along a second direction; the multiple sub-pixels including a first sub-pixel and a second sub-pixel; Multiple data lines, each of which is electrically connected to the first sub-pixel and the second sub-pixel respectively; Multiple gate line groups, each gate line group including a first gate line and a second gate line, the first gate line and the second gate line being located on opposite sides of the same pixel row; the first gate line being electrically connected to a first sub-pixel, and the second gate line being electrically connected to a second sub-pixel; the activation time of the first gate line and the activation time of the second gate line overlap; wherein, within the scanning time of one image frame, the first gate line is activated before the second gate line; The source voltage compensation method includes: During the charging time of the first sub-pixel, a first voltage V1 is provided to the data line, and, During the charging time of the second sub-pixel, a second voltage V2 is provided to the data line, wherein, The first voltage V1 and the second voltage V2 satisfy V1=V2-ΔV; ΔV=ΔV1-ΔV2, where ΔV1 is the first feedthrough voltage experienced by the first sub-pixel caused by the signal transition between the first gate line and the second gate line, and ΔV2 is the second feedthrough voltage experienced by the second sub-pixel caused by the signal transition between the first gate line and the second gate line.

14. The source voltage compensation method according to claim 13, characterized in that, Also includes: Provide data voltages of opposite polarity to two adjacent data lines.

15. A display device, characterized in that, It includes a display panel and a source voltage compensation circuit as described in any one of claims 1-12, wherein the source voltage compensation circuit is electrically connected to the data lines in the display panel.

Images