Vapor deposition mask and method for manufacturing electronic device

Abstract

The purpose of the present invention is to provide a vapor deposition mask with which it is possible to minimize a damage region caused by cracking, and a method for manufacturing an electronic device using the vapor deposition mask. A vapor deposition mask according to the present invention has a first surface facing a substrate subject to vapor deposition, and a second surface facing a vapor deposition source on the side opposite from the first surface, the vapor deposition mask having formed therein a plurality of openings that penetrate between the first surface and the second surface, the vapor deposition mask being characterized in that: a plurality of cell regions, each of which is composed of a collection of the openings, are arranged; and division grooves in which at least the outermost layer on the first-surface side is removed are formed between the cell regions. In the present invention, the division grooves are preferably formed so as to surround the cell regions.

Description

Evaporation mask and method for manufacturing electronic device

[0001] The present invention relates to a deposition mask and a method for manufacturing an electronic device.

[0002] For example, a deposition mask is known that is used to paint three colors, RGB, in the production of organic EL displays.

[0003] For example, Patent Document 1 describes a deposition mask made of an SOI substrate, in which a silicon layer functions as a mask. The silicon layer has a large number of openings. Patent Document 2 discloses an invention relating to a deposition mask having a first region and a second region surrounding the first region, in which a large number of openings are formed.

[0004] Patent Document 3 discloses an invention relating to a mask and support assembly having a mask including a plurality of cell portions and a support portion including a frame portion and a grid portion.

[0005] Korean Patent No. 10-2358269 Japanese Patent Publication No. 2022-175925 Japanese Patent Publication No. 2024-14701

[0006] References 1, 2 and 3 do not describe at all what to do when cracks occur in the deposition mask.

[0007] Patent Document 3 discloses an example in which slit lines are formed between cells (see FIG. 23 of Patent Document 3). The slit lines are formed in a grid pattern across the entire mask surface, reaching the outer periphery. As a result, the strength of the mask is significantly reduced. The reduced strength of the mask makes the mask more susceptible to deformation and cracks.

[0008] An object of the present invention is to provide a deposition mask that can minimize areas damaged by cracks, and a method for manufacturing an electronic device using the deposition mask.

[0009] The deposition mask of this embodiment has a first surface facing a substrate to be deposited, a second surface facing a deposition source on the opposite side of the first surface, and an outer periphery edge surrounding the peripheries of the first surface and the second surface, and is a deposition mask in which a plurality of openings penetrating between the first surface and the second surface are formed, and is characterized in that a plurality of cell regions each consisting of a group of the plurality of openings are arranged, and dividing grooves are formed between each cell region by removing at least the outermost layer on the first surface side, and the dividing grooves do not reach the outer periphery edge.

[0010] According to the present invention, each cell region is separated by a dividing groove, and the dividing groove is formed so that it does not reach the outer peripheral edge. This makes it possible to maintain the strength of the mask while containing the crack within the cell region in which it has occurred and preventing the crack from spreading to other cell regions.

[0011] 1 is a plan view showing a deposition mask according to a first embodiment; FIG. 2 is a cross-sectional view of the deposition mask shown in FIG. 1 cut along line AA and viewed from the direction of the arrow; FIG. 3 is a partially enlarged plan view showing a plurality of cell regions of the deposition mask; FIG. 4 is a plan view showing an example of a deposition mask according to a second embodiment; FIG. 5 is a plan view showing an example of a deposition mask according to a third embodiment; FIG. 6 is a plan view showing an example of a deposition mask according to a fourth embodiment; FIG. 7 is a plan view showing an example of a deposition mask according to a fifth embodiment; FIG. 8 is a plan view showing an example of a deposition mask according to a sixth embodiment; FIG. 9 is a partially enlarged cross-sectional view of a deposition mask showing a different configuration of a support portion; FIG. 10 is a cross-sectional view showing a manufacturing method of an electronic device using the deposition mask according to the present embodiment; FIG. 11 is a process diagram showing a first manufacturing method of a deposition mask; FIG. 12 is a process diagram showing a second manufacturing method of a deposition mask; FIG. 13 is a process diagram showing a third manufacturing method of a deposition mask; FIG. 14 is a process diagram showing a fourth manufacturing method of a deposition mask; FIG. 15 is a process diagram showing a fifth manufacturing method of a deposition mask; FIG. 16 is a process diagram showing a sixth manufacturing method of a deposition mask; FIG. 17 is a plan view showing a conventional deposition mask; FIG. 18 is a cross-sectional view showing an example of a deposition mask according to another embodiment; FIG. 19 is a cross-sectional view showing an example of a deposition mask according to another embodiment;

[0012] Hereinafter, embodiments will be described with reference to the drawings. However, the drawings are schematic or conceptual, and the dimensions and ratios of each drawing are not necessarily the same as those in reality. Furthermore, even when the same parts are shown between drawings, the dimensional relationships and ratios between them may be different. In particular, the embodiments shown below are illustrative of structures for embodying the technical idea of ​​the present invention, and do not specify the technical idea of ​​the present invention. In the following description, elements having the same function and configuration are designated by the same reference numerals, and redundant description will be omitted. Furthermore, the lower and upper limits of numerical ranges include a margin of error. Furthermore, the notation "to" includes both the lower and upper limits.

[0013] <Background to the Invention> Vapor deposition masks used for painting different colors of RGB in the production of OLED displays are known, and there is a growing need for vapor deposition masks for painting different colors of RGB.

[0014] In the manufacture of high-definition OLED display devices, a thinner deposition mask is desired to improve the efficiency of deposition using the deposition mask, because a thicker deposition mask increases the shadow effect caused by deposition material accumulating in the openings when a deposited film is formed on a substrate through the openings of the deposition mask, thereby reducing the shape stability of the deposited film.

[0015] However, when the deposition mask is thinned, cracks C are likely to occur in the deposition mask 30 due to the influence of deformation caused by bending of the deposition mask due to its own weight and stress imbalance in the manufacturing process, as shown in Fig. 17. If the crack C first occurs at point D, it will spread from this point toward the edge of the deposition mask 30, causing a problem of the mask damage area spreading over a wide area.

[0016] Furthermore, in Patent Document 3, lattice-shaped slit lines are formed that reach the outer periphery. However, extending the slit lines to both ends in this manner significantly reduces the strength of the mask. This makes the mask more susceptible to distortion and cracks. For example, if a crack occurs at the position of a slit line, it will run in a straight line from one end to the other. This tendency for the mask to distort also makes it more likely for cracks to occur within the cell region.

[0017] Therefore, as a result of intensive research, the inventors have developed a deposition mask that can maintain the strength of the mask and minimize the occurrence of cracks by separating cell regions, which are groups of multiple openings, with grooves and forming the grooves so that they do not reach the outer periphery.

[0018] <Overview of deposition mask 1 according to the present embodiment> Fig. 1 is a cross-sectional view of a deposition mask 1 according to the present embodiment. Fig. 2 is a cross-sectional view of the deposition mask shown in Fig. 1 cut along line AA and viewed from the direction of the arrows. Fig. 3 is a partially enlarged plan view showing a plurality of cell regions of the deposition mask. Fig. 9 is a partially enlarged cross-sectional view of a deposition mask showing a different configuration of the support portion.

[0019] 1 and 2 , the deposition mask 1 has a laminated structure of a membrane 2 and a support 3. The membrane 2 is a substrate including a first surface 2 a and a second surface 2 b that face each other in the thickness direction, and an outer peripheral edge 2 c that surrounds the outer periphery between the first surface 2 a and the second surface 2 b. The thickness of the membrane 2 is not limited, but is 0.5 μm or more and 50 μm or less, preferably 0.5 μm or more and 10 μm or less, and more preferably 0.5 μm or more and 7.5 μm or less.

[0020] The outer peripheral shape of the membrane 2 is preferably a rectangular or disc-shaped wafer, and although there are no restrictions on the diameter (the length of one side in the case of a rectangle), it is preferably about 100 mm to 500 mm.

[0021] Although not limited thereto, the membrane 2 is formed of a single layer or multiple layers. In Fig. 2, the membrane 2 has a laminated structure of a first layer 4 and a second layer 5, the first layer 4 being the layer that is bonded to the support portion 3, and the second layer 5 being the outermost layer of the membrane 2. The first layer 4 and the second layer 5 are each formed of a Si layer, a SiN layer, or a SiO ２ For example, the first layer 4 is preferably formed of a SiO ２ The second layer 5 is a Si layer. However, this is just an example, and the membrane 2 may be a single layer. Alternatively, the membrane 2 may have a laminated structure of three or more layers.

[0022] 1 and 2, a plurality of cell regions 6 are formed in the membrane 2. In Fig. 1 and 2, only one representative cell region 6 is labeled with a reference numeral.

[0023] 1 and 2, between adjacent cell regions 6, there is a region of a predetermined width where no openings 10 are formed (referred to as a "boundary region 7"). As shown in FIG. 1, the plurality of cell regions 6 are arranged in a matrix with the boundary region 7 interposed therebetween. The region where the plurality of cell regions 6 are gathered is referred to as a cell array region 8. Between the cell array region 8 and the end of the membrane 2 is a peripheral region 9.

[0024] As shown in Figures 1 and 2, each cell region 6 is made up of a collection of multiple openings 10. The openings 10 penetrate from the first surface 2a to the second surface 2b of the membrane 2. While Figure 1 shows that a large number of openings 10 are formed in each cell region 6, Figure 2 shows the number of openings 10 reduced and the width of the openings 10 enlarged to make the cross-sectional shape easier to see. As shown in Figure 10, the first surface 2a is the surface facing the deposition substrate 11, and the second surface 2b is the back surface facing the deposition source 12.

[0025] The planar pattern of the openings 10 (the shape when viewed from directly above the membrane 2 toward the first surface 2a) is not limited to any particular shape, and examples include polygons, circles, and ellipses. All of the openings 10 may have the same planar pattern, or some of them may have different patterns. The openings 10 may be arranged regularly, irregularly, or a mixture of regular and irregular patterns.

[0026] The support portion 3 will now be described. As shown in Fig. 2, the support portion 3 is provided on the second surface 2b side of the membrane 2.

[0027] The support part 3 is based on a Si substrate, and the Si substrate is etched away to leave only the necessary portions. The thickness (height) of the support part 3 is not limited, but is, for example, about 100 μm to 1000 μm.

[0028] As shown in FIG. 2, the support portion 3 is not provided in the cell region 6 of the membrane 2, and therefore the cell region 6 is open to both the first surface 2a and the second surface 2b.

[0029] In FIG. 2 , the support parts 3 are provided in the boundary region 7 and the outer peripheral region 9 of the membrane 2, but they may be provided only in the outer peripheral region 9. The membrane 2 can be maintained in a taut state by the support parts 3, eliminating the need for a tensioning process, and the deposition mask 1 of this embodiment can also be closely attached to the deposition substrate 11 using an electrostatic chuck that utilizes electrostatic force. Note that, as shown in FIG. 2 , the support parts 3 provided in the boundary region 7 and the outer peripheral region 9 all have the same height, but, for example, the height of the support parts 3 provided in the boundary region 7 may be lower than the height of the support parts 3 provided in the outer peripheral region 9. However, by making the heights the same, greater strength can be maintained.

[0030] 1 and 2 , division grooves 20 are formed in the boundary region 7 between adjacent cell regions 6 and on the outer periphery of the cell array region 8 (the outer periphery of the cell region 6 located on the outer side). The division grooves 20 do not reach the outer periphery end 2 c.

[0031] The dividing grooves 20 are formed by removing at least the outermost layer of the membrane 2 so that adjacent cell regions 6 are not continuous at least in the outermost layer. In the embodiment shown in FIG. 2 , the second layer 5, which is the outermost layer of the membrane 2, is removed to form the dividing grooves 20. In this case, the second layer 5 is not connected as a "layer" and only a small amount of the constituent elements of the second layer 5 has been analyzed, which can be considered to be "the second layer 5 has been removed." In this embodiment, it is preferable that the second layer 5 is completely removed to form the dividing grooves 20.

[0032] The dividing grooves 20 shown in Fig. 1 continuously surround the periphery of each cell region 6, and are formed separately from the dividing grooves 20 surrounding adjacent cell regions 6. Therefore, two dividing grooves 20 are formed between adjacent cell regions 6. Note that "continuously surrounding" refers to a state of surrounding without a break.

[0033] In this way, it is preferable that the division grooves 20 are provided in the cell array region 8, which is a region where a plurality of cell regions 6 are gathered, and are not formed in the outer periphery region 9. At the very least, the division grooves 20 do not reach the outer periphery edge 2c. In this way, the division grooves 20 are not formed over the entire first surface 2a, but are arranged only in the central region of the first surface 2a, which is spaced inward from the outer periphery edge 2c.

[0034] Although not limited thereto, the distance t between the dividing groove 20 closest to the outer circumferential edge 2c and the outer circumferential edge 2c may be approximately the thickness of the deposition mask 1, and may be, for example, 100 μm to 1000 μm, but may also be 1000 μm or more. In the present embodiment, the number of dividing grooves 20 formed in the boundary region 7 is not limited. Furthermore, even if there is a region in which the cell region 6 cannot be surrounded by the dividing grooves 20, it is sufficient that the dividing grooves 20 can separate the cell region 6 from adjacent cell regions.

[0035] It is also preferable that the dividing grooves 20 penetrate through the membrane 2. As in the embodiment shown in Figure 2, it is preferable that the dividing grooves 20 are formed not only through the outermost second layer 5 but also through to the first layer 4.

[0036] Fig. 3 is an enlarged view of the cell region 6 and its surroundings shown in Fig. 1. In processing the membrane 2, the openings 10 can be formed by dry etching, and the dividing grooves 20 can be formed by dry etching or wet etching.

[0037] Here, the width of the cell region 6 is defined as W1, the width of the dividing groove 20 as W2, and the width of the adjacent cell region 6 as W3 (which roughly corresponds to the width of the boundary region 7). Although not limited thereto, the width W1 is approximately 5 mm to 80 mm, the width W2 is approximately 5 μm to 1000 μm, and the width W3 is approximately 1 mm to 40 mm. When viewed from the entire membrane 2, the dividing groove 20 is formed as a very thin linear groove.

[0038] Furthermore, the width dimension W2 of the dividing groove 20 does not have to be uniform overall; for example, in a partitioned area where cracks C are likely to occur (e.g., near the center of the membrane 2), the width of the dividing groove 20 may be made wider than in other partitioned areas (e.g., near the ends of the membrane 2).

[0039] Furthermore, the dividing grooves 20 do not have to be linear, and may be serpentine, zigzag, curved, or the like, as long as they can separate the cell regions 6. However, from the viewpoint of ease of forming the dividing grooves 20, linear shapes are preferable.

[0040] 9A, the support parts 3 formed on the second surface 2b side of the membrane 2 are configured in one of two ways: as shown in Fig. 9A, a configuration in which the support parts 3 are formed by dividing each cell region 6 (referred to as "pattern A"), and as shown in Fig. 9B, a configuration in which at least some of the support parts 3 dividing each cell region 6 are removed from Fig. 9A (referred to as "pattern B"). In both Fig. 9A and Fig. 9B, the support parts 3 are formed in the outer peripheral region 9 (see Fig. 2).

[0041] The configuration of Figure 9B cannot be realized if the membrane 2 has a single-layer structure (since the dividing grooves 20 penetrate the membrane 2, a support part 3 is required to support each cell region 6 on the second surface 2b side), so as shown in Figure 9B, the membrane 2 is formed, for example, with a laminated structure of a first layer 4 and a second layer 5 as the outermost layer, and at the dividing grooves 20, the second layer 5 is removed while the first layer 4 is left as is.

[0042] The support portion 3 is formed of a single layer or multiple layers. The support portion 3 may be formed of a Si layer, a SiO ２ It is preferable that the insulating layer includes at least one of a silicon nitride layer and a silicon nitride layer.

[0043] 9A and 9B, a layer of the same material as the second layer 5 serving as the outermost surface of the membrane 2 is preferably formed on the rear surface 3a of the support 3. For example, if the second layer 5 is a SiN layer, the SiN layer is formed on the rear surface 3a of the support 3, and the second layer 5 is formed of SiO ２ In the case of a layer, the back surface 3a of the support portion 3 is provided with SiO ２ This allows for a balance of stress to be maintained, and warping and other problems to be prevented.

[0044] In this embodiment, by separating the cell regions 6 with dividing grooves 20, even if a crack C occurs in the cell region 6a, as shown in FIG. 1, the crack C can be contained within the cell region 6a, and the area of ​​mask damage caused by the crack C can be minimized.

[0045] The dividing grooves 20 penetrate the membrane 2, so that the cell regions 6 can be reliably separated from each other, and the cracks C can be reliably contained only within the cell region in which they occur.

[0046] 1, by forming the dividing grooves 20 so as to surround each cell region 6, it is possible to appropriately divide each cell region 6, and it is also possible to control the dividing grooves 20 so that they do not reach the outer peripheral edge 2c. As a result, each cell region 6 can be divided by the dividing grooves 20 while maintaining the mask strength, so that even if a crack C occurs in any divided region, the crack C can be contained only within the divided region in which the crack C occurred, and the mask damage region can be minimized.

[0047] 1 and 3, the dividing grooves 20 are formed so as to individually surround each cell region 6. As a result, two dividing grooves 20 exist between each cell region 6. In this way, the presence of multiple dividing grooves 20 makes it possible to properly separate each cell region 6 even if, for example, one of the dividing grooves 20 has an interrupted portion, and the effect of providing the dividing grooves 20 (reduction of mask damaged regions) can be reliably achieved.

[0048] 3, a plurality of dividing grooves 20 provided between cell regions 6 can be connected by connecting grooves 21. This allows the regions partitioned by the dividing grooves 20 to be further subdivided, making it easier to reliably achieve the effect of providing the dividing grooves 20 (reduction of mask damage regions).

[0049] <Detailed Description of Dividing Groove 20 in Other Embodiments> The configuration of the dividing groove 20 is not limited to that shown in Fig. 1. For example, the configurations shown in Figs.

[0050] In the second embodiment shown in Fig. 4, the dividing grooves 20 are formed intermittently. As shown in Fig. 4, each dividing groove 20 is arranged so as to surround the periphery of each cell region 6. Also, as shown in Fig. 4, each dividing groove 20 is arranged so that each intermittent portion 20a does not face each other in the row and column direction. Therefore, each intermittent portion 20a faces an adjacent dividing groove 20 in the row and column direction, and adjacent cell regions 6 do not communicate linearly via the intermittent portion 20a.

[0051] 5, the dividing grooves 20 are also formed intermittently, but in Fig. 5, the dividing grooves 20 are arranged with a shift in the row and column direction so that the intermittent portions 20a of adjacent dividing grooves 20 do not face each other in the row and column direction between the cell regions 6. In Fig. 5, the length of each dividing groove 20 is equal to or greater than half the length of one side of the cell region 6. Therefore, by shifting the multiple dividing grooves 20 between the cell regions 6, adjacent cell regions 6 do not communicate linearly through the intermittent portions 20a.

[0052] In both of the embodiments shown in Figures 4 and 5, the dividing grooves 20 are provided with intermittent portions 20a, which effectively maintains the mask strength. In addition, by arranging the dividing grooves 20 in a staggered manner so that the intermittent portions 20a do not face each other, cracks are less likely to occur in adjacent cell regions 6 through the intermittent portions 20a, and therefore the area of ​​mask damage due to cracks can be minimized.

[0053] In the fourth embodiment shown in Figure 6, each cell region 6 is surrounded by a continuous dividing groove 20. However, unlike Figure 1, the dividing grooves 20 extend continuously between the cell regions 6, are arranged in a lattice pattern, and surround the outer periphery of the cell array region 8. Therefore, in Figure 6, each cell region 6 is not surrounded by an individual dividing groove 20, but a common dividing groove 20 is arranged between adjacent cell regions 6. In Figure 6, the dividing grooves 20 do not extend to the outer peripheral end 2c, so the mask strength can be maintained. However, in Figure 6, if a crack occurs at the position of the dividing groove 20, it is likely to spread linearly, so it is preferable to provide intermittent portions 20a as in Figures 4 and 5.

[0054] In the fifth embodiment shown in Fig. 7, the cell regions 6 are arranged in a staggered pattern. This effectively minimizes the area of ​​the mask that is damaged by cracks while maintaining the mask strength. In other words, cracks are less likely to occur linearly than when the cell regions 6 are arranged in a matrix, and the occurrence of cracks can be limited to a narrower range.

[0055] In the sixth embodiment shown in Fig. 8, an intermittent portion 20a is provided in the dividing groove 20 surrounding each cell region 6 shown in Fig. 6. By providing the intermittent portion 20a, the mask strength can be increased compared to the embodiment shown in Fig. 6.

[0056] 10 , the deposition mask 1 is placed between a substrate 11 to be deposited and a deposition source 12. At this time, the first surface 2 a of the membrane 2 of the deposition mask 1 faces the substrate 11 to be deposited, and the second surface 2 b of the membrane 2 faces the deposition source 12. A plurality of openings 10 are formed in the membrane 2, and, for example, the opening width is narrower on the first surface side than on the second surface side.

[0057] The deposition mask 1 is placed on a holder (not shown) of a deposition device, and an electrostatic chuck can be used to fix the deposition mask 1 and the deposition substrate 11. The membrane 2 and the deposition substrate 11 are spaced apart from each other, but they may also be in contact with each other. The deposition mask 1 and the deposition substrate 11 are rotated around the axis of the holder.

[0058] The deposition material (deposition particles) 13 from the deposition source 12 passes through the openings 10 in the deposition mask 1 and reaches the surface 11 a of the deposition substrate 11 , forming a deposition film 14 .

[0059] In this embodiment, examples of electronic devices include OLED microdisplay panels, liquid crystal panels, solar cells, etc., and the present invention is particularly suited to a method for manufacturing an OLED microdisplay panel as an organic electronic device.

[0060] The deposition mask 1 of this embodiment can minimize the area of ​​the mask that is damaged by cracks. Therefore, the deposition mask 1 can be used to form a deposition film 14 having a desired pattern width with high precision, thereby improving yield.

[0061] <Method of Manufacturing the Vapor Deposition Mask 1 in the Present Embodiment> Fig. 11 is a process chart showing a first method of manufacturing the vapor deposition mask. ２ An SOI substrate 25 consisting of a layer 23 and a Si layer 24 is prepared. Then, an outermost layer 26 of a membrane is formed on the surface of the SOI substrate 25. The outermost layer 26 may be, but is not limited to, a SiN layer or a SiO ２ Formed in layers.

[0062] 11B, dividing grooves 20 that separate the cell regions 6 are formed by etching on the surface of the outermost layer 26 using a mask pattern (not shown). Next, in the step of FIG. 11C, a plurality of openings 10 are formed in the cell region 6 by etching using a mask pattern (not shown). At this time, the openings 10 are formed in the Si layer 24 and the outermost layer 26 of the SOI substrate. Therefore, the membrane 2 is composed of two layers: the Si layer 24 and the outermost layer 26.

[0063] Next, in FIG. 11D, the Si substrate 22 and SiO ２ The layer 23 is etched from the rear surface side. At this time, the Si substrate 22 and the SiO ２ The layer 23 is removed, leaving the other portions, thereby forming the support portion 3 in the peripheral region 9 and the boundary region 7 of the membrane 2.

[0064] Alternatively, as shown in FIG. 11E from the step of FIG. 11A, the opening 10 in the cell region 6 and the dividing groove 20 surrounding the cell region 6 may be simultaneously formed by etching using a mask pattern (not shown). As shown in FIG. 11E, the outermost layer 26 and the Si layer 24 are etched to form the opening 10 and the dividing groove 20. Next, as shown in FIG. 11F, the Si substrate 22 of the SOI substrate 25 is etched from the backside. At this time, the Si substrate 22 facing the cell region 6 of the membrane 2 is removed, leaving other areas. As a result, the support portion 3 is formed in the peripheral region 9 and boundary region 7 of the membrane 2.

[0065] 12A and 12B are process diagrams showing a second method for manufacturing a deposition mask. ２ An SOI substrate 25 consisting of a layer 23 / Si layer 24 is prepared.

[0066] 12B, the dividing grooves 20 that separate the cell regions 6 are formed by etching the Si layer 24, which is the outermost layer, using a mask pattern (not shown). At this time, the dividing grooves 20 are formed by etching the Si layer 24 with SiO ２ Layers up to 23 are formed.

[0067] 12C, a mask pattern (not shown) is used to form a plurality of openings 10 in the cell region 6 by etching. At this time, the openings 10 are formed only in the Si layer 24. Therefore, in this embodiment, the membrane 2 is composed of a single layer of the Si layer 24.

[0068] Next, in FIG. 12D, the Si substrate 22 and SiO ２ The layer 23 is etched from the rear surface side. At this time, the Si substrate 22 and the SiO ２The layer 23 is removed, leaving the other portions, thereby forming the support portion 3 in the peripheral region 9 and the boundary region 7 of the membrane 2.

[0069] 12A to 12E, the opening 10 in the cell region 6 and the dividing groove 20 surrounding the cell region 6 may be simultaneously formed by etching using a mask pattern (not shown). As shown in Fig. 12E, the outermost Si layer 24 is etched to form the opening 10 and the dividing groove 20. Therefore, in this embodiment, the membrane 2 is composed of a single layer of the Si layer 24.

[0070] Next, in FIG. 12F, the Si substrate 22 and SiO ２ The layer 23 is etched from the rear surface side. At this time, the Si substrate 22 and the SiO ２ The layer 23 is removed, leaving the other portions, thereby forming the support portion 3 in the peripheral region 9 and the boundary region 7 of the membrane 2.

[0071] 13A and 13B are process diagrams showing a third method for manufacturing a deposition mask. ２ An SOI substrate 25 consisting of a layer 23 and a Si layer 24 is prepared. Then, the outermost layer 26 of the membrane 2 is formed on the surface of the SOI substrate 25. Although not limited thereto, the outermost layer 26 may be a SiN layer or a SiO ２ Formed in layers.

[0072] 13B, dividing grooves 20 that separate the cell regions 6 are formed by etching in the outermost layer 26 using a mask pattern (not shown). Next, in the step of FIG. 13C, a plurality of openings 10 are formed in the cell region 6 by etching using a mask pattern (not shown). As shown in FIG. 13C, the openings 10 are formed in the outermost layer 26, the Si layer 24, and the SiO ２ The membrane 2 is formed up to the layer 23. ２ The silicon layer 23 , the silicon layer 24 , and the outermost layer 26 constitute a three-layer structure.

[0073] 13D , the Si substrate 22 of the SOI substrate 25 is etched from the back surface side. At this time, the Si substrate 22 facing the cell region 6 of the membrane 2 is removed, and other portions are left. As a result, the support portion 3 is formed in the outer periphery region 9 and boundary region 7 of the membrane 2.

[0074] 13A to 13E, the opening 10 in the cell region 6 and the dividing groove 20 surrounding the cell region 6 may be simultaneously formed by etching using a mask pattern (not shown). ２ The membrane 2 is then etched down to the layer 23 to form the openings 10 and the dividing grooves 20. ２ The silicon layer 23 , the silicon layer 24 , and the outermost layer 26 constitute a three-layer structure.

[0075] 13F, the Si substrate 22 of the SOI substrate 25 is etched from the back surface side. At this time, the Si substrate 22 facing the cell region 6 of the membrane 2 is removed, and other portions are left. As a result, the support portion 3 is formed in the outer periphery region 9 and boundary region 7 of the membrane 2.

[0076] 14A and 14B are process diagrams showing a fourth method for manufacturing the deposition mask 1. In FIG. ２ An SOI substrate 25 consisting of a layer 23 / Si layer 24 is prepared.

[0077] 14B, dividing grooves 20 that separate the cell regions 6 are formed by etching on the surface of the Si layer 24 using a mask pattern (not shown). Next, in the step of FIG. 14C, a plurality of openings 10 are formed in the cell region 6 by etching using a mask pattern (not shown). At this time, the openings 10 are formed in the Si layer 24 and the SiO ２ The membrane 2 is then formed up to the layer 23. ２ The layer 23 and the Si layer 24 are stacked together.

[0078] 14D , the Si substrate 22 of the SOI substrate 25 is etched from the back surface side. At this time, the Si substrate 22 facing the cell region 6 of the membrane 2 is removed, and other portions are left. As a result, the support portion 3 is formed in the outer periphery region 9 and boundary region 7 of the membrane 2.

[0079] 14A to 14E, the opening 10 in the cell region 6 and the dividing groove 20 surrounding the cell region 6 may be simultaneously formed by etching using a mask pattern (not shown). ２ The layer 23 is etched to form the openings 10 and the dividing grooves 20. As a result, the membrane 2 is ２ The layer 23 and the Si layer 24 are stacked together.

[0080] 14F, the Si substrate 22 of the SOI substrate 25 is etched from the back surface side. At this time, the Si substrate 22 facing the cell region 6 of the membrane 2 is removed, and other portions are left. As a result, the support portion 3 is formed in the outer periphery region 9 and boundary region 7 of the membrane 2.

[0081] 15A is a process diagram showing a fifth method for manufacturing the deposition mask 1. In FIG. 15A, a Si substrate 22 is prepared, and a first layer 27 and a second layer 28 are laminated on the surface of the Si substrate 22. For example, the first layer 27 is made of, but is not limited to, SiO ２ Alternatively, the first layer 27 may be a SiN layer and the second layer 28 may be a SiO ２ Formed in layers.

[0082] 15B, dividing grooves 20 that separate the cell regions 6 are formed by etching in the second layer 28, which serves as the outermost layer, using a mask pattern (not shown). Next, in the step of FIG. 15C, a plurality of openings 10 are formed in the cell region 6 by etching using a mask pattern (not shown). At this time, the openings 10 are formed from the second layer 28 to the first layer 27. As a result, the membrane 2 is formed with a stacked structure of the first layer 27 and the second layer 28.

[0083] 15D, the Si substrate 22 is etched from the rear surface side. At this time, the Si substrate 22 facing the cell region 6 of the membrane 2 is removed, and other portions are left. As a result, the support portion 3 is formed in the outer periphery region 9 and boundary region 7 of the membrane 2.

[0084] 15A to 15E, the opening 10 in the cell region 6 and the dividing groove 20 surrounding the cell region 6 may be simultaneously formed by etching using a mask pattern (not shown). As shown in Fig. 15E, etching is performed from the second layer 28 to the first layer 27 to form the opening 10 and the dividing groove 20. As a result, the membrane 2 is formed with a laminated structure of the first layer 27 and the second layer 28.

[0085] 15F, the Si substrate 22 is etched from the back surface side. At this time, the Si substrate 22 facing the cell region 6 of the membrane 2 is removed, and other portions are left. As a result, the support portion 3 is formed in the outer periphery region 9 and boundary region 7 of the membrane 2.

[0086] 16A is a process chart showing a fifth method for manufacturing the vapor deposition mask 1. In Fig. 16A, a Si substrate 22 is prepared, and an outermost layer 29 is laminated on the surface of the Si substrate 22. Although not limited thereto, the outermost layer 29 is formed of a SiN layer, for example.

[0087] 16B, dividing grooves 20 that separate the cell regions 6 are formed by etching in the outermost layer 29 using a mask pattern (not shown), and then, as shown in Fig. 16C, a plurality of openings 10 are formed in the cell regions 6 by etching. Alternatively, the dividing grooves 20 in Fig. 16B and the openings 10 in Fig. 16C may be formed simultaneously. As a result, the membrane 2 is formed with a single-layer structure consisting of only the outermost layer 29.

[0088] 16D, the Si substrate 22 is etched from the back surface side. At this time, the Si substrate 22 facing the cell region 6 of the membrane 2 is removed, and other portions are left. As a result, the support portion 3 is formed in the outer periphery region 9 and boundary region 7 of the membrane 2.

[0089] In this embodiment, a SiO film is formed on the surface of the SOI substrate 25 or the surface of the Si substrate 22, and includes at least the outermost layer of the membrane 2. ２ The SiN layer and the SiN layer can be formed by plasma enhanced chemical vapor deposition (PE-CVD).

[0090] In the above, the dividing groove 20 is formed before the opening 10 is formed, or the dividing groove 20 is formed simultaneously with the opening 10, but the dividing groove 20 can also be formed after the opening 10 is formed.

[0091] When the dividing grooves 20 and the openings 10 are formed simultaneously, the dividing grooves 20 and the openings 10 can be formed at one time by using a large mask pattern including the patterns of the dividing grooves 20 and the openings 10, thereby improving manufacturing efficiency. Alternatively, in a configuration in which each cell region 6 is surrounded by a dividing groove 20 as shown in Figure 3, the patterns of the dividing grooves 20 and the openings 10 can be formed for each cell region 6 using a mask with a unit pattern of the cell region 6 and the dividing grooves 20 surrounding it.

[0092] On the other hand, when the division grooves 20 and the openings 10 are formed in separate steps, the division grooves 20 and the openings 10 can be formed separately using a mask having a pattern for the division grooves 20 and a mask having a pattern for the openings 10. In this case, the depth of the division grooves 20 and the depth (height) of the openings 10 can be changed by changing the etching conditions.

[0093] Although the embodiments and modifications have been described, other embodiments may be obtained by combining the above embodiments and modifications in whole or in part.

[0094] Furthermore, the present invention is not limited to the above-described embodiments and modifications, and may be variously changed, substituted, or modified within the scope of the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way due to technological advances or other derived technologies, it may be implemented using that method. Therefore, the claims cover all embodiments that may fall within the scope of the technical idea.

[0095] For example, as shown in FIG. 18, a silicon substrate 32 having a frame shape is coated with a film of SiN or SiO ２The membrane 31 may be formed in a central region from which the silicon substrate 32 has been removed, and the plurality of openings 10 and dividing grooves 20 may be formed in the membrane 31. The membrane is formed by CVD, but it is preferable to use SiN from the viewpoint of ease of stress control.

[0096] In addition, in this embodiment, a deposition mask can be configured by combining an SOI substrate and a SiN layer. In Fig. 19, a SiN layer 45 is formed on the back side (support substrate 44 side, the side facing the deposition source 12) of an SOI substrate 39. In Fig. 20, a SiN layer 45 is formed on the front side (semiconductor layer 42 side, the side facing the deposition substrate 11) of the SOI substrate 39. In Fig. 21, a SiN layer 45 is formed on both the back side and the front side of the SOI substrate 39. In a configuration in which the SiN layer 45 is formed on the front side (semiconductor layer 42 side) of the SOI substrate 39, an opening 10 is formed continuous with the semiconductor layer 42.

[0097] By providing the SiN layer 45, stress control of the deposition mask is facilitated and distortion, etc. can be suppressed. Furthermore, the SiN layer 45 formed on the front side of the SOI substrate 39 is preferably thinner than the SiN layer 45 formed on the back side of the SOI substrate 39. Although not limited thereto, the thickness of the SiN layer 45 formed on the front side of the SOI substrate 39 is approximately 0.05 μm to 0.5 μm, and the thickness of the SiN layer 45 formed on the back side of the SOI substrate 39 is approximately 0.05 μm to 3 μm. Because the semiconductor layer 42 is thinner than the support substrate 44 and also has numerous openings 10 formed in the semiconductor layer 42, the SiN layer 45 formed on the front side of the SOI substrate 39 is thinner than the SiN layer 45 formed on the back side of the SOI substrate 39 to achieve balanced stress control between the front side and the back side.

[0098] The openings 10 can be formed in the SOI substrate 39 by using the Bosch process, and in the SiN layer 45 by dry etching. The same applies to the dividing grooves 20.

[0099] In addition, in this embodiment, at least one of the support 3 and the membrane 2 may have a polycrystalline silicon structure. Since polycrystalline silicon does not have a clear cleavage plane, it is less likely to break in the cleavage direction than single-crystal silicon, which has a cleavage plane. Although it is technically difficult to produce a large substrate from a single-crystal silicon material, using a polycrystalline silicon structure for the deposition mask 1 makes it easy to form a silicon substrate larger than a single-crystal silicon substrate. Furthermore, by making the planar shape of the deposition mask 1 polygonal (e.g., rectangular), the chamfering efficiency can be improved compared to a round deposition mask 1, and the number of surfaces can also be increased. A large-sized silicon substrate is preferably 500 mm x 500 mm or larger.

[0100] The effects of the present invention will be explained below with reference to examples and comparative examples, but the present invention is not limited to the following examples.

[0101] Experiments were conducted to confirm the effect of suppressing mask breakage using the samples of Experimental Examples 1 to 9 and Comparative Examples 1 and 2. Table 1 below shows the membrane configuration, presence or absence of dividing grooves, and configuration of the support part for each sample.

[0102]

[0103] (Experimental Example 1) A deposition mask of Experimental Example 1 was formed using the manufacturing method of Fig. 11. The membrane of Experimental Example 1 had a laminated structure of a Si layer / SiN layer. In Experimental Example 1, two samples were fabricated as the rear surface pattern of the support portion: Pattern A of Fig. 9A and Pattern B of Fig. 9B.

[0104] (Experimental Example 2) A deposition mask of Experimental Example 2 was formed using the manufacturing method of FIG. 11. The membrane of Experimental Example 2 was a Si layer / SiO ２ In Experimental Example 1, two samples were produced as the rear surface pattern of the supporting portion, that is, pattern A in FIG. 9A and pattern B in FIG. 9B.

[0105] (Experimental Example 3) A deposition mask of Experimental Example 3 was formed using the manufacturing method of Fig. 12. The membrane of Experimental Example 2 had a single-layer Si structure. In Experimental Example 3, a sample of Pattern A in Fig. 9A was fabricated as the rear surface pattern of the support portion.

[0106] (Experimental Example 4) A deposition mask of Experimental Example 4 was formed using the manufacturing method of FIG. 13. The membrane of Experimental Example 4 was made of SiO ２ In Experimental Example 4, two samples were fabricated as the rear surface pattern of the support portion, that is, pattern A in FIG. 9A and pattern B in FIG.

[0107] (Experimental Example 5) A deposition mask of Experimental Example 5 was formed using the manufacturing method of FIG. 13. The membrane of Experimental Example 5 was made of SiO ２ Layer / Si / SiO ２ In Experimental Example 5, two samples were produced as the rear surface pattern of the supporting portion, that is, pattern A in FIG. 9A and pattern B in FIG. 9B.

[0108] (Experimental Example 6) A deposition mask of Experimental Example 6 was formed using the manufacturing method of FIG. 14. The membrane of Experimental Example 6 was made of SiO ２ In Experimental Example 6, two samples were fabricated as the rear surface pattern of the support portion, that is, pattern A in FIG. 9A and pattern B in FIG. 9B.

[0109] Experimental Example 7 A deposition mask of Experimental Example 7 was formed using the manufacturing method of FIG. 15. The membrane of Experimental Example 7 was made of SiO ２ In Experimental Example 7, two samples were fabricated as the rear surface pattern of the support portion, that is, pattern A in FIG. 9A and pattern B in FIG.

[0110] (Experimental Example 8) A deposition mask of Experimental Example 8 was formed using the manufacturing method of FIG. 15. The membrane of Experimental Example 8 was a SiN layer / SiO ２ In Experimental Example 8, two samples were produced as the rear surface pattern of the support portion, that is, pattern A in FIG. 9A and pattern B in FIG. 9B.

[0111] (Experimental Example 9) A deposition mask of Experimental Example 9 was formed using the manufacturing method of Fig. 16. The membrane of Experimental Example 8 had a single-layer structure of a SiN layer. In Experimental Example 8, the rear surface pattern of the support portion was pattern A of Fig. 9A.

[0112] 1, in Experimental Examples 1 to 9, the dividing grooves 20 were formed so as to continuously surround the periphery of each cell region 6 and to be separate from the dividing grooves 20 surrounding adjacent cell regions 6. In none of the experimental examples did the dividing grooves 20 reach the outer peripheral end 2c.

[0113] In a configuration in which the dividing groove 20 reaches the outer peripheral end 2 c, if the outer peripheral end 2 c is cracked or broken when it comes into contact with the outer peripheral end 2 c during handling or removal from a device, the cracks will easily propagate from the end to the entire surface. Therefore, in an embodiment in which the dividing groove 20 does not reach the outer peripheral end 2 c, the effects of propagation can be suppressed.

[0114] (Comparative Example 1) This is a configuration in which the dividing groove is not provided in the configuration of Experimental Example 1. (Comparative Example 2) This is a configuration in which the dividing groove is not provided in the configuration of Experimental Example 7.

[0115] (Experiment to confirm the effect of suppressing mask breakage in each sample) The outer peripheral region of each sample was placed on a support stand, and a weight was placed on the center of the membrane. The membrane was then intentionally deflected to cause a crack. The weight was increased in 2 g increments until a crack occurred.

[0116] The occurrence of cracks was confirmed visually, and the crack initiation point was observed using an SEM (Regulus 8220 manufactured by Hitachi High-Technologies). Then, it was determined which cell regions the crack had propagated from the crack initiation point. The maximum number of cell regions that had propagated (number of cell damage regions) was calculated. The results are shown in Table 2 below.

[0117]

[0118] In all of Experimental Examples 1 to 9, which had dividing grooves, the cell damage region was 1, and it was confirmed that the cracks did not extend to other cell regions. Note that the experimental examples using back surface patterns A and B are examples in which the dividing grooves were formed by removing the outermost layer of the membrane, and the experimental example using only back surface pattern A is an example in which the dividing grooves penetrated the membrane, but in all cases the cell damage region remained at 1, and good results were obtained.

[0119] This application is based on Japanese Patent Application No. 2024-112077, filed on July 12, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. A deposition mask having a first surface facing a substrate to be deposited, a second surface opposite the first surface facing a deposition source, and an outer periphery surrounding the peripheries of the first surface and the second surface, and having a plurality of openings formed therein that penetrate between the first surface and the second surface, wherein a plurality of cell regions each consisting of a group of the plurality of openings are arranged, and between each cell region, dividing grooves are formed by removing at least the outermost layer on the first surface side, and the dividing grooves do not reach the outer periphery.

2. The deposition mask according to claim 1, wherein the dividing groove is formed so as to surround the cell region.

3. The deposition mask according to claim 2, wherein the dividing groove continuously surrounds the periphery of the cell region, and the separating grooves surrounding adjacent cell regions are separated from each other.

4. The deposition mask according to claim 1, wherein the dividing grooves intermittently surround the periphery of the cell region.

5. The deposition mask according to claim 2, wherein a plurality of the dividing grooves are arranged between the cell regions, and the plurality of dividing grooves are arranged so that the intermittent portions do not face each other.

6. The deposition mask according to claim 1, wherein the cell regions are arranged in a staggered pattern.

7. The deposition mask according to claim 1, wherein the dividing groove penetrates between the first surface and the second surface.

8. The deposition mask according to claim 1, comprising: a membrane on which a plurality of the cell regions are arranged; and a support portion formed on the second surface side of the membrane, at least in the outer peripheral region of the membrane.

9. The deposition mask according to claim 8, wherein the membrane is formed of a single layer or multiple layers.

10. The membrane is made of a Si layer, SiO ２ 10. The deposition mask according to claim 9, comprising at least one of a silicon nitride layer and a silicon nitride layer.

11. The deposition mask according to claim 9, wherein the total thickness of the membrane is 0.5 μm or more and 7.5 μm or less.

12. The deposition mask according to claim 8, wherein the supporting portion is formed of a single layer or multiple layers.

13. The support portion is made of a Si layer, SiO ２ The deposition mask according to claim 12, comprising at least one of a silicon nitride layer and a silicon nitride layer.

14. The deposition mask according to claim 1, characterized in that the deposition mask is made of an SOI substrate, and a SiN layer is formed on the front side, or the back side, or both the front side and the back side, on which the opening is formed.

15. The deposition mask according to claim 1, characterized in that the deposition mask has a structure in which a membrane having the opening is supported by a support, and at least one of the membrane and the support has a polycrystalline silicon structure.

16. A method for manufacturing an electronic device, comprising: using the deposition mask according to claim 1 between a substrate to be deposited and a deposition source; and depositing a deposition material onto the surface of the substrate through the openings.

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