Filter circuit and common mode noise filter

Abstract

A filter circuit (1) comprises: a first terminal (P1) and a second terminal (P2) which are each an input-output terminal for a high frequency signal for performing filter processing; a third terminal (P3) to be connected to a reference potential; a first inductor (11), a second inductor (21), a third inductor (12), and a fourth inductor (22); and a first capacitor (31) and a second capacitor (32). The third inductor (12) is magnetically coupled to the second inductor (21) in the forward direction. The fourth inductor (22) is magnetically coupled to the first inductor (11) in the forward direction. The first inductor (11) and the second inductor (21) are connected in series. The first inductor (11) is connected to the third inductor (12) via a first connection line (401). The third inductor (12) is connected to the first terminal (P1). The second inductor (21) is connected to the fourth inductor (22) via the second connection line (402). The fourth inductor (22) is connected to the second terminal (P2). The first capacitor (31) is connected between the second inductor (21) and the first connection line (401). The second capacitor (32) is connected between the first inductor (11) and the second connection line (402). An intermediate connection node (ND3) at which the first inductor (11) and the second inductor (21) are connected in series is connected to the third terminal (P3).

Description

Filter circuits, common mode noise filters

[0001] The present invention relates to a common mode noise filter and a filter circuit that can be used as a common mode noise filter.

[0002] Various common mode noise filters have been devised in the past. The common mode noise filter described in Patent Document 1 is configured using a pair of T-type circuits. The T-type circuit has first and second terminals through which high-frequency signals to be filtered are input and output. Two inductors are connected in series between the first and second terminals. The two series-connected inductors are magnetically coupled with a predetermined coupling coefficient k. The intermediate connection node of the two series-connected inductors is connected to the third terminal of the T-type circuit.

[0003] The common mode noise filter of Non-Patent Document 1 has a configuration in which one capacitor is connected in parallel to the series circuit of inductors in the T-type circuit shown in Patent Document 1. As a result, the common mode noise filter of Non-Patent Document 1 has improved filter characteristics compared to the common mode noise filter of Patent Document 1.

[0004] U.S. Patent No. 8,525,617

[0005] An Ultra-Compact Common Mode Bandstop Filter With Modified-T Circuits in Integrated Passive Device(IPD) Process

[0006] In the common mode noise filters disclosed in Patent Document 1 and Non-Patent Document 1, the smaller the difference in inductance between the two inductors connected in series between the input and output terminals, in other words, the smaller the difference in inductance between the two inductors connected to the intermediate connection node, the better the filter characteristics can be obtained. The best filter characteristics can be obtained when the inductances of the two inductors are the same.

[0007] However, when the circuits shown in Patent Document 1 and Non-Patent Document 1 are constructed using a circuit board in which a conductor pattern is formed on an insulating substrate, it is difficult to make the lengths of the two inductors the same.

[0008] For this reason, it is difficult to achieve the desired excellent filter characteristics with the circuit configurations shown in Patent Document 1 and Non-Patent Document 1.

[0009] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a filter circuit that can achieve desired excellent filter characteristics.

[0010] A filter circuit according to one embodiment of the present invention comprises a first terminal and a second terminal which are input / output terminals for high-frequency signals to be filtered, a third terminal for connection to a reference potential, a first inductor, a second inductor, a third inductor, a fourth inductor, a first capacitor, and a second capacitor.

[0011] The third inductor is magnetically coupled to the second inductor in a forward direction. The fourth inductor is magnetically coupled to the first inductor in a forward direction. The first inductor and the second inductor are connected in series. The first inductor is connected to the third inductor through a first connecting line. The third inductor is connected to a first terminal. The second inductor is connected to the fourth inductor through a second connecting line. The fourth inductor is connected to a second terminal. The first capacitor is connected between the second inductor and the first connecting line. The second capacitor is connected between the first inductor and the second connecting line. An intermediate connection node where the first inductor and the second inductor are connected in series is connected to a third terminal.

[0012] In this configuration, by providing the first connection line and the second connection line, the length of the first inductor and the length of the second inductor can be made the same, making their respective inductances the same and configuring a desired inductance. Furthermore, the length of the third inductor and the length of the fourth inductor can be made the same, making their respective inductances the same and configuring a desired inductance. Furthermore, by setting the positional relationship between the first inductor and the fourth inductor and the positional relationship between the second inductor and the third inductor to a desired relationship, it is possible to configure a desired magnetic field coupling between the first inductor and the fourth inductor, a desired magnetic field coupling between the second inductor and the third inductor, and a first capacitor and a second capacitor with a desired capacitance.

[0013] According to the present invention, desired excellent filter characteristics can be achieved.

[0014] FIG. 1 is a circuit diagram of a filter circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a common-mode noise filter according to an embodiment of the present invention. FIG. 3A is a graph showing the attenuation characteristics of a T-type filter circuit according to an embodiment of the present invention and a reference T-type filter circuit. FIG. 3B is a graph showing an example of the filter characteristics (pass characteristics for a pair of differential signals) of a common-mode noise filter according to an embodiment of the present invention (the common-mode noise filter of the present application) and a reference common-mode noise filter. FIG. 4 is a circuit diagram of a reference T-type filter circuit. FIG. 5 is a plan view showing an example of the structure of a filter circuit according to an embodiment of the present invention. FIGS. 6A, 6B, and 6C are side cross-sectional views showing an example of the structure of a filter circuit according to an embodiment of the present invention. FIGS. 7A and 7B are plan views of conductor patterns formed on each conductor layer of a filter circuit according to an embodiment of the present invention. FIG. 8 is a circuit diagram of a three-stage common-mode noise filter. FIG. 9 is a plan view showing an example of a derivative example of the structure of a filter circuit according to an embodiment of the present invention.

[0015] A filter circuit and a common mode noise filter according to an embodiment of the present invention will be described with reference to the drawings.

[0016] (Circuit Configuration of Filter Circuit 1) FIG. 1 is a circuit diagram of a filter circuit according to an embodiment of the present invention.

[0017] 1, the filter circuit 1 includes a first inductor 11, a second inductor 21, a third inductor 12, a fourth inductor 22, a first capacitor 31, a second capacitor 32, a first resistor 41, and a second resistor 42. The filter circuit 1 also includes a first terminal P1, a second terminal P2, and a third terminal P3.

[0018] The first terminal P1 and the second terminal P2 are input / output terminals for high frequency signals that are filtered by the filter circuit 1. The third terminal P3 is a terminal for connection to a reference potential in order to realize the filter characteristics of the filter circuit 1.

[0019] The first inductor 11 and the second inductor 21 are connected in series. An intermediate connection node ND3 where the first inductor 11 and the second inductor 21 are connected is connected to the third terminal P3.

[0020] The first inductor 11 is connected to the third inductor 12 through a first connection line 401. The third inductor 12 is connected to the first terminal P1.

[0021] The second inductor 21 is connected to the fourth inductor 22 through the second connection line 402. The fourth inductor 22 is connected to the second terminal P2.

[0022] The first capacitor 31 is connected between the first connection line 401 and the connection terminal side of the second inductor 21 that is connected to the second connection line 402. This connection point is a connection node ND12.

[0023] The second capacitor 32 is connected between the second connection line 402 and the connection terminal side of the first inductor 11 connected to the first connection line 401. This connection point is a connection node ND22.

[0024] The third inductor 12 is magnetically coupled to the second inductor 21 in the forward direction. The fourth inductor 22 is magnetically coupled to the first inductor 11 in the forward direction.

[0025] The first resistor 41 is inserted in the first connection line 401 closer to the first inductor 11 than the connection node ND11 of the first capacitor 31. In other words, the first resistor 41 is inserted in the first connection line 401 between the connection node ND11 and the connection node ND22.

[0026] The second resistor 42 is inserted on the second connection line 402 closer to the second inductor 21 than the connection node ND21 of the second capacitor 32. In other words, the second resistor 42 is inserted between the connection node ND12 and the connection node ND21 on the second connection line 402. Note that the first resistor 41 and the second resistor 42 can be omitted from the circuit perspective.

[0027] The above connection relationship can also be expressed as follows when expressed based on the first terminal P1, the second terminal P2, and the third terminal P3, in other words, in correspondence with the flow of high-frequency signals transmitted through the filter circuit 1. Note that the following description will be given of a configuration in which the first resistor 41 and the second resistor 42 are omitted.

[0028] The first terminal P1 is connected to one end of a parallel circuit of the first capacitor 31 and the second capacitor 32 through the third inductor 12. The third inductor 12 is magnetically coupled to the second inductor 21 in the forward direction.

[0029] The other end of the parallel circuit of the first capacitor 31 and the second capacitor 32 is connected to the second terminal P2 through the fourth inductor 22. The fourth inductor 22 is magnetically coupled to the first inductor 11 in the forward direction.

[0030] A series circuit of a first inductor 11 and a second inductor 21 is connected in parallel to the parallel circuit of the first capacitor 31 and the second capacitor 32. In this case, the first inductor 11 is connected to a connection node ND22 where the third inductor 12 and the second capacitor 32 are connected. The second inductor 21 is connected to a connection node ND12 where the fourth inductor 22 and the first capacitor 31 are connected.

[0031] The third terminal P3 is connected to an intermediate connection node ND3 between the first inductor 11 and the second inductor 21.

[0032] With this configuration, the filter circuit 1 functions as a band-stop filter that attenuates a predetermined frequency band for high-frequency signals transmitted between the first terminal P1 and the second terminal P2.

[0033] (Circuit Configuration of Common Mode Noise Filter 2) FIG. 2 is a circuit diagram of a common mode noise filter according to an embodiment of the present invention.

[0034] 2, the common mode noise filter 2 includes a filter circuit 1A, a filter circuit 1B, a first shunt capacitor 51A, a second shunt capacitor 51B, and a shunt inductor 60. The filter circuit 1A corresponds to a "first filter circuit" of the present invention, and the filter circuit 1B corresponds to a "second filter circuit" of the present invention.

[0035] The filter circuit 1A includes a first inductor 11A, a second inductor 21A, a third inductor 12A, a fourth inductor 22A, a first capacitor 31A, a second capacitor 32A, a first resistor 41A, and a second resistor 42A. The filter circuit 1A also includes a plurality of connection nodes ND11A, ND12A, ND21A, and ND22A, an intermediate connection node ND3A, a first terminal P1A, a second terminal P2A, and a third terminal P3A.

[0036] The first inductor 11A, the second inductor 21A, the third inductor 12A, the fourth inductor 22A, the first capacitor 31A, the second capacitor 32A, the first resistor 41A, and the second resistor 42A have the same configuration as the first inductor 11, the second inductor 21, the third inductor 12, the fourth inductor 22, the first capacitor 31, the second capacitor 32, the first resistor 41, and the second resistor 42 of the filter circuit 1 shown in FIG. 1, respectively.

[0037] The plurality of connection nodes ND11A, ND12A, ND21A, ND22A, intermediate connection node ND3A, first terminal P1A, second terminal P2A, and third terminal P3A have the same configurations as the plurality of connection nodes ND11, ND12, ND21, ND22, intermediate connection node ND3, first terminal P1, second terminal P2, and third terminal P3 of the filter circuit 1 shown in FIG. 1, respectively.

[0038] The filter circuit 1B includes a first inductor 11B, a second inductor 21B, a third inductor 12B, a fourth inductor 22B, a first capacitor 31B, a second capacitor 32B, a first resistor 41B, and a second resistor 42B. The filter circuit 1B also includes a plurality of connection nodes ND11B, ND12B, ND21B, and ND22B, an intermediate connection node ND3B, a first terminal P1B, a second terminal P2B, and a third terminal P3B.

[0039] The first inductor 11B, the second inductor 21B, the third inductor 12B, the fourth inductor 22B, the first capacitor 31B, the second capacitor 32B, the first resistor 41B, and the second resistor 42B have the same configuration as the first inductor 11, the second inductor 21, the third inductor 12, the fourth inductor 22, the first capacitor 31, the second capacitor 32, the first resistor 41, and the second resistor 42 of the filter circuit 1 shown in FIG. 1, respectively.

[0040] The multiple connection nodes ND11B, ND12B, ND21B, ND22B, intermediate connection node ND3B, first terminal P1B, second terminal P2B, and third terminal P3B have the same configurations as the multiple connection nodes ND11, ND12, ND21, ND22, intermediate connection node ND3, first terminal P1, second terminal P2, and third terminal P3 of the filter circuit 1 shown in FIG. 1, respectively.

[0041] One terminal of a first shunt capacitor 51A is connected to a third terminal P3A of the filter circuit 1A.

[0042] One terminal of a second shunt capacitor 51B is connected to a third terminal P3B of the filter circuit 1B.

[0043] The other terminal of the first shunt capacitor 51A and the other terminal of the second shunt capacitor 51B are connected to each other. A ground node to which the other terminal of the first shunt capacitor 51A and the other terminal of the second shunt capacitor 51B are connected is connected to a reference potential via a shunt inductor 60.

[0044] With this configuration, for example, one of a pair of differential signals is input to the common mode noise filter 2 through the first terminal P1A, transmitted through the filter circuit 1A, and output from the second terminal P2A, and the other of the pair of differential signals is input to the first terminal P1B, transmitted through the filter circuit 1B, and output from the second terminal P2B. The common mode noise filter 2 then suppresses common mode noise superimposed on the pair of differential signals.

[0045] FIG. 3A is a graph showing the attenuation characteristics of a T-type filter circuit according to an embodiment of the present invention and a reference T-type filter circuit, and FIG. 3B is a graph showing an example of the filter characteristics (pass characteristics for a pair of differential signals) of a common mode noise filter according to an embodiment of the present invention (the common mode noise filter of the present application) and a reference common mode noise filter.

[0046] The reference common mode noise filter includes a pair of reference T-type filter circuits shown in FIG. 4 and has the configuration described in Non-Patent Document 1. FIG. 4 is a circuit diagram of the reference T-type filter circuit. As shown in FIG. 4, the reference T-type filter circuit 1P includes a first inductor 11P, a second inductor 21P, and one capacitor 30P. The first inductor 11P and the second inductor 21P are connected in series between the first terminal P1 and the second terminal P2. The capacitor 30P is connected in parallel to the series circuit of the first inductor 11P and the second inductor 21P.

[0047] As shown in FIG. 3A, the filter circuit 1 of the present invention can obtain attenuation characteristics substantially similar to those of the reference filter circuit.

[0048] The filter circuit 1 of the present application also utilizes magnetic coupling between the third inductor 12 and the second inductor 21 between the first terminal P1 and the capacitor 30, and magnetic coupling between the fourth inductor 22 and the first inductor 11 between the second terminal P2 and the capacitor 30. Furthermore, the filter circuit 1 of the present application includes two capacitors, namely, the first capacitor 31 and the second capacitor 32. This allows the filter circuit 1 to adjust the attenuation at the attenuation pole frequency, the width of the attenuation band, and the attenuation characteristics by using a configuration including multiple capacitors, which differs from the magnetic coupling of inductors simply connected in series as in the reference filter circuit. As a result, as shown in FIG. 3A , the filter circuit 1 of the present application can increase the attenuation at the attenuation pole frequency compared to the reference filter circuit, and easily widen the frequency bands over which attenuations of −10 dB, −20 dB, and −30 dB are obtained.

[0049] By including such a filter circuit 1, the common mode noise filter 2 of the present invention can obtain pass characteristics that are substantially the same as those of a common mode noise filter including a reference filter circuit, as shown in FIG. 3B.

[0050] Furthermore, the above-described circuit configuration is substantially the same whether a differential signal is input from the first terminals P1A, P1B and output from the second terminals P2A, P2B or whether a differential signal is input from the second terminals P2A, P2B and output from the first terminals P1A, P1B. Therefore, the common mode noise filter 2 can achieve substantially the same filter characteristics (characteristics for suppressing common mode noise) in both directions, regardless of the input direction of the differential signal.

[0051] Furthermore, the common mode noise filter 2 of the present invention has the above-described circuit configuration, and thereby provides the following advantageous effects.

[0052] (Structure of Filter Circuit 1 Constituting Common Mode Noise Filter 2) FIG. 5 is a plan view showing an example of the structure of a filter circuit according to an embodiment of the present invention. FIGS. 6A, 6B, and 6C are side cross-sectional views showing an example of the structure of a filter circuit according to an embodiment of the present invention. FIG. 6A is an A-A' cross-sectional view of FIG. 5, FIG. 6B is a B-B' cross-sectional view of FIG. 5, and FIG. 6C is a CC' cross-sectional view of FIG. 5. FIGS. 7A and 7B are plan views of conductor patterns formed on each conductor layer of the filter circuit according to an embodiment of the present invention. FIG. 7A shows the first conductor layer, and FIG. 7B shows the second conductor layer.

[0053] As shown in Figures 5, 6(A), 6(B), and 6(C), the filter circuit 1 includes a substrate 90. The substrate 90 includes a base material 900 and multiple insulator layers 91, 92, and 93. The base material 900 is, for example, a semiconductor substrate and is made of an undoped semiconductor. The insulator layer 91 is formed on the surface of the base material 900 and is made of a highly insulating material such as SiN. The insulator layers 92 and 93 are made of a material having a predetermined dielectric constant. The insulator layers 92 and 93 are formed in this order on the surface of the insulator layer 91.

[0054] The interface (contact surface) between the insulator layer 91 and the insulator layer 92 is used as a second conductor layer CLY2, and the interface between the insulator layer 92 and the insulator layer 93 is used as a first conductor layer CLY1.

[0055] The filter circuit 1 includes, as conductor patterns, a first inductor 11, a second inductor 21, a third inductor 12, a fourth inductor 22, and a plurality of wiring patterns 81, 82, and 83. The filter circuit 1 also includes a plurality of via conductors VIA41 and VIA42. The first inductor 11, the second inductor 21, the third inductor 12, the fourth inductor 22, and the plurality of wiring patterns 81, 82, and 83 are configured as linear conductors. The linear conductors are conductors that extend in a predetermined direction and have a predetermined width.

[0056] (First conductor layer CLY1) As shown in Figures 6(A), 6(B), and 6(C), the first inductor 11 and the second inductor 21 are formed on the first conductor layer CLY1 (the interface between the insulator layer 92 and the insulator layer 93).

[0057] 7A , the first inductor 11 includes a main conductor 111 and an end conductor 112. The main conductor 111 has a linear shape extending in the X-axis direction. The end conductor 112 is connected to the other end of the main conductor 111 in the extending direction, and has a shape that extends and protrudes in the Y-axis direction relative to the main conductor 111.

[0058] The end conductor 113 (first end conductor) is connected to one end of the main conductor 111 in the extension direction, and has a shape that protrudes in the Y-axis direction relative to the main conductor 111. The end conductor 113 is connected to the main conductor 111, but is a conductor that mainly connects the main conductor 111 to the via conductor VIA41. The second inductor 21 includes a main conductor 211 and an end conductor 212. The main conductor 211 has a linear shape that extends in the X-axis direction. The end conductor 212 is connected to the other end of the main conductor 211 in the extension direction, and has a shape that protrudes in the Y-axis direction relative to the main conductor 211.

[0059] The end conductor 213 (second end conductor) is connected to one end of the main conductor 211 in the extension direction, and has a shape that protrudes in the Y-axis direction relative to the main conductor 111. The end conductor 213 is connected to the main conductor 211, but is a conductor that mainly connects the main conductor 211 to the via conductor VIA42.

[0060] The main conductor 111 of the first inductor 11 and the main conductor 211 of the second inductor 21 are arranged at a predetermined distance in the Y-axis direction. The main conductor 111 of the first inductor 11 and the main conductor 211 of the second inductor 21 extend parallel to the X-axis and run side by side. The length of the main conductor 111 and the length of the main conductor 211 are the same, and the width of the main conductor 111 and the width of the main conductor 211 are the same.

[0061] The end conductor 112 of the first inductor 11 and the end conductor 212 of the second inductor 21 are arranged at the same position in the X-axis direction. The end conductor 112 and the end conductor 212 have the same length and width. The widths of the end conductors 112 and 212 are also the same as the widths of the main conductors 111 and 211. The tip ends of the end conductors 112 and 212 are connected to each other and to the wiring pattern 83.

[0062] The end conductor 113 and the end conductor 213 are disposed at the same position in the X-axis direction.

[0063] The tip of the end conductor 113 and the tip of the end conductor 213 are different in the X-axis direction and are arranged with a gap (conductor-free portion) GAP1 in between. In this case, in the Y-axis direction, the tip of the end conductor 113 is located closer to the main conductor 211 than the tip of the end conductor 213. In other words, in the Y-axis direction, the tip of the end conductor 213 is located closer to the main conductor 111 than the tip of the end conductor 113.

[0064] As a result, the end conductors 113 and 213 are configured to form an S-shaped gap GAP1 in plan view. The end conductors 113 and 213 have regions with a predetermined area that are at the same position in the Y-axis direction.

[0065] The length by which the end conductor 113 protrudes from the main conductor 111 is the same as the length by which the end conductor 213 protrudes from the main conductor 211 .

[0066] The gap GAP1 is not limited to an S-shape, but may be a crank-shape.

[0067] The end conductor 113 is wider than the main conductor 111, and its protruding length (length in the Y-axis direction) is sufficiently shorter than the length in the direction in which the main conductor 111 extends (length in the X-axis direction). Therefore, the end conductor 113 hardly contributes to forming the inductance of the first inductor 11. In other words, the inductance of the first inductor 11 is formed almost entirely by the main conductor 111 and the end conductor 112.

[0068] The end conductor 213 is wider than the main conductor 211, and its protruding length (length in the Y-axis direction) is sufficiently shorter than the length in the direction in which the main conductor 211 extends (length in the X-axis direction). Therefore, the end conductor 213 hardly contributes to forming the inductance of the second inductor 21. In other words, the inductance of the second inductor 21 is formed almost entirely by the main conductor 211 and the end conductor 212.

[0069] With this configuration, the inductance of the first inductor 11 is the same as the inductance of the second inductor 21. Furthermore, the first inductor 11 and the second inductor 21 form a series circuit, and the intermediate connection node ND3 thereof is connected to the wiring pattern 83 and to the third terminal P3.

[0070] (Second conductor layer CLY2) As shown in Figures 6(A), 6(B), and 6(C), the third inductor 12 and the fourth inductor 22 are formed on the second conductor layer CLY2 (the interface between the insulator layer 91 and the insulator layer 92).

[0071] 7B, the third inductor 12 includes a main conductor 121. The main conductor 121 has a linear shape extending in the X-axis direction.

[0072] The fourth inductor 22 includes a main conductor 221. The main conductor 221 has a linear shape extending in the X-axis direction.

[0073] The main conductor 121 of the third inductor 12 and the main conductor 221 of the fourth inductor 22 are spaced apart at a predetermined distance in the Y-axis direction. This distance is the same as the distance between the main conductor 111 of the first inductor 11 and the main conductor 211 of the second inductor 21.

[0074] The main conductor 121 of the third inductor 12 and the main conductor 221 of the fourth inductor 22 extend parallel to the X-axis and run side by side. The length of the main conductor 121 and the length of the main conductor 221 are the same, and the width of the main conductor 121 and the width of the main conductor 221 are the same.

[0075] The end conductor 122 (third end conductor) is connected to one end of the main conductor 121 in the extending direction, and has a shape that protrudes in the Y-axis direction relative to the main conductor 121.

[0076] The end conductor 122 is wider than the main conductor 121, and its protruding length (length in the Y-axis direction) is sufficiently shorter than the length in the direction in which the main conductor 121 extends (length in the X-axis direction). Therefore, the end conductor 122 hardly contributes to forming the inductance of the third inductor 12. In other words, the inductance of the third inductor 12 is formed almost entirely by the main conductor 121.

[0077] The end conductor 222 (fourth end conductor) is connected to one end of the main conductor 211 in the extending direction, and has a shape that protrudes in the Y-axis direction relative to the main conductor 221.

[0078] The end conductor 222 is wider than the main conductor 221, and its protruding length (length in the Y-axis direction) is sufficiently shorter than the length in the direction in which the main conductor 221 extends (length in the X-axis direction). Therefore, the end conductor 222 hardly contributes to forming the inductance of the fourth inductor 22. In other words, the inductance of the fourth inductor 22 is formed almost entirely by the main conductor 221.

[0079] With this configuration, the inductance of the third inductor 12 and the inductance of the fourth inductor 22 are the same.

[0080] The end conductor 122 and the end conductor 222 are disposed at the same position in the X-axis direction.

[0081] The tip of the end conductor 122 and the tip of the end conductor 222 are different in the X-axis direction and are arranged with a gap (conductor-free portion) GAP2 in between. In this case, in the Y-axis direction, the tip of the end conductor 122 is located closer to the main conductor 221 than the tip of the end conductor 222. In other words, in the Y-axis direction, the tip of the end conductor 222 is located closer to the main conductor 121 than the tip of the end conductor 122.

[0082] As a result, the end conductors 122 and 222 are configured to form an S-shaped gap GAP2 in plan view. The end conductors 122 and 222 have regions with a predetermined area that are at the same position in the Y-axis direction.

[0083] The length by which the end conductor 122 protrudes from the main conductor 121 is the same as the length by which the end conductor 222 protrudes from the main conductor 221 .

[0084] In the X-axis direction, the arrangement of the tip of the end conductor 122 and the tip of the end conductor 222 is opposite to the arrangement of the tip of the end conductor 212 and the tip of the end conductor 112 .

[0085] The end of the main conductor 121 opposite to the end to which the end conductor 122 is connected is connected to the wiring pattern 81. The end of the main conductor 221 opposite to the end to which the end conductor 222 is connected is connected to the wiring pattern 82.

[0086] 5, 6A, 6B, and 6C, the first inductor 11 and the fourth inductor 22 substantially overlap in the stacking direction (plan view direction) of the substrate 90. More specifically, a portion of the first inductor 11 over a predetermined length in the extension direction of the main conductor 111 and the fourth inductor 22 over the entire extension direction of the main conductor 221 of the fourth inductor 22 overlap.

[0087] With this configuration, the first inductor 11 and the fourth inductor 22 have a portion that runs parallel to each other and are magnetically coupled to each other. At this time, due to a connection relationship that will be described later, the first inductor 11 and the fourth inductor 22 are magnetically coupled in the forward direction.

[0088] The end conductor 113 and the end conductor 222 substantially overlap each other except for their respective tip portions. In this manner, the end conductor 113 and the end conductor 222 face each other via the insulator layer 93, thereby forming the second capacitor 32. The main conductor 111 of the first inductor 11 and the main conductor 211 of the fourth inductor 22 face each other via the insulator layer 93. This facing portion is also used as part of the configuration of the second capacitor 32.

[0089] The second inductor 21 and the third inductor 12 substantially overlap in the stacking direction (planar view) of the substrate 90. More specifically, a portion of a predetermined length in the direction in which the main conductor 211 of the second inductor 21 extends overlaps with the entirety in the direction in which the main conductor 121 of the third inductor 12 extends.

[0090] With this configuration, the second inductor 21 and the third inductor 12 have a portion that runs parallel to each other and are magnetically coupled to each other. At this time, due to a connection relationship that will be described later, the second inductor 21 and the third inductor 12 are magnetically coupled in the forward direction.

[0091] The end conductor 213 and the end conductor 122 substantially overlap each other except for their respective tip portions. In this manner, the end conductor 213 and the end conductor 122 face each other across the insulator layer 93, thereby forming the first capacitor 31. The main conductor 211 of the second inductor 21 and the main conductor 121 of the third inductor 12 face each other across the insulator layer 93. This facing portion is also used as part of the configuration of the first capacitor 31.

[0092] In the stacking direction (planar view) of the substrate 90, the tip end of the end conductor 122 and the tip end of the end conductor 113 overlap. A via conductor VIA 41 is formed at this overlapping position. The via conductor VIA 41 penetrates the insulator layer 93 and connects to the end conductor 122 and the end conductor 113. The via conductor VIA 41 constitutes the first resistor 41 and also constitutes the first connection line 401.

[0093] In the stacking direction (planar view) of the substrate 90, the tip end portion of the end conductor 213 and the tip end portion of the end conductor 222 overlap. A via conductor 42 is formed at this overlapping position. The via conductor 42 penetrates the insulator layer 93 and connects to the end conductor 213 and the end conductor 222. The via conductor 42 constitutes the second resistor 42 and also constitutes the second connection line 402.

[0094] In this way, the filter circuit 1 is configured using the substrate 90 having the above structure.

[0095] In the above structure, the first inductor 11 and the second inductor 21 have the same length and width, and therefore the inductance of the first inductor 11 and the inductance of the second inductor 21 are the same.

[0096] Furthermore, the third inductor 12 and the fourth inductor 22 have the same length and width, so the inductance of the third inductor 12 and the inductance of the fourth inductor 22 are the same.

[0097] This allows the filter circuit 1 to achieve desired excellent filter characteristics.

[0098] In particular, when the frequency band to be attenuated by the filter circuit 1 is a high frequency band, it is necessary to reduce the inductance by shortening the lengths of the first inductor 11 and the second inductor 21. In this case, the difference in the inductance between the first inductor 11 and the second inductor 21, which is caused by the difference between the lengths of the first inductor 11 and the second inductor 21, has a significant impact on the filter characteristics. However, with the above structure, the lengths of the first inductor 11 and the second inductor 21 can be made the same more reliably and with high precision, so the filter circuit 1 can more reliably achieve the desired excellent filter characteristics.

[0099] This problem of difference in inductance due to length also occurs in the third inductor 12 and the fourth inductor 22. However, the above structure makes it possible to more reliably and accurately make the lengths of the third inductor 12 and the fourth inductor 22 the same, so that the filter circuit 1 can more reliably achieve the desired excellent filter characteristics.

[0100] Furthermore, the filter circuit 1 configures the second capacitor 32 using the third inductor 12 connected to the wiring pattern 81 (first terminal P1). The filter circuit 1 configures the first capacitor 31 using the fourth inductor 22 connected to the wiring pattern 82 (second terminal P2).

[0101] This makes it possible to suppress undesired parasitic inductance between the first terminal P1 and the second capacitor 32, and undesired parasitic inductance between the second terminal P2 and the first capacitor 31. Therefore, the filter circuit 1 can more reliably achieve the desired excellent filter characteristics.

[0102] Furthermore, the above-described structure (conductor pattern) results in a substantially identical structure (conductor pattern) whether a differential signal is input from the first terminal P1 and output from the second terminal P2 or input from the second terminal P2 and output from the first terminal P1. Therefore, the common mode noise filter 2 including the filter circuit 1 can achieve substantially identical filter characteristics (characteristics for suppressing common mode noise) in both directions, regardless of the input direction of the differential signal.

[0103] Furthermore, with the above-described structure, the first inductor 11 (main conductor 111) and the second inductor 21 (main conductor 211) have a shape that extends in a direction (X-axis direction) perpendicular to the direction (Y-axis direction) in which the wiring pattern 81 (first terminal P1) and the wiring pattern 82 (second terminal P2) are aligned. Therefore, even if the lengths are changed to adjust the inductance of the first inductor 11 and the inductance of the second inductor 21, the lengths of the filter circuit 1 in the direction (Y-axis direction) in which the wiring pattern 81 (first terminal P1) and the wiring pattern 82 (second terminal P2) are aligned do not change.

[0104] Therefore, in the filter circuit 1, the inductance of the first inductor 11 and the inductance of the second inductor 21 can be appropriately set in accordance with the desired filter characteristics without changing the length in the direction (Y-axis direction) in which the wiring pattern 81 (first terminal P1) and the wiring pattern 82 (second terminal P2) of the filter circuit 1 are aligned. The same effect can be obtained for the third inductor 12 and the fourth inductor 22.

[0105] In the above-described configuration, the first inductor 11 and the second inductor 21 may be formed on the second conductor layer CLY2, and the third inductor 12 and the fourth inductor 22 may be formed on the first conductor layer CLY1.

[0106] (Configuration of a Multi-Stage Common-Mode Noise Filter) FIG. 8 is a circuit diagram of a three-stage common-mode noise filter.

[0107] As shown in FIG. 8, the common mode noise filter 3 differs from the common mode noise filter 2 described above in the number of stages.

[0108] The common mode noise filter 3 has a configuration in which single-stage common mode noise filters 2A, 2B, and 2C are connected in series. The common mode noise filters 2A, 2B, and 2C have almost the same configuration as the common mode noise filter 2 described above.

[0109] Each of the common mode noise filters 2A, 2B, and 2C has a configuration in which adjacent input / output terminals are connected to one another and each includes a pair of the filter circuit 1 according to the first embodiment. The grounding wiring of each of the common mode noise filters 2A, 2B, and 2C has the above-described shunt capacitor configuration and shares a shunt inductor.

[0110] With this configuration, the common mode noise filter 3 can achieve the same effects as the common mode noise filter 2. Furthermore, by configuring the single-stage common mode noise filter 2 into multiple stages, the common mode noise filter 3 can achieve, for example, steeper attenuation characteristics.

[0111] Although the common mode noise filter 3 has a three-stage configuration, the number of stages is not limited to three, and can be set appropriately depending on the desired characteristics.

[0112] 9 is a plan view showing an example of a derivative of the structure of the filter circuit according to the embodiment of the present invention. The circuit configuration of the derivative filter circuit 1X is similar to the circuit configuration of the filter circuit 1 according to the first embodiment, and therefore a description thereof will be omitted.

[0113] 9 , the filter circuit 1X of the derivative example differs from the filter circuit 1 according to the first embodiment in the directions in which the first inductor 11, the second inductor 21, the third inductor 12, and the fourth inductor 22 extend. Other configurations of the filter circuit 1X are similar to those of the filter circuit 1, and therefore, a description of similar parts will be omitted.

[0114] In the filter circuit 1X, the first inductor 11, the second inductor 21, the third inductor 12, and the fourth inductor 22 extend along the Y-axis direction in Fig. 9. In other words, the first inductor 11, the second inductor 21, the third inductor 12, and the fourth inductor 22 extend along the direction in which the wiring pattern 81 (first terminal P1) and the wiring pattern 82 (second terminal P2) are aligned (the Y-axis direction).

[0115] Even with this configuration, the circuit configuration of the filter circuit 1 shown in FIG. 1 can be realized.

[0116] In this way, by providing the circuit configuration of the filter circuit 1 shown in FIG. 1, the physical configuration of the substrate 90 can be set in a wider variety of ways.

[0117] <1> A filter circuit comprising: a first terminal and a second terminal which are input / output terminals for a high frequency signal to be filtered; a third terminal for connection to a reference potential; a first inductor, a second inductor, a third inductor, and a fourth inductor; a first capacitor, and a second capacitor; wherein the third inductor is magnetically coupled to the second inductor in a forward direction; the fourth inductor is magnetically coupled to the first inductor in a forward direction; the first inductor and the second inductor are connected in series; the first inductor is connected to the third inductor through a first connecting line; the third inductor is connected to the first terminal; the second inductor is connected to the fourth inductor through a second connecting line; the fourth inductor is connected to the second terminal; the first capacitor is connected between the second inductor and the first connecting line; the second capacitor is connected between the first inductor and the second connecting line; and an intermediate connection node at which the first inductor and the second inductor are connected in series is connected to the third terminal.

[0118] <2> The filter circuit according to <1>, further comprising: a first resistor inserted in the first connection line closer to the first inductor than the connection node of the first capacitor; and a second resistor inserted in the second connection line closer to the second inductor than the connection node of the second capacitor.

[0119] <3> A common mode noise filter comprising: a first filter circuit having the configuration of the filter circuit described in <1> and transmitting one differential signal of a pair of differential signals; a second filter circuit having the configuration of the filter circuit and transmitting the other differential signal of the pair of differential signals; a first shunt capacitor connected to a third terminal of the first filter circuit; a second shunt capacitor connected to a third terminal of the second filter circuit; and a shunt inductor connecting a grounding node, at which the first shunt capacitor and the second shunt capacitor are connected, to a reference potential.

[0120] <4> The common mode noise filter according to <3>, comprising a plurality of the common mode noise filters, wherein the first terminals and the second terminals of the plurality of common mode noise filters are connected in sequence, the reference potential is shared, and the common mode noise filters are configured in a plurality of stages.

[0121] <5> A filter circuit formed on a substrate configured by laminating a plurality of insulating layers and including a first conductor layer and a second conductor layer at different positions in a lamination direction, comprising: a first inductor and a second inductor each configured by a conductor pattern of the first conductor layer; and a third inductor and a fourth inductor each configured by a conductor pattern of the second conductor layer, wherein the first inductor and the second inductor are connected to each other; the first inductor and the second inductor have the same length; the third inductor and the fourth inductor have the same length; the first inductor and the fourth inductor run side by side and overlap when viewed in the lamination direction; the second inductor and the third inductor run side by side and overlap when viewed in the lamination direction; the insulating layer between the first conductor layer and the second conductor layer includes a first via conductor connecting the first inductor and the third inductor and a second via conductor connecting the second inductor and the fourth inductor; a first capacitor is formed by a portion where the second inductor and the third inductor face each other; a second capacitor is formed by a portion where the first inductor and the fourth inductor face each other;

[0122] <6> The filter circuit according to <5>, comprising: a first end conductor connecting the first inductor to the first via conductor; a second end conductor connecting the second inductor to the second via conductor; a third end conductor connecting the third inductor to the first via conductor; and a fourth end conductor connecting the fourth inductor to the second via conductor, wherein the second end conductor and the third end conductor overlap in the stacking direction to form a part of the first capacitor, and the first end conductor and the fourth end conductor overlap in the stacking direction to form a part of the second capacitor.

[0123] 1, 1A, 1B, 1P, 1X: Filter circuit 2, 2A, 2B, 2C: Common mode noise filter 3: Common mode noise filter 11, 11A, 11B, 11P: First inductor 12, 12A, 12B: Third inductor 21, 21A, 21B, 21P: Second inductor 22, 22A, 22B: Fourth inductor 30, 30P: Capacitor 31, 31A, 31B: First capacitor 32, 32A, 32B: Second capacitor 41, 41A, 41B: First resistor 42, 42A, 42B: Second resistor 51A: First shunt capacitor 51B: Second shunt capacitor 60: Shunt inductor 81, 82, 83: Wiring pattern 90: Substrate 91, 92, 93: Insulator layer 111, 121, 211, 221: main conductor 112, 113, 122, 212, 213, 222: end conductor 401: first connection line 402: second connection line 900: substrate CLY1: first conductive layer CLY2: second conductive layer GAP1, GAP2: gap ND11, ND11A, ND11B, ND12, ND21, ND22: connection node ND3, ND3A, ND3B: intermediate connection node P1, P1A, P1B: first terminal P2, P2A, P2B: second terminal P3, P3A, P3B: third terminal VIA41, VIA42: via conductor k: coupling coefficient

Claims

1. A filter circuit comprising: a first terminal and a second terminal which are input / output terminals for high frequency signals to be filtered; a third terminal for connection to a reference potential; a first inductor, a second inductor, a third inductor, and a fourth inductor; a first capacitor, and a second capacitor; wherein the third inductor is magnetically coupled to the second inductor in a forward direction; the fourth inductor is magnetically coupled to the first inductor in a forward direction; the first inductor and the second inductor are connected in series; the first inductor is connected to the third inductor through a first connecting line; the third inductor is connected to the first terminal; the second inductor is connected to the fourth inductor through a second connecting line; the fourth inductor is connected to the second terminal; the first capacitor is connected between the second inductor and the first connecting line; the second capacitor is connected between the first inductor and the second connecting line; and an intermediate connection node where the first inductor and the second inductor are connected in series is connected to the third terminal.

2. The filter circuit according to claim 1, comprising: a first resistor inserted in the first connection line closer to the first inductor than the connection node of the first capacitor; and a second resistor inserted in the second connection line closer to the second inductor than the connection node of the second capacitor.

3. A common mode noise filter comprising: a first filter circuit having the configuration of the filter circuit according to claim 1 and transmitting one of a pair of differential signals; a second filter circuit having the configuration of said filter circuit and transmitting the other of said pair of differential signals; a first shunt capacitor connected to a third terminal of said first filter circuit; a second shunt capacitor connected to the third terminal of said second filter circuit; and a shunt inductor connecting a ground node, where said first shunt capacitor and said second shunt capacitor are connected, to a reference potential.

4. The common mode noise filter according to claim 3, comprising a plurality of said common mode noise filters, the first terminals and second terminals of said plurality of common mode noise filters being connected in sequence, the reference potential being shared, and the common mode noise filters being configured in a plurality of stages.

5. A filter circuit formed on a substrate constituted by laminating a plurality of insulating layers and having a first conductor layer and a second conductor layer at different positions in the lamination direction, comprising: a first inductor and a second inductor each constituted by a conductor pattern of the first conductor layer; and a third inductor and a fourth inductor each constituted by a conductor pattern of the second conductor layer, wherein the first inductor and the second inductor are connected to each other; the first inductor and the second inductor have the same length; the third inductor and the fourth inductor have the same length; the first inductor and the fourth inductor run side by side and overlap when viewed in the lamination direction; the second inductor and the third inductor run side by side and overlap when viewed in the lamination direction; the insulating layer between the first conductor layer and the second conductor layer comprises a first via conductor connecting the first inductor and the third inductor and a second via conductor connecting the second inductor and the fourth inductor; a first capacitor is formed by the opposing portion of the second inductor and the third inductor; a second capacitor formed by a portion where the first inductor and the fourth inductor face each other.

6. The filter circuit according to claim 5, comprising: a first end conductor connecting the first inductor to the first via conductor; a second end conductor connecting the second inductor to the second via conductor; a third end conductor connecting the third inductor to the first via conductor; and a fourth end conductor connecting the fourth inductor to the second via conductor, wherein the second end conductor and the third end conductor overlap in the stacking direction to form a part of the first capacitor, and the first end conductor and the fourth end conductor overlap in the stacking direction to form a part of the second capacitor.

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