System with 3D conductive exterior routing and method of fabrication

Abstract

Device and method that conformally deposits metal conductors to both the vertical and horizontal sides of components of a stacked multi-component device having one or more die and a substrate to provide an interpackage or intercomponent routing or metal plane for ground, power, and / or signal along the exterior surfaces of the components. The deposited metal layer, e.g., as a film, has a thickness on the multiple deposited surfaces that are approximately the same, e.g., having an aspect ratio close to 1:1. In routing along the exterior surfaces of the components of the stacked device, costly through-silicon vias and other via structures employed in the die or substrate for the multi-component device can beneficially be minimized or avoided in the device or component.

Description

Attorney Docket No.10046-620WO1 8424 MEA SYSTEM WITH 3D CONDUCTIVE EXTERIOR ROUTING AND METHOD OF FABRICATION RELATED APPLICATION

[0001] This PCT patent application claims priority to, and the benefit of, U.S. Provisional Patent Application No. 63 / 669,197, filed July 9, 2024, entitled “System with 3D Conductive Exterior Routing and Method of Fabrication,” which is incorporated by reference herein in its entirety. BACKGROUND

[0002] In semiconductor processing and electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection that passes through a silicon wafer or die. TSVs are high-performance interconnects used, for example, to fabricate 3D packages or 3D integrated circuits. Semiconductor processing and electronic engineering also employ wire-bond or flip chips to fabricate the 3D packages or 3D integrated circuits.

[0003] Three-dimensional integrated circuits are manufactured by stacking dies or semiconductor devices and then interconnecting them vertically, for example, using TSV or metal-metal connections, to form a single integrated device. The device can often achieve performance improvements at reduced power and a smaller footprint than conventional two- dimensional processes. Current stacked chip interconnection schemes rely on Through Silicon Vias for both signal and power routing.

[0004] There is a benefit to improving the three-dimensional integrated circuits and various stacked devices.

[0005] In addition, increases in the thermal dissipated power (TDP) of microelectronic systems, including multi-chip packages such as those used for AI chips / machine learning (AI / ML) and high-performance computing (HPC) workloads, have increased the need for more thermal dissipation capabilities in semiconductor processing and electronic engineering.

[0006] There is also a benefit to improving the thermal management of three-dimensional integrated circuits and various stacked devices. SUMMARY

[0007] An exemplary device and associated method of fabrication and use are disclosed that conformally deposits metal conductors to both the vertical and horizontal sides of components of a stacked multi-component device having one or more die and a substrate to provide an interpackage or intercomponent routing or metal plane for ground, power, and / orAttorney Docket No.10046-620WO1 8424 MEA signal along the exterior surfaces of the components. The deposited metal layer, e.g., as a film, has a thickness on the multiple deposited surfaces that are approximately the same, e.g., having an aspect ratio close to 1:1. In routing along the exterior surfaces of the components of the stacked device, costly through-silicon vias and other via structures employed in the die or substrate for the multi-component device can beneficially be minimized or avoided in the device or component.

[0008] The deposition is preferably performed using a metal-organic decomposition (MOD) process, e.g., using a spray or ink-jetting method. When ink jetted, the conductors (e.g., as films) can naturally form conformally thick patterns by directly depositing the metal via a laser or electron beam, while a spraying operation can employ apertures or liftoff lithography and corresponding layer growing for pattern creation. Other processes can be used to form the conformal layers, e.g., deposition of nanoparticle inks, Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD), which can also operate in combination with the MOD process in forming the exemplary devices.

[0009] The exemplary conductive routing utilizes chip space that is currently unused while concurrently providing for alternative or additional routing paths. As noted, the conductors can serve various purposes, such as signal transmission, power distribution, or grounding. In an example, the exemplary system and method can be used to enhance the Power Distribution network for the top die, especially if it has backside power enabled. The exemplary system and method may be implemented for electrical integrated circuits as well as photonic integrated circuits, quantum integrated circuits, or other types of integrated circuits.

[0010] In addition to conductors, the exemplary system and method can deposit dielectric material to both the vertical and horizontal sides of the components. The deposition can be in combination with the metal layers and can be formed over each layer to form a parallel plate structure.

[0011] The dielectric and metal layers (e.g., conductive films, patterns, structures, and similar elements) can be manufactured on individual wafers, dies, chips, or chiplets while these devices are distinct from a 3D assembly. Subsequently, during the stacking or assembly process, the exemplary system may be employed to establish electrical connections among these structures.

[0012] In another aspect, a second exemplary system and method are disclosed that integrates single or two-phase cooling directly into the microelectronic package using a conformal hermetic film covering a stacked die and any surface components. For single phaseAttorney Docket No.10046-620WO1 8424 MEA cooling, a lid may be employed to facilitate liquid cooling. For two-phase cooling, the base hermetic film is employed as a template for the growth of a wicking material. The lid can complete the assembly similar to commercial vapor chambers. The second exemplary system and method can reduce the expected junction temperature of stacked semiconductor die by reducing the thermal impedance to the external thermal bath.

[0013] In an aspect, a method is disclosed comprising: providing a substrate having a top surface; attaching a die onto said substrate, wherein the die has a top surface and a side surface; and depositing a metal to generate a uniform metal layer on the top surface of the substrate, the top surface of the die, and the side surface of the die to form a continuous uniformly thick conductor between the die and the substrate, wherein the metal layer forms at least one conductor, including a first conductor, as a power line, a ground line or plane, or a signal line, wherein the top surface of the substrate and the top surface of the die has a first thickness, and wherein the side surface of the die has a second thickness, wherein the first thickness is substantially similar to the second thickness (e.g., within 5% - 25%).

[0014] In some embodiments, the top surface of the die includes an exposed top metal contact surrounded by a passivation layer, wherein the at least one conductor is deposited over the exposed top metal contact to form an electric contact between a circuit of the die and a circuit or electrical structure of the substrate.

[0015] In some embodiments, the first conductor is a signal line, wherein the at least one conductor includes (i) a second conductor that forms a power line or plane and (ii) a third conductor that forms a ground line or plane.

[0016] In some embodiments, the first conductor is a power line or plane, wherein the at least one conductor includes (i) a second conductor that forms a signal line and (ii) a third conductor that forms a ground line or plane.

[0017] In some embodiments, the first conductor is a ground line or plane, wherein the at least one conductor includes (i) a second conductor that forms a power line or plane and (ii) a third conductor that forms a signal line.

[0018] In some embodiments, the die does not have through-silicon vias (TSV) for a power line, wherein the power line provided by a portion of the at least one conductor is formed outside of the die.

[0019] In some embodiments, the step of depositing the metal to generate the uniform metal layer on the top surface of the substrate, the top surface of the die, and the side surface of the die comprises a Metal Organic Decomposition (MOD) process.Attorney Docket No.10046-620WO1 8424 MEA

[0020] In some embodiments, the Metal Organic Decomposition process employs a spray operation (e.g., using apertures or liftoff lithography).

[0021] In some embodiments, the Metal-Organic Decomposition process employs an ink jetting operation (e.g., to form a pattern as the metal layer).

[0022] In some embodiments, the step of depositing the metal to generate the uniform metal layer on the top surface of the substrate, the top surface of the die, and the side surface of the die comprises at least one of deposition of nanoparticle inks, Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD).

[0023] In some embodiments, the method includes depositing a dielectric material to generate a dielectric layer over the at least one conductor; and depositing additional metal to generate a second metal layer over the dielectric layer.

[0024] In some embodiments, the die or structure includes a plurality of trench structures, wherein the at least one conductor, the dielectric layer, and the second metal layer are formed over the plurality of trench structures to form capacitors (e.g., decoupling capacitors).

[0025] In some embodiments, the metal and metal layer include silver, gold, platinum, nickel, or copper.

[0026] In some embodiments, the die comprises an individual wafer, a chip, or a chiplet.

[0027] In another aspect, a device comprising: a substrate having a top surface; and a die coupled to said substrate, wherein the die has a top surface and a side surface; the die and substrate having a uniform metal layer deposited on the top surface of the substrate, the top surface of the die, and the side surface of the die to form a continuous uniformly thick conductor between the die and the substrate, wherein the metal layer forms at least one conductor, including a first conductor, as a power line, a ground line or plane, or a signal line, wherein the top surface of the substrate and the top surface of the die has a first thickness, and wherein the side surface of the die has a second thickness, wherein the first thickness is substantially similar to the second thickness (e.g., within 5% - 25%).

[0028] In some embodiments, the top surface of the die includes an exposed top metal contact surrounded by a passivation layer, and wherein the at least one conductor is deposited over the exposed top metal contact to form an electric contact between a circuit of the die and a circuit or electrical structure of the substrate.

[0029] In some embodiments, the first conductor is a signal line, and wherein the at least one conductor includes (i) a second conductor that forms a power line or plane and (ii) a third conductor that forms a ground line or plane.Attorney Docket No.10046-620WO1 8424 MEA

[0030] In some embodiments, the first conductor is a power line or plane, wherein the at least one conductor includes (i) a second conductor that forms a signal line and (ii) a third conductor that forms a ground line or plane.

[0031] In some embodiments, the first conductor is a ground line or plane, wherein the at least one conductor includes (i) a second conductor that forms a power line or plane and (ii) a third conductor that forms a signal line.

[0032] In some embodiments, the continuous uniformly thick conductor between the die and the substrate is formed of a Metal Organic Decomposition (MOD) process, a deposition of nanoparticle ink process, Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD).

[0033] In some embodiments, the device includes a plurality of decoupling capacitors formed by (i) the at least one conductor and (ii) a dielectric layer and a second metal layer each deposited over a plurality of trench structures located on the die or substrate.

[0034] In some embodiments, the die comprises an individual wafer, a chip, or a chiplet.

[0035] In some embodiments, the substrate comprises an individual wafer, a chip, or a chiplet.

[0036] In another aspect, a method (e.g., for Integrated Heat Spreader) is disclosed comprising: providing a substrate having a top surface; attaching a die onto said substrate, wherein the die has a top surface and a side surface; depositing a sealing layer over the top surface of the substrate, the side surface of the die, and the top surface of the die to form a sealed coating of the die and substrate; and attaching a housing to the substrate to define a volume over the top surface of the substrate and the top surface of the die, wherein the housing has an inlet, wherein coolant are directable into the inlet, the coolant being configured in the volume to draw heat from the substrate and die to thermally regulate the temperature of the die and substrate.

[0037] In some embodiments, the housing includes an outlet, wherein the coolant is circulatable into the inlet, through the volume, and out the outlet to regulate the temperature of the die and substrate.

[0038] In some embodiments, the coolant is configured to evaporate from at least one of (i) surfaces of the die, including the top surface of the die, and (ii) the top surface of the substrate and to condense at a condensing portion of the housing (e.g., inwardly facing to the die and substrate).Attorney Docket No.10046-620WO1 8424 MEA

[0039] In some embodiments, the seal layer forms a uniform hermetic seal that covers the substrate (e.g., organic substrate and the die (e.g., as a part of stacked chips).

[0040] In some embodiments, the step of depositing the sealing layer employs a Metal- Organic Decomposition (MOD) process.

[0041] In some embodiments, the Metal Organic Decomposition process employs a spray operation (e.g., using apertures or liftoff lithography).

[0042] In some embodiments, the Metal-Organic Decomposition process employs an ink jetting operation (e.g., to form a pattern as the metal layer).

[0043] In some embodiments, the step of depositing the sealing layer employs at least one of deposition of nanoparticle inks, Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD).

[0044] In some embodiments, the die is a part of a multi-chip package.

[0045] In some embodiments, the sealing layer has (i) a first thickness at a first region on the die or substrate and (ii) a second thickness at a second region on the die or substrate, wherein the second thickness is thicker than the first thickness, and wherein the first thickness was formed of a first deposition process (e.g., MOD), and wherein the second thickness was formed of the first deposition process in combination with a second deposition process.

[0046] In some embodiments, the second deposition process is different from the first deposition process.

[0047] In some embodiments, the second deposition process is the same as the first deposition process.

[0048] In some embodiments, at least one of the top surfaces of the die and the top surface of the substrate is patterned to form a finned heat sink.

[0049] In some embodiments, at least one of the top surfaces of the die or the top surface of the substrate is patterned to form a pin-finned heat sink.

[0050] In some embodiments, the housing includes a wicking layer.

[0051] In some embodiments, the housing includes a wicking structure that extends from the wicking layer, the wicking structure is configured to extend from the condensing portion of the housing to at least one of (i) the top surface of the substrate or (ii) a second wicking layer formed thereon..

[0052] In some embodiments, the method includes depositing a wicking layer at the condensing portion of the housing.Attorney Docket No.10046-620WO1 8424 MEA

[0053] In some embodiments, the housing includes a wicking layer formed over the condensing portion of the housing, wherein the housing includes one or more wall sections that define in part the volume, including a first wall section, and wherein the wicking layer extends from the condensing portion of the housing to the first wall section to contact a wicking layer formed on the top surface of the substrate, to form a closed loop circulation of the coolant from the wicking layer formed over the condensing portion of the housing to the wicking layer formed on the top surface of the substrate.

[0054] In some embodiments, the die and substrate are a part of any one of the above- discussed devices.

[0055] In another aspect, a device is disclosed comprising: a substrate having a top surface; a die coupled to said substrate, wherein the die has a top surface and a side surface; a sealing layer formed over the top surface of the substrate, the side surface of the die, and the top surface of the die to form a sealed coating of the die and substrate; and a housing mechanically coupled to the substrate to define a volume over the top surface of the substrate and the top surface of the die, wherein the housing has an inlet, wherein coolant is directable into the inlet, the coolant being configured in the volume to draw heat from the substrate and die to thermally regulate temperature of the die and substrate.

[0056] In some embodiments, the device includes the coolant.

[0057] In some embodiments, the housing includes an outlet, wherein the coolant is circulatable into the inlet, through the volume, and out the outlet to regulate the temperature of the die and substrate.

[0058] In some embodiments, the coolant is configured to evaporate from at least one of (i) surfaces of the die, including the top surface of the die, and (ii) the top surface of the substrate and to condense at a condensing portion of the housing (e.g., inwardly facing to the die and substrate).

[0059] In some embodiments, the seal layer forms a uniform hermetic seal that covers the substrate (e.g., organic substrate and the die (e.g., as a part of stacked chips).

[0060] In some embodiments, the sealing layer is formed via at least one of a Metal Organic Decomposition (MOD) process, deposition of nanoparticle inks, Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD).

[0061] In some embodiments, the die is a part of a multi-chip package.Attorney Docket No.10046-620WO1 8424 MEA

[0062] In some embodiments, the sealing layer has (i) a first thickness at a first region on the die or substrate and (ii) a second thickness at a second region on the die or substrate, wherein the second thickness is thicker than the first thickness.

[0063] In some embodiments, at least one of the top surfaces of the die and the top surface of the substrate is patterned to form a finned heat sink (e.g., pin-finned heat sink).

[0064] In some embodiments, the housing includes a wicking layer.

[0065] In some embodiments, the housing includes a wicking structure that extends from the wicking layer, the wicking structure is configured to extend from the condensing portion of the housing to at least one of (i) the top surface of the substrate or (ii) a second wicking layer formed thereon..

[0066] In some embodiments, the housing includes a wicking layer formed over the condensing portion of the housing, wherein the housing includes one or more wall sections that define in part the volume, including a first wall section, and wherein the wicking layer extends from the condensing portion of the housing to the first wall section to contact a wicking layer formed on the top surface of the substrate, to form a closed loop circulation of the coolant from the wicking layer formed over the condensing portion of the housing to the wicking layer formed on the top surface of the substrate.

[0067] In some embodiments, the die and substrate are a part of any one of the above- discussed devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments and together with the description, serve to explain the principles of the methods and systems.

[0069] Embodiments of the present invention may be better understood from the following detailed description when read in conjunction with the accompanying drawings. Such embodiments, which are for illustrative purposes only, depict novel and non-obvious aspects of the invention. The drawings include the following figures:

[0070] Figs.1A – 1G each shows an exemplary stacked multi-component device that has conformally deposited metal conductors on its exterior surface at both the vertical and horizontal sides of its components (e.g., dies and substrate) to provide an interpackage or intercomponent routing or metal plane for ground, power, and / or signal along the exterior surfaces in accordance with an illustrative embodimentAttorney Docket No.10046-620WO1 8424 MEA

[0071] Figs.2A – 2D shows typical connections of TSVs to CMOS circuits through local interconnects.

[0072] Figs. 3A and 3B each shows an example method, respectively, to fabricate a stacked multi-component device that has conformally deposited metal conductors on its exterior surface at both the vertical and horizontal sides of its components (e.g., dies and substrate) to provide an interpackage or intercomponent routing or metal plane for ground, power, and / or signal along the exterior surfaces in accordance with an illustrative embodiment.

[0073] Figs. 4A and 4B show examples of in-situ decoupling capacitors that can be formed in the die or substrate of a multi-stack device from the 3D conductive exterior routings in accordance with an illustrative embodiment.

[0074] Figs. 5A and 5B each show a multi-chip package configured with an integrated heat spreader in accordance with an illustrative embodiment. Fig. 5C and 5D show a detail view of the connection by a capillary underfill solder process.

[0075] Fig.6A shows an example configuration of the die or substrate configured with a finned heat sink in accordance with an illustrative embodiment.

[0076] Fig. 6B shows an example cooling loop system employing the device described in relation to Fig.5A in accordance with an illustrative embodiment.

[0077] Figs. 7A – 7C each shows an example of a vapor chamber having a multi-stack device in accordance with an illustrative embodiment. DETAILED DESCRIPTION

[0078] Some references, which may include various patents, patent applications, and publications, are cited in a reference list and discussed in the disclosure provided herein. The citation and / or discussion of such references is provided merely to clarify the description of the disclosed technology and is not an admission that any such reference is “prior art” to any aspects of the disclosed technology described herein. In terms of notation, “[n]” corresponds to the nth reference in the reference list. For example, Ref. [1] refers to the 1st reference in the list. All references cited and discussed in this specification are incorporated herein by reference in their entireties and to the same extent as if each reference was individually incorporated by reference.

[0079] Example System

[0080] Figs. 1A – 1G each shows an exemplary stacked multi-component device 100 (shown as 100a, 100b, 100c, 100d, 100e, 100f, and 100g) that has conformally deposited metal conductors on its exterior surface at both the vertical and horizontal sides of its componentsAttorney Docket No.10046-620WO1 8424 MEA (e.g., dies and substrate) to provide an interpackage or intercomponent routing or metal plane for ground, power, and / or signal along the exterior surfaces in accordance with an illustrative embodiment. Fig.1A shows a first example of the exemplary device 100a configured with 3D conductive exterior routings. Fig.1B shows a second example of the exemplary device 100b with 3D conductive exterior routings. Fig.1C shows a third example of the exemplary device 100c configured with 3D conductive exterior routings and through-silicon vias. Fig.1D shows a fourth example of the exemplary device 100d configured with 3D conductive exterior plane structure. Fig. 1E shows a fifth example of the exemplary device 100e configured with 3D conductive exterior routing over multiple dies or components. Figs.1F and 1G each shows a sixth and seventh example, respectively, of the exemplary devices 100f, 100g configured with 3D conductive exterior routing over multiple dies or components in another stacked configuration.

[0081] As used herein, a “die” can include an individual wafer or wafer component, a chip, a chiplet, or other integrated circuits comprising semiconducting, photonic, or quantum material on which a given functional circuit is fabricated.

[0082] In the example shown in Fig. 1A and 1B, the exemplary device 100a includes a substrate 102 and a die 104 (shown as 104a, 104b) having 3D conductive exterior routings 106 formed on the vertical and horizontal sides of its components 102, 104. The substrate 102 has a top surface 107a. The die 104 is coupled to the substrate 102 and has a top surface 108a and a side surface 108b. The 3D conductive exterior routings 106 is formed of a uniform metal layer deposited on the top surface 107a of the substrate 102, the top surface 108a of the die 104a, 104b, and the side surface 108b of the die 104a, 104b and form a continuous uniformly thick conductor between the die 104a, 104b and the substrate 104. The 3D conductive exterior routing(s) 106, as the metal layer, forms at least one conductor, including a first conductor, as a power line, a ground line or plane, or a signal line. Uniform contiguous 3D conductive exterior routing(s) 106 can provide better management of overall current density, thereby reducing the risk of electromigration.

[0083] In some embodiments, the top surface 107a of the substrate 102 and the top surface 108a of the die 104 has a first thickness, and the side surface 108b of the die 104 has a second thickness that is substantially similar to the first thickness (e.g., within 1% - 25%, e.g., less than 1%, about 1%, about 2%, about 3%, about 4%, about 5%, about 6%, about 7%, about 8%, about 9%, about 10%, about 11%, about 12%, about 13%, about 14%, about 15%, aboutAttorney Docket No.10046-620WO1 8424 MEA 16%, about 17%, about 18%, about 19%, about 20%, about 21%, about 22%, about 23%, about 24%, about 25%).

[0084] Referring to Fig. 1A, side view 101a and isometric view 101b show a canonical example assembly of the exemplary device 100 where two stacked dies 104a, 104b are positioned on top of the package substrate 102. The bottom die 104b is oriented face down, while the top die 104a is positioned face up. The term “face” of a wafer, die, chip, or chiplet refers to the side of the semiconductor or component 105 having active devices such as diodes and transistors. The term "backside" of a wafer, die, chip, or chiplet refers to an opposing surface of the device. Fig.1B shows a second example of the exemplary device 100b with 3D conductive exterior routings.

[0085] The attachment of the top die 104a onto the bottom die 104b is facilitated by the conformal conductive straps 106 (shown as 106a, 106b, 106c, 106d, 106e, 106f, 106g in view 101b) to establish the electrical connection between the two dies. In view 101b, the 3D conductive exterior routing(s) 106a – 106f are conformal in thicknesses and are electrically isolated from one other, e.g., as 1.8V, 3.3V, 5V, 12V, -1.8V, -3.3V, -5V, -12V, GND1, GND2, a clock signal (CLK), data signals. In some embodiments, the 3D conductive exterior routing 106 can form buses, e.g., having 8 or 9 conductors (e.g., 8 data and / or GND), 12 or 13 conductors (e.g., 12 data and / or GND), 16 or 17 conductors (e.g., 16 data and / or GND), 32 or 33 conductors (e.g., 32 data and / or GND), 64 or 65 conductors (e.g., 64 data and / or GND), among others. In Fig.1B, both the top and bottom chips / dies 104a, 104b are oriented face up (having active circuits 105) and also in electrical contact with the conformal conductive 3D conductive exterior routing(s) 106a – 106f.

[0086] View 101c (Fig.1A) shows a portion of the side view 101a. The dies 104a, 104b and substrate 102 may include one or more IO pins or power / GND connection 111, each comprising a conductor formed with a top metal layer 110 of an integrated circuit formed by the die (e.g., 104a, 104b). The metal layer 110 may be isolated from the 3D conducive exterior routing 106 by a passivation layer 112 formed at the surface of the die (e.g., 104a, 104b). Other connections may be employed, e.g., via RDL or package balls, among others.

[0087] While shown with two dies, the number of dies and components can be greater than 2, e.g., 3, 4, 5, 6, 7, 8, 9, 10, 11, 12. In some embodiments, the number of dies or components is greater than 12.Attorney Docket No.10046-620WO1 8424 MEA

[0088] In some embodiments, the first conductor is a signal line (e.g., 106a), the second conductor (e.g., 106b) forms a power line or plane, and the third conductor (e.g., 106c) forms a ground line or plane.

[0089] In some embodiments, the first conductor is a power line or plane (e.g., 106a), the second conductor (e.g., 106b) forms a signal line, and the third conductor (e.g., 106c) forms a ground line or plane.

[0090] In some embodiments, the first conductor is a ground line or plane (e.g., 106a), the second conductor (e.g., 106b) forms a power line or plane, and the third conductor (e.g., 106c) forms a signal line.

[0091] In some embodiments, the die does not have through-silicon vias (TSV) for a power line.

[0092] Present technology utilizes wire bonds [5] or TSVs. Wire bonds are not conformal and must be protected, e.g., using mold compound. TSVs are often used for 3D chip stacking but require expensive processing equipment. The approach disclosed herein differs by being 1) conformal to the die structure, 2) relatively inexpensive, and 3) providing for an alternative electrical path for electrical power distribution which in turn improves power quality to the microsystem.

[0093] Three-dimensional stacked dies require through-silicon vias (TSVs) or through- semiconductor vias to operate. However, TSVs come with high costs and significant design constraints. Moreover, restricting electrical conduction through TSVs limits current density, thereby reducing the amount of power that can be transmitted through these conductors. A cost- effective alternative would find practical application in certain scenarios. This approach can be used in conjunction with traditional approaches such as TSVs.

[0094] TSVs use precious semiconductor chip real estate, are expensive, and must be shared with other purposes. For example, TSVs are used for signaling in addition to power and ground. By utilizing the exterior of the chip, the exemplary system and method provide an alternative conductive path that can be utilized to improve the power integrity of the overall stack.

[0095] The line / space fidelity of the exemplary exterior conductive surface routing (also interchangeably referred to as 3D conductive straps) can be defined using processes such as photolithography. The 3D conductive straps are conformal to the chips / dies and can be as thick as 1 mm per chip (or multiple millimeters with a plurality of chips). The height can be limited by the lithography depth of field (currently optimized for two-dimensional features). WithAttorney Docket No.10046-620WO1 8424 MEA additional optimization of the tooling or development of direct write tooling, the height of the 3D conductor can be increased.

[0096] Power distribution within stacked die will become increasingly more difficult. The exemplary system and method approach can make stacked die more economically viable, utilizing unused real estate, and improve the power delivery to stacked die, e.g., to increase stacking or provide for potentially new computing architectures.

[0097] TSV Example + 3D conductive exterior routings. Fig.1C shows a third example of the exemplary device 100c configured with 3D conductive exterior routings 106 and through-silicon vias 114. In the example shown in Fig. 1C, the exemplary device 100c as a stacked die device as a bottom die 104b that includes TSVs 114. The top die 104a establishes electrical connections with the TSVs 114 through a bonding layer 224a. The bottom die 104b establishes an electrical connection to the substrate 102 (e.g., PCB) through a bonding layer 116a. In the example, both the top and bottom dies 104a, 104b are oriented with their active sides 226a, 226b facing downward (i.e., “face down”). The stacked device 100c includes package ball 118 to mount, e.g., to a printed circuit board or another device. The bonding layers 116a, 116b may employ package balls or RDL bumps, among others.

[0098] 3D conductive exterior plane. Fig.1D shows a fourth example of the exemplary device 100d configured with 3D conductive exterior plane structure 107, similar to 3D conductive exterior routing 106. In Fig.1D, both the top and bottom chips / dies 104a, 104b are oriented face up (having active circuits 105) and also in electrical contact with the conformal conductive 3D conductive exterior routings 106a – 106c and the conformal conductive 3D conductive exterior plane 107. The plane structure 107 may be employed for power or GND. In some embodiments, the plane is employed for EMI insulation.

[0099] Chiplets. Fig.1E shows a fifth example of the exemplary device 100e configured with 3D conductive exterior routing over multiple dies or components. In Fig. 1E, three top dies (104a, 104c, 104d) are oriented face up (having active circuits 105), and the bottom die 104b is oriented face down. The dies 104a, 104b, 104c, 104d, and substrate 102 are in electrical contact with each other via conformal conductive 3D conductive exterior routings 106a, 106b. Fig.1E shows an example of the integration of chiplets that can be electrically connected into a single device.

[0100] Multi-layer stacked device. Fig. 1F and 1G each shows a sixth and seventh example, respectively, of the exemplary devices 100f, 100g configured with 3D conductive exterior routing over multiple dies or components in another stacked configuration.Attorney Docket No.10046-620WO1 8424 MEA

[0101] In the example shown in Fig.1F and 1G, to provide for the connections, some of each of the dies 104 (shown as 104a, 104b, 104c, 104d) includes connections or IO pins (e.g., 111) having metal layer 110 to electrical connect to the 3D conductive exterior routing 106 or plane 107.

[0102] Example Conforming Uniform Deposition. Metal-organic decomposition (MOD) can be used to deposit metals onto the surfaces (e.g., 107a, 108a, 108b). Metal-organic decomposition (MOD) [3] can also be used to deposit dielectrics onto surfaces (e.g., 107a, 108a, 108b). Materials (metal) may include and are not limited to silver, gold, platinum, nickel, copper, or a mixture thereof in a conductive ink or conductive film. Dielectrics may include monomers or prepolymers that may be deposited via Metal-organic decomposition or deposition via nanoparticle inks, Chemical Vapor Deposition (CVD), and Physical Vapor Deposition (PVD), among others.

[0103] Metal-organic decomposition (and other deposition operation) can include screen printing, spraying, or ink jetting. Deposited films can be cured, e.g., at temperatures of 180°C. In some embodiments, the curing can be between 150 °C and 300 °C, e.g., around 150 °C, around 230 °C, around 240 °C, around 250 °C, around 260 °C, around 270 °C, around 280 °C, around 290 °C, around 300 °C. In some embodiments, the curing temperature is less than 150 °C. In some embodiments, the curing temperature is greater than 300 °C.

[0104] In some embodiments, the deposited films can be cured using UV radiation. Film thicknesses (post curing) can be between 500 nanometers (nm) and 30 microns (µm), e.g., about 500 nm, about 510 nm, about 520 nm, about 530 nm, about 540 nm, about 550 nm, about 560 nm, about 570 nm, about 580 nm, about 590 nm, about 600 nm, about 610 nm, about 620 nm, about 630 nm, about 640 nm, about 650 nm, about 660 nm, about 670 nm, about 680 nm, about 690 nm, about 700 nm, about 710 nm, about 720 nm, about 730 nm, about 740 nm, about 750 nm, about 760 nm, about 770 nm, about 780 nm, about 790 nm, about 800 nm, about 810 nm, about 820 nm, about 830 nm, about 840 nm, about 850 nm, about 860 nm, about 870 nm, about 880 nm, about 890 nm, about 900 nm, about 910 nm, about 920 nm, about 930 nm, about 940 nm, about 950 nm, about 960 nm, about 970 nm, about 980 nm, about 990 nm, about 1 µm, about 1.1 µm, about 1.2 µm, about 1.3 µm, about 1.4 µm, about 1.5 µm, about 1.6 µm, about 1.7 µm, about 1.8 µm, about 1.9 µm, about 2 µm, about 2.1 µm, about 2.2 µm, about 2.3 µm, about 2.4 µm, about 2.5 µm, about 2.6 µm, about 2.7 µm, about 2.8 µm, about 2.9 µm, about 3 µm, about 3 µm, about 3.1 µm, about 3.2 µm, about 3.3 µm, about 3.4 µm, about 3.5 µm, about 3.6 µm, about 3.7 µm, about 3.8 µm, about 3.9 µm, about 4 µm, about 4.1 µm, aboutAttorney Docket No.10046-620WO1 8424 MEA 4.2 µm, about 4.3 µm, about r.4 µm, about 4.5 µm, about 4.6 µm, about 4.7 µm, about 4.8 µm, about 4.9 µm, about 5 µm, about 5.5 µm, about 6 µm, about 6.5 µm, about 7 µm, about 7.5 µm, about 8 µm, about 8.5 µm, about 9 µm, about 9.5 µm, about 10 µm, about 10.5 µm, about 11 µm, about 11.5 µm, about 12 µm, about 12.5 µm, about 13 µm, about 13.5 µm, about 14 µm , about 14.5 µm, about 15 µm, about 15.5 µm, about 16 µm, about 16.5 µm, about 17 µm, about 17.5 µm, about 18 µm, about 18.5 µm, about 19 µm, about 19.5 µm, about 20 µm, about 20.5 µm, about 21 µm, about 21.5 µm, about 22 µm, about 22.5 µm, about 23 µm, about 23.5 µm, about 24 µm, about 24.5 µm, about 25 µm, about 25.5 µm, about 26 µm, about 26.5 µm, about 27 µm, about 27.5 µm, about 28 µm, about 28.5 µm, about 29 µm, about 29.5 µm, about 30 µm. In some embodiments, the layer conductor thickness is greater than 30 um. Thicker film thicknesses, in some embodiments, can be deposited, e.g., using electroplating using the deposited material as a seed layer.

[0105] Patterning operation. If the film is deposited using ink jetting, the resulting pattern is determined by the electron jetting process. Alternatively, for films coated via spraying, surface patterning can be achieved through various methods. These methods include using an aperture approach during the spray coating process, creating a hydrophobic surface, or employing traditional photolithographic lift off§ techniques.

[0106] To facilitate 3D lift off, the industry has developed photoresist spray coating equipment, e.g., [2]. Each of the processes can control and define the pattern on the surface of the sprayed film.

[0107] Single Die and Stacked Die Package Discussion

[0108] Figs. 2A – 2D shows the typical connection of TSVs to CMOS circuits through local interconnects. The local interconnects of Figs.2A – 2D can be used in combination with the 3D conductive exterior routing or planes of Figs.1A – 1G.

[0109] Single die package. Fig.2A shows a side perspective of a single die package 200a having a semiconductor die 202 (shown as “die 202”) flipchipped onto a package substrate 204. In the configuration, the die 202 is positioned with its face 206 downward, where the face 206 denotes the side of the die 202 containing the active integrated circuits. The package substrate 204 includes through-silicon vias 208 that connect the die 202 to the printed circuit board (PCB) 210. In the example, the die 202 connects to the package substrate 204 through redistribution-layer (RDL) bumps 212. The package substrate 204 connects to the PCB 210 through package balls 214. An example routing 216a-216e is shown between the die 202 andAttorney Docket No.10046-620WO1 8424 MEA the PCB 212 through external routing 216a, 216b on the package substrate through the TSV 216c, and exterior bumps 216d, 216e to routing 216f on the PCB 212.

[0110] Fig. 2B shows a stacked die device 200b having a bottom die 218 that includes TSVs 220. In the example shown in Fig.2A, the top die 222 establishes electrical connections with the TSVs 220 through a bonding layer 224a. The bottom die 218 establishes an electrical connection to the PCB (e.g., 212) through a bonding layer 224b. In the example, both the top and bottom dies 222, 218 are oriented with their active sides 226a, 226b facing downward (i.e., “face down”). The stacked device 200b includes package ball 214 to mount, e.g., to a PCB (e.g., 212) or another device. The bonding layers 224a, 224b may employ package balls (e.g., 214) or RDL bumps (e.g., 212).

[0111] Stacked die with TSVs. Fig. 2C shows a three-dimensional stacked die 200c having vertical electrical connections formed by through-silicon vias 220. While TSVs 220 are necessary for vertical interconnections, they often present a costly option for many applications.

[0112] TSV + Metal Routing. Fig. 2D shows a four-stacked die structure 200d interconnected via through-silicon vias 220. In Fig. 2D, an electrical model of the internal metal tracings are additionally shown.

[0113] Example Method of Fabrication

[0114] Figs. 3A and 3B each shows an example method 300a, 300b, respectively, to fabricate a stacked multi-component device (e.g., 100) that has conformally deposited metal conductors on its exterior surface at both the vertical and horizontal sides of its components (e.g., dies and substrate) to provide an interpackage or intercomponent routing or metal plane for ground, power, and / or signal along the exterior surfaces in accordance with an illustrative embodiment.

[0115] The method includes providing a substrate (e.g., 102) having a top surface (e.g., 107a); attaching a die (e.g., 104, 104a, 104b, 104c, etc.) onto the substrate(e.g., 102) where the die (e.g., (e.g., 104, 104a, 104b, 104c, etc.) has a top surface (e.g., 108a) and a side surface (e.g., 108b); and depositing a metal to generate a uniform metal layer (e.g., 106) on the top surface (e.g.., 107a) of the substrate (e.g., 102), the top surface (e.g., 108a) of the die (e.g., 104, 104a, 104b, 104c, etc.), and the side surface (e.g., 108b) of the die (e.g., 104, 104a, 104b, 104c, etc.) to form a continuous uniformly thick conductor between the die (e.g., 104, 104a, 104b, 104c, etc.) and the substrate (e.g., 102) where the metal layer (e.g., 106) forms at least one conductor, including a first conductor, as a power line, a ground line or plane, or a signalAttorney Docket No.10046-620WO1 8424 MEA line. The top surface of the substrate and the top surface of the die have a first thickness where the side surface of the die has a second thickness, wherein the first thickness is substantially similar to the second thickness (e.g., within 5% - 25%).

[0116] In some embodiments, the top surface 107a of the substrate 102 and the top surface 108a of the die 104 has a first thickness, and the side surface 108b of the die 104 has a second thickness that is substantially similar to the first thickness (e.g., within 1% - 25%, e.g., less than 1%, about 1%, about 2%, about 3%, about 4%, about 5%, about 6%, about 7%, about 8%, about 9%, about 10%, about 11%, about 12%, about 13%, about 14%, about 15%, about 16%, about 17%, about 18%, about 19%, about 20%, about 21%, about 22%, about 23%, about 24%, about 25%).

[0117] In some embodiments, the top surface of the die includes an exposed top metal contact (e.g., 110) surrounded by a passivation layer (e.g., 112), and the conductor (e.g., 106) is deposited over the exposed top metal contact (e.g., 110) to form an electric contact between a circuit of the die (e.g., 104, 104a, 104b, 104c, etc.) and a circuit or electrical structure of the substrate (e.g., 102).

[0118] In some embodiments, the first conductor is a signal line (e.g., 106a), the second conductor (e.g., 106b) forms a power line or plane, and the third conductor (e.g., 106c) forms a ground line or plane.

[0119] In some embodiments, the first conductor is a power line or plane (e.g., 106a), the second conductor (e.g., 106b) forms a signal line, and the third conductor (e.g., 106c) forms a ground line or plane.

[0120] In some embodiments, the first conductor is a ground line or plane (e.g., 106a), the second conductor (e.g., 106b) forms a power line or plane, and the third conductor (e.g., 106c) forms a signal line.

[0121] In some embodiments, the die does not have through-silicon vias (TSV) for a power line.

[0122] The step of depositing the metal to generate the uniform metal layer (e.g., 106) on the top surface (e.g., 107a) of the substrate (e.g., 102), the top surface (e.g., 108a) of the die (e.g., 104, 104a, 104b, 104c, etc.), and the side surface (e.g., 108b) of the die (e.g., 104, 104a, 104b, 104c, etc.) comprise Metal Organic Decomposition (MOD) process.

[0123] Spray Operation. In some embodiments, the Metal Organic Decomposition process employs a spray operation (e.g., using apertures or liftoff lithography). Fig.3A shows a deposition operation 300a using Metal Organic Decomposition to deposit a conformalAttorney Docket No.10046-620WO1 8424 MEA uniform layer (e.g., metal layer 106) over a device. In the example shown in Fig.3A, the device (e.g., 100a, 100b, 100c, 100d, 100e) corresponds to those shown in Fig.1A – 1E, though other devices can be employed, including those shown or referenced herein, among others. Operation 300a includes providing (302) a device (e.g., 100) and bonding (304) the dies (e.g., 104, now referenced as 305a, 305b) and components (e.g., 102, now referenced as 305c) of the device together via a bonding layer (e.g., 116, now referenced as 307).

[0124] Operation 300a then includes depositing (306) a photoresist layer 309 over the device and patterning (308) a cured portion 311 of the photoresist layer 309. Operation 300a then includes removing (310) the photoresist layer 309 and applying (312) the Metal-Organic Decomposition process via a spraying action to form a uniformed conformal 3D conductive exterior routing (e.g., 106). The photoresist 311 can be removed to provide (314) a fully or partially fabricated structure.

[0125] Ink jet operation. In some embodiments, the Metal-Organic Decomposition process employs an ink-jetting operation (e.g., to form a pattern as the metal layer). Fig. 3B shows a deposition operation 300b using Metal Organic Decomposition to deposit a conformal uniform layer (e.g., metal layer 106) over a device via an inkjet operation. In the example shown in Fig.3B, the device (e.g., 100a, 100b, 100c, 100d, 100e) corresponds to those shown in Fig. 1A – 1E, though other devices can be employed, including those shown or referenced herein, among others.

[0126] Operation 300b includes providing (302) a device and bonding (304) the dies (e.g., 104, now referenced as 305a, 305b) and components of the device together (e.g., 102, now referenced as 305c) via a bonding layer (e.g., 116, now referenced as 307).

[0127] Operation 300b then includes depositing (316) via a Metal-Organic Decomposition process via an inkjet operation to directly form a uniformed conformal 3D conductive exterior routing (e.g., 106). The inkjet operation includes depositing the material at a first position 317a to a second position 317b to provide (318) a fully or partially fabricated device.

[0128] In addition to MOD, deposition of nanoparticle inks, Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD) may be used, among others described herein.

[0129] In some embodiments, the method further includes depositing a dielectric material to generate a dielectric layer over the conductor and depositing additional metal to generate a second metal layer over the dielectric layer.Attorney Docket No.10046-620WO1 8424 MEA

[0130] In some embodiments, the die or structure includes a plurality of trench structures, where the conductor, the dielectric layer, and the second metal layer are formed over the plurality of trench structures to form capacitors (e.g., decoupling capacitors).

[0131] Backside Power and In-Situ Decouple Cap

[0132] Figs. 4A and 4B show examples of in-situ decoupling capacitors that can be formed in the die (e.g., 104) or substrate (e.g., 102) from the 3D conductive exterior routings 106. In the example shown in Fig.4A, the routings 106 (shown 106’ and 106”) are interleaved and overlapping across a dielectric layer 402 (e.g., via MOD deposition) to form either a backside or frontside contact with the chip or die. For example, one of the films is in electrical contact with ground (i.e., Vss) while the other is in electrical contact with power (i.e., Vdd). In embodiments where the chip or die (e.g., 104) has multiple power rails, then a plurality of overlapping or interleaving structures may be employed to form a Power Distribution Network (PDN) of the chips. PDN can benefit high-performance processors, and the benefit of backside or buried power distribution has been reported [3], [4].

[0133] Fig. 4B shows deep trench capacitors formed of the 3D conductive exterior routings 106. The backside of a die or chip may be formed with backside deep trench etching, then, employing the exemplary method, 3D conductive exterior routings 106’, 106” of metal and dielectric (402) can be formed in the trench structure 404 to fabricate Deep Trench Capacitors (DTC). The DTCs could improve the decoupling capacitance of any 3D PDN system.

[0134] Figs. 1G shows the multi-stack device 100g configured with deep trench capacitors 406 and in-situ decoupling capacitors 408.

[0135] Integrated Heat Spreader

[0136] In another aspect, a second exemplary system and method are disclosed that integrates single or two-phase cooling directly into the microelectronic package using a conformal hermetic film covering a stacked die and any surface components. For single phase cooling, a lid may be employed to facilitate liquid cooling. For two-phase cooling, the base hermetic film is employed as a template for the growth of a wicking material. The lid can complete the assembly similar to commercial vapor chambers. The second exemplary system and method can reduce the expected junction temperature of stacked semiconductor die by reducing the thermal impedance to the external thermal bath. The second exemplary system and method may be employed to cool the die and substrate described in relation to Figs.1A – 1G, among other examples described herein.Attorney Docket No.10046-620WO1 8424 MEA

[0137] Figs. 5A and 5B each shows a multi-chip package 500 (shown as 500a, 500b) having a substrate 502 and a die 504. The substrate 502 has a top surface 506, and the die 504 (shown as 504a, 504b) is coupled to the substrate 502 and has a top surface 508a and a side surface 508b. A sealing layer 506 is formed over the top surface 506 of the substrate 502, the side surface 508b of the die 502, and the top surface 508a of the die 502 to form a sealed coating of the die 504 and substrate 504. A housing mechanically 510 is coupled to the substrate 502 to define a volume 512 over the top surface 506 of the substrate 502 and the top surface 508a of the die 504. The housing has an inlet 514. The sealing layer 506 forms a uniform hermetic seal that covers the substrate (e.g., 502) (e.g., organic substrate) and the die (e.g., 504a, 504b).

[0138] A coolant 513 is directable into the inlet 514, the coolant 513 is configured in volume 512 to draw heat from the substrate 502 and die 504a, 504b to thermally regulate the temperature of the die 504a, 504b and substrate 502. Indeed, the outer surface of the assembly is coated in a thin layer of metal. In one embodiment, this layer is deposited via a spray or ink jet of Metal-Organic Decomposition (MOD). A uniform hermetic seal covers the organic substrate and the stacked chips. This seal can be applied using spray or inkjet Metal-Organic Decomposition (MOD). The MOD process can create a seal up to thirty microns thick, and additional thickness can be achieved with subsequent electro-deposition or electroless plating if necessary.

[0139] In the example shown in Fig. 5A, the housing 510 includes an outlet 516 where the coolant 513 is circulatable 518 into the inlet 514, through the volume 512, and out the outlet 516 to regulate the temperature of the die 504a, 504b and substrate 502.

[0140] The housing 510 may be attached, e.g., mechanically coupled, to the substrate (e.g., 502) via seam sealing or soldering. In some embodiments, a capillary underfill solder process may be used in which MOD is drawn into the interface by capillary forces and then a thermal process is applied to form the metal solder. The inset image in Fig.5A and 5D shows the housing 510, as a lid directly soldered onto the film 506, e.g., as a solder mask defined Pad 515 [6]. Fig.5C shows housing 510, as a lid, being coupled to the substrate 501 by a capillary underfill solder process.

[0141] Example of coolants (e.g., 513) includes and are not limited to water fluorinert [7], Novec 649 [8]. Table 1 provides examples of other coolants 513

[0010] and their associated thermal properties. The in-situ liquid cooling

[0010] ,

[0011] can employ single- or two-phase cooling.Attorney Docket No.10046-620WO1 8424 MEA

[0142] In typical microelectronic packages, the package assembly ends with an Integrated Heat Spreader (IHS) which is also known as a lid. A thin layer of polymer or metal connects the top of the chip surface to the IHS. Any addition of a vapor chamber, chill plate, or other heat sink is in addition to the microelectronic assembly. In the disclosed invention, liquid cooling or a vapor chamber is integrated directly into the microelectronic assembly. By integrating these features, a reduction in the thermal resistance between the semiconductor devices and the ambient is achieved.

[0143] Microelectronic assemblies such as those used in AI / ML applications are dissipating significant power (e.g., greater than 400W). This power must be efficiently extracted from the microelectronics to maintain performance and reliability. Without novel thermal management approaches, it will be difficult to increase the density of microelectronics (including 3DHI assemblies).

[0144] Commercial systems are already utilizing ad hoc liquid cooling. This approach will enable a simplified approach that will be more effective while reducing the BOM complexity of microelectronic systems. The invention requires additional processing steps in the assembly process. However, these processes will be high-yield and could be batch processed. Table 1 Coolant Freezing Flash Viscosity Thermal Specific Density chemistry point point kg.m-1.s-1conductivity heat kg.m-3Attorney Docket No.10046-620WO1 8424 MEA Ga-ln-Sn -10 None 0.0022 39 365 6363513 is configured to evaporate from at least one of (i) surfaces (508a, 508b) of the die (504a, 504b) and (ii) the surface 506 of the substrate 502 and to condense at a condensing portion of the housing 510 (e.g., inwardly facing to the die and substrate). The condensing portion can be at the top of the housing 510.

[0146] In some embodiments, the sealing layer 506 is formed via at least one of a Metal Organic Decomposition (MOD) process, deposition of nanoparticle inks, Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD). The sealing layer 506 has (i) a first thickness at a first region on the die or substrate and (ii) a second thickness at a second region on the die or substrate, wherein the second thickness is thicker than the first thickness.

[0147] Die Surface Finned Heat Sink. In some embodiments, the die (e.g., 504) and / or substrate (e.g., 502) include a pattern or structure that forms a finned heat sink (e.g., pin-finned heat sink) in volume 512. The in-situ liquid cooling

[0010] ,

[0011] can employ single- or two-phase cooling.

[0148] Fig. 6A shows an example configuration of the die (e.g., 504) or substrate (e.g., 502) configured with a finned heat sink 602. Additional description of finned heat sink 602 may be found in Mallavarapu, Akhila, et al. "Ruthenium-assisted chemical etching of silicon: Enabling CMOS-compatible 3D semiconductor device nanofabrication." ACS Applied Materials & Interfaces 13.1 (2020): 1169-1177, which is incorporated by reference herein.

[0149] In some embodiments, a pin-finned heat sink 604 may be implemented. Additional descriptions of the pin-finned heat sink may be found in Sarvey, Thomas E., et al. "Monolithic integration of a micropin-fin heat sink in a 28-nm FPGA."IEEE Transactions on Components, Packaging and Manufacturing Technology7.10 (2017): 1617-1624, which is incorporated by reference herein.

[0150] In some embodiments, micromachined jets 606 may be used for liquid impingement cooling. Additional descriptions of liquid impingement cooling may be found in Wang, Evelyn N., et al. "Micromachined jets for liquid impingement cooling of VLSI chips." Journal of Microelectromechanical systems 13.5 (2004): 833-842, which is incorporated by reference herein.

[0151] The dimensions of the fins can be optimized to improve heat conduction from the semiconductor chip to the cooling fluid. Various techniques can be employed to create these fin structures on the chips, as indicated by the two references provided. Micromachined jetsAttorney Docket No.10046-620WO1 8424 MEA 606 show that the port location can be adjusted to allow the cooling liquid to directly impinge onto the chips.

[0152] Fig.6B shows an example cooling loop system employing the device 500a. The cooling loop system further shows a close loop channel having a heat exchanger and pump. A controller can operate the pump, e.g., based on temperature sensed via sensors. The controller may store the instructions to execute the sequence of operations to regulate the temperature of the device. The controller as a computing system or interconnected machine logic circuits or circuit modules, or sets or modules thereof, may implement a sequence of computer- implemented acts or program modules. Accordingly, the logical operations described herein are referred to variously as state operations, acts, or modules. These operations, acts, and / or modules can be implemented in software, in firmware, in special purpose digital logic, in hardware, and any combination thereof. It should also be appreciated that more or fewer operations can be performed than shown in the figures and described herein. These operations can also be performed in a different order than those described herein.

[0153] The computer system is capable of executing the software components described herein for the exemplary method or systems. In an embodiment, the computing device may comprise two or more computers in communication with each other that collaborate to perform a task. For example, but not by way of limitation, an application may be partitioned in such a way as to permit concurrent and / or parallel processing of the instructions of the application.

[0154] The processing unit may be a programmable processor that performs arithmetic and logic operations necessary for the operation of the computing device. While only one processing unit is shown, multiple processors may be present. As used herein, processing unit and processor refers to a physical hardware device that executes encoded instructions for performing functions on inputs and creating outputs, including, for example, but not limited to, microprocessors (MCUs), microcontrollers, graphical processing units (GPUs), and application-specific circuits (ASICs). Thus, while instructions may be discussed as executed by a processor, the instructions may be executed simultaneously, serially, or otherwise executed by one or multiple processors. The computing device may also include a bus or other communication mechanism for communicating information among various components of the computing device.

[0155] Computing devices may have additional features / functionality. For example, the computing device may include additional storage, such as removable storage and non-Attorney Docket No.10046-620WO1 8424 MEA removable storage. Computing devices of the controller may also contain network connection(s) that allow the device to communicate with other devices, such as over the communication pathways described herein. The controller operates with sensors, e.g., temperature sensors, pressure sensors, and pump sensors, to control the thermal regulation loop.

[0156] Example Vapor Chamber

[0157] In some embodiments, the multi-stacked device is placed in a housing 510 that forms a vapor chamber, the housing 510 includes a wicking layer.

[0158] Vapor chambers are two-phase devices with a surface that efficiently spreads heat from high power or high heat flux electronics. Typically used in place of the base plate in a standard metal heat sink or heat pipe in a two-phase heat sink, these devices can reduce the conduction loss (Delta-T) in a thermal assembly by 50% or more, resulting in a solution with lower overall thermal resistance. Vapor chambers

[0015] are also known as planar heat pipes or heat spreaders.

[0159] Figs. 7A – 7C each shows an example of a vapor chamber 700 (shown as 700a, 700b, 700c) having a multi-stack device. In the example shown in Fig. 7A, the housing 510 includes a wicking layer 702. In the vapor chamber 700a, a cooling liquid 702 evaporates from the die's surface of the multi-stack device and condenses on the lid of the assembly. The condensed liquid returns to the cold side of the vapor chamber, wicking towards the chip / die, and the process repeats.

[0160] In the example shown in Fig. 7A, the housing 510 includes a wicking structure 704 that extends from the wicking layer 702. The wicking structure 704 is configured to extend from the condensing portion of the housing 510 to at least one of (i) the top surface of the substrate (e.g., 502) or (ii) a second wicking layer 706 formed thereon.

[0161] Patterning the wicking material, as shown in [Cheng 2021], may facilitate preferential capillary flow toward hotspots on the die surface. Examples of other wick patterns

[0016] and print wick

[0017] may be found in Cheng, Xin, Guang Yang, and Jingyi Wu. "Recent advances in the optimization of evaporator wicks of vapor chambers: From mechanism to fabrication technologies." Applied Thermal Engineering 188 (2021): 116611 and Print Wick: Zou, Dingsen, et al. "Design and fabrication of a large area ultra-thin vapor chamber based on Print-Wick-Structuring technology."IEEE Transactions on Components, Packaging and Manufacturing Technology(2023), respectively.Attorney Docket No.10046-620WO1 8424 MEA

[0162] Fig.7B shows two examples 708, 710 of the wicking material (e.g., 702, 706). In one example, copper foam

[0018] is employed as the wicking material. In another example, the wicking material is a copper mesh

[0019] . In both examples, the pore size of the copper foam or the size of the copper mesh can be optimized to control the capillary flow of the cooling liquid.

[0163] Fig. 7C depicts an embodiment where the copper mesh or copper foam extends from the cold side of the vapor chamber to the hot side, enabling the condensation and return of the cooling fluid. In this example, and others, the copper foam can be plated onto the assembly using the underlying metal substrate. In the case of the hermetic seal mentioned in Figure 1, the underlying metal substrate is the MOD hermetic seal. Indeed, the housing includes a wicking layer formed over the condensing portion of the housing, the housing including one or more wall sections that define in part the volume. The wicking layer extends from the condensing portion of the housing to the first wall section to contact a wicking layer formed on the top surface of the substrate, to form a closed loop circulation of the coolant from the wicking layer formed over the condensing portion of the housing to the wicking layer formed on the top surface of the substrate. Additional examples of closed-loop circulation may be found in

[0020] .

[0164] Conclusion

[0165] Unless otherwise expressly stated, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not actually recite an order to be followed by its steps or it is not otherwise specifically stated in the claims or descriptions that the steps are to be limited to a specific order, it is no way intended that an order be inferred, in any respect. This holds for any possible non-express basis for interpretation, including: matters of logic with respect to the arrangement of steps or operational flow; plain meaning derived from grammatical organization or punctuation; the number or type of embodiments described in the specification.

[0166] While the methods and systems have been described in connection with certain embodiments and specific examples, it is not intended that the scope be limited to the particular embodiments set forth, as the embodiments herein are intended in all respects to be illustrative rather than restrictive.

[0167] In this specification and in the claims that follow, reference will be made to a number of terms, which shall be defined to have the following meanings:Attorney Docket No.10046-620WO1 8424 MEA

[0168] As used herein, “comprising” is to be interpreted as specifying the presence of the stated features, integers, steps, or components as referred to, but does not preclude the presence or addition of one or more features, integers, steps, or components, or groups thereof. Moreover, each of the terms “by”, “comprising,” “comprises”, “comprised of,” “including,” “includes,” “included,” “involving,” “involves,” “involved,” and “such as” are used in their open, non-limiting sense and may be used interchangeably. Further, the term “comprising” is intended to include examples and aspects encompassed by the terms “consisting essentially of” and “consisting of.” Similarly, the term “consisting essentially of” is intended to include examples encompassed by the term “consisting of.

[0169] As used in the specification and the appended claims, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a compound”, “a composition”, or “a cancer”, includes, but is not limited to, two or more such compounds, compositions, or cancers, and the like.

[0170] It should be noted that ratios, concentrations, amounts, and other numerical data can be expressed herein in a range format. It can be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint. It is also understood that there are a number of values disclosed herein, and that each value is also herein disclosed as “about” that particular value in addition to the value itself. For example, if the value “10” is disclosed, then “about 10” is also disclosed. Ranges can be expressed herein as from “about” one particular value, and / or to “about” another particular value. Similarly, when values are expressed as approximations, by use of the antecedent “about,” it can be understood that the particular value forms a further aspect. For example, if the value “about 10” is disclosed, then “10” is also disclosed.

[0171] When a range is expressed, a further aspect includes from the one particular value and / or to the other particular value. For example, where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the disclosure, e.g. the phrase “x to y” includes the range from ‘x’ to ‘y’ as well as the range greater than ‘x’ and less than ‘y’. The range can also be expressed as an upper limit, e.g. ‘about x, y, z, or less’ and should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of ‘less than x’, less than y’, and ‘less than z’. Likewise, the phrase ‘about x, y, z, or greater’ should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of ‘greater than x’, greater than y’, and ‘greaterAttorney Docket No.10046-620WO1 8424 MEA than z’. In addition, the phrase “about ‘x’ to ‘y’”, where ‘x’ and ‘y’ are numerical values, includes “about ‘x’ to about ‘y’”.

[0172] It is to be understood that such a range format is used for convenience and brevity, and thus, should be interpreted in a flexible manner to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. To illustrate, a numerical range of “about 0.1% to 5%” should be interpreted to include not only the explicitly recited values of about 0.1% to about 5%, but also include individual values (e.g., about 1%, about 2%, about 3%, and about 4%) and the sub- ranges (e.g., about 0.5% to about 1.1%; about 5% to about 2.4%; about 0.5% to about 3.2%, and about 0.5% to about 4.4%, and other possible sub-ranges) within the indicated range.

[0173] As used herein, the terms “about,” “approximate,” “at or about,” and “substantially” mean that the amount or value in question can be the exact value or a value that provides equivalent results or effects as recited in the claims or taught herein. That is, it is understood that amounts, sizes, formulations, parameters, and other quantities and characteristics are not and need not be exact, but may be approximate and / or larger or smaller, as desired, reflecting tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those of skill in the art such that equivalent results or effects are obtained. In some circumstances, the value that provides equivalent results or effects cannot be reasonably determined. In such cases, it is generally understood, as used herein, that “about” and “at or about” mean the nominal value indicated ±10% variation unless otherwise indicated or inferred. In general, an amount, size, formulation, parameter or other quantity or characteristic is “about,” “approximate,” or “at or about” whether or not expressly stated to be such. It is understood that where “about,” “approximate,” or “at or about” is used before a quantitative value, the parameter also includes the specific quantitative value itself, unless specifically stated otherwise.

[0174] As used herein, the terms “optional” or “optionally” means that the subsequently described event or circumstance can or cannot occur, and that the description includes instances where said event or circumstance occurs and instances where it does not.

[0175] Throughout this application, various publications may have been referenced. The disclosures of these publications in their entireties are hereby incorporated by reference into this application in order to more fully describe the state of the art to which this invention pertains.Attorney Docket No.10046-620WO1 8424 MEA Reference List [1] https: / / electroninksgccmy.sharepoint.com / :p: / g / personal / melbs_electroninks_com / EdcVXLLaAhJCmdc5Y9ciH3wBnkouM09AeUSoT4dBytzgmw?rtime=55F0LOs-3Eg [2] https: / / www.sono-tek.com / industry / semiconductor / photoresist-and-polyimide-deposition / [3] Nibhanupudi, SS Teja, et al. "A holistic evaluation of buried power rails and back-side(2022): 4453-4459. [4] Hossen, Md Obaidul, et al. "Power delivery network (PDN) modeling for backside-PDN configurations with buried power rails and $\mu $ TSVs." IEEE Transactions on Electron Devices 67.1 (2019): 11-17. [5] https: / / www.ewh.ieee.org / soc / cpmt / presentations / cpmt0210b.pdf [6] smd-nsmd / [7][8] https: / / en.wikipedia.org / wiki / Perfluoro(2-methyl-3-pentanone) [9] https: / / www.electronics-cooling.com / 2006 / 05 / an-overview-of-liquid-coolants-for- electronics-cooling /

[0010] "Two-Phase Liquid Cooling forMicroelectronics viaFin Heat Sink." IEEE Transactions on Components, Packaging and Manufacturing Technology (2024).

[0011] https: / / www.intel.com / content / www / us / en / newsroom / news / key-investments-advance- data-center-sustainability.html#gs.6xabuu

[0012] Mallavarapu, Akhila, et al. "Ruthenium-assisted chemical etching of silicon: Enabling CMOS-compatible 3D semiconductor device nanofabrication." ACS Applied Materials & Interfaces 13.1 (2020): 1169-1177.

[0013] Sarvey, Thomas E., et al. "Monolithic integration of a micropin-fin heat sink in a 28-nm FPGA."IEEE Transactions on Components, Packaging and Manufacturing Technology7.10 (2017): 1617-1624.

[0014] Wang, Evelyn N., et al. "Micromachined jets for liquid impingement cooling of VLSI chips." Journal of Microelectromechanical systems 13.5 (2004): 833-842.

[0015] https: / / celsiainc.com / technology / vapor-chamber /

[0016] Wick Pattern: Cheng, Xin, Guang Yang, and Jingyi Wu. "Recent advances in the optimization of evaporator wicks of vapor chambers: From mechanism to fabrication technologies." Applied Thermal Engineering 188 (2021): 116611.Attorney Docket No.10046-620WO1 8424 MEA

[0017] Print Wick: Zou, Dingsen, et al. "Design and fabrication of a large area ultra-thin vapor chamber based on Print-Wick-Structuring technology."IEEE Transactions on Components, Packaging and Manufacturing Technology(2023).

[0018] Shin, Heon-Cheol, and Meilin Liu. "Copper foam structures with highly porous nanostructured walls."Chemistry of materials16.25 (2004): 5460-5464.

[0019] McNally, Dylan P., Ryan Lewis, and Y. C. Lee. "Characterization of hybrid wicking structures for flexible vapor chambers." Journal of Electronic Packaging 141.1 (2019): 011005.

[0020] Example Liquid Return: Zhou, Feng, Jingzhi Zhou, and Xiulan Huai. "Advancements and challenges in ultra-thin vapor chambers for high-efficiency electronic thermal management: A comprehensive review." International Journal of Heat and Mass Transfer 214 (2023): 124453

Claims

Attorney Docket No.10046-620WO1 8424 MEA WHAT IS CLAIMED IS:

1. A method comprising: providing a substrate having a top surface; attaching a die onto said substrate, wherein the die has a top surface and a side surface; and depositing a metal to generate a uniform metal layer on the top surface of the substrate, the top surface of the die, and the side surface of the die to form a continuous uniformly thick conductor between the die and the substrate, wherein the metal layer forms at least one conductor, including a first conductor, as a power line, a ground line or plane, or a signal line, wherein the top surface of the substrate and the top surface of the die have a first thickness, and wherein the side surface of the die has a second thickness, wherein the first thickness is substantially similar to the second thickness.

2. The method of claim 1, wherein the top surface of the die includes an exposed top metal contact surrounded by a passivation layer, and wherein the at least one conductor is deposited over the exposed top metal contact to form an electric contact between a circuit of the die and a circuit or electrical structure of the substrate.

3. The method of claim 1 or 2, wherein the first conductor is a signal line, and wherein the at least one conductor includes (i) a second conductor that forms a power line or plane or (ii) a third conductor that forms a ground line or plane.

4. The method of claim 1 or 2, wherein the first conductor is a power line or plane, and wherein the at least one conductor includes (i) a second conductor that forms a signal line or (ii) a third conductor that forms a ground line or plane.

5. The method of claim 1 or 2, wherein the first conductor is a ground line or plane, and wherein the at least one conductor includes (i) a second conductor that forms a power line or plane and (ii) a third conductor that forms a signal line.Attorney Docket No.10046-620WO1 8424 MEA 6. The method of claim 1 or 2, wherein the die does not have through-silicon vias (TSV) for a power line, wherein the power line provided by a portion of the at least one conductor is formed outside of the die.

7. The method of any one of claims 1-6, wherein the step of depositing the metal to generate the uniform metal layer on the top surface of the substrate, the top surface of the die, and the side surface of the die comprises Metal Organic Decomposition (MOD) process.

8. The method of claim 7, wherein the Metal-Organic Decomposition process employs a spray operation.

9. The method of claim 7, wherein the Metal-Organic Decomposition process employs an ink jetting operation.

10. The method of any one of claims 1-5, wherein the step of depositing the metal to generate the uniform metal layer on the top surface of the substrate, the top surface of the die, and the side surface of the die comprises at least one of deposition of nanoparticle inks, Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD).

11. The method of any one of claims 1-10 further comprising: depositing a dielectric material to generate a dielectric layer over the at least one conductor; and depositing additional metal to generate a second metal layer over the dielectric layer.

12. The method of claim 11, wherein the die or structure includes a plurality of trench structures, wherein the at least one conductor, the dielectric layer, and the second metal layer are formed over the plurality of trench structures to form capacitors.

13. The method of any one of claims 1-12, wherein the metal and metal layer includes silver, gold, platinum, nickel, or copper.

14. The method of any one of claims 1-13, wherein the die comprises an individual wafer, a chip, or a chiplet.Attorney Docket No.10046-620WO1 8424 MEA 15. A device comprising: a substrate having a top surface; and a die coupled to said substrate, wherein the die has a top surface and a side surface; the die and substrate having a uniform metal layer deposited on the top surface of the substrate, the top surface of the die, and the side surface of the die to form a continuous uniformly thick conductor between the die and the substrate, wherein the metal layer forms at least one conductor, including a first conductor, as a power line, a ground line or plane, or a signal line, wherein the top surface of the substrate and the top surface of the die have a first thickness, and wherein the side surface of the die has a second thickness, wherein the first thickness is substantially similar to the second thickness.

16. The device of claim 15, wherein the top surface of the die includes an exposed top metal contact surrounded by a passivation layer, and wherein the at least one conductor is deposited over the exposed top metal contact to form an electric contact between a circuit of the die and a circuit or electrical structure of the substrate.

17. The device of claim 15 or 16, wherein the first conductor is a signal line, and wherein the at least one conductor includes (i) a second conductor that forms a power line or plane or (ii) a third conductor that forms a ground line or plane.

18. The device of claim 15 or 16, wherein the first conductor is a power line or plane, and wherein the at least one conductor includes (i) a second conductor that forms a signal line or (ii) a third conductor that forms a ground line or plane.

19. The device of claim 15 or 16, wherein the first conductor is a ground line or plane, and wherein the at least one conductor includes (i) a second conductor that forms a power line or plane and (ii) a third conductor that forms a signal line.

20. The device of claim 15, wherein the continuous uniformly thick conductor between the die and the substrate is formed of a Metal Organic Decomposition (MOD) process, aAttorney Docket No.10046-620WO1 8424 MEA deposition of nanoparticle ink process, Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD).

21. The device of any one of claims 15 – 20, comprising: a plurality of decoupling capacitors formed by (i) the at least one conductor and (ii) a dielectric layer and a second metal layer each deposited over a plurality of trench structures located on the die or substrate.

22. The device of any one of claims 15-21, wherein the die comprises an individual wafer, a chip, or a chiplet.

23. The device of any one of claims 15-21, wherein the substrate comprises an individual wafer, a chip, or a chiplet.

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