CXL memory module, error correction method, control chip, medium, and system

Abstract

A CXL memory module, an error correction method, a control chip, a medium, and a system. The CXL memory module comprises an error correction unit (120) and a plurality of memory chips (130). The error correction unit (120) is configured to: when data is written into the memory chips (130), on the basis of a preset number of bits, encode data to be written, so as to generate a check code of the data to be written; and when data is read from the memory chips (130), on the basis of a check code of data to be read, decode the data to be read, so as to output data having undergone error correction processing, wherein the preset number of bits is determined on the basis of the number of bits of data read and written by the CXL memory module at one time.

Description

CXL memory modules, error correction methods, control chips, media, and systems

[0001] This application claims priority to Chinese Patent Application No. 2024109779946, filed on July 19, 2024, entitled "CXL Memory Module, Error Correction Method, Control Chip, Medium and System", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of data access technology, and particularly to a CXL memory module, error correction method, control chip, medium, and system. Background Technology

[0003] In some application scenarios, such as data centers performing large-scale computing tasks, a large number of computing nodes, processors, and memory chips often need to work together. A single read / write error can cause significant losses, thus placing extremely high demands on the reliability of memory chips in these scenarios. To improve the reliability of memory chips, these application scenarios typically require memory chips with ECC (Error Checking and Correcting) functionality. ECC adds additional checksums to the data through encoding, and then detects and corrects errors through decoding during data transmission or storage.

[0004] In some technologies, the ECC module in a memory chip can encode 64 bits of data at a time, generating an 8-bit checksum to form a 72-bit data packet; or, the ECC module can encode 32 bits of data at a time, generating an 8-bit checksum, and then combining the two encoded data into an 80-bit data packet. This encoding method also requires widening the data bit width of the DIMM (Dual Inline Memory Module) slots carrying the memory chip to 72 or 80 bits. In this way, the memory chip can output or input one encoded data packet at a time, correcting a maximum of one error bit, at a capacity cost of 12.5-25%.

[0005] CXL is a memory protocol in which memory chips are connected to the host through a CXL controller chip. In the CXL protocol, the amount of data read and written at one time can be 512 bits.

[0006] Summary of the Invention

[0007] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims. Embodiments of this disclosure provide a CXL memory module, an error correction method, a control chip, a medium, and a system.

[0008] In a first aspect, embodiments of this disclosure provide a CXL memory module, including an error correction unit and multiple memory chips; the error correction unit is configured to: when writing data to the memory chips, encode the data to be written according to a preset number of bits to generate a check code for the data to be written; when reading data from the memory chips, decode the data to be read based on the check code of the data to be read to output the data after error correction; wherein, the preset number of bits is determined based on the number of bits of data read and written by the CXL memory module in one operation.

[0009] Secondly, this disclosure provides an error correction method applied to a control chip in a CXL memory module. The control chip includes at least one error correction unit, and the CXL memory module also includes multiple memory chips. The method includes: when writing data to the memory chip, encoding the data to be written according to a preset number of bits to generate a check code for the data to be written, and storing the data to be written and the check code for the data to be written in the memory chip. The preset number of bits is determined based on the number of bits of data read and written by the CXL memory module at one time; when reading data from the memory chip, decoding the data to be read based on the check code of the data to be read to output the error-corrected data.

[0010] Thirdly, this disclosure provides a control chip applied to a CXL memory module. The control chip includes a processor and at least one error correction unit. The CXL memory module also includes multiple memory chips. The error correction unit is configured to: when writing data to a memory chip, encode the data to be written according to a preset number of bits to generate a checksum of the data to be written; when reading data from a memory chip, decode the data to be read based on the checksum of the data to be read to output the error-corrected data; wherein the preset number of bits is determined based on the number of bits of data read and written by the CXL memory module at one time; the processor of the control chip is configured to execute the error correction method in the above embodiments.

[0011] Fourthly, this disclosure provides a non-transient computer storage medium, which stores a computer program that, when executed by a processor, implements the error correction method described in the above embodiments.

[0012] Fifthly, this disclosure provides a computer system including a host and the CXL memory module described in the above embodiments. The host communicates with the CXL memory module through the CXL interface to realize the discovery, configuration, and data transmission of the CXL memory module. The CXL memory module can perform error detection and correction on the stored data.

[0013] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0014] Overview of the attached figures

[0015] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0016] Figure 1 is a schematic diagram of the structure of an embodiment of the CXL memory module disclosed herein;

[0017] Figure 2A is a structural schematic diagram of another embodiment of the CXL memory module disclosed herein;

[0018] Figure 2B is a structural schematic diagram of another embodiment of the CXL memory module disclosed herein;

[0019] Figure 2C is a structural schematic diagram of another embodiment of the CXL memory module disclosed herein;

[0020] Figure 3 is a structural schematic diagram of another embodiment of the CXL memory module disclosed herein;

[0021] Figure 4 is a structural schematic diagram of another embodiment of the CXL memory module disclosed herein;

[0022] Figure 5 is a flowchart illustrating an embodiment of the error correction method of this disclosure;

[0023] Figure 6 is a flowchart illustrating an embodiment of the error correction method of this disclosure;

[0024] Figure 7 is a schematic diagram of the structure of a control chip according to an embodiment of the present disclosure;

[0025] Figure 8 is a schematic diagram of the structure of an embodiment of the computer system disclosed herein.

[0026] Detailed Explanation

[0027] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features described herein can be combined arbitrarily.

[0028] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0029] The ordinal numbers such as "first" and "second" in this disclosure are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0030] This disclosure describes several embodiments, but these descriptions are exemplary and not restrictive, and many more embodiments and implementations are possible within the scope of the embodiments described herein, which will be apparent to those skilled in the art. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with or in lieu of any other feature or element in any other embodiment.

[0031] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form the scheme defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other disclosed schemes to form another scheme defined by the claims. Therefore, it should be understood that any feature shown and discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0032] Furthermore, in describing representative embodiments, the specification may have presented methods and processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described in this disclosure to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and process should not be limited to performing the steps in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this disclosure.

[0033] As shown in Figure 1, this embodiment of the present disclosure provides a CXL memory module, which may include a control chip 110, an error correction unit 120, and multiple memory chips 130.

[0034] The control chip 110, also known as the CXL controller, may have a CXL interface based on the CXL protocol, allowing the host CPU to interact with it. For example, based on the CXL.io protocol, the host CPU can send instructions to the control chip 110; based on the CXL.mem protocol, the host CPU can read data from the memory chip 130 and write external data to it. The control chip 110 also has a DDR (Double Data Rate) controller, enabling its CPU to manage the memory chip 130.

[0035] Memory chip 130 can be mounted on DIMM strips, and each DIMM strip can support multiple memory chips 130. The data width of the DIMM strip can be 64 bits or 72 bits. In some technologies, memory chips with ECC functionality require 72-bit DIMM strips, while memory chips without ECC functionality only require 64-bit DIMM strips. In this embodiment, the data width of the DIMM strip supporting memory chip 120 can be 64 bits.

[0036] The error correction unit 120 is configured to: when writing data to the memory chip 130, encode the data to be written according to a preset number of bits to generate a check code for the data to be written; when reading data from the memory chip 130, decode the data to be read based on the check code of the data to be read to output the data after error correction, wherein the preset number of bits is determined based on the number of bits of data read and written by the CXL memory module in one operation.

[0037] In this embodiment, error correction processing refers to the error correction unit 120 determining whether there are error bits in the data to be read through decoding. If there are no error bits, the data to be read is directly output; if there are error bits, the error bits are corrected based on the checksum of the data to be read, and the corrected data is output.

[0038] In this embodiment, the error correction unit 120 can be set in the control chip 110 or memory chip 130 in the form of hardware circuit. It detects and corrects errors in the data input and output of the CXL memory module by encoding and decoding. The encoding and decoding can use linear error correction codes (e.g., Hamming codes) or cyclic error correction codes (e.g., BCH (Bose–Chaudhuri–Hocquenghem codes)) to add 20 check bits to the 512-bit data packet, thereby correcting errors of no more than 2 bits (i.e., 2 error bits).

[0039] The preset bit width can be determined based on the number of bits of data read and written by the CXL memory module in a single operation. The data read and written by the CXL memory module in a single operation (also known as a data packet) refers to the maximum amount of data that an external device (such as a host) can read or write at a time when accessing the CXL memory module. Its size can be determined according to the CXL protocol. For example, if the CXL 2.0 protocol specifies that the CXL memory module reads and writes 512 bits (i.e., 64B) of data at a time, then the preset bit width can be 512 bits. That is, the error correction unit 120 can encode and decode 512 bits of data at a time. In this way, the data read or written by the CXL memory module only needs to be encoded or decoded once by the error correction unit 120 each time.

[0040] As an example, when the host writes data to the CXL memory module, before the control chip 110 stores the data to be written into the memory chip 130, the error correction unit 120 can encode the data to be written to generate a checksum. When the data to be written is greater than 512 bits, multiple write operations are required, with each write operation consisting of 512 bits of data (i.e., one data packet). During this process, the error correction unit 120 encodes the data for each write operation, generates a checksum for that write operation, and stores the write operation data and the checksum in the memory chip 130. After all the data to be written has been written, it is divided into multiple data packets, each corresponding to a checksum.

[0041] When the host reads data from the CXL memory module, before the control chip 110 returns the data to the host, the error correction unit 120 can decode the data to verify whether there are any error bits. If there are no error bits, the data to be read is output; if there are error bits, the error bits are corrected according to the checksum, and the corrected data is output. The control chip 110 then returns the data output by the error correction unit 120 to the host. In this process, the CXL memory module outputs 512 bits of data each time, and the error correction unit 120 can decode this part of the data according to the checksum of each output data to perform error correction processing.

[0042] In this embodiment, the error correction unit of the CXL memory module can encode the data written to the memory chip according to the amount of data read and written by the CXL memory module at one time, and decode the data read from the memory chip to realize error correction processing of the data. This allows the CXL memory module to have more efficient error correction capability at a lower capacity cost, and does not require expanding the data bit width of the DIMM strip, which helps to reduce the cost of the CXL memory module.

[0043] In some embodiments, the control chip is configured to: send the data to be written to the error correction unit to generate a checksum for the data to be written; store the data to be written and the checksum for the data to be written into a memory chip; retrieve the data to be read and the checksum for the data to be read from the memory chip; send the data to be read and the checksum for the data to be read to the error correction unit, and return the data output by the error correction unit after decoding to the host.

[0044] In this embodiment, the control chip can store the check code obtained by the error correction unit and the data to be written into the memory chip so that when reading data, the data to be read can be decoded and error corrected according to the check code corresponding to the data to be read.

[0045] In some embodiments, one or more error correction units may be set on the control chip according to actual needs, so as to flexibly meet the error correction needs in actual applications.

[0046] In some embodiments, the CXL memory module can adopt the structure shown in Figure 2A. In Figure 2A, multiple memory chips are connected to the control chip through one or more dual-inline-memory modules (DIMMs). Each DIMM includes at least two sub-channels. The control chip can store the data to be written and the checksum of the data to be written into the memory chips connected to different sub-channels, and the different sub-channels belong to the same DIMM.

[0047] In this embodiment, DIMMs using the DDR5 standard and other protocols that include sub-channels can store the data to be written and its checksum in two sub-channels of the same DIMM. This is compatible with existing memory chips (such as DRAM) and enables parallel processing of data and checksum.

[0048] In some embodiments, the CXL memory module can also adopt the structure shown in Figure 2B. In Figure 2B, the control chip and multiple memory chips include one or more memory channels. Each memory channel is connected to a memory chip with a preset check code storage area. The control chip can store the data to be written into a memory chip connected to a memory channel and store the check code of the data to be written into the check code storage area corresponding to that memory channel.

[0049] In this embodiment, a checksum storage area can be pre-determined in the memory chip connected to each memory channel to centrally store the checksum of the data in that memory channel. In this way, the control chip can store the data and its checksum in different areas of the same memory channel, which helps to improve memory utilization.

[0050] In any of the above embodiments, the control chip is further provided with a cache, and the control chip is further configured to: load check codes that meet preset conditions into the cache; and, when it is necessary to read or write check codes, prioritize reading or writing check codes from the cache; the check codes that meet preset conditions refer to the check codes corresponding to multiple data with consecutive storage addresses.

[0051] Here, the quantity of multiple data items can be limited. For example, checksums corresponding to a certain number or more data items can be loaded into the cache. When the cache space is insufficient, some checksums can be written back to the memory chip.

[0052] As an example, the CXL memory module can be configured with SRAM (Static Random Access Memory) on the control chip as a cache. The CXL memory module reads and writes 512 bits of data at a time. When the data being written is greater than 512 bits, it needs to be divided into multiple data segments, encoded sequentially, and stored in the memory chip. These data segments are stored contiguously in the memory chip. In this case, after storing the checksums of these data segments in the memory chip, these checksums can be stored in the cache so that the control chip can directly read the checksums from the cache, thereby further improving error correction efficiency. Referring to Figure 2C, which shows a schematic diagram of an embodiment of the CXL memory module of this disclosure, the error correction unit 210 can be located in the control chip 220. The control chip 220 and the multiple memory chips 230 include at least two memory channels, with different memory channels connected to different memory chips.

[0053] In this embodiment, the data to be written includes the data to be stored. The control chip 220 is configured to store the check codes of the data to be stored and the data to be written into memory chips connected to different memory channels according to a predetermined address correspondence.

[0054] As an example, a memory channel for storing the checksum can be pre-selected from multiple memory channels, and then an address mapping relationship can be established between the addresses of this memory channel and the addresses of other memory channels. The control chip 220 can then store the data to be stored and the checksum of the data to be written into memory chips 230 connected to different memory channels according to this address mapping relationship.

[0055] In this embodiment, the checksum of the data to be written and the data to be stored are stored in memory chips connected to different memory channels respectively. The control chip can realize parallel reading and parallel writing of data and checksum, which helps to improve error correction efficiency.

[0056] In some examples, data in the CXL memory module is accessed simultaneously by multiple host processors. When one of the host processors updates this data, to ensure data consistency, the host typically generates metadata to record the update information. This metadata is then stored along with the data in the CXL memory module so that the metadata can be read simultaneously with the data later. In this case, the control chip of the CXL memory module needs to support up to 6 bits of metadata attached to each data packet. In some technologies, the metadata is typically stored contiguously with the data in the same memory channel. Since the CXL memory module reads 512 bits of data at a time, this requires two read operations each time a 512-bit data packet and its metadata are read, resulting in higher resource consumption for the CXL memory module.

[0057] Therefore, in some optional implementations of this embodiment, the data to be written may include the data to be stored and the metadata of the data to be stored. When storing the data to be written, the control chip 220 is configured to store the metadata and the check code of the data to be written continuously in the memory chip.

[0058] In this embodiment, the data to be stored can be data accessed simultaneously by multiple host processors, while the metadata is used to record update information of the data to be stored by one or more of the multiple host processors. When a host processor writes the data to be stored into the CXL memory module, the metadata can be attached to the data to be stored and transmitted together to the control chip 220, so that the data to be stored and its metadata are stored together in the CXL memory module.

[0059] At this time, the error correction unit 210 can simultaneously encode the data to be stored and its metadata to generate a check code for the data to be written (i.e., the data to be stored and its metadata). Subsequently, the data to be stored and its metadata can be decoded and corrected based on the check code.

[0060] In this embodiment, the control chip 220 stores the data to be stored, along with metadata and a checksum, into memory chips connected to different memory channels. Since the metadata (maximum 6 bits) and checksum (e.g., 20 bits) are relatively small, they can be stored consecutively in memory chips connected to the same memory channel. When the control chip 220 reads the data to be stored, it can simultaneously read the data, metadata, and checksum from both memory channels. This requires only a single read operation, helping to reduce the power consumption of the CXL memory module.

[0061] In this embodiment, the error correction unit 220 encodes each 512-bit data to obtain a 20-bit check code. Each time the control chip 220 reads data from the memory chip 230, it may include 512 bits of data to be read and a 20-bit check code attached to the data to be read.

[0062] Referring to FIG2C, in some optional embodiments of this embodiment, the control chip 220 is further provided with a cache 240; the control chip 220 is also configured to: load the check code and metadata that meet the preset conditions into the cache 240; and, when it is necessary to read or write the check code, prioritize reading or writing the check code and metadata from the cache 240.

[0063] In this embodiment, the checksum and metadata that meet the preset conditions are the checksum and metadata corresponding to multiple data items with consecutive storage addresses. For example, the CXL memory module reads and writes 512 bits of data at a time. When the written data is greater than 512 bits, it needs to be divided into multiple data items, encoded sequentially, and stored in the memory chip. Since these data items have consecutive storage addresses in the memory chip, after storing the checksum and metadata of these data items in the memory chip, they can be loaded into the cache 240 so that the control chip can directly read the checksum and metadata of these data items from the cache, thereby further improving error correction efficiency.

[0064] Figure 3 shows a schematic diagram of an embodiment of the CXL memory module of this disclosure. As shown in Figure 3, the control chip 310 is provided with an error correction unit 320 and an address converter 330.

[0065] In this embodiment, the address converter 330 is configured to convert the first address carried in the write data instruction into a target memory address. The control chip 310 is configured to store the data to be written and the checksum of the data to be written (collectively referred to as the encoded data in the figure) in a contiguous storage space in the memory chip 340 based on the target memory address.

[0066] In this embodiment, the first address carried in the write data instruction represents the original storage address where the data to be written is expected to be stored in the memory chip, while the target storage address represents the actual storage address of the data to be written in the memory chip. When the data to be written and its checksum are combined and stored consecutively in the memory chip, the actual storage space occupied is greater than the number of bits of the data to be written, which causes an offset between the target storage address of the data to be written and the first address in the write data instruction. At this time, the target storage address can be calculated by the address converter 330 based on the first address and the number of bits of the checksum.

[0067] In some optional implementations of this embodiment, the target storage address can be determined based on the first address and the number of bits in the checksum.

[0068] In a specific example, since the smallest unit of storage address in memory chip 340 is 1B (Byte), when using a 24-bit checksum, the data written by control chip 310 each time includes 512 bits of write data and its 24-bit checksum, totaling 67B. This makes full use of storage space and facilitates address management when data and checksum are stored continuously.

[0069] In this example, each data written to memory chip 340 includes a 3-byte checksum. Consequently, the actual storage address length is 3 bytes longer than the expected storage address length. Assuming the number of bits to be written is no more than 512 bits, meaning the control chip 310 can write the data to memory chip 340 at once, in this case, the actual storage space occupied by the data to be written and its checksum is 3 bytes longer than the storage space occupied by the data itself. Therefore, the address converter 330 can add 3 to the address length in the first address to obtain the target storage address.

[0070] In another example of this implementation, when multiple data packets need to be written continuously to the memory chip, the starting address (i.e., the target storage address) of the first data packet is the same as the first address; for the nth data packet, its target storage address needs to be accumulated by (n-1) m based on its first address, where m is the number of words corresponding to the number of check bits. As an example, assuming that the number of bits of the data to be written is greater than 512 bits, the control chip needs to divide the data to be written into multiple data packets, and write one encoded data packet (i.e., the data obtained by merging the data packet and its check code) to the memory chip 340 each time. Since each encoded data packet occupies 3B more storage space than the data packet (i.e., the number of check bits is 24 bits), the address converter 330 can determine the address length increment based on the data volume of the data packet, and then combine it with the address length in the first address to determine the target storage address. For the actual storage address of each encoded data packet, in addition to the increase in address length, its starting address also needs to be accumulated by the address increment of the encoded data packets before that encoded data packet. For example, the starting address of the first encoded data packet remains unchanged, but the address length is increased by 3; the starting address and address length of the second encoded data packet are both increased by 3; and the starting address of the third encoded data packet is increased by 6, and the address length is increased by 3.

[0071] In this embodiment, the target storage address of the data to be written is determined by an address converter, and the data to be written and its check code are continuously stored in the memory chip according to the target storage address. This does not require additional memory channel resources and helps to reduce the power consumption of the CXL memory module.

[0072] In some optional embodiments of this example, the control chip 310 may also be provided with a cache, and the control chip 310 is further configured to: load the check code that meets the preset conditions into the cache; and, when it is necessary to read or write the check code, prioritize reading or writing the check code from the cache.

[0073] In this embodiment, the check code that meets the preset conditions is the check code corresponding to multiple data with consecutive storage addresses. With the help of caching, the error correction efficiency of the CXL memory module can be improved.

[0074] In some optional embodiments of the example, the address converter 330 is further configured to record the mapping relationship between the first address and the target storage address; and to convert the second address carried in the read data instruction into the target read address according to the mapping relationship, so that the control chip can read the data to be read and the check code of the data to be read from the memory chip according to the target read address.

[0075] In this embodiment, the second address represents the expected storage address of the data to be read when it is written to the memory chip (corresponding to the first address mentioned above), and the target read address represents the actual storage address of the data to be read and its checksum in the memory chip (corresponding to the target storage address mentioned above).

[0076] As an example, when calculating the target memory address, the address converter 330 can record the correspondence between the first address and the target memory address. When the control chip 310 receives a read data instruction, it can send the second address carried in the read data instruction to the address converter 330. The address converter 330 looks up the target memory address (i.e., the target read address) corresponding to the second address in the correspondence and returns it to the control chip 310, so that the control chip 310 can read the data to be read and its checksum from the memory chip 340.

[0077] In some embodiments, the error correction unit may also be disposed in the memory chip. As shown in FIG4, the CXL memory module includes a control chip 410 and a plurality of memory chips 420, and each memory chip 420 is provided with at least one error correction unit 430.

[0078] In this embodiment, the error correction unit is located inside the memory chip, so that the error correction units of multiple memory chips are relatively independent and do not interfere with each other, which helps to improve the error correction efficiency.

[0079] In some optional implementations of this embodiment, the page size of each memory page in multiple memory chips can be set to an integer multiple of a preset size, where the preset size is the sum of the number of bits in the checksum generated by the error correction unit and the number of bits in the data read and written by the CXL memory module in one operation. In this way, data and its checksum can be stored in the same memory page, which helps improve the utilization efficiency and error correction efficiency of the memory chips.

[0080] In a specific example, the error correction unit generates a 20-bit checksum. Assuming that the CXL memory module reads and writes 512 bits of data at a time, the page size of the memory chip can be an integer multiple of 532, such as 532 bits, 1064 bits, etc.

[0081] As shown in Figure 5, this embodiment of the present disclosure also provides an error correction method applied to the control chip of the CXL memory module in the above embodiment. The control chip includes at least one error correction unit, and the CXL memory module also includes multiple memory chips. The method includes the following steps.

[0082] Step 510: When writing data into the memory chip, the data to be written is encoded according to a preset number of bits to generate a check code for the data to be written, and the data to be written and the check code are stored in the memory chip.

[0083] The preset bit width is determined based on the number of bits of data read and written by the CXL memory module in a single operation. For example, the CXL2.0 protocol specifies that the CXL memory module reads and writes 512 bits of data in a single operation, so the preset bit width can be 512 bits.

[0084] Step 520: When reading data from the memory chip, the data to be read is decoded based on the checksum of the data to be read, and the data after error correction is output.

[0085] As an example, after decoding the data to be read, the error correction unit can determine whether there are any error bits in the data. If there are error bits, it corrects the error bits based on the checksum of the data and outputs the corrected data. Optionally, if there are no error bits in the data to be read, it directly outputs the data to be read.

[0086] In this embodiment, the data written to the memory chip can be encoded according to the amount of data read and written by the CXL memory module at one time, and the data read from the memory chip can be decoded to achieve error correction processing. This allows the CXL memory module to have more efficient error correction capabilities at a lower capacity cost, and it does not require expanding the data width of the DIMM strip, which helps to reduce the cost of the CXL memory module.

[0087] As shown in Figure 6, one embodiment of the error correction method disclosed herein may further include the following steps.

[0088] Step 610: Send the data to be written to the error correction unit to generate a check code for the data to be written.

[0089] Step 620: Store the data to be written and the verification code of the data to be written into the memory chip.

[0090] Step 630: Obtain the data to be read and the verification code of the data to be read from the memory chip.

[0091] Step 640: Send the data to be read and the checksum of the data to be read to the error correction unit, and return the data output by the error correction unit after decoding to the host.

[0092] In this embodiment, the checksum obtained by the error correction unit and the data to be written can be stored in the memory chip of the CXL memory module so that when reading data, the data to be read can be decoded and error corrected according to the checksum corresponding to the data to be read.

[0093] In some embodiments, the control chip is further provided with a cache; the error correction method of this disclosure may further include: loading a check code that meets preset conditions into the cache; and, when it is necessary to read or write a check code, preferentially reading or writing a check code from the cache; the check code that meets the preset conditions is the check code corresponding to multiple data with consecutive storage addresses.

[0094] In this embodiment, storing the checksum in a cache can improve the reading speed of the checksum, which helps to further improve the error correction efficiency of the CXL memory module.

[0095] In some embodiments, multiple memory chips are connected to a control chip through one or more dual in-line memory modules, and each dual in-line memory module includes at least two sub-channels; step 510 above may include: storing the data to be written and the check code of the data to be written into memory chips connected to different sub-channels respectively, and the different sub-channels belong to the same dual in-line memory module.

[0096] In some embodiments, the control chip and the multiple memory chips include one or more memory channels, and each memory chip connected to the memory channel has a preset check code storage area; the above step 510 may include: storing the data to be written into the memory chip connected to a memory channel, and storing the check code of the data to be written into the check code storage area corresponding to the memory channel.

[0097] In some embodiments, the control chip is provided with at least one error correction unit; the control chip and multiple memory chips include at least two memory channels, with different memory channels connected to different memory chips; the data to be written includes data to be stored. Furthermore, step 510 above can store the data to be written and its checksum into the memory chips in the following manner: according to a predetermined address correspondence, the data to be stored and the checksum of the data to be written are respectively stored into memory chips connected to different memory channels.

[0098] In some embodiments, the data to be written includes the data to be stored and the metadata of the data to be stored. Step 510 above may include: storing the metadata and the checksum of the data to be written continuously in the memory chip.

[0099] In this embodiment, when reading the data to be stored, the data to be stored, metadata, and checksum can be read simultaneously from two memory channels. In this way, only one read operation is required, which helps to reduce the power consumption of the CXL memory module.

[0100] In some embodiments, the control chip is further provided with a cache; the error correction method of the CXL memory module disclosed herein further includes: loading check codes and metadata that meet preset conditions into the cache; and, when it is necessary to read or write check codes, reading or writing check codes and metadata from the cache is given priority; the check codes and metadata that meet preset conditions are check codes and metadata corresponding to multiple data with consecutive storage addresses.

[0101] In this embodiment, step 620 may further include: converting the first address carried in the write data instruction into a target storage address; and storing the data to be written and the check code of the data to be written in a contiguous storage space in the memory chip based on the target storage address.

[0102] In some optional implementations of this embodiment, the target storage address can be determined based on the first address and the number of bits in the checksum.

[0103] In this embodiment, the first address of the data to be written is converted into the target storage address, and the data to be written and its check code are continuously stored in the memory chip according to the target storage address. This does not require additional memory channel resources and helps to reduce the power consumption of the CXL memory module.

[0104] Optionally, the method may further include: recording the mapping relationship between the first address and the target storage address; converting the second address carried in the read data instruction into the target read address according to the mapping relationship, so that the control chip can read the data to be read from the memory chip according to the target read address.

[0105] Figure 7 shows a schematic diagram of the structure of a control chip in one embodiment of the present disclosure. This control chip is applied to a CXL memory module. As shown in Figure 7, the control chip 710 includes at least one error correction unit 720, and the CXL memory module also includes multiple memory chips 730.

[0106] The error correction unit 720 is configured to: when writing data to the memory chip 730, encode the data to be written according to a preset number of bits to generate a check code for the data to be written; when reading data from the memory chip 730, decode the data to be read based on the check code of the data to be read to output the data after error correction; wherein, the preset number of bits is determined based on the number of bits of data read and written by the CXL memory module in one operation.

[0107] The processor of the control chip 710 is configured to execute the error correction method in any of the above embodiments.

[0108] This disclosure also provides a non-transient computer storage medium, which stores a computer program that, when executed by a processor, implements the error correction method described in the above embodiments.

[0109] This disclosure also provides a computer system, as shown in FIG8. The computer system includes a host 810 and a CXL memory module 820 in any of the above embodiments. The host 810 communicates with the CXL memory module 820 through a CXL interface to realize one or more of the following: discovery, configuration, and data transmission of the CXL memory module 820. The CXL memory module 820 can perform error detection and correction on the stored data.

[0110] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A CXL memory module, comprising an error correction unit and a plurality of memory chips; the error correction unit is configured to: when writing data into the memory chips, encode the to-be-written data according to a preset bit number to generate a check code of the to-be-written data; when reading data from the memory chips, decode the to-be-read data based on the check code of the to-be-read data to output data after error correction processing; wherein the preset bit number is determined based on the bit number of data read or written by the CXL memory module at a time. 2.The CXL memory module of claim 1, further comprising a control chip, the control chip is configured to: send the to-be-written data to the error correction unit to generate a check code of the to-be-written data; store the to-be-written data and the check code of the to-be-written data into the memory chips; obtain to-be-read data and a check code of the to-be-read data from the memory chips; send the to-be-read data and the check code of the to-be-read data to the error correction unit, and return data output by the error correction unit to a host.

3. The CXL memory module of claim 2, wherein, At least one error correction unit is provided in the control chip.

4. The CXL memory module of claim 3, wherein, The control chip and the plurality of memory chips comprise at least two memory channels, different memory channels are connected to different memory chips; the to-be-written data comprises to-be-stored data; The control chip is configured to store the to-be-written data and the check code of the to-be-written data into the memory chips, comprising: storing the to-be-stored data and the check code of the to-be-written data into the memory chips connected to different memory channels according to a predetermined address correspondence.

5. The CXL memory module of claim 4, wherein, The to-be-written data further comprises metadata of the to-be-stored data; The control chip is further configured to: store the metadata and the check code of the to-be-written data continuously in the memory chips.

6. The CXL memory module of claim 5, wherein, The control chip is further provided with a cache; The control chip is further configured to: load check codes and metadata meeting a preset condition into the cache; and when reading or writing check codes is needed, preferentially reading or writing check codes and metadata from the cache; the check codes and metadata meeting the preset condition refer to check codes and metadata corresponding to a plurality of data with continuous storage addresses.

7. The CXL memory module of claim 3, wherein, The control chip further comprises an address converter configured to convert a first address carried in a write data instruction into a target storage address; The control chip is configured to store the to-be-written data and the check code of the to-be-written data into the memory chips, comprising: storing the to-be-written data and the check code of the to-be-written data in a continuous storage space in the memory chips based on the target storage address.

8. The CXL memory module of claim 7, wherein, The address converter is further configured to: record a mapping relationship between the first address and the target storage address; and convert a second address carried in a read data instruction into a target read address according to the mapping relationship, so that the control chip reads the to-be-read data and the check code of the to-be-read data from the memory chips according to the target read address.

9. The CXL memory module of claim 7, wherein, The control chip further comprises an address converter configured to convert a first address carried in the write data instruction into a target storage address, the target storage address being determined based on the first address and a bit number of the check code.

10. The CXL memory module of claim 7, wherein, The preset bit number is 512 bits, and the bit number of the check code generated by the error correction unit is 24 bits.

11. The CXL memory module of claim 3, wherein, The plurality of memory chips are connected to the control chip through one or more dual in-line memory modules, and each dual in-line memory module comprises at least two sub-channels. The control chip is configured to store the to-be-written data and the check code of the to-be-written data into the memory chips, and the storage comprises storing the to-be-written data and the check code of the to-be-written data into memory chips connected to different sub-channels, the different sub-channels belonging to the same dual in-line memory module.

12. The CXL memory module of claim 3, wherein, The control chip and the plurality of memory chips comprise one or more memory channels, and each memory channel is connected to a memory chip in which a check code storage area is preset. The control chip is configured to store the to-be-written data and the check code of the to-be-written data into the memory chips, and the storage comprises storing the to-be-written data into a memory chip connected to a memory channel and storing the check code of the to-be-written data into a check code storage area corresponding to the memory channel.

13. The CXL memory module of claim 3, 7, 11, or 12, wherein, The control chip is further provided with a cache. The control chip is further configured to load check codes meeting preset conditions into the cache. When it is necessary to read or write check codes, the check codes are preferentially read or written from the cache; the check codes meeting the preset conditions refer to check codes corresponding to a plurality of data with continuous storage addresses.

14. The CXL memory module of claim 1, wherein, Each of the memory chips is provided with at least one error correction unit.

15. The CXL memory module of claim 14, wherein, The page size of each memory page in the memory chip is an integer multiple of a preset size, and the preset size is the sum of a bit number of the check code generated by the error correction unit and a bit number of data read or written by the CXL memory module at a time.

16. The CXL memory module of claim 4 or 15, wherein, The preset bit number is 512 bits, and the bit number of the check code generated by the error correction unit is 20 bits.

17. An error correction method applied to a control chip in a CXL memory module, the control chip being provided with at least one error correction unit, and the CXL memory module further comprising a plurality of memory chips, the method comprising: When writing data into the memory chips, encoding to-be-written data according to a preset bit number to generate a check code of the to-be-written data, and storing the to-be-written data and the check code of the to-be-written data into the memory chips, the preset bit number being determined based on a bit number of data read or written by the CXL memory module at a time; When reading data from the memory chips, decoding to-be-read data based on a check code of the to-be-read data to output data after error correction processing.

18. The method of claim 17, further comprising: sending the to-be-written data to the error correction unit to generate a check code of the to-be-written data; storing the to-be-written data and the check code of the to-be-written data into the memory chips. acquire the to-be-read data and the check code of the to-be-read data from the memory chip; and, send the to-be-read data and the check code of the to-be-read data to the error correction unit, and return the data decoded and output by the error correction unit to the host. The control chip and the plurality of memory chips are connected through at least two memory channels, different memory channels are connected to different memory chips; the to-be-written data includes to-be-stored data; 19. The method of claim 18, wherein, and, The to-be-stored data and the check code of the to-be-written data are stored in the memory chip according to a predetermined address correspondence relationship. The to-be-written data further includes metadata of the to-be-stored data; 20. The method of claim 19, wherein, The method further includes: storing the metadata and the check code of the to-be-written data continuously in the memory chip. The control chip is further provided with a cache; 21. The method of claim 20, wherein, The method further includes: loading the check code and the metadata meeting a preset condition into the cache; and in the case of reading or writing the check code, preferentially reading or writing the check code and the metadata from the cache; the check code and the metadata meeting the preset condition are check codes and metadata corresponding to a plurality of data with continuous storage addresses. The to-be-written data and the check code of the to-be-written data are stored in the memory chip, including:

22. The method of claim 18, wherein, The first address carried in the write data instruction is converted into a target storage address; Based on the target storage address, the to-be-written data and the check code of the to-be-written data are stored in a continuous storage space in the memory chip.

23. The method of claim 22, further comprising: recording a mapping relationship between the first address and the target storage address; According to the mapping relationship, a second address carried in a read data instruction is converted into a target read address, so as to read the to-be-read data and the check code of the to-be-read data from the memory chip according to the target read address. The target storage address is determined based on the first address and the number of bits of the check code.

24. The method of claim 22, wherein, The plurality of memory chips are connected to the control chip through one or more dual in-line memory modules, and each dual in-line memory module includes at least two sub-channels; 25. The method of claim 18, wherein, The to-be-written data and the check code of the to-be-written data are stored in the memory chip, including: the to-be-written data and the check code of the to-be-written data are stored in the memory chips connected by different sub-channels, and the different sub-channels belong to the same dual in-line memory module. The control chip and the plurality of memory chips are connected through one or more memory channels, and a check code storage area is preset in the memory chip connected by each memory channel; 26. The method of claim 18, wherein, The to-be-written data and the check code of the to-be-written data are stored in the memory chip, including: the to-be-written data is stored in the memory chip connected by a memory channel, and the check code of the to-be-written data is stored in the check code storage area corresponding to the memory channel. The control chip is further provided with a cache; 27. The method of claim 19, 22, 25, or 26, wherein, The method further includes: loading the check code and the metadata meeting a preset condition into the cache; and in the case of reading or writing the check code, preferentially reading or writing the check code and the metadata from the cache; the check code and the metadata meeting the preset condition are check codes and metadata corresponding to a plurality of data with continuous storage addresses. The method further comprises: loading the check code meeting the preset condition into the cache; and in the case of reading or writing check code, preferentially reading or writing check code from the cache; the check code meeting the preset condition The check code corresponding to the plurality of data with consecutive storage addresses. 28.A control chip applied to a CXL memory module, the control chip comprising a processor and at least one error correction unit, and the CXL memory module further comprises a plurality of memory chips, wherein The error correction unit is configured to: when writing data into the memory chip, encode the data to be written according to a preset number of bits to generate a check code of the data to be written; When reading data from the memory chip, decode the data to be read based on the check code of the data to be read to output the data after error correction processing; wherein the preset number of bits is determined based on the number of bits of the data read or written by the CXL memory module at a time; The processor of the control chip is configured to perform the error correction method of any one of claims 17 to 27. 29.A non-transitory computer storage medium, the computer storage medium storing a computer program, the computer program being executed by a processor to implement the error correction method of any one of claims 17 to 27. 30.A computer system comprising a host and a CXL memory module of any one of claims 1 to 16, the host communicating with the CXL memory module through a CXL interface to implement one or more of discovery, configuration and data transmission of the CXL memory module; and the CXL memory module can perform error detection and correction on the stored data.

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