CXL memory module, memory repair method, chip, medium, and system

Abstract

A CXL memory module, a memory repair method, a chip, a medium, and a system. The CXL memory module comprises a control chip and one or more memory chips managed by the control chip, the control chip or the memory chip being provided with an error correction unit. The control chip is configured to: establish an error record table, and store error correction information recorded when the error correction unit corrects data, the error correction information comprising memory address information of an error bit; determine an unreliable storage unit in the memory chip on the basis of the error record table; and replace the unreliable storage unit with a predetermined redundant storage unit.

Description

CXL memory module, method for repairing memory, chip, medium and system

[0001] The present application claims priority from the Chinese patent application No. 2024109553348 filed on July 17, 2024, and entitled "CXL memory module, method for repairing memory, chip, medium and system", the contents of which are to be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] The embodiments of the present disclosure relate to, but are not limited to, the technical field of data access, and in particular to a CXL memory module, a method for repairing memory, a chip, a medium and a system. BACKGROUND

[0003] CXL (Compute Express Link) is a memory interface protocol based on the PCIe (Peripheral Component Interconnect Express) physical layer, and based on the CXL protocol, the CXL memory module can expand the memory of a computer.

[0004] SUMMARY

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims. Embodiments of the present disclosure provide a CXL memory module, a method for repairing memory, a chip, a medium and a system.

[0006] In a first aspect, the embodiments of the present disclosure provide a CXL memory module, comprising a control chip, an error correction unit and a plurality of memory chips managed by the control chip, wherein the control chip is configured to: establish an error record table, store error correction information recorded by the error correction unit when correcting data, and the error correction information comprises memory address information of error bits that occur; determine an unreliable storage unit in the memory chip according to the error record table; and replace the unreliable storage unit with a pre-determined redundant storage unit.

[0007] In a second aspect, the embodiments of the present disclosure provide a method for repairing memory, applied to the CXL memory module in the above embodiments, the CXL memory module comprising a control chip and one or more memory chips managed by the control chip, and an error correction unit is arranged in the control chip or the memory chip, and the method comprises: establishing an error record table, storing error correction information recorded by the error correction unit when correcting data, and the error correction information comprises memory address information of error bits that occur; determining an unreliable storage unit in the memory chip according to the error record table; and replacing the unreliable storage unit with a pre-determined redundant storage unit.

[0008] In a third aspect, the embodiments of the present disclosure provide a control chip, applied to a CXL memory module, the CXL memory module further comprising one or more memory chips managed by the control chip, the control chip comprising a processor and an error correction unit, and configured to execute the method for repairing memory in the above embodiments.

[0009] In a fourth aspect, the embodiments of the present disclosure provide a memory chip, applied to the CXL memory module in the above embodiments, the memory chip being provided with an error correction unit and a replacement unit; the error correction unit being configured to: determine whether the data read from the memory chip is erroneous, perform error correction when the data is erroneous, and record error correction information, the error correction information comprising memory address information of the error bit; and send the error correction information to the control chip in the CXL memory module; the replacement unit being configured to: in response to receiving a replacement instruction from the control chip, replace an unreliable storage unit pointed to by the replacement instruction with a redundant storage unit, and record an address correspondence relationship between the unreliable storage unit and the redundant storage unit.

[0010] In a fifth aspect, the embodiments of the present disclosure provide a non-transitory computer storage medium, the computer readable storage medium storing a computer program, the computer program being executed by a processor to implement the method for repairing memory in the above embodiments.

[0011] In a sixth aspect, the embodiments of the present disclosure provide a computer system, comprising a host and the CXL memory module in the above embodiments, the host communicating with the CXL memory module through a CXL interface to realize discovery, configuration and data transmission of the CXL memory module, the CXL memory module being configured to: perform error correction processing on data; identify an unreliable storage unit in the memory chip according to error correction information recorded during error correction, and replace the unreliable storage unit with a redundant storage unit.

[0012] Other aspects can become apparent from the following detailed description, taken in conjunction with the accompanying drawings.

[0013] SUMMARY

[0014] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0015] FIG. 1 is a structural schematic diagram of one embodiment of a CXL memory module of the present disclosure;

[0016] FIG. 2 is a structural schematic diagram of another embodiment of a CXL memory module of the present disclosure;

[0017] FIG. 3 is a flow schematic diagram of one embodiment of a method for repairing memory of the present disclosure;

[0018] FIG. 4 is a flowchart of another embodiment of the method for repairing memory of the present disclosure;

[0019] FIG. 5 is a flowchart of updating the error record table in one embodiment of the method for repairing memory of the present disclosure;

[0020] FIG. 6 is a flowchart of determining the unreliable address in one embodiment of the method for repairing memory of the present disclosure;

[0021] FIG. 7 is a structural diagram of one embodiment of the control chip of the present disclosure;

[0022] FIG. 8 is a structural diagram of one embodiment of the memory chip of the present disclosure;

[0023] FIG. 9 is a structural diagram of one embodiment of the computer system of the present disclosure.

[0024] DETAILED DESCRIPTION

[0025] Embodiments of the present disclosure will be described in detail below with reference to the drawings. The embodiments of the present disclosure and the features in the embodiments can be combined with each other as long as there is no conflict.

[0026] The embodiments of the present disclosure are not necessarily limited to the sizes shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0027] The ordinal numbers "first", "second", and the like in the present disclosure are set in order to avoid confusion of the components, and do not represent any order, number, or importance.

[0028] The present disclosure describes a plurality of embodiments, but the description is exemplary, not limiting, and more embodiments and implementation schemes can be possible within the scope of the embodiments described in the present disclosure for those skilled in the art. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Unless specifically limited, any feature or element of any embodiment can be used with any other feature or element of any other embodiment, or can replace any other feature or element of any other embodiment.

[0029] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed herein can also be combined with any conventional feature or element to form a solution defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other disclosed solutions to form another solution defined by the claims. Therefore, it should be understood that any feature shown and discussed in the present disclosure can be implemented alone or in any appropriate combination. Accordingly, the embodiments are not to be restricted, except as by the appended claims and their equivalents. Moreover, various modifications and changes can be made within the scope of the claims.

[0030] Furthermore, in describing representative embodiments, the specification can have presented the method and process described as a particular sequence of steps. However, to the extent that the method or process depends on more than one step, the method or process should not be limited to the described particular order of steps. Other steps can be performed in between steps described herein. It is also possible that described steps could be executed at the same time as other steps described herein rather than sequentially. Accordingly, the presently described method and process steps need not be performed in the order described. The order of execution of the steps has been severed merely for illustrative purposes. The identification of steps in the description of the method and process of the application accordingly is not intended to be limited to the order in which the steps are invoked, unless specifically stated by the context.

[0031] In the description of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0032] In practice, when a memory chip is manufactured, there can be failed or unreliable storage units in the memory chip. The memory chip needs to be tested before it is shipped out of the factory to detect the failed or unreliable storage units, and replace the failed or unreliable storage units with predetermined redundant storage units, and then burn the replacement information on the eFuse in the chip. However, due to the stress accumulated in the chip during the integrated circuit production process, it takes a long time to release, resulting in a high failure rate in the first six months after the memory chip is shipped out, and these hidden dangers cannot be detected on the production line. Therefore, for application fields such as data centers that have high requirements for the reliability of data storage, the failure of the memory chip in use is still a problem that needs to be solved urgently.

[0033] FIG. 1 shows a structural schematic diagram of one embodiment of a CXL memory module of the present disclosure. As shown in FIG. 1, the CXL memory module includes a control chip 110, an error correction unit 120, and a plurality of memory chips 130 managed by the control chip.

[0034] The control chip 110 can also be referred to as a CXL controller, which can be provided with a CXL interface based on the CXL protocol, so that the host CPU (Host CPU) interacts with the control chip 110 through the CXL interface. For example, based on the CXL.io protocol, the host CPU can send instructions to the control chip 110; based on the CXL.mem protocol, the host CPU can read data from the memory chip 130, and write external data to the memory chip 130. The control chip 110 can also be provided with a DDR (Double Data Rate) controller, so that the CPU of the control chip 110 manages the memory chip 120.

[0035] The error correction unit 120 provided in the CXL memory module can implement an ECC (Error Checking and Correcting) function. The error correction unit 120 encodes the data written into the memory chip 130 to generate a check code of the data. When data needs to be read from the memory chip 130, the error correction unit 120 can use the previously generated check code to detect whether there are error bits (i.e., bits) in the read data, and correct the error bits.

[0036] The error correction unit 120 can be provided in the memory chip 130, and one error correction unit 120 can be provided in each memory chip 130. Alternatively, the error correction unit 120 can also be provided in the control chip 110. The control chip 110 can be provided with one or more error correction units 120 according to actual needs. The error correction information recorded by the error correction unit 120 when correcting data can be sent to the processor (i.e., the CPU Core in FIG. 1) of the control chip 110 through the related logic circuit inside the control chip 110.

[0037] For example, when the error correction unit 120 adopts different error correction strategies, the number of error bits corrected each time is also different. For example, when an 8-bit check code is used to correct 64-bit data, one error bit in the data can be corrected at a time. When a check code with more bits is used, more error bits can be corrected at a time.

[0038] In some optional embodiments of the present embodiment, the error correction unit 120 can be configured to, when correcting data, record the memory address information of the error bits when the number of the error bits is not less than a preset number, as the error correction information.

[0039] As an example, assuming that the error correction unit 120 can correct a maximum of 3 error bits each time, the preset number can be 2. Then, when performing error correction processing, if there is only 1 error bit in the data, the error correction unit only needs to correct the error bit, and does not need to generate error correction information; if there are 2 or 3 error bits in the data, the error correction unit needs to generate error correction information after correcting the error bits. In this way, the data amount of the error record table can be reduced, which helps to save resources.

[0040] In the embodiment, the control chip 110 is configured to: establish an error record table, store error correction information recorded by the error correction unit 120 when correcting the data, the error correction information including memory address information of the error bits that occur; determine unreliable storage units in the memory chip 130 according to the error record table; and replace the unreliable storage units with the pre-determined redundant storage units.

[0041] As an example, the error record table can be in the form of a sequence, and a plurality of error correction information is sorted according to the occurrence time of the error bits. The error correction information corresponding to the latest error bit can be arranged at the front of the sequence, so that the sorting of the error correction information is associated with the occurrence time of the error bits, facilitating the maintenance and management of the error record table by the control chip. For example, when the error correction information stored in the error record table reaches the upper limit, the error correction information sorted at the rear of the sequence can be deleted preferentially.

[0042] In some optional embodiments of the embodiment, when the number of error bits recorded in the error correction information is not less than the preset number, the control chip 110 can update the error record table based on the error correction information.

[0043] In the embodiment, the control chip 110 can only record error correction information with a large number of error bits, so as to reduce the data amount of the error record table.

[0044] In an optional embodiment of the embodiment, the redundant storage area and the replacement relationship table can be pre-set in each memory chip 130. After the control chip 110 determines the memory address information of the unreliable storage units, the control chip 110 can send the memory address information and the replacement instruction to the corresponding memory chip 130. The memory chip 130 replaces the unreliable storage units with the redundant storage units in the internal redundant storage area, and records the address correspondence relationship between the unreliable storage units and the redundant storage units in the replacement relationship table.

[0045] In another optional implementation of the embodiment, a redundant storage area can be determined in the memory chip 130, which is shared by multiple memory chips 130. The control chip 110 can replace the unreliable storage unit with a redundant storage unit in the redundant storage area, and record the address correspondence relationship between the unreliable storage unit and the redundant storage unit as a replacement relationship.

[0046] In one example, since the minimum unit of the memory address in the CXL memory module is a byte (B), the memory address information of the error bit can be the address of the 8 storage units corresponding to the byte containing the error bit in the memory chip 130. In this way, each error correction information can correspond to 8 storage units with error bits. The control chip 110 can determine that each group of unreliable storage units determined according to the error record table includes 8 storage units. Then, the control chip 110 can replace the row or column where the unreliable storage unit is located with a row or column composed of redundant storage units, and record the address mapping relationship between the row or column where the unreliable storage unit is located and the row or column composed of redundant storage units. In this way, when the row or column where the unreliable storage unit is located is accessed subsequently, the row or column composed of redundant storage units can be accessed according to the address mapping relationship, so as to repair the unreliable storage unit in the memory chip 130 in units of rows or columns.

[0047] In another example, since the minimum unit of reading and writing data in the CXL memory module is a word (i.e., containing multiple bytes), the address of the word containing the error bit in the memory chip 130 can be used as the memory address information in the error correction information, that is, each error correction information corresponds to a word with error bits. In this way, the control chip 110 can determine that each group of unreliable storage units determined according to the error record table corresponds to an unreliable word. Then, the control chip 110 can replace the unreliable word with a replacement word composed of redundant storage units in units of words, and record the address mapping relationship between the unreliable word and the replacement word. In this way, when the unreliable word is accessed subsequently, the replacement word can be accessed according to the address mapping relationship, so as to repair the unreliable storage unit in the memory chip in units of words.

[0048] In the embodiment, the control chip 110 can complete the replacement process of the unreliable storage unit and the redundant storage unit when starting up, or can periodically perform the replacement process.

[0049] The CXL memory module in the embodiment can establish an error record table according to error correction information recorded when the error correction unit performs error correction processing on data, and identify unreliable storage units in the memory chip according to the error correction information in the error record table, and then replace the unreliable storage units with redundant storage units. The unreliable storage units in the memory chip can be dynamically repaired during use of the CXL memory module, which helps to improve the reliability of the CXL memory module in processing data.

[0050] As shown in FIG. 1, in some optional embodiments, the CXL memory module can further include a flash memory 140; and the control chip 110 is further configured to: in response to a shutdown instruction, store the error record table into the flash memory 140; and in response to a startup instruction, load the error record table from the flash memory 140.

[0051] In the embodiment, the CXL memory module can use the flash memory to implement persistent storage of the error record table.

[0052] In some optional implementations of the embodiment, the control chip 110 can periodically store the error record table into the flash memory 140 to update the error record table in the flash memory 140.

[0053] In some embodiments, the error correction information can further include an error occurrence frequency corresponding to the memory address information of the error bit; and the control chip determines the unreliable storage unit according to the error occurrence frequency, including: determining, from the error record table, memory address information with an error occurrence frequency greater than a preset frequency as an unreliable address; and the storage unit pointed to by the unreliable address is the unreliable storage unit.

[0054] In the embodiment, the error occurrence frequency represents the number of times of error bits in the plurality of storage units corresponding to the error correction information, and the greater the error occurrence frequency, the poorer the reliability of the plurality of storage units corresponding to the error correction information. Therefore, determining the unreliable storage unit according to the error occurrence frequency can more accurately identify the unreliable storage unit in the memory chip, and further more accurately repair the memory chip.

[0055] For example, the preset frequency can be a fixed value; or a set composed of a plurality of values, which is dynamically selected by the control chip according to a preset repair strategy.

[0056] In some optional implementations of the embodiment, the control chip is further configured to: after replacing the unreliable storage unit with the predetermined redundant storage unit, delete the error correction information corresponding to the unreliable address from the error record table.

[0057] Deleting the error correction information corresponding to the replaced unreliable storage unit can determine the accuracy and timeliness of the information in the error record table, which not only avoids the error record table occupying too much storage resource due to errors, but also ensures the repair accuracy.

[0058] In some embodiments, the control chip is further configured to update the error record table according to the new error correction information when the new error correction information is received.

[0059] Since the error correction processing of the error correction unit is performed in real time, the control chip updates the error record table according to the new error correction information, which can ensure the timeliness of the information in the error record table.

[0060] In an optional implementation of the embodiment, the error record table includes a sequence of a plurality of error correction information arranged according to the occurrence time of the error bit, for example, the error bit corresponding to the error correction information with the latest occurrence time is arranged at the front of the sequence. The occurrence time of the error bit can be represented by the generation time of the error correction information.

[0061] The control chip can update the error record table by the following steps: searching the memory address information in the new error correction information in the error record table, determining whether the target error correction information corresponding to the memory address information exists in the error record table; in the case that the target error correction information exists, updating the error times in the target error correction information, and arranging the target error correction information at the front of the sequence; in the case that the target error correction information does not exist, setting the error times in the new error correction information to 1, and arranging the new error correction information at the front of the sequence.

[0062] In the implementation, the error record table adopts the form of sequence, which can associate the position of the error correction information with the occurrence time of the error bit, facilitating the update and maintenance of the error record table. When the control chip receives the new error correction information, it can determine the update mode according to the existing error correction information in the error record table, and update the error record table more accurately and efficiently.

[0063] In an example of the implementation, the control chip is further configured to delete one or more error correction information at the back of the sequence when the number of error correction information in the error record table reaches a number threshold.

[0064] As an example, the number threshold can be determined according to the storage space of the error record table. For example, the upper limit of the storage of the error record table is m error correction information, and the number threshold can be set to m or m-1 or other smaller values.

[0065] In the example, when the number of error correction information reaches the number threshold, the error correction information at the back of the sequence can be deleted, which can avoid the loss of error correction information caused by data overflow on the premise of ensuring the timeliness of the error correction information.

[0066] In some embodiments, the error correction information further comprises a number of error bits; and the control chip is configured to establish the error record table by: establishing a plurality of sequences according to the number of error bits, each sequence comprising a plurality of error correction information with the same number of error bits arranged according to the time of occurrence of the error bits; and merging the plurality of sequences to form the error record table.

[0067] For example, assuming that the error correction unit can correct n error bits in the data at a time, the control chip can divide all the error correction information into n sets according to the number of error bits, each set corresponding to a number of error bits, for example, the error correction information in set A contains 1 error bit, the error correction information in set B contains 2 error bits, and the error correction information in set C contains n error bits. Then, the control chip can sort the error correction information in each set according to the time of occurrence of the error bits, thereby obtaining n sequences, each sequence corresponding to a number of error bits. The n sequences are taken as the error record table.

[0068] In this embodiment, the plurality of sequences are constructed according to the number of error bits, which can improve the degree of subdivision of the error correction information in the error record table, and help to more accurately identify the unreliable storage units.

[0069] In some optional implementations of this embodiment, the sequence with a larger number of error bits can be placed in front of the sequence with a smaller number of error bits, and the plurality of sequences are merged into one sequence. When the data in the error record table reaches a preset number, the error correction information at the end of the merged sequence can be deleted.

[0070] Alternatively, the control chip can manage the error correction information in the plurality of sequences respectively, and when the error correction information in each sequence reaches an upper limit, the error correction information at the end of the sequence can be deleted.

[0071] In some embodiments, different filtering criteria can be set for different sequences according to the number of error bits, so as to determine the unreliable storage units.

[0072] In one example of this embodiment, the preset number of times can be a set of a plurality of values, and each sequence corresponds to a value in the set; and the control chip can determine the unreliable address corresponding to the unreliable storage unit by: for each sequence, comparing the number of errors included in each error correction information in the sequence with the value corresponding to the sequence, to determine the unreliable address included in the sequence.

[0073] In this example, different numbers of error bits correspond to different filtering criteria, for example, the more error bits contained in the error correction information in a sequence, the smaller the value corresponding to the sequence; and the fewer error bits contained in the error correction information in a sequence, the larger the value corresponding to the sequence.

[0074] Assuming that the error correction unit can correct 2 error bits in the data each time, the preset number of times can be a set {10, 20}, and the error record table includes a sequence a and a sequence b, where each error correction information in the sequence a contains 1 error bit, and each error correction information in the sequence b contains 2 error bits. Correspondingly, the sequence a corresponds to a value of 20, and the sequence b corresponds to a value of 10. When the error correction information in the sequence a contains an error number greater than 20, the error correction information is determined as an unreliable address; when the error correction information in the sequence b contains an error number greater than 10, the error correction information is determined as an unreliable address.

[0075] In this example, different screening criteria are set according to the number of error bits, which helps to more accurately identify the unreliable address corresponding to the unreliable storage unit in the memory chip, thereby further improving the pertinence of repairing the memory chip.

[0076] In another example of the embodiment, each sequence corresponds to a weight coefficient; and the control chip can determine the unreliable address corresponding to the unreliable storage unit by the following steps: determining the weight of the error correction information based on the error number contained in the error correction information and the weight coefficient corresponding to the sequence where the error correction information is located; in the case that the number of error correction information corresponding to the memory address information is 1, taking the weight of the error correction information as the error number correction value of the memory address information; in the case that the number of error correction information corresponding to the memory address information is greater than 1, taking the sum of the weights of the plurality of error correction information corresponding to the memory address information as the error number correction value of the memory address information; and determining the memory address information with an error number correction value greater than the preset number of times as an unreliable address.

[0077] In this example, the weight coefficient corresponding to the sequence is positively correlated with the number of error bits contained in the error correction information in the sequence, that is, the greater the number of error bits, the greater the weight coefficient corresponding to the sequence.

[0078] Assuming that the error correction unit can correct 2 error bits in the data each time, the preset number of times can be 20, and the error record table includes a sequence c and a sequence d, where each error correction information in the sequence c contains 1 error bit, and each error correction information in the sequence d contains 2 error bits. Correspondingly, the weight coefficient corresponding to the sequence c is 2, and the weight coefficient corresponding to the sequence d is 3. The error correction information E in the sequence c contains an error number of 6, and the error correction information F contains an error number of 4; the error correction information G in the sequence d contains an error number of 2, the error correction information H contains an error number of 4, and the error correction information M contains an error number of 10; wherein the error correction information E and the error correction information G have the same memory address information i, the error correction information F and the error correction information H have the same memory address information j, and the error correction information M contains the memory address information k.

[0079] The following results can be obtained: the weight of the error correction information E is the product of 6 and 2, that is, 12; the weight of the error correction information G is the product of 2 and 3, that is, 6; and the error correction value of the memory address information i is the sum of 12 and 6, that is, 18. By analogy, the error correction value of the memory address information j is 20, and the error correction value of the memory address information k is the weight of the error correction information M, that is, 30. By comparison, it can be determined that the memory address information j and the memory address information k are unreliable addresses.

[0080] In this example, different weight coefficients are set for different sequences for different numbers of error bits, and the error correction value of the memory address information is determined by the number of errors and the weight coefficient. The reliability of the storage unit corresponding to the memory address information can be more accurately represented, which helps to more accurately identify the unreliable address corresponding to the unreliable storage unit in the memory chip, thereby further improving the pertinence of repairing the memory chip.

[0081] Referring next to FIG. 2, as shown in FIG. 2, the CXL memory module includes a control chip 210 and a plurality of memory chips 220, and at least one error correction unit 230 is arranged in each memory chip 220. In this embodiment, the interface of each memory chip 220 in the plurality of memory chips is provided with a plurality of signal lines, each signal line corresponding to a number of error bits; and the error correction unit 230 is configured to send the number of error bits contained in the error correction data to the control chip 210 through the plurality of signal lines.

[0082] As an example, the error correction unit 230 can correct 2 error bits each time, and the interface of each memory chip 220 is provided with 2 signal lines: signal line 1 and signal line 2, corresponding to 1 error bit and 2 error bits respectively. When the signal line 1 outputs a high level, the control chip 210 can determine that the data corrected by the error correction unit 230 contains 1 error bit; when the signal line 2 outputs a high level, the control chip 210 can determine that the data corrected by the error correction unit 230 contains 2 error bits; and when the signal line 1 and the signal line 2 both output a low level, the control chip 210 can determine that there is no error bit in the data.

[0083] In this embodiment, the error correction unit is arranged in each memory chip, which can improve the error correction efficiency of the CXL memory module.

[0084] FIG. 3 shows a flowchart of one embodiment of a method for repairing a memory according to the present disclosure, which is applied to the CXL memory module in any of the above embodiments, and the CXL memory module includes a control chip, an error correction unit, and one or more memory chips managed by the control chip. As shown in FIG. 3, the flow includes the following steps 310 to 330.

[0085] Step 310, establishing an error record table to store error correction information recorded by the error correction unit when correcting the data.

[0086] The error correction information includes memory address information of the error bit.

[0087] In some optional embodiments of the present embodiment, the error correction information is obtained by recording memory address information of the error bit as the error correction information when the number of corrected error bits is not less than a preset number when correcting the data. The data amount of the error record table can be reduced, which helps to save resources.

[0088] Step 320, determining unreliable storage units in the memory chip according to the error record table.

[0089] Step 330, replacing the unreliable storage units with the predetermined redundant storage units.

[0090] The method for repairing the memory of the present embodiment can establish an error record table according to error correction information recorded by the error correction unit when correcting the data, identify unreliable storage units in the memory chip according to the error correction information in the error record table, and then replace the unreliable storage units with redundant storage units. The unreliable storage units in the memory chip can be dynamically repaired during the use of the CXL memory module, which helps to improve the reliability of the CXL memory module in processing data.

[0091] Referring to FIG. 4, FIG. 4 shows a flowchart of one embodiment of the method for repairing the memory of the present disclosure. As shown in FIG. 4, the flowchart includes the following steps 410 to 430.

[0092] Step 410, establishing an error record table to store error correction information recorded by the error correction unit when correcting the data.

[0093] In the present embodiment, the error correction information further includes the number of errors corresponding to the memory address information of the error bit.

[0094] In some optional embodiments of the present embodiment, the step includes updating the error record table based on the error correction information when the number of error bits recorded in the error correction information is not less than a preset number.

[0095] In the present embodiment, whether to record in the error record table can be determined according to the number of error bits contained in the error correction information, so as to reduce the data amount of the error record table.

[0096] Step 420, determining memory address information with an error number greater than a preset number from the error record table as an unreliable address.

[0097] The storage unit pointed to by the unreliable address is an unreliable storage unit.

[0098] Step 430, replacing the unreliable storage unit with the predetermined redundant storage unit.

[0099] In the embodiment, the unreliable storage unit is determined according to the number of errors, which can more accurately identify the unreliable storage unit in the memory chip, and further more accurately repair the memory chip.

[0100] In some optional embodiments of the embodiment, the flow shown in FIG. 4 can further include: step 440, deleting the error correction information corresponding to the unreliable address from the error record table.

[0101] Deleting the error correction information corresponding to the replaced unreliable storage unit can determine the accuracy and timeliness of the information in the error record table, which not only avoids the error record table from occupying too much storage resource, but also ensures the repair accuracy.

[0102] In some embodiments, the method for repairing the memory of the present disclosure further includes: when receiving new error correction information, updating the error record table according to the new error correction information.

[0103] Since the error correction processing is performed in real time, updating the error record table according to the received new error correction information can ensure the timeliness of the information in the error record table.

[0104] FIG. 5 shows a flow diagram of updating the error record table in one embodiment of the method for repairing the memory of the present disclosure, as shown in FIG. 5, the flow includes the following steps 510 to 530.

[0105] Step 510, finding the memory address information in the new error correction information in the error record table, and determining whether there is target error correction information corresponding to the memory address information in the error record table.

[0106] In the embodiment, the error record table is a sequence in which a plurality of error correction information is arranged according to the occurrence time of the error bit.

[0107] Step 520, in the case where the target error correction information exists, updating the number of errors in the target error correction information, and arranging the target error correction information at the front of the sequence.

[0108] Step 530, in the case where the target error correction information does not exist, setting the number of errors in the new error correction information to 1, and arranging the new error correction information at the front of the sequence.

[0109] In the embodiment, the error record table is in the form of a sequence, and the position of the error correction information and the time of the error bit can be associated, so that the error record table can be updated and maintained conveniently. When new error correction information is received, the updating manner can be determined according to the existing error correction information in the error record table, and the error record table can be updated more accurately and efficiently.

[0110] In some optional embodiments of the embodiment, the method can further include: when the number of error correction information in the error record table reaches a number threshold, deleting one or more error correction information at the last of the sequence. On the premise of ensuring the timeliness of the error correction information, the loss of the error correction information caused by data overflow can be avoided.

[0111] In some embodiments, the error correction information further includes the number of error bits; and the error record table can be established by: establishing a plurality of sequences according to the number of error bits, each sequence including a plurality of error correction information with the same number of error bits arranged according to the time of the error bits; and merging the plurality of sequences to form the error record table.

[0112] In the embodiment, a plurality of sequences are constructed according to the number of error bits, which can improve the subdivision degree of the error correction information in the error record table, and help to identify the unreliable storage units more accurately.

[0113] In some embodiments, the preset number of times is a set of a plurality of values, and each sequence corresponds to a value in the set; and the step 420 can include: for each sequence, comparing the number of error times included in each error correction information in the sequence with the value corresponding to the sequence to determine the unreliable address included in the sequence.

[0114] In the example, different screening criteria are set according to the number of error bits, which helps to identify the unreliable address corresponding to the unreliable storage unit in the memory chip more accurately, and further improves the pertinence of repairing the memory chip.

[0115] In some embodiments, each sequence corresponds to a weight coefficient; and the step 420 can further include the flow shown in FIG. 6, which includes the following steps 610 to 640.

[0116] The step 610 includes: determining the weight of the error correction information based on the number of error times included in the error correction information and the weight coefficient corresponding to the sequence where the error correction information is located.

[0117] The step 620 includes: in the case where the number of error correction information corresponding to the memory address information is 1 (i.e. not more than 1), taking the weight corresponding to the error correction information as the error times correction value of the memory address information.

[0118] In step 630, in a case where the number of error correction information corresponding to the memory address information is greater than 1, the sum of the weights of the plurality of error correction information corresponding to the memory address information is taken as the error times correction value of the memory address information.

[0119] In step 640, the memory address information with the error times correction value greater than the preset number of times is determined as the unreliable address.

[0120] In the embodiment, different weight coefficients are set for different sequences for different numbers of error bits, and the error times correction value of the memory address information is determined by the error times and the weight coefficient, which can more accurately represent the unreliability of the storage unit corresponding to the memory address information, and helps to more accurately identify the unreliable address corresponding to the unreliable storage unit in the memory chip, thereby further improving the pertinence of repairing the memory chip.

[0121] In some embodiments, the CXL memory module further includes a flash memory; and the method further includes: in response to a shutdown instruction, storing the error record table into the flash memory; and in response to a startup instruction, loading the error record table from the flash memory. The persistent storage of the error record table can be implemented.

[0122] In some optional implementations of the embodiment, the method can further include: periodically storing the error record table into the flash memory to update the error record table in the flash memory.

[0123] As shown in FIG. 7, the disclosure also provides a control chip applied to a CXL memory module, the CXL memory module further includes one or more memory chips 720 managed by the control chip 710, the control chip 710 includes a processor 711 and an error correction unit 712, and the control chip 710 is configured to execute the method for repairing the memory in any of the above embodiments.

[0124] The disclosure also provides a non-transitory computer storage medium, which stores a computer program, and the computer program is executed by a processor to implement the method for repairing the memory in any of the above embodiments.

[0125] As shown in FIG. 8, the disclosure also provides a memory chip applied to the CXL memory module in any of the above embodiments, the memory chip is provided with an error correction unit 810 and a replacement unit 820; the error correction unit 810 is configured to: determine whether the data read from the memory chip is erroneous, perform error correction when the data is erroneous, and record error correction information, the error correction information including memory address information of the error bit; and send the error correction information to a control chip; and the replacement unit 820 is configured to: in response to receiving a replacement instruction from the control chip, replace an unreliable storage unit pointed by the replacement instruction with a redundant storage unit, and record the address correspondence relationship between the unreliable storage unit and the redundant storage unit.

[0126] In some embodiments, the interface of the memory chip is provided with a signal line 830; the error correction unit 810 is configured to send the error correction information to the control chip through the signal line.

[0127] In some embodiments, the error correction information further includes the number of error bits that occur; and the structure of the memory chip is provided with a plurality of signal lines, each signal line corresponding to the number of error bits.

[0128] As shown in FIG. 9, the present disclosure also provides a computer system, including a host 910 and a CXL memory module 920 in any of the above embodiments, the host 910 communicates with the CXL memory module 920 through a CXL interface, realizing the discovery, configuration and data transmission of the CXL memory module 920, the CXL memory module 920 is configured to: perform error correction processing on data; identify unreliable storage units in the memory chip according to the error correction information recorded during error correction, and replace the unreliable storage units with redundant storage units.

[0129] Those of ordinary skill in the art can understand that all or some of the steps in the above disclosed method, the functional modules / units in the system and the device can be implemented as software, firmware, hardware and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some components or all components can be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on a computer readable medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, as known to those of ordinary skill in the art, communication media generally includes computer readable instructions, data structures, program modules or other data in modulated data signals such as carrier waves or other transmission mechanisms, and can include any information delivery medium.

Claims

1. A CXL memory module, comprising a control chip and one or more memory chips managed by the control chip, and an error correction unit is arranged in the control chip or the memory chip, wherein the control chip is configured to: establish an error record table, store error correction information recorded by the error correction unit when correcting data, the error correction information comprising memory address information of an error bit that occurs; determine an unreliable storage unit in the memory chip according to the error record table; and replace the unreliable storage unit with a predetermined redundant storage unit. The error correction information further comprises the number of error bits that occur.

2. The CXL memory module of claim 1, wherein, And The control chip is configured to determine the unreliable storage unit in the memory chip according to the error record table, comprising: the control chip determines, from the error record table, memory address information with a number of errors greater than a preset number as an unreliable address, the storage unit pointed to by the unreliable address being the unreliable storage unit. The control chip is further configured to delete the error correction information corresponding to the unreliable address from the error record table after replacing the unreliable storage unit with the predetermined redundant storage unit.

3. The CXL memory module of claim 2, wherein, The error correction unit is configured to, when correcting data, record, as the error correction information, memory address information of an error bit that occurs if the number of error bits is not less than a preset number.

4. The CXL memory module of claim 2, wherein, The control chip is configured to store error correction information recorded by the error correction unit when correcting data, comprising: updating the error record table based on the error correction information if the number of error bits recorded in the error correction information is not less than a preset number.

5. The CXL memory module of claim 2, wherein, The control chip is further configured to update the error record table according to new error correction information when the new error correction information is received.

6. The CXL memory module of one of claims 2 to 5, wherein, The error record table comprises a plurality of sequences of the error correction information arranged in order of occurrence of error bits.

7. The CXL memory module of claim 6, wherein, The control chip is configured to update the error record table according to new error correction information when the new error correction information is received, comprising: the control chip searches for memory address information in the new error correction information in the error record table to determine whether target error correction information corresponding to the memory address information exists in the error record table; in the case where the target error correction information exists, the control chip updates the number of errors in the target error correction information and arranges the target error correction information at the front of the sequence; and in the case where the target error correction information does not exist, the control chip sets the number of errors in the new error correction information to 1 and arranges the new error correction information at the front of the sequence. The error correction information further comprises the number of error bits that occur.

8. The CXL memory module of claim 7, wherein, And The control chip is configured to establish the error record table, comprising: the control chip establishes a plurality of sequences according to the number of error bits, each sequence comprising a plurality of error correction information with the same number of error bits arranged in order of occurrence of error bits. The control chip takes the plurality of sequences as the error record table. ​ 9. The CXL memory module of claim 8, wherein, The preset number of times is a set composed of multiple values, and each sequence corresponds to a value in the set; The control chip is configured to determine, from the error record table, memory address information with an error number of times greater than a preset number of times as unreliable address, including: the control chip, for each sequence, comparing the error number of times contained in each error correction information in the sequence with the value corresponding to the sequence to determine the unreliable address included in the sequence. Each sequence corresponds to a weight coefficient; 10. The CXL memory module of claim 8, wherein, And, The control chip is configured to determine, from the error record table, memory address information with an error number of times greater than a preset number of times as unreliable address, including: the control chip, based on the error number of times contained in the error correction information and the weight coefficient corresponding to the sequence in which the error correction information is located, determines the weight of the error correction information; In the case where the number of error correction information corresponding to the memory address information is 1, the control chip takes the weight of the error correction information as the error number of times correction value of the memory address information; In the case where the number of error correction information corresponding to the memory address information is greater than 1, the control chip takes the sum of the weights of the multiple error correction information corresponding to the memory address information as the error number of times correction value of the memory address information; The control chip determines the memory address information with an error number of times correction value greater than the preset number of times as the unreliable address. Each interface of the memory chip is provided with multiple signal lines, and each signal line corresponds to a number of error bits; 11. The CXL memory module of claim 8, wherein, Each memory chip is provided with at least one error correction unit, and the error correction unit is configured to send the number of error bits contained in the error correction data to the control chip through the multiple signal lines. The control chip is further configured to delete one or more error correction information at the back of the error record table when the number of error correction information in the error record table reaches a number threshold.

12. The CXL memory module of claim 7, wherein, The CXL memory module further comprises a flash memory; 13. The CXL memory module of claim 1, wherein, The control chip is further configured to store the error record table in the flash memory in response to a shutdown instruction, and load the error record table from the flash memory in response to a startup instruction. The control chip is further configured to periodically store the error record table in the flash memory to update the error record table in the flash memory.

14. The CXL memory module of claim 13, wherein, 15. A method for repairing memory, applied to the CXL memory module of any one of claims 1 to 14, the CXL memory module comprising a control chip and one or more memory chips managed by the control chip, and an error correction unit is arranged in the control chip or the memory chip, the method comprising: establishing an error record table to store error correction information recorded by the error correction unit when correcting data, the error correction information comprising memory address information of error bits; determining unreliable storage units in the memory chip according to the error record table; replacing the unreliable storage units with predetermined redundant storage units. The error correction information further comprises an error number of times of error bits corresponding to the memory address information; 16. The method of claim 15, wherein, And, ​ The determining of the unreliable storage unit in the memory chip according to the error record table comprises: determining, from the error record table, memory address information with an error number greater than a preset number as an unreliable address, and the storage unit pointed to by the unreliable address being the unreliable storage unit.

17. The method of claim 16, after said replacing said unreliable memory cells with said predetermined redundant memory cells, said method further comprising: The error correction information corresponding to the unreliable address is deleted from the error record table.

18. The method of claim 16, wherein, The error correction information is obtained by: when performing error correction on data, if the number of error bits is not less than a preset number, recording the memory address information of the error bits as the error correction information.

19. The method of claim 16, wherein, The storing of the error correction information recorded when the error correction unit performs error correction on data comprises: if the number of error bits recorded in the error correction information is not less than a preset number, updating the error record table based on the error correction information.

20. The method of one of claims 16 to 19, further comprising: When new error correction information is received, the error record table is updated according to the new error correction information.

21. The method of claim 20, wherein, The error record table comprises a plurality of sequences of error correction information arranged according to the occurrence time of error bits. In addition, The updating of the error record table according to the new error correction information comprises: searching for memory address information in the new error correction information in the error record table, determining whether target error correction information corresponding to the memory address information exists in the error record table, updating the error number in the target error correction information if the target error correction information exists, and arranging the target error correction information at the front of the sequence; and if the target error correction information does not exist, setting the error number in the new error correction information to 1 and arranging the new error correction information at the front of the sequence.

22. The method of claim 21, wherein, The error correction information further comprises the number of error bits; and The error record table is established by: establishing a plurality of sequences according to the number of error bits, each sequence comprising a plurality of error correction information with the same number of error bits arranged according to the occurrence time of error bits; and taking the plurality of sequences as the error record table.

23. The method of claim 22, wherein, The preset number is a set of a plurality of values, and each sequence corresponds to a value in the set; The determining of the memory address information with an error number greater than a preset number from the error record table as an unreliable address comprises: for each sequence, comparing the error number contained in each error correction information in the sequence with the value corresponding to the sequence to determine the unreliable address included in the sequence.

24. The method of claim 22, wherein, Each sequence corresponds to a weight coefficient; and The determining of the memory address information with an error number greater than a preset number from the error record table as an unreliable address comprises: determining the weight of the error correction information based on the error number contained in the error correction information and the weight coefficient corresponding to the sequence where the error correction information is located. In a case where the number of error correction information corresponding to the memory address information is 1, the weight corresponding to the error correction information is taken as the error number correction value of the memory address information. ​ In the case that the number of error correction information corresponding to the memory address information is greater than 1, the sum of the weights of the plurality of error correction information corresponding to the memory address information is taken as the error times correction value of the memory address information; The memory address information with the error times correction value greater than the preset number of times is determined as the unreliable address.

25. The method of claim 21, further comprising: When the number of error correction information in the error record table reaches the number threshold, the last one or more error correction information in the sequence is deleted.

26. The method of claim 15, wherein, The CXL memory module further comprises a flash memory; The method further comprises: in response to a shutdown instruction, storing the error record table into the flash memory; in response to a startup instruction, loading the error record table from the flash memory. The error record table is periodically stored into the flash memory to update the error record table in the flash memory.

27. The method of claim 26, further comprising: 28.A control chip applied to a CXL memory module, the CXL memory module further comprising one or more memory chips managed by the control chip, the control chip comprising a processor and an error correction unit, and the control chip being configured to perform the method for repairing memory according to any one of claims 15 to 27. 29.A memory chip applied to the CXL memory module according to any one of claims 1 to 14, the memory chip being provided with an error correction unit and a replacement unit; The error correction unit is configured to: determine whether the data read from the memory chip is erroneous, perform error correction when the data is erroneous, and record error correction information, the error correction information comprising memory address information of the error bit; and send the error correction information to a control chip in the CXL memory module; The replacement unit is configured to: in response to receiving a replacement instruction from the control chip, replace an unreliable storage unit pointed by the replacement instruction with a redundant storage unit, and record the address correspondence relationship between the unreliable storage unit and the redundant storage unit. The interface of the memory chip is provided with a signal line; 30. The memory chip of claim 29, wherein, The error correction unit is configured to send the error correction information to the control chip through the signal line. The error correction information further comprises the number of error bits; and 31. The memory chip of claim 30, wherein, The interface of the memory chip is provided with a plurality of signal lines, each signal line corresponding to the number of error bits. 32.A non-transitory computer storage medium, the computer storage medium storing a computer program, the computer program being executed by a processor to implement the method for repairing memory according to any one of claims 15 to 27. 33.A computer system comprising a host and a CXL memory module according to any one of claims 1 to 14, the host communicating with the CXL memory module through a CXL interface to implement discovery, configuration and data transmission of the CXL memory module, and the CXL memory module being configured to: perform error correction processing on data; identify an unreliable storage unit in a memory chip according to error correction information recorded during error correction, and replace the unreliable storage unit with a redundant storage unit. ​

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