Laterally diffused metal oxide semiconductor field-effect transistor and manufacturing method therefor

Abstract

The present disclosure relates to a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: forming a hard mask on a main surface of a wafer; performing active region photolithography and etching, and removing the hard mask at a position where a field oxide layer needs to be formed; forming the field oxide layer; forming a patterned photoresist layer on the main surface, wherein the photoresist layer covers a position where no drift region needs to be formed; and performing drift region implantation by using the photoresist layer as an implantation blocking layer, wherein ions implanted during drift region implantation pass through the hard mask and the field oxide layer and enter the wafer. In the present disclosure, during drift region implantation, the implanted ions at the edge of the field oxide layer are blocked by using the hard mask, so as to avoid excessive PN junction depth and excessively high ion doping concentration at this position. Rapid depletion of the implanted ions in a JFET region at this position is achieved, thereby reducing the electric field strength at this position, and optimizing and improving the voltage withstand and reliability of the device.

Description

Lateral diffusion metal oxide semiconductor field effect tube and manufacturing method thereof Cross-reference to related applications This application claims priority to the Chinese patent application No. 2024109797412, filed on July 19, 2024, and entitled "Lateral diffusion metal oxide semiconductor field effect tube and manufacturing method thereof", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular, to a manufacturing method of a lateral diffusion metal oxide semiconductor field effect tube, and to a lateral diffusion metal oxide semiconductor field effect tube. BACKGROUND

[0002] In a BCD (Bipolar-Complementary Metal Oxide Semiconductor-Double-diffused Metal Oxide Semiconductor, Bipolar-CMOS-DMOS, bipolar-complementary metal oxide semiconductor-double-diffused metal oxide semiconductor) process platform, in order to meet the requirements of the voltage resistance, on-resistance ratio and driving current capacity of the LDMOS (Lateral DMOS, lateral diffusion metal oxide semiconductor field effect tube) and other electrical characteristics, the drift region of the device is usually formed by ion implantation technology. Taking an N-channel LDMOS (NLDMOS) as an example, an exemplary method is to implant impurities of different energies from the surface of the silicon layer to the body after the growth of the LOCOS (Local Oxidation of Silicon, local oxidation of silicon) field oxide, so as to form an N-type drift region with a certain junction depth. However, due to the influence of the LOCOS field oxide topography, the junction depth of the JFET (Junction Field-Effect Transistor, junction field-effect transistor) region at the front end of the beak of the drift region is deeper and the impurity doping is more than that under the field oxide. When the drain end of the NLDMOS is biased at a high voltage, this region is difficult to deplete quickly, thus seriously affecting the voltage resistance and HCI (Hot Carrier Injection, hot carrier injection) reliability of the NLDMOS device. SUMMARY

[0003] Therefore, it is necessary to provide a manufacturing method of a lateral diffusion metal oxide semiconductor field effect tube capable of optimizing the drift region implantation.

[0004] A method for manufacturing a lateral diffusion metal oxide semiconductor field effect transistor, comprising: forming a hard mask on a main surface of a wafer; performing active region lithography and etching to remove the hard mask at a position where a field oxide layer is needed to be formed; forming the field oxide layer; forming a patterned photoresist layer on the main surface, covering a position where a drift region is not needed to be formed; performing drift region implantation with the photoresist layer as an implantation blocking layer, implantation ions of the drift region implantation penetrating the hard mask and the field oxide layer into the wafer.

[0005] The method for manufacturing a lateral diffusion metal oxide semiconductor field effect transistor as above, in the drift region implantation, the hard mask is used to block implantation ions at a bird beak of the field oxide layer, so as to avoid too deep PN junction depth and too high ion doping concentration at the bird beak, and the implantation ions in a JFET region at the bird beak can be quickly depleted, so as to reduce electric field intensity at the bird beak and optimize device voltage resistance and reliability.

[0006] In one of the embodiments, the step of forming the field oxide layer is formed by a local oxidation of silicon isolation (LOCOS) process.

[0007] In one of the embodiments, when the step of forming the field oxide layer is completed, the hard mask is overlapped on the bird beak of the field oxide layer.

[0008] In one of the embodiments, the drift region implantation comprises a first implantation and a second implantation, and an implantation energy of the second implantation is greater than an implantation energy of the first implantation.

[0009] In one of the embodiments, the hard mask is a silicon nitride layer.

[0010] In one of the embodiments, the implantation energy of the first implantation is 300 keV to 800 keV.

[0011] In one of the embodiments, the thickness of the hard mask is to

[0012] In one of the embodiments, the lateral diffusion metal oxide semiconductor field effect transistor is an N-channel lateral diffusion metal oxide semiconductor field effect transistor, the drift region is an N-type drift region, and the drift region implantation is implantation of N-type ions.

[0013] In one of the embodiments, before the step of forming the hard mask on the main surface of the wafer, a P-type well region of the lateral diffusion metal oxide semiconductor field effect transistor is formed.

[0014] In one of the embodiments, after the step of implanting in the drift region, further comprising: removing the hard mask; forming a P-type body region in the P-type well region; forming an N-type source region in the P-type body region.

[0015] In one of the embodiments, after the step of forming the P-type well region and before the step of forming a hard mask on the main surface of the wafer, further comprising forming a pad oxide layer on the main surface; the hard mask is formed on the pad oxide layer.

[0016] It is also necessary to provide a lateral diffusion metal oxide semiconductor field effect transistor.

[0017] A lateral diffusion metal oxide semiconductor field effect transistor is formed by the manufacturing method of any one of the preceding embodiments.

[0018] The lateral diffusion metal oxide semiconductor field effect transistor, when implanting in the drift region, uses the hard mask to block the implanting ions at the bird beak of the field oxide layer, thereby avoiding the PN junction depth being too deep and the ion doping concentration being too high at this place, and the implanting ions in the JFET region at this place can be quickly depleted, thereby reducing the electric field intensity at this place and optimizing the device voltage resistance and reliability. BRIEF DESCRIPTION OF DRAWINGS

[0019] For better describing and illustrating the embodiments and / or examples of the inventions disclosed herein, one or more drawings can be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and / or examples, and the best mode presently understood of these inventions.

[0020] Fig. 1 is a schematic cross-sectional view of an exemplary NLDMOS device structure.

[0021] Fig. 2 is a schematic view of the NLDMOS of Fig. 1 during drift region implantation.

[0022] Fig. 3 is a flowchart of a manufacturing method of a lateral diffusion metal oxide semiconductor field effect transistor according to an embodiment of the present application.

[0023] Fig. 4 is a schematic cross-sectional view of the device after step S140 of the manufacturing method of a lateral diffusion metal oxide semiconductor field effect transistor according to an embodiment of the present application.

[0024] Fig. 5 is a schematic view of the drift region implantation of step S150 of the manufacturing method of a lateral diffusion metal oxide semiconductor field effect transistor according to an embodiment of the present application.

[0025] Fig. 6 is a schematic cross-sectional view of the device after removing the hard mask of the manufacturing method of a lateral diffusion metal oxide semiconductor field effect transistor according to an embodiment of the present application.

[0026] FIG. 7 is a flow chart of a method of manufacturing a lateral diffusion metal oxide semiconductor field effect transistor according to another embodiment of the present application. DETAILED DESCRIPTION

[0027] For the purposes of this disclosure, reference will be made to the accompanying drawings which form a part of the present disclosure. The drawings are not necessarily to scale of the preferred embodiments of the present disclosure. It is to be understood that the drawings are solely for the purpose of illustration of the embodiments of the present disclosure and are not intended for use in the determination of critical dimensions, and are merely meant to illustrate the general principles or aspects of the present disclosure. In the drawings:

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs. The terminology used in the description of the present disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used in this description of the present disclosure, the singular forms "a", "an" and "the" include plural references unless the context clearly dictates otherwise. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. By the term "connection" in the present specification, if there is a transmission of electrical signals or data between the circuits, modules, units, etc. connected to each other, it should be understood as "electrical connection", "communication connection", etc. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0030] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] The disclosed embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the disclosure should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implantation occurs. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the disclosure.

[0033] The semiconductor field vocabulary used herein is the technical vocabulary commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, simply P+ type represents the P-type of heavy doping concentration, P type represents the P-type of medium doping concentration, P- type represents the P-type of light doping concentration, N+ type represents the N-type of heavy doping concentration, N type represents the N-type of medium doping concentration, and N- type represents the N-type of light doping concentration.

[0034] Taking the NLDMOS device as an example. In the working process of the NLDMOS device, the conduction current flows along the silicon-oxide interface of the device surface. In order to obtain lower on-resistance and larger current driving capability, increasing the doping concentration of the drift region at the silicon-oxide interface of the surface is an effective way to improve the on-resistance and driving current characteristics of the device. In order to achieve the above purpose, high-dose impurity implantation can be performed on the surface of the JFET region at the front end of the drift region and under the LOCOS field oxide, especially the doping concentration of the drift region under the LOCOS field oxide is closely related to the current driving capability of the device. In addition, a high-energy implantation is further performed to form the bottom drift region junction depth. However, due to the influence of the LOCOS topography, the field oxide at the beak (i.e. the two ends of the field oxide layer shown in FIG. 1) is relatively thin and has weak ion implantation blocking ability. Therefore, compared with the main body region of the drift region under the thick field oxide, the JFET drift region junction depth at the beak is deeper (as shown by the arrowed line segments at the two ends in FIG. 1). And the high-concentration impurity implantation is far away from the surface of the device bulk silicon, and the surface field plate has weakened depletion capability, so the JFET drift region is difficult to be depleted, the electric field strength at the beak is large, which brings great difficulty to the high-voltage and high-reliability design of the device.

[0035] As shown in FIG. 2, the drift region is formed by three implantations. The first implantation (1st) forms a drift region JFET region with a certain concentration in the beak region; the second implantation (2nd) needs to penetrate the LOCOS field oxide region to form a high-concentration impurity doping under the same; and the third implantation (3rd) is a high-energy impurity implantation to realize the junction depth distribution of the bottom of the drift region. As can be seen from FIG. 1, the beak lacks thick field oxide blocking, so the JFET drift region formed at the beak has a very deep junction depth (refer to the arrowed line segments at the two ends in FIG. 1). Compared with the thick field oxide under the LOCOS, the JFET region at the beak has three impurity implantations, so the doping concentration is higher and far away from the surface of the device, and the depletion capability of the Poly (polysilicon) field plate is weakened. Under the condition of high voltage bias at the drain end, the drift region at the beak is difficult to be depleted quickly, and a large electric field is easily formed, which causes the device to break down in advance, and the breakdown voltage BV of the device is difficult to improve.

[0036] FIG. 3 is a flowchart of a manufacturing method of a lateral diffusion metal oxide semiconductor field effect transistor according to an embodiment of the present application, including the following steps:

[0037] S110, forming a hard mask on the front surface of the wafer.

[0038] A hard mask 52 is formed on the main surface (i.e. the front surface) of the substrate 10 of the wafer. In one embodiment of the present application, the substrate 10 is a semiconductor substrate, which can be made of undoped monocrystalline silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), strained SOI (SSOI), S-SiGeOI, SiGeOI, and GeOI, etc., and can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. In the embodiment shown in FIG. 4, the material of the substrate 10 is monocrystalline silicon.

[0039] S120, performing active region lithography and etching, and removing the hard mask at the position where the field oxide layer is to be formed.

[0040] In one embodiment of the present application, photoresist is coated on the hard mask 52, and then exposed using an active region mask, followed by development and other processes, so that the photoresist is removed at the position where the field oxide layer is to be formed, exposing the etching window, and then the hard mask 52 under the etching window is etched and removed.

[0041] S130, forming a field oxide layer.

[0042] Through an oxidation process, a field oxide layer 40 is formed at the position where the hard mask 52 is etched and removed. In one embodiment of the present application, the field oxide layer 40 is formed by the LOCOS process.

[0043] S140, forming a patterned photoresist layer on the front surface of the wafer, covering the position where the drift region is not to be formed.

[0044] In one embodiment of the present application, photoresist is coated on the front surface of the wafer, and then exposed using a drift region mask, followed by development and other processes, so that the photoresist is removed at the position where the drift region is to be formed, forming a photoresist layer 62, as shown in FIG. 4.

[0045] S150, performing drift region implantation with the photoresist layer as an implantation barrier layer.

[0046] In one embodiment of the present application, the drift region implantation includes a first implantation and a second implantation, the implantation energy of the second implantation is greater than that of the first implantation. Further, the impurity ions of the first implantation penetrate the field oxide layer 40 and the hard mask 52, and form a doped region 1st near the surface of the substrate 10 under the field oxide layer 40 and near the surface of the substrate 10 under the bird's beak, see Fig. 5. The second implantation is a high-energy ion implantation, and forms a doped region 2nd as shown in Fig. 5, which is used to form the bottom drift region junction depth distribution.

[0047] After the drift region implantation is completed, the photoresist layer 62 is removed first, and then the hard mask 52 is completely removed, as shown in Fig. 6.

[0048] The manufacturing method of the lateral diffusion metal oxide semiconductor field effect transistor described above, when the drift region is implanted, the hard mask 52 is used to block the implantation ions at the bird's beak of the field oxide layer 40, which takes into account the high-concentration implantation design requirements of the JFET region, while reducing the total dose of impurity implantation in this region, thereby avoiding the PN junction depth being too deep and the ion doping concentration being too high, and enabling the implantation ions in the JFET region to be quickly depleted, thereby reducing the electric field strength in this region and optimizing the device voltage resistance and reliability. Moreover, the drift region implantation of this method only needs to be performed in two implantations, which can reduce one implantation compared with the drift region implantation scheme shown in Fig. 2, which needs to be performed in three implantations, thereby improving the manufacturing efficiency.

[0049] In one embodiment of the present application, after the field oxide layer 40 is formed in step S130, the hard mask 52 is overlapped with the bird's beak of the field oxide layer, with the edge of the hard mask 52 being on the bird's beak, as shown in Fig. 4.

[0050] In one embodiment of the present application, the hard mask 52 is a silicon nitride layer. In step S110, silicon nitride is deposited on the front surface of the wafer as the hard mask 52. Before the drift region implantation, there is a thin film of silicon nitride remaining in the bird's beak region of the LOCOS field oxide layer, and the silicon nitride has strong impurity implantation blocking ability as a hard mask version. Using the hard mask 52 as an implantation mask layer for the bird's beak region of the LOCOS field oxide layer, on the one hand, reduces the implantation depth of impurities in the bird's beak region, and on the other hand, effectively suppresses the channeling effect of high-energy implantation impurities, which is helpful to form a relatively shallow junction depth distribution in the drift region JFET region.

[0051] The first drift region implantation in step S150 needs to penetrate the field oxide layer 40, and the implantation energy is set according to the thickness of the field oxide layer. In one embodiment of the present application, the implantation energy of the first drift region implantation is 300 keV to 800 keV.

[0052] In one embodiment of the present application, the thickness of the silicon nitride as the hard mask 52 is about 50 nm to 100 nm, for example, about 70 nm. ​​

[0053] In one embodiment of the present application, the lateral diffusion metal oxide semiconductor field effect tube is an N-channel lateral diffusion metal oxide semiconductor field effect tube, and the drift region is an N-type drift region (N-drift), and the drift region implantation is implantation of N-type ions. In another embodiment of the present application, the lateral diffusion metal oxide semiconductor field effect tube can also be a P-channel lateral diffusion metal oxide semiconductor field effect tube. That is, the present application is also applicable to the manufacture of PLDMOS or PLDMOS drift regions.

[0054] In one embodiment of the present application, the substrate 10 is a P-type substrate.

[0055] FIG. 7 is a flow chart of a method for manufacturing a lateral diffusion metal oxide semiconductor field effect tube according to another embodiment of the present application, including the following steps:

[0056] S210, forming a P-type well region.

[0057] The P-type well region 22 is formed in the substrate 10. In one embodiment of the present application, the P-type well region 22 is a high-voltage well region (High Voltage PWell, HV PWell).

[0058] S220, forming a pad oxide layer on the front surface of the wafer.

[0059] In one embodiment of the present application, the pad oxide layer can be formed on the front surface of the substrate 10 by a thermal oxidation process.

[0060] S230, forming a hard mask on the front surface of the wafer.

[0061] In one embodiment of the present application, silicon nitride is deposited on the pad oxide layer as the hard mask 52.

[0062] S240, performing active region lithography and etching, and removing the hard mask at positions where the field oxide layer is to be formed.

[0063] In one embodiment of the present application, photoresist is coated on the hard mask 52, then exposed using an active region lithography plate, followed by processes such as development, so that the photoresist is removed at positions where the field oxide layer is to be formed, exposing the etching window, and then etching and removing the hard mask 52 below the etching window.

[0064] S250, forming a field oxide layer.

[0065] In one embodiment of the present application, the field oxide layer 40 is formed on the front surface of the substrate 10 at positions without the hard mask 52 by a LOCOS process.

[0066] S260, a patterned photoresist layer is formed on the front surface of the wafer, covering the positions where the drift region is not needed.

[0067] The structure after the photoresist layer 62 is formed is shown in FIG. 4.

[0068] S270, the photoresist layer is used as an implantation barrier layer, and the drift region implantation is performed.

[0069] In an embodiment of the present application, the drift region implantation includes a first implantation and a second implantation. The first implantation is performed by penetrating the field oxide layer 40 and the hard mask 52, and forms a doped region 1st near the surface of the substrate 10 under the field oxide layer 40 and near the surface of the substrate 10 under the bird's beak, as shown in FIG. 5. The second implantation is a high-energy ion implantation, and forms a doped region 2nd as shown in FIG. 5, which is used to form the bottom drift region junction depth distribution.

[0070] S280, the hard mask is completely removed.

[0071] After the drift region implantation is completed, the photoresist layer 62 is removed, and then the hard mask 52 is completely removed, as shown in FIG. 6.

[0072] In an embodiment of the present application, after the hard mask 52 is removed, a step of forming a P-type body region in the P-type well region 22 is further included, and a step of forming a source region of the NLDMOS in the P-type body region is further included.

[0073] The present application further provides a lateral diffusion metal oxide semiconductor field effect transistor formed by the manufacturing method of any one of the preceding embodiments.

[0074] Based on the above embodiments, the drift region of the lateral diffusion metal oxide semiconductor field effect transistor prepared by the manufacturing method of the lateral diffusion metal oxide semiconductor field effect transistor of the present application has a greatly reduced JFET region junction depth, and is much smaller than the junction depth of the main body of the drift region under the LOCOS. The formed JFET high-concentration implantation region is closer to the surface of the device, and the field plate has a strengthened depletion effect thereon. The manufacturing method of the lateral diffusion metal oxide semiconductor field effect transistor eliminates the first JFET surface impurity implantation step of the drift region implantation in the scheme shown in FIG. 2, and combines the high-concentration impurity implantation under the LOCOS, which meets the design requirements of the JFET region high-concentration implantation while reducing the total dose of the impurity implantation in the region. Therefore, when the device drain is biased at a high voltage, the prepared drift region JFET region can be quickly depleted, which helps to achieve the design requirements of large current, low on-resistance, high voltage and high reliability.

[0075] It should be understood that, although the steps in the flowcharts of the present application are shown in a sequence as indicated by arrows, the steps are not necessarily executed in the order as indicated by the arrows. Unless otherwise specified herein, the execution of the steps is not necessarily limited to the order as indicated by the arrows, and the steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the present application can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution of the steps or stages is not necessarily sequential, but can be performed in rotation or alternation with at least some of the other steps or the steps or stages in the other steps.

[0076] In the description of the present specification, the description referring to the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0077] The technical features of the above-described embodiments can be combined in any manner. In order to make the description concise, not all possible combinations of the technical features of the above-described embodiments are described, however, as long as the combinations of the technical features do not contradict each other, they should be considered to be within the scope of the present specification.

[0078] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be noted that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A method for manufacturing a lateral diffusion metal oxide semiconductor field effect transistor, comprising: forming a hard mask on a main surface of a wafer; performing active region lithography and etching to remove the hard mask at a location where a field oxide layer is desired to be formed; forming the field oxide layer; forming a patterned photoresist layer on the main surface, covering over a location where a drift region is not desired to be formed; performing a drift region implantation with the photoresist layer as an implantation barrier, implantation ions of the drift region implantation penetrating through the hard mask and the field oxide layer into the wafer.

2. The method of manufacturing a lateral diffusion metal oxide semiconductor field effect transistor according to claim 1, wherein, The step of forming the field oxide layer is formed by a local oxidation of silicon isolation (LOCOS) process.

3. The method of manufacturing a lateral diffusion metal oxide semiconductor field effect transistor according to claim 1 or 2, wherein, The hard mask is overlapped with a beak of the field oxide layer when the step of forming the field oxide layer is completed.

4. The method of manufacturing a lateral diffusion metal oxide semiconductor field effect transistor according to any one of claims 1 to 3, wherein, The drift region implantation includes a first implantation and a second implantation, the implantation energy of the second implantation is greater than the implantation energy of the first implantation.

5. The method of manufacturing a lateral diffusion metal oxide semiconductor field effect transistor according to claim 4, wherein, The hard mask is a silicon nitride layer.

6. The method of manufacturing a lateral diffusion metal oxide semiconductor field effect transistor according to claim 4 or 5, wherein, The implantation energy of the first implantation is 300 keV to 800 keV.

7. The method of manufacturing a lateral diffusion metal oxide semiconductor field effect transistor according to any one of claims 1 to 6, wherein, The hard mask has a thickness of from 1 to 10 nm 8. The method of manufacturing a lateral diffusion metal oxide semiconductor field effect transistor according to any one of claims 1 to 7, wherein, The lateral diffusion metal oxide semiconductor field effect transistor is an N-channel lateral diffusion metal oxide semiconductor field effect transistor, the drift region is an N-type drift region, and the drift region implantation is implanting N-type ions.

9. The method of manufacturing a lateral diffusion metal oxide semiconductor field effect transistor according to any one of claims 1 to 8, wherein, Before the step of forming a hard mask on a main surface of a wafer, the method further comprises: forming a P-type well region of the lateral diffusion metal oxide semiconductor field effect transistor.

10. The method of manufacturing a lateral diffusion metal oxide semiconductor field effect transistor of claim 9, wherein, After the step of performing a drift region implantation, the method further comprises: removing the hard mask; forming a P-type body region in the P-type well region; forming an N-type source region in the P-type body region.

11. The method of manufacturing a lateral diffused metal oxide semiconductor field effect transistor according to any one of claims 1 to 10, wherein, The step of performing active region lithography and etching to remove the hard mask at a location where a field oxide layer is desired to be formed includes: coating a photoresist on the hard mask, exposing using an active region lithography plate, developing to make the active region photoresist be removed at a location where the field oxide layer is desired to be formed to expose an etching window, and etching the hard mask under the etching window to be removed.

12. The method of manufacturing a lateral diffusion metal oxide semiconductor field effect transistor according to claim 9 or 10, wherein, The P-type well region is a high voltage well region.

13. The method of manufacturing a lateral diffused metal oxide semiconductor field effect transistor according to any one of claims 1 to 12, wherein, Before the step of forming a hard mask on a main surface of a wafer, the method further comprises: forming a pad oxide layer on the main surface of the wafer by a thermal oxidation process.

14. The method of manufacturing a lateral diffusion metal oxide semiconductor field effect transistor of claim 13, wherein, The step of forming a hard mask on a main surface of a wafer includes: depositing silicon nitride on the pad oxide layer as the hard mask.

15. A lateral diffused metal oxide semiconductor field effect transistor, wherein, is manufactured by the method of any one of claims 1-14.

Images