IGBT device and preparation method therefor

Abstract

Provided in the present invention are an IGBT device and a preparation method therefor. The IGBT device comprises a semiconductor layer, a base region, trench gate structures, an emitter region, a contact region, an interlayer dielectric layer, collector regions, a dielectric layer and electrodes, wherein the semiconductor layer comprises a cell region and a termination region; the trench gate structures are embedded in an upper surface layer of the semiconductor layer in the cell region; the base region is located on an upper surface layer of the cell region, and an edge of the base region extends to the termination region; the emitter region is located on an upper surface layer of the base region in the cell region; the contact region is located on the upper surface layer of the base region; the interlayer dielectric layer covers the upper surface of the semiconductor layer and the upper surfaces of the trench gate structures; the collector regions are arranged on a lower surface layer of the semiconductor layer at intervals; the dielectric layer covers the bottom face of the semiconductor layer and is provided with collector contact holes therein; and the electrodes are electrically connected to the corresponding regions, respectively. In the present invention, by means of providing the dielectric layer covering the bottom face of the semiconductor layer and electrically connecting collectors to the collector regions by means of the collector contact holes in the dielectric layer, the hole injection efficiency of the back face of a device is decreased, and the switching loss of the device is reduced.

Description

An IGBT device and its fabrication method Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to an IGBT device and its preparation method. Background Technology

[0002] The Insulated Gate Bipolar Transistor (IGBT) combines the voltage control of the Insulated Gate Field Effect Transistor (MOS) with the current modulation characteristics of the Bipolar Junction Transistor (BJT). As shown in Figure 1, which is a schematic cross-sectional view of the cell structure of a field-off IGBT device, it includes a semiconductor layer 01, a substrate 011, a drift region 012, a base region 013, a contact region 014, an emitter region 015, a collector region 016, a carrier storage layer 017, a trench gate structure 02, an interlayer dielectric layer 03, an emitter 04, and a collector 05. It features high input impedance, low switching loss, high speed, and low voltage drive power, and is widely used in many fields such as new energy vehicles, photovoltaic inverters, mobile energy storage, frequency converters, power transmission and transformation, high-speed train traction, industrial drives, and clean energy. The doping concentration of the back collector region of this device is usually very high, which gives the collector region a high hole concentration so that the electrons in the drift region can undergo conductivity modulation effect, resulting in a low forward conduction voltage drop. However, when the IGBT device is turned off, there is no electron injection due to the high hole concentration. It can only rely on emitter extraction and the disappearance of hole recombination in the drift region, which leads to current tailing and large turn-off loss, limiting the development of IGBTs to higher frequencies.

[0003] To address the aforementioned issues, transparent anode IGBTs have emerged. Figure 2 shows a cross-sectional view of the cell structure of a transparent anode IGBT device, including a semiconductor layer 01, substrate 011, drift region 012, base region 013, contact region 014, emitter region 015, collector region 016, carrier storage layer 017, doped layer 018, trench gate structure 02, interlayer dielectric layer 03, emitter 04, and collector 05. By adding a low-concentration P-type region to the back side, the overall P-type concentration on the back side is reduced, thereby lowering the hole emission efficiency, which helps reduce reverse current tailing and overall turn-off losses. However, the reduction in hole injection efficiency is limited, and the device still exhibits relatively high hole injection efficiency. Therefore, its switching losses remain relatively high, and the device reliability is relatively poor.

[0004] Therefore, there is an urgent need to find an IGBT device that can reduce hole injection efficiency and improve device reliability. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an IGBT device and its fabrication method to solve the problems of high hole injection efficiency and poor reliability of transparent anode IGBT devices in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides an IGBT device, comprising:

[0007] A first conductivity type semiconductor layer includes a cell region and a terminal region surrounding the cell region;

[0008] Multiple spaced trench gate structures are embedded in the upper surface of the semiconductor layer in the cell region;

[0009] A second conductivity type base region is located on the upper surface of the cell region and its edge extends to a predetermined distance from the upper surface of the terminal region. The bottom surface of the base region is higher than the bottom surface of the trench gate structure.

[0010] The first conductivity type emitter region is located on the upper surface of the base region in the cell region and is adjacent to the sidewall of the trench gate structure.

[0011] The second type of conductive contact area is located on the upper surface of the base region. The sidewall of the contact area located in the cell region is adjacent to the sidewall of the emitter region away from the trench gate structure. The bottom surface of the contact area is not higher than the bottom surface of the emitter region.

[0012] An interlayer dielectric layer covers the upper surface of the semiconductor layer and the trench gate structure;

[0013] An emitter penetrates the interlayer dielectric layer and is electrically connected to the emitter region and the contact region;

[0014] Multiple collector regions of the second conductivity type are spaced apart, and are located at least on the lower surface of the semiconductor layer in the cell region;

[0015] A dielectric layer covering the bottom surface of the semiconductor layer, wherein the dielectric layer has a collector contact hole penetrating the dielectric layer and exposing the collector region on its bottom surface; and

[0016] The collector and gate are provided, wherein the collector fills the collector contact hole and is electrically connected to the collector region, and the gate is electrically connected to the trench gate structure.

[0017] Optionally, the semiconductor layer includes a first conductivity type substrate and a first conductivity type drift region stacked sequentially, wherein the doping concentration of the drift region is less than the doping concentration of the substrate.

[0018] Optionally, a first conductivity type carrier storage layer is further provided below the base region, and the trench gate structure penetrates the carrier storage layer and extends its bottom surface into the semiconductor layer below the carrier storage layer.

[0019] Optionally, the lower surface layer of the semiconductor layer in the cell region is further provided with a second conductivity type doped layer, and the collector region penetrates at least through the doped layer.

[0020] Optionally, the doping concentration of the doped layer is lower than the doping concentration of the collector region.

[0021] Optionally, the lower surface layer of the semiconductor layer in the terminal region is provided with a plurality of spaced-apart collector regions that are electrically connected to the collector electrode.

[0022] Optionally, the collector region is located on the lower surface of the semiconductor layer in the region directly below the base region.

[0023] Optionally, a terminal structure is provided in the terminal region. The terminal structure includes a buffer trench structure, a first stop ring of the second conductivity type, a second stop ring of the first conductivity type, and a field plate. The buffer trench structure is located at the edge of the terminal region near the cell region and is spaced at a predetermined distance from the trench grid structure. The two side walls of the buffer trench structure along the arrangement direction of the trench grid structure are respectively adjacent to the side wall of the base region in the terminal region and the first stop ring adjacent to the cell region. A plurality of spaced first stop rings are located on the upper surface of the terminal region. The second stop rings are located at the edge of the terminal region away from the cell region. The field plate is at least electrically connected to the second stop ring.

[0024] Optionally, the upper surface of the first cutoff ring adjacent to the cell region in the terminal region is provided with a contact area electrically connected to the emitter; the first cutoff ring located between the first cutoff ring and the second cutoff ring adjacent to the cell region is electrically connected to the field plate.

[0025] Optionally, the buffer trench structure includes: a buffer trench, wherein the sidewall near the cell region is adjacent to the sidewall of the base region located in the terminal region, and the bottom surface of the buffer trench is lower than the bottom surface of the base region; an isolation dielectric layer covering the inner wall and bottom surface of the buffer trench; and a conductive filling layer filling the buffer trench.

[0026] Optionally, the trench gate structure includes: a gate trench embedded in the upper surface layer of the semiconductor layer; a gate conductive layer filling the gate trench; and a gate dielectric layer covering the bottom surface and inner wall of the gate trench, and enclosing the bottom surface and sidewall of the gate conductive layer.

[0027] Optionally, the interlayer dielectric layer is further provided with an emitter contact hole and a gate contact hole that penetrate the interlayer dielectric layer, the bottom of the emitter contact hole exposing the emitter region and the contact region, and the bottom surface of the gate contact hole exposing the gate conductive layer.

[0028] Optionally, the doping concentration of the base region is less than the doping concentration of the contact region.

[0029] Optionally, the first conductivity type includes either N-type or P-type, the second conductivity type includes either N-type or P-type, and the first conductivity type is the opposite of the second conductivity type.

[0030] This invention also provides a method for fabricating an IGBT device, comprising the following steps:

[0031] A first conductivity type semiconductor layer is provided, including a cell region and a terminal region surrounding the cell region. A plurality of spaced trench gate structures are formed in the cell region, and a second conductivity type base region is formed on the upper surface of the cell region. The bottom surface of the base region is higher than the bottom surface of the trench gate structure, and the edge of the base region extends to a predetermined distance on the upper surface of the terminal region.

[0032] A first conductivity type emission region is formed on the upper surface of the base region in the cell region, and the emission region is adjacent to the sidewall of the trench gate structure.

[0033] A second type of conductive contact area is formed on the upper surface of the base region. The sidewall of the contact area located in the cell region is adjacent to the sidewall of the emitter region away from the trench gate structure. The bottom surface of the contact area is not higher than the bottom surface of the emitter region.

[0034] An interlayer dielectric layer is formed covering the upper surface of the semiconductor layer and the trench gate structure;

[0035] An emitter is formed that penetrates the interlayer dielectric layer and is electrically connected to the emitter region and the contact region, and a gate is electrically connected to the trench gate structure.

[0036] A dielectric layer is formed covering the bottom surface of the semiconductor layer, wherein the dielectric layer has a plurality of spaced-apart collector contact holes that penetrate the dielectric layer; and

[0037] Using the dielectric layer as a mask, a second conductivity type collector region is formed on the lower surface of the semiconductor layer, forming a collector electrode that fills the collector electrode contact hole and is electrically connected to the collector region.

[0038] As described above, the IGBT device and its fabrication method of the present invention, by having collector regions spaced apart on the lower surface of the semiconductor layer, covering the lower surface of the semiconductor layer with a dielectric layer, forming collector contact holes in the dielectric layer, and using the dielectric layer after forming the collector contact holes as a mask to form collector regions, and finally forming a filler electrically connected to the collector regions, reduces the contact area between the collector and the second conductivity type region of the lower surface of the semiconductor layer, thereby reducing the area of ​​holes injected into the drift region from the back of the device, allowing holes to be injected into the drift region intermittently, significantly reducing the hole injection efficiency, improving the switching speed of the device, and reducing the turn-off loss of the device; by covering the bottom surface of the terminal region with a dielectric layer, so that the second conductivity type region of the lower surface of the semiconductor layer in the terminal region has no contact with the collector, the hole injection efficiency of the terminal region is reduced, thereby further reducing the total hole injection efficiency in the device, reducing hole accumulation in the terminal region and current accumulation at the emitter edge of the device, avoiding device failure due to overcurrent, improving the reliability of the device, and having high industrial application value. Attached Figure Description

[0039] Figure 1 shows a schematic cross-sectional view of the cell structure of a field-stop IGBT device.

[0040] Figure 2 shows a schematic cross-sectional view of the cell structure of a transparent anode IGBT device.

[0041] Figure 3 shows a cross-sectional structural diagram of the IGBT device of the present invention.

[0042] Figure 4 shows another cross-sectional view of the IGBT device of the present invention.

[0043] Figure 5 shows a cross-sectional structural diagram of a cell in the IGBT device of the present invention.

[0044] Figure 6 shows another cross-sectional view of the cell structure in the IGBT device of the present invention.

[0045] Figure 7 shows a schematic cross-sectional view of the semiconductor layer in the cell region of the IGBT device fabrication method of the present invention.

[0046] Figure 8 shows a schematic cross-sectional view of the cell structure in the cell region after the gate trench is formed in the fabrication method of the IGBT device of the present invention.

[0047] Figure 9 shows a schematic cross-sectional view of the cells in the slightly cellular region after the base region is formed in the fabrication method of the IGBT device of the present invention.

[0048] Figure 10 shows a schematic cross-sectional view of the cell structure in the cell region after the emitter is formed in the fabrication method of the IGBT device of the present invention.

[0049] Figure 11 shows a cross-sectional view of the IGBT device fabrication method of the present invention after the dielectric layer is formed in the cell region.

[0050] Reference numerals: 01 Semiconductor layer; 011 Substrate; 012 Drift region; 013 Base region; 014 Contact region; 015 Emitter region; 016 Collector region; 017 Carrier storage layer; 018 Doped layer; 02 Trench gate structure; 03 Interlayer dielectric layer; 04 Emitter; 05 Collector; 1 Semiconductor layer 11 Cell region; 12 Termination region; 121 Buffer trench structure; 122 First cutoff ring; 123 Second cutoff ring; 124 Field plate; 13 Substrate; 14 Drift region; 15 Base region; 151 Emitter region; 152 Contact region; 16 Collector region; 17 Carrier storage layer; 18 Doped layer; 2 Trench gate structure; 21 Trench; 22 Gate dielectric layer; 23 Gate conductive layer; 3 Interlayer dielectric layer; 4 Dielectric layer; 41 Collector contact hole; 5 Emitter; 6 Collector. Detailed Implementation

[0051] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] Please refer to Figures 3 to 11. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the figures only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0053] Example 1

[0054] This embodiment provides an IGBT device, as shown in Figures 3, 4, 5, and 6, which are respectively schematic diagrams of one cross-sectional structure, another cross-sectional structure, one cell structure, and another cell structure of the IGBT device. The device includes a first conductivity type semiconductor layer 1, a second conductivity type base region 15, a trench gate structure 2, a first conductivity type emitter region 151, a second conductivity type contact region 152, an interlayer dielectric layer 3, an emitter 5, a second conductivity type collector region 16, a dielectric layer 4, a collector electrode 6, and a gate (not shown). The semiconductor layer 1 includes a cell region 11 and a terminal region 12 surrounding the cell region 11. Multiple spaced trench gate structures 2 are embedded in the upper surface of the semiconductor layer 1 in the cell region 11. The base region 15 is located on the upper surface of the cell region 11 and its edge extends to a predetermined distance from the upper surface of the terminal region 12. The bottom surface of base region 15 is higher than the bottom surface of trench gate structure 2; emitter region 151 is located on the upper surface of base region 15 in cell region 11 and its sidewall near trench gate structure 2 is adjacent to the sidewall of trench gate structure 2; contact region 152 is located on the upper surface of base region 15, and the sidewall of contact region 152 in cell region 11 is adjacent to the sidewall of emitter region 151 away from trench gate structure 2, and the bottom surface of contact region 152 is not higher than the bottom surface of emitter region 151; interlayer dielectric layer 3 covers semiconductor layer 1 and trench gate structure 2. The upper surface of the trench gate structure 2; the emitter 5 penetrates the interlayer dielectric layer 3 and is electrically connected to the emitter region 151 and the contact region 152; multiple spaced collector regions 16 are located at least on the lower surface of the semiconductor layer 1 in the cell region 11; the dielectric layer 4 covers the bottom surface of the semiconductor layer 1, and the dielectric layer 4 has a collector contact hole 41 that penetrates the dielectric layer 4 and exposes the collector region 16 on the bottom surface; the collector 6 fills the collector contact hole 41 and is electrically connected to the collector region 16, and the gate is electrically connected to the trench gate structure 2.

[0055] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite in nature. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0056] As an example, the semiconductor layer 1 includes a first conductivity type substrate 13 and a first conductivity type drift region 14 stacked sequentially, wherein the doping concentration of the drift region 14 is less than the doping concentration of the substrate 13.

[0057] Specifically, substrate 13 serves as the electric field termination layer of the device. While ensuring device performance, the thickness, size, shape, and doping concentration of substrate 13 can be selected according to actual conditions and are not limited here. Similarly, the thickness, size, shape, and doping concentration of drift region 14 can be selected according to actual conditions and are not limited here. Here, thickness refers to the distance between the upper surface and the lower surface of substrate 13 (drift region 14).

[0058] Specifically, while ensuring device performance, the size and shape of the cell region 11 can be selected according to the actual situation, and are not restricted here; the size and shape of the terminal region 12 surrounding the cell region 11 can be selected according to the actual situation, and are not restricted here.

[0059] Specifically, the trench gate structure 2 includes a gate trench 21, a gate dielectric layer 22, and a gate conductive layer 23. The gate trench 21 is embedded in the upper surface layer of the semiconductor layer 1. The gate dielectric layer 22 covers the bottom surface and inner wall of the gate trench 21. The gate conductive layer 23 fills the gate trench 21. The gate dielectric layer 22 wraps the bottom surface and sidewall of the gate conductive layer 23.

[0060] Specifically, while ensuring device performance, the depth, opening size, and opening shape of the gate trench 21 can be selected according to actual conditions and are not limited here; the thickness of the gate dielectric layer 22 can be selected according to actual conditions and is not limited here. The depth here refers to the distance between the bottom surface of the gate trench 21 and the opening of the gate trench 21 (i.e., the upper surface of the semiconductor layer 1).

[0061] Specifically, the material of the gate dielectric layer 22 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0062] Specifically, base region 15 is used to form the conductive trench of the device. The doping concentration of base region 15 is less than that of contact region 152. While ensuring device performance, the thickness and doping concentration of base region 15 can be selected according to actual conditions, and are not limited here. The thickness here refers to the distance between the bottom surface of base region 15 and the top surface of base region 15 (i.e., the top surface of semiconductor layer 1).

[0063] Specifically, the contact type between the emitter region 151 and the emitter 5 is an ohmic contact. The emitter region 151 located between two adjacent trench gate structures 2 can be spaced at both ends of the base region 15 along the arrangement direction of the trench gate structure 2, or it can be located on the upper surface of the base region 15 between two adjacent trench gate structures 2.

[0064] Specifically, while ensuring device performance, the doping concentration, thickness, and size of the emitter region 151 can be selected according to actual conditions, and are not restricted here. The thickness here refers to the distance between the bottom surface of the emitter region 151 and the top surface of the emitter region 151 (i.e., the top surface of semiconductor layer 1).

[0065] Specifically, when the emission area 151 between two adjacent trench grid structures 2 is spaced at both ends of the base region 15 along the arrangement direction of the trench grid structures 2, the contact area 152 is located between the emission areas 151 between the two ends of the base region 15, and the sidewall of the contact area 152 along the arrangement direction of the trench grid structures 2 is adjacent to the sidewall of the emission area 151 away from the trench grid structures 2; when the emission area 151 is located on the upper surface of the entire base region 15 between two adjacent trench grid structures 2, the upper surface of the contact area 152 is flush with the lower surface of the emission area 151.

[0066] Specifically, while ensuring device performance, the distance between the bottom surface of the contact area 152 and the bottom surface of the emitter area 151, as well as the doping concentration of the contact area 152, can be selected according to actual conditions and are not restricted here; the size and shape of the contact area 152 can be selected according to actual conditions and are not restricted here.

[0067] As an example, a first conductivity type carrier storage layer 17 is also provided below the base region 15, and the trench gate structure 2 penetrates the carrier storage layer 17 and extends its bottom surface into the semiconductor layer 1 below the carrier storage layer 17.

[0068] Specifically, the base region 15 and the carrier storage layer 17 are stacked. The carrier storage layer 17 is used to prevent holes in the drift region 14 from entering the base region 15, so as to increase the hole concentration near the emitter and reduce the on-state voltage drop of the device.

[0069] Specifically, the doping concentration of the carrier storage layer 17 is greater than that of the drift region 14. While ensuring device performance, the thickness and doping concentration of the carrier storage layer 17 can be selected according to actual conditions, and are not limited here. The thickness here refers to the distance between the upper and lower surfaces of the carrier storage layer 17.

[0070] Specifically, the material of the interlayer dielectric layer 3 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0071] Specifically, the interlayer dielectric layer 3 is also provided with an emitter contact hole and a gate contact hole that penetrate the interlayer dielectric layer 3. The bottom of the emitter contact hole exposes the emitter region 151 and the contact region 152, and the bottom surface of the gate contact hole exposes the gate conductive layer 23.

[0072] Specifically, while ensuring device performance, the opening size and shape of the emitter contact hole can be selected according to the actual situation and are not restricted here; the opening size and shape of the gate contact hole can be selected according to the actual situation and are not restricted here; the distance between the emitter contact hole and the gate contact hole can be selected according to the actual situation and is not restricted here.

[0073] Specifically, the gate contact hole can penetrate only the interlayer dielectric layer 3, or it can penetrate the interlayer dielectric layer 3 while extending its bottom surface into the gate conductive layer 23; the emitter contact hole can penetrate only the interlayer dielectric layer 3, or it can extend its bottom surface into the semiconductor layer 1. That is, during the formation of the emitter contact hole, the semiconductor layer 1 covered by the interlayer dielectric layer 3 is etched, and when the bottom surface of the emitter contact hole extends into the semiconductor layer 1, the bottom surface of the emitter contact hole is not lower than the bottom surface of the emitter region 151.

[0074] Specifically, the emitter 5 fills the emitter contact hole and forms an ohmic contact with the emitter region 151 and contact region 152 exposed at the bottom of the emitter contact hole. The gate fills the gate contact hole to form an electrical connection with the gate conductive layer 23. While filling the emitter contact hole, the emitter 5 can also cover a part of the upper surface of the interlayer dielectric layer 3 to facilitate the lead-out of the emitter 5. While filling the gate contact hole, the gate can also cover a part of the upper surface of the interlayer dielectric layer 3 to facilitate the lead-out of the gate.

[0075] Specifically, the material of the emitter 5 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials; the material of the gate includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials.

[0076] As an example, the lower surface layer of the semiconductor layer 1 in the cell region 11 is further provided with a second conductivity type doped layer 18, and the collector region 16 penetrates at least through the doped layer 18.

[0077] As an example, the doping concentration of the doped layer 18 is lower than that of the collector region 16.

[0078] Specifically, the doped layer 18 is used to recombine excess electrons in the drift region 14 when the device is off, so that the electron lifetime in the layer is low, reducing the reverse current tail of the device and thus reducing the turn-off loss of the device. When the device is on, holes are injected into the drift region 14 to reduce the on-state voltage drop of the device.

[0079] Specifically, while ensuring device performance, the thickness and doping concentration of the doped layer 18 can be selected according to actual needs, and are not restricted here.

[0080] Specifically, the collector region 16 is used to inject holes into the drift region 14 when the device is turned on, and the contact type between the collector region 16 and the collector electrode 6 is an ohmic contact. Under the premise of ensuring device performance, the number, doping concentration, shape and thickness of the collector regions 16 can be selected according to the actual situation, and are not restricted here; the distance between two adjacent collector regions 16 can be selected according to the actual situation, and are not restricted here.

[0081] As an example, the lower surface layer of the semiconductor layer 1 in the terminal region 12 is provided with a plurality of spaced-apart collector regions 16 that are electrically connected to the collector electrode 6, that is, the lower surface layer of the substrate 13 in the terminal region 12 is also provided with collector regions 16.

[0082] As an example, the collector region 16 is located on the lower surface of the semiconductor layer 1 in the region directly below the base region 15. That is, the collector region 16 in the terminal region 12 is only located in the region directly below the base region 15, which can further reduce the hole injection efficiency on the back side of the device, reduce the switching loss of the device, and improve the reliability of the device.

[0083] Specifically, while ensuring device performance, the lower surface layer of semiconductor layer 1 in terminal region 12 may not have a collector region 16.

[0084] Specifically, the dielectric layer 4 is used to block the electrical contact between the doped layer 18 and the collector 6, so that the collector 6 only contacts the collector region 16, reducing the contact area between the collector 6 and the second conductivity type region on the bottom surface of the semiconductor layer 1. This allows only the very small collector region 16 in the device to inject holes into the drift region 14, reducing the hole injection efficiency from the second conductivity type region on the back side of the device into the drift region 14, thereby reducing the turn-off loss of the device.

[0085] Specifically, while ensuring device performance, the thickness of dielectric layer 4 can be selected according to actual conditions and is not limited here; the opening size and opening shape of collector contact hole 41 can be selected according to actual conditions and are not limited here; collector contact hole 41 can only penetrate dielectric layer 4, or it can extend from the bottom surface into collector region 16.

[0086] Specifically, the material of dielectric layer 4 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0087] Specifically, the dielectric layer 4 covers the lower surface of the semiconductor layer 1 in the terminal region 12. When the lower surface of the semiconductor layer 1 in the terminal region 12 is provided with a collector region 16, the dielectric layer 4 below the semiconductor layer 1 in the terminal region 12 is also provided with a collector contact hole 41 that exposes the collector region 16. The number of collector regions 16 in the terminal region 12 can be selected according to the actual situation.

[0088] As an example, a terminal structure is provided in the terminal region 12. The terminal structure includes a buffer trench structure 121, a first cut-off ring 122 of the second conductivity type, a second cut-off ring 123 of the first conductivity type, and a field plate 124. The buffer trench structure 121 is located at the edge of the terminal region 12 near the cell region 11 and is spaced apart from the trench grid structure 2 by a predetermined distance. The two side walls of the buffer trench structure 121 along the arrangement direction of the trench grid structure 2 are respectively adjacent to the side wall of the base region 15 in the terminal region 12 and the first cut-off ring 122 of the adjacent cell region 11. A plurality of spaced first cut-off rings 122 are located on the upper surface of the terminal region 12. The second cut-off ring 123 is located at the edge of the terminal region 12 away from the cell region 11. The field plate 124 is electrically connected to at least the second cut-off ring 123.

[0089] Specifically, the buffer trench structure 121 includes a buffer trench, an isolation dielectric layer, and a filling conductive layer. The sidewall of the buffer trench near the cell region 11 is adjacent to the sidewall of the base region 15 located in the terminal region 12. The isolation dielectric layer covers the inner wall and bottom surface of the buffer trench. The filling conductive layer fills the buffer trench, and the bottom surface of the buffer trench is lower than the bottom surface of the base region. When a carrier storage layer 17 is provided in the device, the bottom surface of the buffer trench is lower than the bottom surface of the carrier storage layer 17.

[0090] Specifically, while ensuring device performance, the depth, opening size, and opening shape of the buffer trench can be selected according to actual conditions and are not limited here; the thickness of the isolation dielectric layer can be selected according to actual conditions and is not limited here. In this embodiment, the depth of the buffer trench is the same as the depth of the gate trench.

[0091] Specifically, the material of the isolation dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; the material of the filling conductive layer includes polysilicon or other suitable conductive materials. In this embodiment, the isolation dielectric layer and the gate dielectric layer are made of the same material, and the gate conductive layer and the filling conductive layer are made of the same material, both of which are polysilicon.

[0092] Specifically, the upper surface of the base region 15 between the buffer trench structure 121 and the trench grid structure 2 is also provided with a contact area 152 that is electrically connected to the emitter 5, and the emitter is electrically connected to the contact area 152 through the emitter contact hole.

[0093] As an example, a contact area 152 electrically connected to the emitter 5 is formed on the upper surface of the first cutoff ring 122 adjacent to the cell region 11 in the terminal region 12. The contact area 152 forms an ohmic contact area with the emitter 5 so that the first cutoff ring 122 is electrically connected to the emitter 5.

[0094] Specifically, the bottom surface of the first stop ring 122 is lower than the bottom surface of the buffer trench structure 121.

[0095] As an example, the first stop ring 122 located between the first stop ring 122 and the second stop ring 123 in the adjacent cell region 11 is electrically connected to the field plate 25. That is, the interlayer dielectric layer 3 covering the terminal region 12 is provided with a field plate contact hole that penetrates the interlayer dielectric layer 3. The bottom surface of the field plate contact hole exposes the first stop ring 122 between the first stop ring 122 and the second stop ring 123. The field plate 124 fills the field plate contact hole and covers part of the upper surface of the interlayer dielectric layer 3 to reduce the peak value of the tip electric field of the terminal region 12 in the device.

[0096] Specifically, the doping concentration of the second field stop ring 124 is greater than that of the first field stop ring 123, and the bottom surface of the second field stop ring 124 is higher than the bottom surface of the first field stop ring 123.

[0097] Specifically, while ensuring device performance, the number of first field cutoff rings 123 in the termination area 12 can be selected according to actual conditions, and is not limited here; the size of the first field cutoff ring 123 can be selected according to actual conditions, and is not limited here; the size of the second field cutoff ring 124 can be selected according to actual conditions, and is not limited here.

[0098] Specifically, while ensuring device performance, the number, size, and shape of the field plate 124 located above the region between the first cutoff ring 122 and the second cutoff ring 123 in the neighboring cell region 11 can be selected according to actual conditions and are not restricted here; the size and shape of the field plate 124 electrically connected to the second field cutoff ring 124 can be selected according to actual conditions and are not restricted here.

[0099] Specifically, the material of the field plate 124 includes polycrystalline silicon, titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials. In this embodiment, a polycrystalline silicon layer is used as the field plate 124.

[0100] Specifically, the material of collector 6 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials.

[0101] Specifically, by spaced-apart collector regions 16 on the lower surface of semiconductor layer 1 in cell region 11, and dielectric layer 4 covering the bottom surface of semiconductor layer 1, collector 6 contacts collector regions 16 through collector contact hole 41, avoiding contact between collector 6 and doped layer 18 or substrate 13 on the lower surface of semiconductor layer 1. This reduces the area of ​​holes injected from the back of the device into drift region 14 and allows holes to be injected into drift region 14 intermittently, significantly reducing the efficiency of hole injection from the back of the device into drift region 14, thereby reducing device turn-off loss, improving device switching speed, and enhancing device reliability.

[0102] Specifically, by covering the bottom surface of the terminal region 12 of the device with dielectric layer 4 and making the terminal region 12 non-contact with the collector 6, the hole injection efficiency of the terminal region 12 can be reduced, the hole accumulation in the terminal region 12 area and the current accumulation at the emitter 5 at the edge of the device can be reduced, and the device can be prevented from failing due to overcurrent, thereby further improving the reliability of the product.

[0103] The IGBT device in this embodiment improves the device structure by spaced collector regions 16 on the lower surface of semiconductor layer 1 in cell region 11 and covering the lower surface of semiconductor layer 1 with dielectric layer 4. The collector 6 is electrically connected to collector region 16 through collector contact hole. By reducing the area of ​​collector region 16 and the contact area between collector 6 and collector region 16, the area for injecting holes from the back of the device into drift region 14 is reduced, and the holes are injected into drift region 14 intermittently, which significantly reduces the efficiency of hole injection from the back of the device into drift region 14, improves the switching speed of the device, and reduces the turn-off loss of the device. By covering the bottom surface of terminal region 12 of the device with dielectric layer 4, the second conductivity type region of the lower surface of semiconductor layer 1 in terminal region 12 is not in contact with collector 6, which reduces the hole injection efficiency of terminal region 12, reduces hole accumulation in terminal region 12 and current accumulation at the emitter 5 at the edge of the device, avoids device failure due to overcurrent, and improves the reliability and performance of the device.

[0104] Example 2

[0105] This embodiment provides a method for fabricating an IGBT device, including the following steps:

[0106] S1: A first conductivity type semiconductor layer is provided, including a cell region and a terminal region surrounding the cell region, a plurality of trench gate structures are formed in the cell region, and a second conductivity type base region is formed on the upper surface of the cell region, the bottom surface of the base region is higher than the bottom surface of the trench gate structure, and the edge of the base region extends to a predetermined distance on the upper surface of the terminal region.

[0107] S2: A first conductivity type emission region is formed on the upper surface of the base region in the cell region, and the emission region is adjacent to the sidewall of the trench gate structure.

[0108] S3: A second type of conductive contact area is formed on the upper surface of the base region. The sidewall of the contact area located in the cell region is adjacent to the sidewall of the emitter region away from the trench gate structure. The bottom surface of the contact area is not higher than the bottom surface of the emitter region.

[0109] S4: Form an interlayer dielectric layer covering the upper surface of the semiconductor layer and the trench gate structure;

[0110] S5: Form an emitter that penetrates the interlayer dielectric layer and is electrically connected to the emitter region and the contact region, and a gate that is electrically connected to the trench gate structure;

[0111] S6: Form a dielectric layer covering the bottom surface of the semiconductor layer, wherein the dielectric layer has a plurality of spaced-apart collector contact holes that penetrate the dielectric layer;

[0112] S7: Using the dielectric layer as a mask, a second conductivity type collector region is formed on the lower surface of the semiconductor layer, forming a collector electrode that fills the collector electrode contact hole and is electrically connected to the collector region.

[0113] Please refer to Figures 7 to 9, and perform steps S1 and S2: Provide a first conductivity type semiconductor layer 1 including a cell region 11 and a terminal region 12 surrounding the cell region 12; form a plurality of spaced trench gate structures 2 in the cell region 1; and form a second conductivity type base region 15 on the upper surface of the cell region 11, with the bottom surface of the base region 15 higher than the bottom surface of the trench gate structure 2, and the edge of the base region 15 extending to a predetermined distance on the upper surface of the terminal region 12; form a first conductivity type emitter region 151 on the upper surface of the base region 15 in the cell region 11, with the emitter region 151 adjacent to the sidewall of the trench gate structure 2; and form a first conductivity type emitter region 151 on the upper surface of the base region 15 in the cell region 11, with the emitter region adjacent to the sidewall of the trench gate structure 2.

[0114] Specifically, cell region 11 is used to form the cell structure of IGBT device, and terminal region 12 is used to form the terminal structure of IGBT device.

[0115] Specifically, as shown in Figure 7, which is a cross-sectional structural diagram of semiconductor layer 1 in cell region 11, semiconductor layer 1 includes a first conductivity type substrate 13 and a first conductivity type drift region 14 stacked sequentially. The doping concentration of drift region 14 is less than that of substrate 13.

[0116] Specifically, before forming the trench gate structure 2, the process includes step 17 of forming a first conductivity type carrier storage layer on the upper surface of the drift region 14.

[0117] Specifically, the doping concentration of the carrier storage layer 17 is greater than that of the drift region 14, and the method for forming the carrier storage layer 17 includes ion implantation or other suitable methods. In this embodiment, the upper surface layer of the drift region 14 is heavily doped with a first conductivity type by ion implantation, and then a push junction is formed to obtain a carrier storage layer 17 of a predetermined thickness.

[0118] Specifically, the sidewall of the carrier storage layer 17 extends into the terminal region 12, and the sidewall of the carrier storage layer 17 is spaced at a preset distance from the cell region 11. While ensuring device performance, the distance between the sidewall of the carrier storage layer 17 and the cell region 11 can be selected according to the actual situation, and is not limited here.

[0119] Specifically, as shown in Figure 8, which is a cross-sectional view of the cell structure in the cell region 11 after the formation of the gate trench 21, the formation of the trench gate structure 2 includes the following steps: forming a patterned first masking layer on the upper surface of the semiconducting layer 1; forming a gate trench 21 based on the patterned first masking layer; sequentially forming a gate dielectric material layer covering the inner wall and bottom surface of the gate trench 21 and a gate conductive material layer filling the gate trench 21, wherein the gate dielectric material layer also covers the exposed upper surface of the semiconductor layer 1 and the gate conductive material layer also covers the upper surface of the gate dielectric material layer; removing the gate conductive material layer above the semiconductor layer 1, and using the gate dielectric material layer covering the inner wall and bottom surface of the gate trench 21 as the gate dielectric layer 22, and the gate conductive material layer in the gate trench 21 as the gate conductive layer 23.

[0120] Specifically, the method for forming the patterned first masking layer is the commonly used photoresist coating, drying, exposure, and development process, which will not be elaborated here.

[0121] Specifically, the method for forming the gate trench 21 based on the patterned first masking layer includes dry etching, wet etching, or other suitable methods.

[0122] Specifically, after forming the gate trench 21 and before forming the gate dielectric material layer, the process also includes a step of removing the first masking layer. The method for removing the first masking layer is the commonly used photoresist layer stripping method, which will not be described in detail here.

[0123] Specifically, methods for forming the gate dielectric material layer include chemical vapor deposition, physical vapor deposition, thermal oxidation, or other suitable methods; methods for forming the gate conductive material layer include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0124] Specifically, the gate conductive material layer above semiconductor layer 1 can be removed simultaneously with the gate dielectric material layer covering the exposed upper surface of semiconductor layer 1, or the gate dielectric material layer covering the exposed upper surface of semiconductor layer 1 can be retained. Methods for removing the gate conductive material layer above semiconductor layer 1 include dry etching, wet etching, chemical mechanical polishing, or other suitable methods. For example, the process for removing the gate conductive material layer can be a dry etching process, a wet etching process, or a chemical mechanical polishing process, or a combination of two or three of these processes.

[0125] Specifically, when a carrier storage layer 17 is formed in the drift region 14, the gate trench 21 penetrates the carrier storage layer 17 and extends its bottom surface into the drift region 14 below the carrier storage layer 17, and the bottom surface of the gate trench 21 is spaced apart from the bottom surface of the drift region 14 by a predetermined distance.

[0126] Specifically, as shown in Figure 9, which is a schematic cross-sectional view of the cell structure in the cell region 11 after the base region 15 is formed, the base region 15 is formed on the upper surface of the carrier storage layer 17, and the method for forming the base region 15 includes ion implantation or other suitable methods.

[0127] Specifically, while ensuring device performance, the distance between the base region 15 extending to the sidewall of the terminal region 12 and the cell region 11 can be selected according to the actual situation, and is not restricted here.

[0128] Specifically, the emission region 151 is located on the upper surface of the base region 15 between two adjacent trench gate structures 2. The emission region 151 located on the upper surface of the base region 15 between two adjacent trench gate structures 2 can be spaced apart at both ends of the base region 15 near the trench gate structure 2, or it can be located entirely on the upper surface of the base region 15. The method of forming the emission region 151 includes ion implantation or other suitable methods.

[0129] Referring again to Figure 10, steps S3, S4, and S5 are performed: a second conductivity type contact region 152 is formed on the upper surface of the base region 15. The sidewall of the contact region 152 located in the cell region 11 is adjacent to the sidewall of the emitter region 151 away from the trench gate structure 2. The bottom surface of the contact region 152 is not higher than the bottom surface of the emitter region 151. An interlayer dielectric layer 3 is formed covering the upper surface of the semiconductor layer 1 and the trench gate structure 2. An emitter 5 and a gate electrically connected to the trench gate structure 2 are formed, penetrating the interlayer dielectric layer 3 and electrically connected to the emitter region 151 and the contact region 152.

[0130] Specifically, the contact area 152 is formed before the interlayer dielectric layer 3 is formed, and it is located between the two emitter areas 151 between two adjacent trench gate structures 2 and adjacent to the sidewall of the emitter area 15. Alternatively, it can be formed after the interlayer dielectric layer 3 is formed and before the emitter 5 is formed.

[0131] Specifically, the contact type between the contact region 152 and the emitter 5 is an ohmic contact, and the method for forming the contact region 152 includes ion implantation or other suitable methods.

[0132] Specifically, the methods for forming the interlayer medium layer 3 include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0133] Specifically, while ensuring device performance, the thickness of the interlayer dielectric layer 3 can be selected according to the actual situation, and is not restricted here.

[0134] Specifically, after forming the interlayer dielectric layer 3 and before forming the emitter 5, the process also includes forming an emitter contact hole and a gate contact hole in the interlayer dielectric layer 3. The emitter contact hole penetrates the interlayer dielectric layer 3 and exposes the emitter region 151 and the contact region 152 at the bottom. The gate contact hole penetrates the interlayer dielectric layer 3 and exposes the gate conductive layer 23 at the bottom.

[0135] Specifically, the emitter contact hole and the gate contact hole can be formed simultaneously or in stages. The methods for forming the emitter contact hole include dry etching, wet etching, or other suitable methods; the methods for forming the gate contact hole include dry etching, wet etching, or other suitable methods.

[0136] Specifically, the emitter 5 fills the emitter contact hole and forms an ohmic contact with the emitter region 151 and the contact region 152 exposed through the bottom of the emitter contact hole, respectively. The gate fills the gate contact hole and is electrically connected to the gate conductive layer 23.

[0137] Specifically, as shown in Figure 10, which is a schematic cross-sectional view of the cell structure in the cell region 11 after the emitter 5 is formed, the method for forming the emitter 5 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; the method for forming the gate includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0138] Specifically, the emitter 5 and the gate can be formed simultaneously or in stages. In this embodiment, a metal layer that fills the emitter contact hole and the gate contact hole and covers the upper surface of the interlayer dielectric layer 3 is formed simultaneously first, and then the metal layer on the upper surface of the interlayer dielectric layer 3 is etched to obtain the gate and emitter 5 simultaneously.

[0139] Please refer to Figure 11 and perform steps S6 and S7: form a dielectric layer 4 covering the bottom surface of the semiconductor layer 1, and provide a plurality of collector contact holes 41 spaced apart and penetrating the dielectric layer 4; use the dielectric layer 4 as a mask to form a second conductivity type collector region 16 located on the lower surface of the semiconductor layer 1, and form a collector 6 that fills the collector contact holes 41 and is electrically connected to the collector region 16.

[0140] Specifically, after forming the emitter 5 and the gate, and before forming the dielectric layer 4, the process also includes forming a second conductivity type doped layer 18 on the lower surface of the substrate 13 in the cell region 11.

[0141] Specifically, methods for forming the doped layer 18 include ion implantation or other suitable methods.

[0142] Specifically, the doped layer 18 is used to accelerate the recombination of carriers stored in the drift region 14 when the device is turned off, reduce the reverse tail current of the device, and inject holes into the drift region 14 when the device is forward-biased. Under the condition of ensuring device performance, the lower surface layer of the substrate 13 may or may not have a doped layer 18.

[0143] Specifically, when a doped layer 18 is formed on the lower surface of the substrate 13, a dielectric layer 4 covers the lower surface of the doped layer 18. The method for forming the dielectric layer 4 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0144] Specifically, as shown in Figure 11, which is a cross-sectional view of the cell structure in the cell region 11 after the dielectric layer 4 is formed, the formation of the collector region 16 includes the following steps: forming a patterned second masking layer on the side of the dielectric layer 4 facing away from the semiconductor layer 1; forming a collector contact hole 41 penetrating the dielectric layer 4 based on the patterned second masking layer, with the bottom surface of the collector contact hole 41 exposing the substrate 13; and forming the collector region 16 located on the lower surface of the substrate 13 using the dielectric layer 4 after the collector contact hole 41 is formed as a mask layer.

[0145] Specifically, the method for forming the patterned second masking layer is the commonly used photoresist coating, drying, exposure, and development process, which will not be elaborated here.

[0146] Specifically, the method for forming the collector contact hole 41 based on the patterned second masking layer includes dry etching, wet etching, or other suitable methods.

[0147] Specifically, after forming the collector contact hole 41 and before forming the collector region 16, there is also a step of removing the second masking layer. The method for removing the second masking layer is the commonly used photoresist stripping method, which will not be described in detail here.

[0148] Specifically, the methods for forming the current collector region 16 include ion implantation or other suitable methods.

[0149] Specifically, when a doped layer 18 is formed on the lower surface of substrate 13, the doping concentration of collector region 16 is greater than the doping concentration of doped layer 18.

[0150] Specifically, the contact type between the collector 6 and the collector region 16 is an ohmic contact, and the method for forming the collector 6 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0151] Specifically, a terminal structure is also formed in the terminal region 12. The terminal structure includes a buffer trench structure 121, a first cutoff ring 122 of the second conductivity type, a second cutoff ring 123 of the first conductivity type, and a field plate 124. The buffer trench structure 121 is located at the edge of the terminal region 12 near the cell region 11 and is spaced apart from the trench grid structure 2 by a predetermined distance. The two side walls of the buffer trench structure 121 along the arrangement direction of the trench grid structure 2 are respectively adjacent to the side wall of the base region 15 in the terminal region 12 and the first cutoff ring 122 of the adjacent cell region 11. A plurality of spaced first cutoff rings 122 are located on the upper surface of the terminal region 12. The second cutoff ring 123 is located at the edge of the terminal region 12 away from the cell region 11. The field plate 124 is electrically connected to at least the second cutoff ring 123.

[0152] Specifically, the buffer trench structure 121 includes a buffer trench, an isolation dielectric layer, and a filling conductive layer. The sidewall of the buffer trench near the cell region 11 is adjacent to the sidewall of the base region 15 located in the terminal region 12. The isolation dielectric layer covers the inner wall and bottom surface of the buffer trench. The filling conductive layer fills the buffer trench, and the bottom surface of the buffer trench is lower than the bottom surface of the base region. When a carrier storage layer 17 is provided in the device, the bottom surface of the buffer trench is lower than the bottom surface of the carrier storage layer 17.

[0153] Specifically, the buffer trench structure 121 can be formed simultaneously with the trench gate structure 2, or it can be formed stepwise with the trench gate structure 2. When the buffer trench structure 121 is formed simultaneously with the trench gate structure 2, the buffer trench, the isolation dielectric layer and the filling conductive layer are formed simultaneously with the gate trench 21, the gate dielectric layer 22 and the gate conductive layer 23, respectively.

[0154] Specifically, a contact area 152 electrically connected to the emitter 5 is formed on the upper surface of the base region 15 between the buffer trench structure 121 and the trench gate structure 2, and on the upper surface of the first stop ring 122 adjacent to the cell region 11 in the terminal region 12. The contact area 152 and the contact area 152 in the cell region 11 are formed synchronously and form an ohmic contact area with the emitter 5, so that the first stop ring 122 is electrically connected to the emitter 5.

[0155] Specifically, the bottom surface of the first cutoff ring 122 is lower than the bottom surface of the buffer trench structure 121, the doping concentration of the first cutoff ring 122 is less than the doping concentration of the contact region 152, and the field plate 124 can be electrically connected to the first cutoff ring 122 located between the first cutoff ring 122 and the second cutoff ring 123 in the neighboring cell region 11, or it can be not electrically connected to the first cutoff ring 122.

[0156] Specifically, the doping concentration of the second stop ring 123 is greater than the doping concentration of the drift region 14. The formation of the field plate 124 includes the following steps: forming a patterned third shielding layer on the upper surface of the interlayer dielectric layer 3 above the terminal region 12; forming a field plate contact hole penetrating the interlayer dielectric layer 3 based on the patterned third shielding layer, with at least the bottom surface of the field plate contact hole exposing the second stop ring 123; forming a field plate material layer that fills the field plate contact hole and covers the upper surface of the interlayer dielectric layer 3, and etching the field plate material layer to obtain the field plate.

[0157] Specifically, the method for forming the patterned third masking layer is the commonly used photoresist coating, drying, exposure, and development process, which will not be elaborated here.

[0158] Specifically, methods for forming field plate contact holes based on a patterned third masking layer include dry etching, wet etching, or other suitable methods.

[0159] Specifically, when the first cut-off ring 122 is electrically connected to the field plate 124, the field plate contact hole penetrates the interlayer dielectric layer 3 above the first cut-off ring 122 that needs to be electrically connected to the field plate 124, and the bottom surface of the first cut-off ring 122 is exposed.

[0160] Specifically, after forming the field plate contact hole and before forming the field plate material layer, the process also includes removing the third masking layer on the upper surface of the interlayer dielectric layer 3. The method for removing the third masking layer is the commonly used photoresist stripping method, which will not be described in detail here.

[0161] Specifically, methods for forming the field plate material layer include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0162] Specifically, methods for etching the field plate material layer include dry etching, wet etching, or other suitable methods.

[0163] Specifically, when a doped layer 18 is formed in the device, the doped layer 18 can also extend to the lower surface of the substrate 13 in the terminal region 12, that is, the doped layer 18 is located on the lower surface of the entire semiconductor layer 1.

[0164] Specifically, the collector region 16 may be located only on the lower surface of the semiconductor layer 1 below the area surrounding the first stop ring 122 of the cell region 11, or it may be located on the entire lower surface of the semiconductor layer 1.

[0165] Specifically, by forming a dielectric layer 4 covering the lower surface of the semiconductor layer 1 and forming a collector contact hole 41 in the dielectric layer 4, and then using the dielectric layer 4 forming the collector contact hole 41 as a mask to form a collector region 16 located on the lower surface of the semiconductor layer 1, the collector 6 is electrically contacted only with the collector region 16 exposed on the bottom surface of the collector contact hole 41 through the isolation of the dielectric layer 4, thereby reducing the contact area between the collector 6 and the lower surface of the semiconductor layer 1 and allowing holes to be injected into the drift region intermittently, which greatly reduces the efficiency of injecting holes into the drift region 14 from the back side of the device.

[0166] Specifically, by reducing the contact area between the collector 6 and the lower surface of the semiconductor layer 1, the tail current of the device is reduced, the switching speed of the device is improved, and the switching loss of the device is reduced.

[0167] The IGBT device fabrication method of this embodiment improves the device fabrication process by forming a dielectric layer 4 covering the lower surface of the semiconductor layer 1, and forming a collector contact hole 41 penetrating the dielectric layer 4. Then, the collector region 16 is formed using the dielectric layer 4 as a mask, so that the collector 6 only makes electrical contact with the collector region 16 exposed on the bottom surface of the collector contact hole 41. This reduces the contact area between the collector 6 and the lower surface of the semiconductor layer 1, and allows holes to be injected into the drift region 14 intermittently. This significantly reduces the efficiency of hole injection from the back of the device into the drift region 14, improves the switching speed of the device, and reduces the switching loss of the device.

[0168] In summary, the IGBT device and its fabrication method of the present invention improve the device structure by spaced-out collector regions on the lower surface of the semiconductor layer and covering the lower surface of the semiconductor layer with a dielectric layer. The collector is then electrically connected to the collector regions through collector contact holes. This reduces the contact area between the collector and the second conductivity type region of the lower surface of the semiconductor layer, thereby reducing the area for hole injection from the back of the device into the drift region. Furthermore, the intermittent injection of holes into the drift region reduces the efficiency of hole injection from the back of the device into the drift region, improving the switching speed and reducing turn-off losses. By covering the bottom surface of the terminal region with a dielectric layer, the second conductivity type region of the lower surface of the semiconductor layer in the terminal region is not in contact with the collector, reducing the hole injection efficiency in the terminal region. This further reduces the overall hole injection efficiency in the device, decreasing hole accumulation in the terminal region and current accumulation at the device's edge emitter, thus improving the device's reliability and performance. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0169] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An IGBT device, characterized by, The semiconductor device comprises: a first conductive type semiconductor layer, including a cell region and a termination region surrounding the cell region; a plurality of spaced trench gate structures embedded in the upper layer of the semiconductor layer in the cell region; a second conductive type base region located in the upper layer of the cell region and extending to a preset distance of the upper layer of the termination region, the bottom surface of the base region being higher than the bottom surface of the trench gate structure; a first conductive type emitter region located in the upper layer of the base region in the cell region and abutting the side wall of the trench gate structure; a second conductive type contact region located in the upper layer of the base region and abutting the side wall of the emitter region away from the side wall of the trench gate structure in the cell region, the bottom surface of the contact region being not higher than the bottom surface of the emitter region; an interlayer dielectric layer covering the upper surfaces of the semiconductor layer and the trench gate structure; an emitter penetrating the interlayer dielectric layer and electrically connected with the emitter region and the contact region; a plurality of spaced second conductive type collector regions located in the lower layer of the semiconductor layer in the cell region; a dielectric layer covering the bottom surface of the semiconductor layer, the dielectric layer being provided with a collector contact hole penetrating the dielectric layer and exposing the collector region at the bottom surface; and a collector and a gate, the collector filling the collector contact hole and electrically connected with the collector region, the gate being electrically connected with the trench gate structure. The semiconductor layer comprises a first conductive type substrate and a first conductive type drift region stacked in sequence, the doping concentration of the drift region being less than the doping concentration of the substrate.

2. The IGBT device of claim 1, wherein: The base region is further provided with a first conductive type carrier storage layer, the trench gate structure penetrating the carrier storage layer and extending to the semiconductor layer below the carrier storage layer at the bottom surface.

3. The IGBT device of claim 1, wherein: The lower layer of the semiconductor layer in the cell region is further provided with a second conductive type doping layer, the collector region penetrating at least the doping layer.

4. The IGBT device of claim 1, wherein: The doping concentration of the doping layer is lower than the doping concentration of the collector region.

5. The IGBT device of claim 4, wherein: The lower layer of the semiconductor layer in the termination region is provided with a plurality of spaced collector regions electrically connected with the collector.

6. The IGBT device of claim 1, wherein: The collector region is located in the lower layer of the semiconductor layer in the region directly below the base region.

7. The IGBT device of claim 1, wherein: The termination region is provided with a termination structure, the termination structure comprising a buffer trench structure, a second conductive type first cutoff ring, a first conductive type second cutoff ring and a field plate, the buffer trench structure being located in the edge of the termination region close to the cell region and spaced a preset distance from the trench gate structure, the two side walls of the buffer trench structure along the arrangement direction of the trench gate structure abutting the side wall of the base region in the termination region and the first cutoff ring adjacent to the cell region, respectively, a plurality of spaced first cutoff rings being located in the upper layer of the termination region, the second cutoff ring being located in the edge of the termination region away from the cell region, and the field plate being electrically connected with at least the second cutoff ring.

8. The IGBT device of claim 1, wherein: ​ 9. The IGBT device of claim 8, wherein: An upper surface of the first termination ring adjacent to the cell region in the terminal region is provided with a contact region electrically connected to the emitter; the first termination ring between the first termination ring adjacent to the cell region and the second termination ring is electrically connected to the field plate.

10. The IGBT device of claim 8, wherein: The buffer trench structure comprises: a buffer trench, a sidewall of which adjacent to the cell region is in abutment with a sidewall of the base region in the terminal region, and a bottom surface of the buffer trench is lower than a bottom surface of the base region; an isolation dielectric layer, covering an inner wall and a bottom surface of the buffer trench; and a conductive filling layer, filling the buffer trench.

11. The IGBT device of claim 1, wherein: The trench gate structure comprises: a gate trench, embedded in an upper surface of the semiconductor layer; a gate conductive layer, filling the gate trench; and a gate dielectric layer, covering a bottom surface and an inner wall of the gate trench, and wrapping a bottom surface and a sidewall of the gate conductive layer.

12. The IGBT device of claim 11, wherein: The interlayer dielectric layer is further provided with an emitter contact hole and a gate contact hole penetrating through the interlayer dielectric layer, a bottom of the emitter contact hole exposing the emitter region and the contact region, and a bottom surface of the gate contact hole exposing the gate conductive layer.

13. The IGBT device of claim 1, wherein: The doping concentration of the base region is less than the doping concentration of the contact region.

14. The IGBT device of claim 1, wherein: The first conductive type comprises one of N-type or P-type, the second conductive type comprises one of N-type or P-type, and the conductive type of the first conductive type is opposite to that of the second conductive type.

15. A method of manufacturing an IGBT device, characterized by, The method comprises the following steps: providing a first conductive type semiconductor layer comprising a cell region and a terminal region surrounding the cell region, forming a plurality of spaced trench gate structures in the cell region, and forming a second conductive type base region in an upper surface of the cell region, a bottom surface of the base region being higher than a bottom surface of the trench gate structure, and an edge of the base region extending to a preset distance of an upper surface of the terminal region; forming a first conductive type emitter region in an upper surface of the base region in the cell region, the emitter region being in abutment with a sidewall of the trench gate structure adjacent to a sidewall of the trench gate structure; forming a second conductive type contact region in the upper surface of the base region, a sidewall of the contact region in the cell region being in abutment with a sidewall of the emitter region away from the sidewall of the trench gate structure, and a bottom surface of the contact region being not higher than a bottom surface of the emitter region; forming an interlayer dielectric layer covering upper surfaces of the semiconductor layer and the trench gate structure; forming an emitter electrically connected to the emitter region and the contact region and a gate electrically connected to the trench gate structure, penetrating through the interlayer dielectric layer; forming a dielectric layer covering a bottom surface of the semiconductor layer, the dielectric layer being provided with a plurality of spaced collector contact holes penetrating through the dielectric layer; and forming a second conductive type collector region in a lower surface of the semiconductor layer, and forming a collector electrically connected to the collector region, filling the collector contact holes, with the dielectric layer as a mask.

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