Semiconductor light-emitting device, electronic device and preparation method

Abstract

A semiconductor light-emitting device, comprising a first electrode, an epitaxial portion, an ohmic contact layer and a second electrode which are sequentially arranged in a first direction, wherein the epitaxial portion comprises a substrate body, a mesa, and a waveguide. The semiconductor light-emitting device further comprises an insulating dielectric and a substrate. The insulating dielectric covers at least parts of the surfaces of the waveguide and the mesa. The substrate is provided on the side of the first electrode facing away from the epitaxial portion, or on the side of the second electrode facing away from the epitaxial portion. The semiconductor light-emitting device provided by the present application does not have a base, thereby saving costs. The present application further discloses a method for preparing the semiconductor light-emitting device and an electronic device.

Description

Semiconductor light emitting device, electronic device and preparation method

[0001] The present application claims priority to the Chinese patent application No. 202410959566.0 filed on July 16, 2024, and titled "Semiconductor light emitting device, electronic device and preparation method", the whole content of the above application is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor, in particular to a semiconductor light emitting device, an electronic device and a preparation method. BACKGROUND

[0003] III-V nitrides are collectively referred to as the third generation of semiconductors, which have the characteristics of large band gap, high breakdown voltage, large thermal conductivity, high electron saturation drift speed, strong chemical stability, etc. III-V nitrides are direct band gap materials, with a continuous adjustable band gap between 0.7eV (InN) and 6.2eV (AlN), and the emission wavelength covers near-infrared, visible light to deep ultraviolet band, so it is an ideal material for making semiconductor light emitting devices such as light emitting diodes, lasers, etc.

[0004] Among them, the nitride laser has the advantages of good directivity, high brightness, long service life, wide color gamut and high efficiency under large current, etc., and has broad prospects in the fields of laser display, laser lighting, industrial processing, etc. In recent years, with the progress of substrate, epitaxy, packaging and other technologies, there have been outstanding breakthroughs in the performance of gallium nitride-based laser chips at home and abroad. On the one hand, for example, continuous power of 6.0W or more blue laser (455nm) and 1.9W green laser (525nm) have been realized; some domestic companies can also produce blue laser (450nm) with a power of 5.0W or more. On the other hand, the medium and low power products of major companies have also realized mass production and delivery and quickly penetrated into the fields of indicator lights, laser pens, stage lights, levels, etc.

[0005] Under the current circumstances, the cost of the laser after mass production will be one of the core competences in market development. However, in the prior art, the structure of the nitride laser contains a substrate, and since the high-quality substrate is expensive, it has a great impact on the total cost of the laser chip. At the same time, in the manufacturing process of the existing laser chip, an n-type electrode must be formed through a series of process procedures such as substrate thinning, polishing, surface treatment and metal deposition, which results in that each substrate can only be used once, thereby seriously hindering the reduction of the cost of the laser chip. SUMMARY

[0006] The present application provides a semiconductor light emitting device, an electronic device and a preparation method, which can reduce the cost of the semiconductor light emitting device.

[0007] In a first aspect, the present application provides a semiconductor light emitting device, comprising a first electrode, an epitaxial part, an ohmic contact layer and a second electrode arranged in sequence along a first direction. The epitaxial part comprises a base, a mesa and a waveguide. The semiconductor light emitting device further comprises an insulating medium and a substrate. The insulating medium is coated on at least part of the surface of the waveguide and the mesa. The substrate is arranged on the side of the first electrode away from the epitaxial part, or on the side of the second electrode away from the epitaxial part.

[0008] The semiconductor light emitting device provided by the present application does not have a substrate, thereby saving cost.

[0009] In some implementations of the present application, the first electrode is an n-type electrode, the ohmic contact layer is a p-type ohmic contact layer, and the second electrode is a p-type electrode.

[0010] In some implementations of the present application, the epitaxial part comprises, arranged in sequence along the first direction, an n-type epitaxial layer, an n-type confinement layer, an n-side waveguide layer, an active region, a p-side waveguide layer, a p-type confinement layer and a p-type contact layer. The waveguide is arranged on the side close to the ohmic contact layer, or on the side close to the first electrode.

[0011] When the waveguide is arranged on the side close to the ohmic contact layer, the mesa comprises the n-side waveguide layer, the active region, the p-side waveguide layer, at least part of the n-type confinement layer and part of the p-type confinement layer; the base comprises the n-type epitaxial layer; and the waveguide comprises the p-type contact layer and another part of the p-type confinement layer.

[0012] When the waveguide is arranged on the side close to the first electrode, the base comprises the p-type contact layer, the p-type confinement layer, the p-side waveguide layer, the active region and part of the n-side waveguide layer; the mesa comprises another part of the n-side waveguide layer and part of the n-type confinement layer; and the waveguide comprises the n-type epitaxial layer and another part of the n-type confinement layer.

[0013] In some implementations of the present application, the n-type epitaxial layer, the n-type confinement layer, the n-side waveguide layer, the active region, the p-side waveguide layer, the p-type confinement layer and the p-type contact layer are all made of a group III nitride material.

[0014] The material of the first electrode, the ohmic contact layer and the second electrode comprises one or more of Ni, Ti, Pd, Pt, Au, Al, TiN, ITO, IGZO.

[0015] The material of the insulating medium comprises one or more of SiO x (x=0-1), SiN x (x=0-1), SiON, Al2O3, AlON, SiAlON, TiO2, Ta2O5, ZrO2, polysilicon.

[0016] In some implementations of the present application, the semiconductor light emitting device further comprises a bonding layer, the substrate is connected to a side of the first electrode away from the epitaxial part or connected to a side of the second electrode away from the epitaxial part through the bonding layer.

[0017] In some implementations of the present application, the material of the substrate comprises one or more of Si, AlN, SiC, and diamond. The bonding layer comprises a metal bonding layer or a non-metal bonding layer. The material of the metal bonding layer comprises one or more of AuSn, NiSn, AuAu, and NiGe. The material of the non-metal bonding layer comprises one or more of NaCl, SiO2, CrO2, Al2O3, and diamond.

[0018] In a second aspect, the present application provides a method for manufacturing the semiconductor light emitting device of the first aspect, comprising:

[0019] growing a sacrificial layer on the substrate, the sacrificial layer being located on a side of the substrate along a first direction;

[0020] growing an epitaxial part on the sacrificial layer, the epitaxial part being located on a side of the sacrificial layer along the first direction;

[0021] depositing an ohmic contact layer on the epitaxial part, the ohmic contact layer being located on a side of the epitaxial part along the first direction;

[0022] depositing a second electrode on the ohmic contact layer, the second electrode being located on a side of the ohmic contact layer along the first direction;

[0023] removing at least part of the sacrificial layer to separate the substrate from the epitaxial part;

[0024] depositing a first electrode on the epitaxial part, the first electrode being located on a side of the epitaxial part along a second direction, the second direction being opposite to the first direction;

[0025] The method for manufacturing the semiconductor light emitting device further comprises: etching the epitaxial part to form a mesa and a waveguide, and depositing an insulating medium on at least part of the surface of the mesa and the waveguide; and bonding the substrate to the first electrode or the second electrode.

[0026] In some implementations of the present application, the sacrificial layer is a porous structure.

[0027] In some implementations of the present application, the sacrificial layer comprises one or more porous gallium nitride layers, and the porous gallium nitride layers are made by one or more of dry etching, wet etching, and electrochemical etching.

[0028] In some implementations of the present application, the sacrificial layer comprises a first porous gallium nitride layer and a second porous gallium nitride layer arranged in sequence along the first direction, and the porosity of the first porous gallium nitride layer is greater than the porosity of the second porous gallium nitride layer.

[0029] In some implementations of the present application, the sacrificial layer is removed by a method of peeling and / or etching to separate the substrate from the epitaxial portion.

[0030] In a third aspect, the present application provides an electronic device comprising a housing and the semiconductor light emitting device as in the first aspect, the semiconductor light emitting device being arranged in the housing. BRIEF DESCRIPTION OF DRAWINGS

[0031] Fig. 1 shows a structural schematic diagram of a semiconductor light emitting device in the prior art;

[0032] Fig. 2 shows a structural schematic diagram of an epitaxial portion in the prior art;

[0033] Fig. 3 shows a flow chart of a preparation method of a semiconductor light emitting device in the prior art;

[0034] Fig. 4(a) shows a state diagram of a processing procedure of a semiconductor light emitting device in the prior art;

[0035] Fig. 4(b) shows a state diagram of a processing procedure of a semiconductor light emitting device in the prior art;

[0036] Fig. 4(c) shows a state diagram of a processing procedure of a semiconductor light emitting device in the prior art;

[0037] Fig. 4(d) shows a state diagram of a processing procedure of a semiconductor light emitting device in the prior art;

[0038] Fig. 5 shows a structural schematic diagram of a semiconductor light emitting device provided in some implementations of the present application;

[0039] Fig. 6 shows a structural schematic diagram of an epitaxial portion in Fig. 5;

[0040] Fig. 7 shows a structural schematic diagram of a semiconductor light emitting device provided in some other implementations of the present application;

[0041] Fig. 8 shows a structural schematic diagram of a semiconductor light emitting device provided in some other implementations of the present application;

[0042] Fig. 9 shows a structural schematic diagram of a semiconductor light emitting device provided in some other implementations of the present application;

[0043] Fig. 10 shows a structural schematic diagram of an epitaxial portion in Fig. 7 and Fig. 8;

[0044] Fig. 11 shows a structural schematic diagram of an epitaxial portion in Fig. 9;

[0045] Fig. 12 shows a flow chart of a preparation method of a semiconductor light emitting device provided in some implementations of the present application;

[0046] Fig. 13(a) shows a state diagram of a process of manufacturing a semiconductor light emitting device according to some embodiments of the present application;

[0047] Fig. 13(b) shows a state diagram of a process of manufacturing a semiconductor light emitting device according to some embodiments of the present application;

[0048] Fig. 13(c) shows a state diagram of a process of manufacturing a semiconductor light emitting device according to some embodiments of the present application;

[0049] Fig. 13(d) shows a state diagram of a process of manufacturing a semiconductor light emitting device according to some embodiments of the present application;

[0050] Fig. 13(e) shows a state diagram of a process of manufacturing a semiconductor light emitting device according to some embodiments of the present application;

[0051] Fig. 13(f) shows a state diagram of a process of manufacturing a semiconductor light emitting device according to some embodiments of the present application. DETAILED DESCRIPTION

[0052] For the purpose of making the object, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0053] The present application provides a semiconductor light emitting device, which can be widely applied in the fields of laser projection, laser illumination, laser communication, industrial processing and surveying and mapping, and the present application is not limited thereto. Hereinafter, the semiconductor light emitting device will be taken as a nitride laser for example to describe the present application.

[0054] In each of the drawings herein, the X-axis direction is the thickness direction of the laser chip. For the purpose of convenience, hereinafter, the direction indicated by the arrow X1 will be referred to as the "upper" direction, and the direction indicated by the arrow X2 will be referred to as the "lower" direction. It should be noted that the positional relationship indicated by "upper" and "lower" in the present application is only based on the positional relationship shown in the drawings, and cannot be regarded as a limitation on the present application.

[0055] Referring to Fig. 1, in some alternative embodiments, the laser 100a includes, in the X1 direction, i.e., sequentially from lower to upper, an n-type electrode 1a, a substrate 8a, an epitaxial portion 2a, a p-type ohmic contact layer 3a and a p-type electrode 4a. The epitaxial portion 2a includes a base 21a, a p-side mesa 22a and a p-side waveguide 23a. The laser 100a further includes an insulating medium 5a, which covers at least part of the surface of the p-side mesa 22a and the p-side waveguide 23a.

[0056] Further, referring to FIG. 2, the epitaxial part 2a includes, in the X1 direction, i.e., sequentially from bottom to top, an n-type epitaxial layer 201a, an n-type confinement layer 202a, an n-side waveguide layer 203a, an active region 204a, a p-side waveguide layer 205a, a p-type confinement layer 206a, and a p-type contact layer 208a. The n-type epitaxial layer 201a and part of the n-type confinement layer 202a together form a base 21a (as the structure enclosed by the dashed box 21a in FIG. 2). The n-side waveguide layer 203a, the active region 204a, the p-side waveguide layer 205a, part of the n-type confinement layer 202a, and part of the p-type confinement layer 206a together form a p-side mesa 22a (as the structure enclosed by the dashed box 22a in FIG. 2). The p-type contact layer 208a and part of the p-type confinement layer 206a together form a p-side waveguide 23a (as the structure enclosed by the dashed box 23a in FIG. 2).

[0057] The preparation method of the laser 100a and the structure of each part during the preparation process are described below in combination with FIGS. 3 and 4.

[0058] The preparation method of the laser 100a is shown in FIG. 3, which includes the following steps.

[0059] Step A1: growing the epitaxial part 2a above the substrate 8a; specifically, sequentially growing the n-type epitaxial layer 201a, the n-type confinement layer 202a, the n-side waveguide layer 203a, the active region 204a, the p-side waveguide layer 205a, the p-type confinement layer 206a, and the p-type contact layer 208a from bottom to top above the substrate 8a (as shown in FIG. 4(a)), and then annealing the p-type confinement layer 206a and the p-type contact layer 208a to activate magnesium (Mg) acceptors, thereby improving the hole concentration and the p-type electrical properties;

[0060] Step A2: depositing a p-type ohmic contact layer 3a above the epitaxial part 2a; and achieving good ohmic contact through an annealing process;

[0061] Step A3: forming the p-side waveguide 23a through processes such as photolithography and etching;

[0062] Step A4: forming the p-side mesa 22a through processes such as photolithography and etching;

[0063] Step A5: depositing an insulating medium 5a on at least part of the surfaces of the p-side mesa 22a and the p-side waveguide 23a (except for the region on the upper surface of the p-side waveguide 23a);

[0064] Step A6: depositing a p-type electrode 4a above the p-type ohmic contact layer 3a; the overall effect of the laser 100a after the processes from steps A2 to A6 is shown in FIG. 4(b);

[0065] Step A7: thinning and polishing the bottom surface of the substrate 8a (as shown by the dashed line at the bottom of FIG. 4(c));

[0066] Step A8: Process treatment is performed on the bottom surface of the substrate 8a and the n-type electrode 1a is deposited (as shown in Fig. 4(d)), and an annealing process can also be performed as necessary to obtain a good ohmic contact.

[0067] The substrate 8a in the laser 100a is made of single-crystal gallium nitride. In the preparation process of the laser 100a, the bottom surface of the substrate 8a needs to be thinned and polished to deposit the n-type electrode 1a. Therefore, each substrate 8a can only be used once. Since the single-crystal gallium nitride substrate 8a of high quality is expensive, the cost of the laser 100a is relatively high.

[0068] In addition, since the conventional thinning method is to directly thin the substrate 8a by chemical mechanical polishing (CMP), the mechanical stress is added to the crystal which is a hard and brittle material, so that when the thickness of the substrate 8a is thinned to below 100 um, the substrate 8a is prone to cracking along certain specific crystal directions. The smaller the thickness (such as below 80 um), the greater the cracking amplitude, which seriously affects the yield, which further increases the cost of the laser 100a.

[0069] To solve the above problems, the present application provides a semiconductor light emitting device which can reduce the cost and reduce the yield. The structure of the semiconductor light emitting device will be introduced below taking the laser 100 as an example.

[0070] Fig. 5 shows a structural schematic diagram of the laser 100 which does not contain a substrate. Referring to Fig. 5, the laser 100 provided by the present application includes the electrode 1 (as an example of a first electrode), the epitaxial part 2, the ohmic contact layer 3 and the electrode 4 (as an example of a second electrode) which are sequentially arranged in the X1 direction (as an example of a first direction) in Fig. 5, i.e. from bottom to top. The epitaxial part 2 includes the base 21, the mesa 22 and the waveguide 23. The laser 100 further includes the insulating medium 5 and the substrate (not shown in Fig. 5), and the insulating medium 5 is coated on at least part of the surface of the mesa 22 and the waveguide 23 (except the area on the upper surface of the waveguide 23). The substrate is arranged on the side of the electrode 1 away from the epitaxial part 2 (i.e. the lower side of the electrode 1), or arranged on the side of the electrode 4 away from the epitaxial part 2 (i.e. the upper side of the electrode 4).

[0071] Further, the preparation process of the laser 100 includes growing a sacrificial layer (not shown in Fig. 5) above the substrate (not shown in Fig. 5) in the X1 direction, preparing the epitaxial part 2, the ohmic contact layer 3, the insulating medium 5 and the electrode 4 above the sacrificial layer, then removing at least part of the sacrificial layer to separate the substrate from the epitaxial part 2, and depositing the electrode 1 below the epitaxial part 2.

[0072] By using the above preparation method, by setting a sacrifice layer between the epitaxial part 2 and the substrate, the substrate can be removed by removing the sacrifice layer after the epitaxial part 2 and the structure grown on the epitaxial part 2 are prepared, thereby obtaining the laser 100 without the substrate shown in FIG. 5. Compared with the laser 100a with the substrate 8a shown in FIG. 1, the laser 100 provided by the present application can reuse the substrate to save cost, and the substrate can be removed by removing the sacrifice layer, thereby avoiding stress damage of the substrate caused by reducing and polishing, thereby reducing the generation of defective products.

[0073] The present application does not limit the specific types of the electrode 1, the electrode 4 and the ohmic contact layer 3. In some embodiments, the electrode 1 is an n-type electrode, the electrode 4 is a p-type electrode, and the ohmic contact layer 3 is a p-type ohmic contact layer. In other embodiments, the electrode 1 can also be a p-type electrode, the electrode 4 can be an n-type electrode, and the ohmic contact layer 3 can be an n-type ohmic contact layer. For the convenience of understanding of those skilled in the art, the embodiments of the present application are introduced below by taking the electrode 1 as an n-type electrode, the ohmic contact layer 3 as a p-type ohmic contact layer, and the electrode 4 as a p-type electrode as an example.

[0074] Referring to FIG. 6, the epitaxial part 2 includes an n-type epitaxial layer 201, an n-type confinement layer 202, an n-side waveguide layer 203, an active region 204, a p-side waveguide layer 205, a p-type confinement layer 206 and a p-type contact layer 208 arranged in sequence along the X1 direction. The p-type confinement layer 206 is internally or below which an electron blocking layer is arranged. Referring to FIGS. 5 and 6, the electrode 1 is in electrical contact with the lower surface of the n-type epitaxial layer 201, the ohmic contact layer 3 is in electrical contact with the upper surface of the p-type contact layer 208, and the electrode 4 is in electrical connection with the ohmic contact layer 3.

[0075] Further, the n-type epitaxial layer 201, the n-type confinement layer 202, the n-side waveguide layer 203, the p-side waveguide layer 205, the p-type confinement layer 206 and the p-type contact layer 208 can all be made of a group-III nitride material, such as Alx1Iny1Ga(1-x1-y1)N, where x1 represents the component content of Al, y1 represents the component content of In, x1 and y1 are both greater than or equal to 0 and less than or equal to 1, and 0≤(x1+y1)≤1.

[0076] Further, the active region 204 can also be made of a group-III nitride material, including Alx2Iny2Ga(1-x2-y2)N or Alx3Iny3Ga(1-x3-y3)N, where x2 and x3 respectively represent the component content of Al in the two materials, y2 and y3 respectively represent the component content of In in the two materials, x2, y2, x3 and y3 are all greater than or equal to 0 and less than or equal to 1, and 0≤(x2+y2)≤1, 0≤(x3+y3)≤1.

[0077] Further, the material of the electrode 1, the ohmic contact layer 3 and the electrode 4 includes but is not limited to one or more of Ni, Ti, Pd, Pt, Au, Al, TiN, ITO, IGZO.

[0078] Further, the material of the insulating medium 5 includes but is not limited to one or more of SiO x (x=0-1), SiN x (x=0-1), SiON, Al2O3, AlON, SiAlON, TiO2, Ta2O5, ZrO2, polysilicon. The size of the insulating medium 5 along the X direction can be 5-2000nm.

[0079] Further, the thickness of the n-type epitaxial layer 201 can be 5-5000nm. The dopant of the n-type epitaxial layer 201 includes but is not limited to any one of silane (SiH4), germane (GeH4), and the doping concentration is 5x10 17 -1x10 20 / cm 3 The structure of the n-type epitaxial layer 201 can be a porous gallium nitride structure.

[0080] Further, the width (the size along the Y direction in FIG. 5) of the ohmic contact layer 3 can be 1-100um, the thickness (the size along the X direction in FIG. 5) of the ohmic contact layer 3 can be 5-1000nm, and the length (the size along the direction perpendicular to the X direction and the Y direction in FIG. 5) of the ohmic contact layer 3 can be 5-2000um. The thickness of the electrode 4 is 0-10um.

[0081] As shown in FIG. 7 and FIG. 8, in some implementations of the present application, the laser 100 further includes a bonding layer 6, and the substrate 7 is connected to the side of the electrode 1 away from the epitaxial part 2 (i.e. the lower side of the electrode 1) or connected to the side of the electrode 4 away from the epitaxial part 2 (i.e. the upper side of the electrode 4) through the bonding layer 6. The substrate 7 should have good heat dissipation function.

[0082] Further, the substrate 7 can be made of high thermal conductivity material. The material of the substrate 7 includes but is not limited to one or more of Si, AlN, SiC, diamond. Preferably, the cleavage direction of the substrate 7 matches the cleavage direction of the nitride, including but not limited to any one of 4H-SiC, 6H-SiC, Si(100). The bonding layer 6 includes a metal bonding layer 6 or a non-metal bonding layer 6. The material of the metal bonding layer 6 includes but is not limited to one or more of AuSn, NiSn, AuAu, NiGe; the material of the non-metal bonding layer 6 includes but is not limited to one or more of NaCl, SiO2, CrO2, Al2O3, diamond.

[0083] In some implementations of the present application, the laser 100 is connected in chip on wafer form on a whole wafer, and the whole wafer can be connected with the whole substrate 7 in the process of bonding the substrate 7, and then the wafer bonded with the substrate 7 is cleaved to form a bar and is coated on the end face, and then the laser 100 is obtained by cutting. Exemplarily, the size of the substrate 7 includes but is not limited to any one of 2 inches and 4 inches.

[0084] When the laser 100 works, the Joule heat mainly comes from the active region 204 (non-radiative recombination) and the p-type confinement layer 206 and the p-type contact layer 208 with large thermal resistance, and the heat needs to be conducted to the substrate for heat dissipation by setting the substrate with good heat dissipation function, so as to enhance the heat dissipation of the laser 100.

[0085] In actual application, when the substrate 7 is connected to the lower side of the electrode 1 through the bonding layer 6, the laser 100 is a positive structure (as shown in FIG. 7). When the substrate 7 is connected to the upper side of the electrode 4 through the bonding layer 6, the laser 100 is a flip-chip structure (as shown in FIGS. 8 and 9). The laser 100 provided by the present application can reduce the overall thickness of the laser 100 because it does not have a substrate. Especially, when the laser 100 is a positive structure, compared with the laser 100a with the substrate 8a shown in FIG. 1, the distance between the heat source in the laser 100 of the present application and the substrate 7 is shortened, and the length of the effective heat dissipation path after the shortening is shown as the size L in FIG. 7, so that the overall thermal resistance and junction temperature of the laser 100 can be improved, and the performance and reliability of the laser 100 are indirectly improved.

[0086] In some implementations of the present application, the waveguide 23 is arranged on the side close to the ohmic contact layer 3 (as shown in FIGS. 7 and 8) or on the side close to the electrode 1 (as shown in FIG. 9). Exemplarily, the width (the size along the Y direction in FIG. 5) of the waveguide 23 is 1-100 um, the depth (the size along the X direction in FIG. 5) is 0-2000 nm, and the length (the size along the direction perpendicular to the X direction and the Y direction in FIG. 5) is 5-2000 um. The width of the waveguide 23 is smaller than the width of the mesa 22.

[0087] When the waveguide 23 is arranged on the side close to the ohmic contact layer 3 (i.e. on the p-side of the laser 100), referring to FIG. 10, the substrate 21, the mesa 22 and the waveguide 23 are arranged in sequence from bottom to top along the X1 direction. The mesa 22 (the structure enclosed by the dashed box 22 in FIG. 10) includes the n-side waveguide layer 203, the active region 204, the p-side waveguide layer 205, the upper part of the n-type confinement layer 202 and the lower part of the p-type confinement layer 206. The substrate 21 (the structure enclosed by the dashed box 21 in FIG. 10) includes the n-type epitaxial layer 201 and the lower part of the n-type confinement layer 202. The waveguide 23 (the structure enclosed by the dashed box 23 in FIG. 10) includes the p-type contact layer 208 and the upper part of the p-type confinement layer 206. In other embodiments, the mesa 22 can also include the n-side waveguide layer 203, the active region 204, the p-side waveguide layer 205, the lower part of the p-type confinement layer 206 and the entire n-type confinement layer 202, and when the mesa 22 includes the entire n-type confinement layer 202, the substrate 21 only includes the n-type epitaxial layer 201.

[0088] When the waveguide 23 is arranged on the side close to the electrode 1 (i.e. on the n-side of the laser 100), referring to FIG. 11, the substrate 21, the mesa 22 and the waveguide 23 are arranged in sequence from top to bottom along the X2 direction. The substrate 21 (the structure enclosed by the dashed box 21 in FIG. 11) includes the p-type contact layer 208, the p-type confinement layer 206, the p-side waveguide layer 205, the active region 204 and the upper part of the n-side waveguide layer 203; the mesa 22 (the structure enclosed by the dashed box 22 in FIG. 11) includes the lower part of the n-side waveguide layer 203 and the upper part of the n-type confinement layer 202, and the waveguide 23 (the structure enclosed by the dashed box 23 in FIG. 11) includes the lower part of the n-type confinement layer 202 and the n-type epitaxial layer 201. The p-type confinement layer 206 contains an electron blocking layer.

[0089] In some implementations of the present application, when the laser 100 is a flip-chip structure, the waveguide 23 can be arranged on the side close to the electrode 1. FIG. 9 shows a flip-chip structure in which the waveguide 23 is arranged on the side close to the electrode 1. In the laser 100 shown in FIG. 9, the side close to the electrode 1 is the n-side of the laser 100, and the side close to the ohmic contact layer 3 is the p-side of the laser 100. Referring to FIG. 9, by arranging the waveguide 23 on the n-side of the laser 100, the ohmic contact layer 3 can be in full contact with the mesa 22, thereby expanding the current injection area on the p-side, improving the local current congestion problem, reducing the contact resistance, and controlling the operating voltage of the device. On the other hand, when the waveguide 23 is arranged on the p-side of the laser 100, since the p-side is covered by the insulating medium 5, the laser 100 can only diffuse heat through the narrow waveguide 23 on the p-side, which can easily cause the temperature of the p-side to be too high. By arranging the laser 100 as a flip-chip structure and arranging the waveguide 23 on the n-side of the laser 100, the present application can solve the problem of the p-side temperature being too high during the use of the laser 100 at a large current, make the heating of the laser 100 more uniform, reduce the thermal power consumption and junction temperature of the laser 100, and thereby improve the performance and reliability of the laser 100. In addition, the full contact between the mesa 22 and the ohmic contact layer 3 can ensure the flatness of the surface, which is more conducive to the effective bonding of the wafer and the substrate 7 in the later stage, and at the same time improves the bonding yield.

[0090] Further, the processing method of the mesa 22 and the waveguide 23 includes but is not limited to any one of dry etching, wet etching, etc. In the prior art, the waveguide is generally arranged on the p-side by dry etching, which can easily cause surface state defects, sidewall damage, etc. on the waveguide 23, not only increasing non-radiative recombination centers or leakage channels, reducing the laser efficiency, but also forming various types of hole compensation, causing the p-type resistance to increase. On the other hand, for narrow and thin lasers, the sidewall roughness caused by dry etching can also cause a series of problems such as lateral light scattering, etc. In the technical solution shown in FIG. 9 of the present application, by arranging the waveguide 23 on the n-side, the above problems can be avoided.

[0091] In a second aspect, referring to FIG. 12, the present application provides a preparation method of any one of the semiconductor light-emitting devices introduced in combination with FIGS. 5 to 11 in the foregoing embodiments, which includes:

[0092] Step B1: epitaxially growing a sacrificial layer 9 on the substrate 8, the sacrificial layer 9 being located on one side of the substrate 8 along the X1 direction, and the thickness of the sacrificial layer 9 can be 0.1-1.0 um;

[0093] Step B2: growing an epitaxial part 2 on the sacrificial layer 9, and then performing active annealing on the p-type confinement layer 206 and the p-type contact layer 208 in the epitaxial part 2; wherein the epitaxial part 2 is located on one side of the sacrificial layer 9 along the X1 direction;

[0094] Step B3: depositing an ohmic contact layer 3 on the epitaxial part 2 and achieving good ohmic contact by annealing; wherein the ohmic contact layer 3 is located on one side of the epitaxial part 2 along the X1 direction;

[0095] Step B4: depositing an electrode 4 on the ohmic contact layer, the electrode 4 being located on one side of the ohmic contact layer along the X1 direction;

[0096] Step B5: removing at least part of the sacrificial layer 9 to separate the substrate 8 from the epitaxial part 2;

[0097] Step B6: processing and depositing an electrode 1 on the epitaxial part 2, the electrode 1 being located on one side of the epitaxial part 2 along the X2 direction in FIG. 5 (as an example of the second direction), and annealing can be performed as necessary to achieve good ohmic contact.

[0098] In the present application, when the laser 100 is in a flip-chip structure, the waveguide 23 can be arranged between the mesa 22 and the ohmic contact layer 3 (i.e., arranged on the p-side, as shown in FIG. 8), or arranged between the mesa 22 and the electrode 1 (i.e., arranged on the n-side, as shown in FIG. 9).

[0099] When the waveguide 23 is arranged on the p-side, the method further comprises, between Step B3 and Step B4: etching the epitaxial part 2 to form the mesa 22 and the waveguide 23, and depositing the insulating medium 5 on at least part of the surface of the mesa 22 and the waveguide 23. The method further comprises, between Step B4 and Step B5: bonding the substrate 7 to the electrode 4.

[0100] Specifically, when the waveguide 23 is arranged on the p-side, the method for preparing the semiconductor light-emitting device comprises:

[0101] Step C1: epitaxially growing a sacrificial layer 9 on the substrate 8, the sacrificial layer 9 being located on one side of the substrate 8 along the X1 direction, and the thickness of the sacrificial layer 9 can be 0.1-1.0 um (as shown in FIG. 13(a));

[0102] Step C2: growing an epitaxial part 2 on the sacrificial layer 9, and then performing active annealing on the p-type confinement layer 206 and the p-type contact layer 208 in the epitaxial part 2; wherein the epitaxial part 2 is located on one side of the sacrificial layer 9 along the X1 direction (as shown in FIG. 13(b));

[0103] Step C3: depositing an ohmic contact layer 3 on the epitaxial part 2 and achieving good ohmic contact by annealing; wherein the ohmic contact layer 3 is located on one side of the epitaxial part 2 along the X1 direction;

[0104] Step C4: forming a waveguide 23 on the epitaxial part 2 by processes such as photolithography and etching;

[0105] Step C5: forming a mesa 22 on the epitaxial part 2 by deep etching;

[0106] Step C6: depositing insulating medium 5 on at least part of the surface of mesa 22 and waveguide 23 (except the area on the upper surface of waveguide 23);

[0107] Step C7: depositing electrode 4 on ohmic contact layer 3, electrode 4 being located on one side of ohmic contact layer 3 along direction Xl (as shown in Fig. 13(c));

[0108] Step C8: performing pattern bonding of electrode 4 with substrate 7 through bonding layer 6 (as shown in Fig. 13(d));

[0109] Step C9: removing at least part of sacrificial layer 9 to separate substrate 8 from epitaxial part 2 (as shown in Fig. 13(e));

[0110] Step C10: processing and depositing electrode 1 on epitaxial part 2, electrode 1 being located on one side of epitaxial part 2 along direction X2 (as an example of second direction) in Fig. 5 (as shown in Fig. 13(f)), and annealing process can be performed as necessary to obtain good ohmic contact.

[0111] When waveguide 23 is arranged on the n side, between step B4 and step B5, there is further included bonding substrate 7 on electrode 4. Between step B5 and step B6, there is further included etching epitaxial part 2 to form mesa 22 and waveguide 23, and depositing insulating medium 5 on at least part of the surface of mesa 22 and waveguide 23.

[0112] Specifically, when waveguide 23 is arranged on the p side, the method for preparing the semiconductor light emitting device includes:

[0113] Step Dl: epitaxially growing sacrificial layer 9 on substrate 8, sacrificial layer 9 being located on one side of substrate 8 along direction Xl, and the thickness of sacrificial layer 9 can be 0.1-1.0 um;

[0114] Step D2: growing epitaxial part 2 on sacrificial layer 9, and then performing active annealing on p-type confinement layer 206 and p-type contact layer 208 in epitaxial part 2; wherein epitaxial part 2 is located on one side of sacrificial layer 9 along direction Xl;

[0115] Step D3: depositing ohmic contact layer 3 on epitaxial part 2, and achieving good ohmic contact through annealing; wherein ohmic contact layer 3 is located on one side of epitaxial part 2 along direction Xl;

[0116] Step D4: depositing electrode 4 on ohmic contact layer 3, electrode 4 being located on one side of ohmic contact layer 3 along direction Xl;

[0117] Step D5: performing pattern bonding of electrode 4 with substrate 7 through bonding layer 6;

[0118] Step D6: removing at least part of sacrificial layer 9 to separate substrate 8 from epitaxial part 2;

[0119] Step D7: Forming waveguide 23 on epitaxial part 2 by photolithography, etching, etc.

[0120] Step D8: Forming mesa 22 on epitaxial part 2 by deep etching;

[0121] Step D9: Depositing insulating medium 5 on at least part of the surface of mesa 22 and waveguide 23 (region other than the upper surface of waveguide 23);

[0122] Step D10: Performing a certain process on epitaxial part 2 and depositing electrode 1 on one side of epitaxial part 2 along the direction X2 in FIG. 5 (as an example of the second direction), and performing an annealing process if necessary to obtain a good ohmic contact.

[0123] Compared with the preparation method of laser 100a shown in FIG. 1, the above preparation method provided by the application has the advantages of improving the performance of the laser and prolonging the service life of the laser. Specifically, the preparation method of laser 100a shown in FIG. 1 is to grow the structure of the laser chip on substrate 8a. Substrate 8a is generally made of gallium nitride single crystal material, and the dislocation density is generally greater than 10 4 / cm 3 Without special epitaxial process treatment, the dislocations can extend into epitaxial part 2a, especially in active region 204. On the one hand, the dislocations act as non-radiative recombination centers, reducing the radiative recombination efficiency and indirectly affecting the light-emitting efficiency of the device. On the other hand, part of the penetrating dislocations also form a leakage channel, thereby increasing the probability of device leakage. In addition, the service life of the laser is related to the dislocation density. The shortening of the service life of the device caused by dislocations may be due to the promotion of impurity diffusion into active layer 204 or the generation of new dislocations or defects.

[0124] In addition, the strain caused by the lattice mismatch between the active region InGaN and the GaN material in laser 100a induces a strong piezoelectric polarization electric field and quantum confined stark effect (QCSE), causing band bending, increasing the spatial separation of electron-hole wave functions, and reducing the radiative recombination probability. This situation will be more serious with the increase of In content (especially for green light). On the other hand, the polarization electric field causes the band tilt of active region 204, which increases the potential barrier for hole injection, so that the holes are injected from the p-side active region 204. The decrease of hole injection and the difficulty of hole transport in the quantum well lead to uneven distribution of carriers and gain, resulting in an increase in the threshold of the laser and a decrease in the slope efficiency.

[0125] In the preparation of the laser 100, by setting the sacrificial layer 9 between the substrate 8 and the epitaxial part 2, the further extension of dislocations in the substrate 8 can be blocked by the sacrificial layer 9, and the sacrificial layer 9 can also effectively relieve the stress of the upper epitaxial material, thereby relieving the QCSE effect in the active region quantum well and improving the radiation recombination probability. On the other hand, the stress relief and dislocation reduction can also help to improve the incorporation of In in the quantum well, thereby improving the performance of the long-wavelength lasing of the laser 100. In addition, by setting the sacrificial layer 9, the substrate 8 and the epitaxial part 2 can be effectively separated by removing the sacrificial layer 9 after the structure above the sacrificial layer 9 is prepared, and the surface of the substrate 8 can be restored to its original performance by micro-processing the surface of the substrate 8, thereby realizing the repeated use of the substrate 8 in the preparation of the laser 100, and reducing the cost of the laser.

[0126] In some implementations of the present application, before the bonding of the substrate 7, the laser is connected to the whole wafer in the form of chip on wafer. In the process of bonding the substrate 7, the whole wafer can be connected to the whole 2-inch or 4-inch substrate 7, and then the wafer bonded with the substrate 7 is divided into each slot unit, and the bar is cleaved and the end face is coated, and then cut to obtain a single laser 100. Further, the cleavage direction of the substrate 7 matches the cleavage direction of the nitride, including but not limited to any one of 4H-SiC, 6H-SiC, Si(100).

[0127] In some implementations of the present application, considering the subsequent scribe line and cleavage process, the preparation method of the semiconductor light emitting device further includes: performing pattern bonding on the substrate 7. In some preferred examples, thinning and polishing of the substrate 7 can also be included.

[0128] Further, the surface micro-processing of the substrate 8 includes but is not limited to one or more of chemical cleaning and polishing. The chemical cleaning agent includes but is not limited to one or more of HF, H2SO4, HCl, H3PO4, H2O2.

[0129] In some implementations of the present application, the sacrificial layer 9 is a porous structure. The sacrificial layer 9 can include one or more porous gallium nitride layers. The porous gallium nitride layers can be prepared by any one of, but not limited to, dry etching, wet etching, and electrochemical etching. The dry etching includes, but is not limited to, inductively coupled plasma (ICP), reactive ion etching (RIE), ion beam etching (IBE), or any other suitable dry etching method. The wet etching and the electrochemical etching can use an etching reagent including an alkaline or an acidic solvent. Exemplarily, the alkaline solvent includes, but is not limited to, any one or a combination of two or more of potassium hydroxide (KOH), sodium hydroxide (NaOH), and tetramethylammonium hydroxide (TMAH). The acidic solvent includes, but is not limited to, any one or a combination of two of phosphoric acid (H3PO4), hydrofluoric acid (HF), and oxalic acid (HO2C-CO2H). The porous gallium nitride structure of the sacrificial layer 9 can be formed before or after the growth of the epitaxial part 2.

[0130] In some implementations of the present application, referring to FIG. 13(a), the sacrificial layer 9 includes a porous gallium nitride layer 91 (as an example of a first porous gallium nitride layer) and a porous gallium nitride layer 92 (as an example of a second porous gallium nitride layer) arranged in sequence along the X1 direction, and the porosity of the porous gallium nitride layer 91 is greater than the porosity of the porous gallium nitride layer 92. Exemplarily, the porous gallium nitride layer 91 has a porous gallium nitride doping concentration of 9x10 17 –3x10 20 / cm 3 , and forms a porosity of 0-80%. The porous gallium nitride layer 92 has a porous gallium nitride doping concentration of 5x10 17 –1x10 20 / cm 3 , and forms a porosity of 0-40%.

[0131] In some implementations of the present application, the epitaxial part 2 can be grown on the sacrificial layer 9 by a metal organic chemical vapor deposition (MOCVD) or a molecular beam epitaxy (MBE) device.

[0132] In some implementations of the present application, an etching mask can be disposed on the upper surface of the epitaxial portion 2 by using a photolithography process, and then a dry etching or wet etching process can be used to etch the upper surface of the epitaxial portion 2 to form the mesa 22 and the waveguide 23. Subsequently, the insulating medium 5 is covered on at least part of the mesa 22 and the waveguide 23, and the ohmic contact layer 3 is exposed from the insulating medium 5.

[0133] In some implementations of the present application, the sacrificial layer 9 can be removed by a peeling and / or etching method to separate the substrate 8 from the epitaxial portion 2. The peeling method can include, but is not limited to, any one of a laser peeling, a mechanical peeling, etc. The etching method can be an electrochemical etching.

[0134] In some implementations of the present application, part of the sacrificial layer 9 can remain on the substrate 8 and the epitaxial portion 2 after separation. Therefore, the lower surface of the substrate 8 and the upper surface of the epitaxial portion 2 can be processed according to actual conditions to completely remove the sacrificial layer 9. For example, the lower surface of the epitaxial portion 2 can be processed by using a polishing or an inductively coupled plasma (ICP) etching process. The upper surface of the substrate 8 after separation can also be processed by using a polishing process, and the polishing thickness can be 0-5 um. The substrate 8 can still be used for growing the epitaxial portion 2 of other lasers 100.

[0135] In some implementations of the present application, the electrode 1 can be deposited below the epitaxial portion 2 by using a magnetron sputtering or an E-beam evaporation method, and annealing is performed to form an ohmic contact between the electrode 1 and the n-type epitaxial layer 201. Similarly, the ohmic contact layer 3 can be deposited above the epitaxial portion 2 by using a magnetron sputtering or an E-beam evaporation method, and annealing is performed to form an ohmic contact between the ohmic contact layer 3 and the p-type contact layer 208. In addition, the electrode 4 can be deposited on the upper surface of the ohmic contact layer 3 and the insulating medium 5 by using an electroplating, a magnetron sputtering or an E-beam evaporation method.

[0136] In some implementations of the present application, the annealing process can use, but is not limited to, one of a rapid annealing furnace and a tube annealing furnace. For example, the annealing temperature can be 300-800 ℃, and the annealing atmosphere gas can include, but is not limited to, one or more of air, O2, N2 or a mixed gas of O2 and N2.

[0137] The semiconductor light-emitting device and the preparation method thereof provided by the present application have the advantages of low epitaxial dislocation density, small stress, low device thermal resistance, small resistance, low cost, etc. The present application is mainly aimed at various nitride laser chip products, and the application fields include, but are not limited to, laser projection, laser illumination, laser communication, industrial processing, measurement and mapping, etc.

[0138] In a third aspect, the present application provides an electronic device, comprising a housing and any one of the semiconductor light emitting devices as described in the foregoing embodiments in combination with FIGS. 5-11, wherein the semiconductor light emitting device is arranged in the housing.

[0139] The above describes the embodiments of the present application by specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in the specification. Although the description of the present application is introduced in combination with some embodiments, it does not mean that the features of the present application are limited to the embodiments. On the contrary, the purpose of introducing the present application in combination with the embodiments is to cover other options or modifications that can be extended based on the claims of the present application. The present application can also not use these details. In addition, in order to avoid confusion or obscure the focus of the present application, some specific details are omitted in the description. It should be noted that the embodiments and features in the embodiments in the present application can be combined with each other without conflict.

[0140] In the embodiments of the present application, the terms "first", "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more of the features.

[0141] In the embodiments of the present application, "and / or" is only a description of the association relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects have an "or" relationship.

[0142] In the description of the embodiments of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connecting" should be understood in a broad sense, for example, "connecting" can be detachable connection, or can be non-detachable connection; can be direct connection, or can be indirect connection through intermediate medium.

[0143] In the description of the present application, it should be noted that the terms "upper", "lower", "top", "bottom" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore cannot be understood as a limitation on the present application.

[0144] In the description of the application, it needs to be explained that, unless otherwise explicitly specified and limited, the terms "set", "install", "connect", "attach" should be understood broadly, for example, can be fixedly connected, can also be detachably connected, or integrally connected; can be mechanically connected, can also be electrically connected; can be directly connected, can also be indirectly connected through an intermediate medium, can be the communication inside two elements. For those skilled in the art, the specific meanings of the above terms in the application can be understood according to the specific circumstances.

[0145] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. A semiconductor light-emitting device, characterized in that, comprises, in sequence along a first direction: a first electrode; an epitaxial part comprising a base, a mesa and a waveguide; an ohmic contact layer; a second electrode; the semiconductor light emitting device further comprises: an insulating medium coated on at least part of a surface of the waveguide and the mesa; a substrate provided on a side of the first electrode away from the epitaxial part, or on a side of the second electrode away from the epitaxial part.

2. The semiconductor light emitting device of Claim 1, wherein, the first electrode is an n-type electrode, the ohmic contact layer is a p-type ohmic contact layer, and the second electrode is a p-type electrode.

3. The semiconductor light emitting device according to claim 2, wherein the epitaxial part comprises, in sequence along the first direction: an n-type epitaxial layer, an n-type confinement layer, an n-side waveguide layer, an active region, a p-side waveguide layer, a p-type confinement layer and a p-type contact layer; the waveguide is provided on a side close to the ohmic contact layer or on a side close to the first electrode; when the waveguide is provided on a side close to the ohmic contact layer, the mesa comprises the n-side waveguide layer, the active region, the p-side waveguide layer, at least part of the n-type confinement layer and a part of the p-type confinement layer; the base comprises the n-type epitaxial layer; and the waveguide comprises the p-type contact layer and another part of the p-type confinement layer; when the waveguide is provided on a side close to the first electrode, the base comprises the p-type contact layer, the p-type confinement layer, the p-side waveguide layer, the active region and a part of the n-side waveguide layer; the mesa comprises another part of the n-side waveguide layer and a part of the n-type confinement layer; and the waveguide comprises the n-type epitaxial layer and another part of the n-type confinement layer.

4. The semiconductor light emitting device according to claim 3, wherein the n-type epitaxial layer, the n-type confinement layer, the n-side waveguide layer, the active region, the p-side waveguide layer, the p-type confinement layer and the p-type contact layer are all made of a group-III nitride material; a material of the first electrode, the ohmic contact layer and the second electrode comprises one or more of Ni, Ti, Pd, Pt, Au, Al, TiN, ITO, IGZO; The material of the insulating medium includes SiO x (x = 0-1), SiN x (x = 0-1), SiON, Al2O3, AlON, SiAlON, TiO2, Ta2O5, ZrO2, polysilicon, or one or more thereof.

5. The semiconductor light emitting device of any of Claims 1-4, wherein, a bonding layer is further included, and the substrate is connected to a side of the first electrode away from the epitaxial part or to a side of the second electrode away from the epitaxial part through the bonding layer.

6. The semiconductor light emitting device according to claim 5, wherein a material of the substrate comprises one or more of Si, AlN, SiC, diamond; the bonding layer comprises a metal bonding layer or a non-metal bonding layer; a material of the metal bonding layer comprises one or more of AuSn, NiSn, AuAu, NiGe; a material of the non-metal bonding layer comprises one or more of NaCl, SiO2, CrO2, Al2O3, diamond.

7. A method of fabricating a semiconductor light emitting device as defined in any one of claims 1 to 6, characterized by, comprises: growing a sacrificial layer on a substrate, the sacrificial layer being on a side of the substrate along a first direction; growing an epitaxial part on the sacrificial layer, the epitaxial part being on a side of the sacrificial layer along the first direction; depositing an ohmic contact layer on the epitaxial part, the ohmic contact layer being located at one side of the epitaxial part along the first direction; depositing a second electrode on the ohmic contact layer, the second electrode being located at one side of the ohmic contact layer along the first direction; removing at least part of the sacrificial layer to separate the substrate from the epitaxial part; depositing a first electrode on the epitaxial part, the first electrode being located at one side of the epitaxial part along a second direction, the second direction being opposite to the first direction; the preparation method further comprises: etching the epitaxial part to form a mesa and a waveguide, and depositing an insulating medium on at least part of the surface of the mesa and the waveguide; and bonding a substrate on the first electrode or the second electrode.

8. The method for fabricating a semiconductor light-emitting device according to claim 7, characterized in that, The sacrificial layer is a porous structure.

9. The method for fabricating a semiconductor light-emitting device according to claim 8, characterized in that, The sacrificial layer comprises one or more porous gallium nitride layers, the porous gallium nitride layers being made by one or more of dry etching, wet etching and electrochemical etching.

10. The method for fabricating a semiconductor light-emitting device according to claim 9, characterized in that, The sacrificial layer comprises a first porous gallium nitride layer and a second porous gallium nitride layer arranged in sequence along the first direction, the first porous gallium nitride layer having a porosity greater than that of the second porous gallium nitride layer.

11. The method for fabricating a semiconductor light-emitting device according to claim 8, characterized in that, The sacrificial layer is removed by a method of peeling and / or etching to separate the substrate from the epitaxial part.

12. An electronic device, comprising: The semiconductor light emitting device as claimed in any one of claims 1 to 6 is arranged in a housing.

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