Thin film transistor, array substrate, and display panel

Abstract

A thin film transistor. The thin film transistor comprises an active layer located on one side of a substrate, and a gate layer located on the side of the active layer away from the substrate. The active layer comprises a first sub-layer and a second sub-layer located on the side of the first sub-layer away from the substrate, wherein the mobility of the first sub-layer is higher than that of the second sub-layer, and the average thickness of the first sub-layer is less than that of the second sub-layer.

Description

Thin-film transistors, array substrates and display panels

[0001] This application claims priority to Chinese patent application No. 202410983767.4, filed on July 19, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a thin-film transistor, an array substrate, and a display panel. Background Technology

[0003] Currently, commonly used active semiconductor materials in the semiconductor display field include amorphous silicon, metal oxides, and low-temperature polycrystalline silicon. The mobility of amorphous silicon is approximately 1 cm⁻¹. 2 / V*s, the mobility of the metal oxide is approximately 10 cm⁻¹. 2 / V*s, the mobility of low-temperature polycrystalline silicon is approximately 80cm. 2 / V*s, where low-temperature polycrystalline silicon has significant material advantages. By increasing the proportion of In and adding Sn, the mobility of metal oxides can be increased to 20 cm⁻¹. 2 / V*s~50cm 2 / V*s, but this is still somewhat different from low-temperature polycrystalline silicon. Summary of the Invention

[0004] On one hand, a thin-film transistor is provided, the thin-film transistor comprising: an active layer located on one side of a substrate, and a gate layer located on the side of the active layer away from the substrate; wherein the active layer comprises: a first sub-layer and a second sub-layer located on the side of the first sub-layer away from the substrate, the mobility of the first sub-layer being higher than the mobility of the second sub-layer; and the average thickness of the first sub-layer being less than the average thickness of the second sub-layer.

[0005] In some embodiments, the ratio of the average thickness of the first sublayer to the average thickness of the second sublayer ranges from 0.1 to 0.85.

[0006] In some embodiments, the average thickness of the first sublayer ranges from 5 nm to 25 nm.

[0007] In some embodiments, the average thickness of the second sublayer ranges from 30 nm to 50 nm.

[0008] In some embodiments, the mobility of the first sublayer is greater than or equal to 20 cm⁻¹ 2 / V*s.

[0009] In some embodiments, the mobility of the second sublayer ranges from 5 cm. 2 / V*s~15cm2 / V*s.

[0010] In some embodiments, the optical band gap of the material of the first sublayer is smaller than the optical band gap of the material of the second sublayer.

[0011] In some embodiments, the optical bandgap of the material of the first sublayer is less than or equal to 2.9 eV.

[0012] In some embodiments, the optical bandgap of the material of the second sublayer is greater than or equal to 3 eV.

[0013] In some embodiments, the first sublayer and the second sublayer meet at least one of the following conditions: the zinc content of the first sublayer is greater than the zinc content of the second sublayer; the gallium content of the first sublayer is less than the gallium content of the second sublayer; the tin content of the first sublayer is greater than the tin content of the second sublayer.

[0014] In some embodiments, the ratio of the zinc content of the first sublayer to the zinc content of the second sublayer ranges from 1.1 to 2; and / or, the ratio of the gallium content of the second sublayer to the gallium content of the first sublayer ranges from 2 to 5.

[0015] In some embodiments, the material of the first sublayer includes at least one of indium gallium oxide, indium tin zinc oxide, and indium gallium zinc tin oxide; and / or, the material of the second sublayer includes indium gallium zinc oxide.

[0016] In some embodiments, the thin-film transistor further includes: an interlayer dielectric layer located on the side of the gate layer away from the substrate; the interlayer dielectric layer includes: a first interlayer dielectric layer and a second interlayer dielectric layer disposed in a direction away from the substrate; wherein the hydrogen atom content of the first interlayer dielectric layer is less than the hydrogen atom content of the second interlayer dielectric layer; and the density of the first interlayer dielectric layer is less than the density of the second interlayer dielectric layer.

[0017] In some embodiments, the thin-film transistor further includes: a first via penetrating the interlayer dielectric layer; the first via includes: a first hole penetrating the first interlayer dielectric layer and a second hole penetrating the second interlayer dielectric layer; wherein the boundary of the first interlayer dielectric layer surrounding the first hole is located inside the boundary of the second interlayer dielectric layer surrounding the second hole.

[0018] In some embodiments, the distance between the boundary of the first interlayer dielectric layer surrounding the first hole and the boundary of the second interlayer dielectric layer surrounding the second hole ranges from 0.5 μm to 1.5 μm.

[0019] In some embodiments, the thin-film transistor further includes: a source / drain metal layer; the source / drain metal layer is located on the side of the active layer away from the substrate, and the source / drain metal layer is connected to the second sub-layer; or, the source / drain metal layer is located on the side of the active layer close to the substrate, and the source / drain metal layer is connected to the first sub-layer.

[0020] On the other hand, an array substrate is provided, the array substrate comprising: a substrate and a plurality of thin-film transistors disposed on the substrate, wherein at least one of the plurality of thin-film transistors is a thin-film transistor as described in any of the above embodiments.

[0021] In some embodiments, the array substrate further includes: a light-shielding layer and a buffer layer, the light-shielding layer being located between the substrate and the active layer of the thin-film transistor, and the buffer layer being located between the light-shielding layer and the active layer; the thin-film transistor includes: a gate insulating layer being located between the active layer and the gate layer of the thin-film transistor; wherein the average thickness of the portion of the buffer layer located between the light-shielding layer and the active layer is greater than the average thickness of the gate insulating layer.

[0022] In another aspect, a display panel is provided, the display panel comprising: an array substrate as described in any of the above embodiments; the display panel further comprising: an opposing substrate and a liquid crystal layer, the opposing substrate being opposite to and spaced apart from the array substrate; the liquid crystal layer being disposed between the array substrate and the opposing substrate.

[0023] In another aspect, a display panel is provided, the display panel comprising: an array substrate as described in any of the above embodiments; the display panel further comprising: a plurality of light-emitting devices, the plurality of light-emitting devices being disposed on the array substrate, the array substrate being used to drive the plurality of light-emitting devices to emit light. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual process of the method, etc. involved in the embodiments of this disclosure.

[0025] Figure 1 is a structural diagram of a thin-film transistor according to some embodiments;

[0026] Figure 2 is a structural diagram of an array substrate according to some embodiments;

[0027] Figure 3 is a schematic diagram of the conduction principle of a thin-film transistor according to some embodiments;

[0028] Figure 4 is another conduction principle diagram of a thin-film transistor according to some embodiments;

[0029] Figure 5 is another conduction principle diagram of a thin-film transistor according to some embodiments;

[0030] Figure 6 is a graph showing the basic characteristics of a thin-film transistor according to some embodiments;

[0031] Figure 7 is a graph showing the electrical stability of a thin-film transistor according to some embodiments;

[0032] Figure 8 is another electrical stability curve of a thin-film transistor according to some embodiments;

[0033] Figure 9 shows a cross-sectional microstructure of a thin-film transistor according to some embodiments, taken using a transmission electron microscope (TEM).

[0034] Figure 10 is an elemental energy spectrum (EDX) of the active layer of a thin-film transistor according to some embodiments;

[0035] Figure 11 is a cross-sectional microstructure of the array substrate taken using a transmission electron microscope according to some embodiments;

[0036] Figure 12 is another structural diagram of an array substrate according to some embodiments;

[0037] Figure 13 is another structural diagram of a thin-film transistor according to some embodiments;

[0038] Figure 14 is a flowchart of a method for fabricating an array substrate according to some embodiments;

[0039] Figures 15 and 16 are structural diagrams corresponding to each step of the fabrication method of the array substrate according to some embodiments;

[0040] Figure 17 is a structural diagram of a display panel according to some embodiments;

[0041] Figure 18 is another structural diagram of a display panel according to some embodiments;

[0042] Figure 19 is a structural diagram of a display device according to some embodiments. Detailed Implementation

[0043] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0044] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0045] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0046] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0047] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0048] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0049] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0050] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on another layer or substrate, or that there is an intermediate layer between the layer or element and another layer or substrate.

[0051] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0052] In some embodiments, as shown in FIG1, the thin-film transistor 10 may include an active layer 12, a gate insulating layer 13, a gate layer 14, an interlayer dielectric layer 15, and a source / drain metal layer 16 disposed on a substrate 11. The thin-film transistor 10 has a gate 141, a source 161, and a drain 162. The gate 141 is located on the gate layer 14, and the source 161 and drain 162 are located on the source / drain metal layer 16. The source 161 and drain 162 are connected to the active layer 12 through a first via H1 penetrating the interlayer dielectric layer 15. When a certain voltage is applied to the gate 141 of the thin-film transistor 10, the active layer 12 is turned on, thereby forming a path between the source 161 and the drain 162, and turning on the thin-film transistor 10.

[0053] For example, the active layer 12 is made of semiconductor material. The high mobility of semiconductor material is of great significance. Higher mobility means that electrons have a faster transport speed in semiconductor material. Higher mobility is beneficial to improving the display quality of the display screen of display device 2000.

[0054] Mobility refers to the average drift velocity of charge carriers under a unit electric field strength, and its unit is centimeters. 2 / (volt-second), expressed in cm 2 / V*s.

[0055] In some examples, the active layer 12 is made of amorphous silicon (a-Si), metal oxide, or low-temperature polycrystalline silicon (LTPS). The mobility of amorphous silicon (a-Si) is approximately 1 cm⁻¹. 2 / V*s, the mobility of the metal oxide is approximately 10 cm⁻¹. 2 / V*s, the mobility of low-temperature polycrystalline silicon is approximately 80cm. 2 / V*s.

[0056] A thin-film transistor 10 formed using metal oxide as the active layer 12 is called an oxide thin-film transistor. Oxide thin-film transistors have been widely studied in recent years due to their flexibility, large-area production capability, and simple manufacturing process. Adding Sn and increasing the proportion of In to the metal oxide can improve its mobility to 20 cm⁻¹. 2 / V*s~50cm 2 However, due to factors such as the preparation process, the mobility of the metal oxide active layer currently prepared is lower than the theoretical value.

[0057] Furthermore, high-mobility metal oxides have smaller optical band gaps (Eg) and chemical activation energies (Ea). A smaller optical band gap (Eg) means electrons can absorb light across a wider wavelength range and transition, thus turning on the thin-film transistor 10 earlier. A smaller chemical activation energy (Ea) means that high-mobility metal oxides are more prone to generating new defects, thereby affecting the electrical stability of the thin-film transistor 10. Therefore, while high-mobility metal oxides improve mobility, they struggle to maintain electrical stability, leading to a reduced lifespan for the thin-film transistor 10.

[0058] Based on this, as shown in FIG2, an embodiment of the present disclosure provides an array substrate 100, the array substrate 100 including a thin film transistor 10, the thin film transistor 10 including: an active layer 12 located on one side of a substrate 11, and a gate layer 14 located on the side of the active layer 12 away from the substrate 11.

[0059] In some embodiments, the active layer 12 may include metal oxide materials and / or metal oxide nitride materials. The metal oxide materials include, but are not limited to, indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), rare earth doped oxide (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O.

[0060] Metallic nitride materials include, but are not limited to, zinc nitride, indium nitride, gallium nitride, tin nitride, cadmium nitride, aluminum nitride, germanium nitride, titanium nitride, silicon nitride, or combinations thereof.

[0061] The active layer material can be amorphous, partially crystalline, single-crystal or polycrystalline, and can also be a single-layer or multi-layer structure.

[0062] As shown in Figure 2, the active layer 12 includes a first sublayer 121 and a second sublayer 122 located on the side of the first sublayer 121 away from the substrate 11. The mobility of the first sublayer 121 is higher than that of the second sublayer 122. The average thickness d1 of the first sublayer 121 is less than that of the average thickness d2 of the second sublayer 122.

[0063] The average thickness refers to the average thickness measured in several different regions selected at certain distances from the same field of view. It can be understood that the thickness of the first sublayer 121 is its dimension in the direction Y perpendicular to the substrate 11, and the thickness of the second sublayer 122 is its dimension in the direction Y perpendicular to the substrate 11.

[0064] By setting the mobility of the first sublayer 121 to be greater than that of the second sublayer 122, and the average thickness d1 of the first sublayer 121 to be less than the average thickness d2 of the second sublayer 122, the thin-film transistor 10 achieves both high mobility and good electrical stability, thereby improving its switching capability and lifespan. The reason why the thin-film transistor 10 provided in the above embodiment has both high mobility and good electrical stability is as follows:

[0065] On the one hand, the mobility of the first sublayer 121 is relatively high; for example, the mobility of the first sublayer 121 is greater than or equal to 20 cm⁻¹. 2 / V*s, materials with high mobility are more likely to absorb visible light and generate photogenerated carriers, i.e., photogenerated defects. The generation of photogenerated defects will affect the electrical stability of the thin film transistor 10, resulting in a lower lifetime of the thin film transistor 10.

[0066] The embodiments of this disclosure form a first sublayer 121 with a relatively small average thickness d1 by setting the average thickness d1 of the first sublayer 121 to be smaller than the average thickness d2 of the second sublayer 122. This can reduce the number of photogenerated defects in the first sublayer 121, thereby reducing the impact of photogenerated defects on the electrical stability of the thin film transistor 10 and improving the lifespan of the thin film transistor 10.

[0067] On the other hand, as shown in Figures 2 and 3, Figure 3 is a schematic diagram of the conduction principle of a thin-film transistor 10 according to some embodiments. The thin-film transistor 10 also includes a gate insulating layer 13, which is located between the active layer 12 and the gate layer 14. Due to defects at the interface of the gate insulating layer 13, such as defects formed during film formation, some carriers of the active layer 12 will be captured by the gate insulating layer 13. This can easily reduce the electrical stability of the thin-film transistor 10, thereby affecting the switching capability and lifespan of the thin-film transistor 10.

[0068] Since the active layer 12 includes a first sublayer 121 and a second sublayer 122, and the mobility of the first sublayer 121 is higher than that of the second sublayer 122, the active layer 12 includes a first conductive channel 12a and a second conductive channel 12b located on both sides of the first conductive channel 12a along the direction Y perpendicular to the substrate 11. The carrier concentration of the first conductive channel 12a is greater than that of the second conductive channel 12b.

[0069] That is, the carriers of the active layer 12 are concentrated in the first conductive channel 12a. If the first conductive channel 12a can be relatively far away from the gate insulating layer 13, then the carriers of the first conductive channel 12a will not be captured by the defects at the interface of the gate insulating layer 13, which is beneficial to improving the electrical stability of the thin film transistor 10.

[0070] For example, factors affecting the position of the first conductive channel 12a in the active layer 12 include: the electric field strength of the gate layer 14, the difference in mobility between the first sublayer 121 and the second sublayer 122, and the difference in average thickness between the first sublayer 121 and the second sublayer 122.

[0071] For example, due to the strong electric field strength of the gate layer 14, the gate layer 14 will pull the first conductive channel 12a closer to the gate insulating layer 13. The second sub-layer 122, with a relatively large average thickness d2, can pull the first conductive channel 12a away from the gate insulating layer 13. The mobility of the first sub-layer 121 is higher than that of the second sub-layer 122. Carriers tend to transport at locations with higher mobility. Therefore, the high mobility of the first sub-layer 121 will pull the first conductive channel 12a away from the gate insulating layer 13.

[0072] The embodiments of this disclosure, by setting the mobility of the first sublayer 121 to be greater than that of the second sublayer 122, and the average thickness d1 of the first sublayer 121 to be less than the average thickness d2 of the second sublayer 122, can make the ratio of the distance d3 between the first conductive channel 12a and the surface m1 of the active layer 12 away from the substrate 11 in the direction Y perpendicular to the substrate 11 to the average thickness d2 of the second sublayer 122 greater than 1 / 2, that is, d3 / d2>1 / 2.

[0073] When the ratio of the distance d3 between the first conductive channel 12a and the surface m1 of the active layer 12 away from the substrate 11 to the average thickness d2 of the second sub-layer 122 is greater than 1 / 2, the trapping of carriers in the first conductive channel 12a by the interface defects of the gate insulating layer 13 can be reduced, so that the first conductive channel 12a maintains a high carrier concentration, thereby improving the electrical stability of the thin film transistor 10 and extending the switching capability and service life of the thin film transistor 10.

[0074] For example, as shown in FIG3, the first conductive channel 12a is located near the interface between the first sublayer 121 and the second sublayer 122. For example, in the direction Y perpendicular to the substrate 11, the proportion of the size d5 of the portion of the first conductive channel 12a located in the first sublayer 121 to the first sublayer 121 is approximately equal to the proportion of the size d6 of the portion of the first conductive channel 12a located in the second sublayer 122 to the second sublayer 122, i.e., d6 / d2≈d5 / d1.

[0075] On the other hand, when the proportion of the portion of the first conductive channel 12a located in the first sublayer 121 in the direction Y perpendicular to the substrate 11 is approximately equal to the proportion of the portion of the first conductive channel 12a located in the second sublayer 122 in the second sublayer 122, a portion of the first conductive channel 12a is located in the first sublayer 121 with higher mobility, which will improve the mobility of the thin film transistor 10.

[0076] Furthermore, the second sublayer 122 can provide carriers to the first sublayer 121, which has a higher mobility, to increase the carrier concentration of the first sublayer 121, thereby increasing the mobility of the thin-film transistor 10.

[0077] Therefore, by setting the mobility of the first sub-layer 121 to be greater than that of the second sub-layer 122, and the average thickness d1 of the first sub-layer 121 to be less than the average thickness d2 of the second sub-layer 122, a portion of the first conductive channel 12a can be located in the first sub-layer 121 with higher mobility. This is beneficial for carrier transport, and the second sub-layer 122 can provide carriers to the first sub-layer 121, thereby enabling the thin-film transistor 10 to have a higher mobility. Furthermore, the first conductive channel 12a can be relatively far from the gate insulating layer 13, reducing the trapping of carriers in the first conductive channel 12a by interface defects in the gate insulating layer 13, thus maintaining a high carrier concentration in the first conductive channel 12a, improving the electrical stability of the thin-film transistor 10, and extending its switching capability and lifespan. Therefore, the embodiments of this disclosure improve the electrical stability of the thin-film transistor 10 while ensuring a high mobility, achieving the goal of enhancing its switching capability and extending its lifespan.

[0078] In some embodiments, as shown in FIG2, the ratio of the average thickness d1 of the first sublayer 121 to the average thickness d2 of the second sublayer 122 is in the range of 0.1 to 0.85, that is, the ratio of d1 / d2 is in the range of 0.1 to 0.85.

[0079] For example, the ratio of the average thickness d1 of the first sublayer 121 to the average thickness d2 of the second sublayer 122 is 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8 or 0.85, etc., and there is no limitation here.

[0080] By setting the ratio of the average thickness d1 of the first sublayer 121 to the average thickness d2 of the second sublayer 122 to be in the range of 0.1 to 0.85, the average thickness d1 of the first sublayer 121 is less than the average thickness d2 of the second sublayer 122.

[0081] In some embodiments, as shown in FIG3, the average thickness d1 of the first sublayer 121 ranges from 5nm to 25nm, and the average thickness d2 of the second sublayer 122 ranges from 30nm to 50nm.

[0082] For example, the average thickness d1 of the first sublayer 121 is 5nm, 10nm, 15nm, 20nm or 25nm, etc., and there is no limitation here.

[0083] For example, the average thickness d2 of the second sublayer 122 is 30nm, 35nm, 40nm, 45nm or 50nm, etc., and there is no limitation here.

[0084] As shown in Figure 3, by setting the average thickness d1 of the first sublayer 121 to be less than or equal to 25nm, the average thickness d1 of the first sublayer 121 is relatively smaller than the average thickness d2 of the second sublayer 122. This effectively solves the problem of excessive photogenerated defects caused by the excessive average thickness d2 of the first sublayer 121, thereby improving the electrical stability of the thin film transistor 10.

[0085] Moreover, by setting the average thickness d1 of the first sublayer 121 to be greater than or equal to 5 nm, it is possible to effectively ensure that the first sublayer 121 has a high carrier concentration.

[0086] As shown in Figure 3, by setting the average thickness d2 of the second sub-layer 122 to be greater than or equal to 30 nm, the setting of the second sub-layer 122 can move the first conductive channel 12a away from the gate insulating layer 13, thereby reducing the capture of charge carriers of the first conductive channel 12a by the interface defects of the gate insulating layer 13.

[0087] For example, as shown in FIG4, FIG4 is another conduction principle diagram of thin film transistor 10 according to some embodiments. If the average thickness d2 of the second sub-layer 122 is too small, the first conductive channel 12a will be close to the gate insulating layer 13, resulting in a more serious problem of the interface defects of the gate insulating layer 13 trapping the carriers of the first conductive channel 12a, causing the electrical stability of the thin film transistor 10 to deteriorate.

[0088] Therefore, setting the average thickness d2 of the second sublayer 122 to be greater than or equal to 30 nm can reduce the capture of charge carriers in the first conductive channel 12a by the interface defects of the gate insulating layer 13, thereby improving the electrical stability of the thin film transistor 10 and extending the switching capability and service life of the thin film transistor 10.

[0089] For example, as shown in FIG5, FIG5 is another conduction principle diagram of thin film transistor 10 according to some embodiments. If the average thickness d2 of the second sub-layer 122 is too large, for example, when the average thickness d2 of the second sub-layer 122 is greater than 50 nm, it will cause the first conductive channel 12a to concentrate in the second sub-layer 122, that is, the first conductive channel 12a is far away from the first sub-layer 121 with higher mobility, which will lead to a decrease in the mobility of the thin film transistor 10.

[0090] Therefore, by setting the average thickness d2 of the second sublayer 122 to be less than or equal to 50 nm, the problem of the first conductive channel 12a being concentrated in the second sublayer 122 can be effectively prevented, thereby improving the mobility of the thin film transistor 10.

[0091] Please refer to Figure 3 again. Under the combined effects of the electric field strength of the gate layer 14, the higher mobility of the first sublayer 121 than the second sublayer 122, the average thickness d1 of the first sublayer 121 ranging from 5 nm to 25 nm, and the average thickness d2 of the second sublayer 122 ranging from 30 nm to 50 nm, the proportion of the portion of the first conductive channel 12a located in the first sublayer 121 in the direction Y perpendicular to the substrate 11 to the first sublayer 121 is approximately equal to the proportion of the portion of the first conductive channel 12a located in the second sublayer 122 to the second sublayer 122.

[0092] This configuration allows the first conductive channel 12a to be located away from the interface of the gate insulating layer 13, effectively solving the problem of carrier trapping in the first conductive channel 12a due to interface defects in the gate insulating layer 13. This improves the electrical stability of the thin-film transistor 10, thereby extending its switching capability and lifespan. Furthermore, in the direction Y perpendicular to the substrate 11, the proportion of the dimension d5 of the portion of the first conductive channel 12a located in the first sub-layer 121 to the first sub-layer 121 is approximately equal to the proportion of the dimension d6 of the portion of the first conductive channel 12a located in the second sub-layer 122 to the second sub-layer 122. The second sub-layer 122 can provide carriers to the first sub-layer 121, further increasing the carrier concentration in the first sub-layer 121 and improving the mobility of the thin-film transistor 10.

[0093] Figure 6 is a basic characteristic curve of the thin-film transistor 10 according to some embodiments. The horizontal axis represents the gate-source voltage of the thin-film transistor 10, denoted as V. GS The unit is V; the vertical axis represents the logarithmic coordinates of the drain current of the thin-film transistor 10, expressed as I. DS The unit is Å. The structure of the thin-film transistor 10 provided in Example 1 is shown in Figure 3. In Example 1, the average thickness d1 of the first sublayer 121 ranges from 5 nm to 25 nm, and the average thickness d2 of the second sublayer 122 ranges from 30 nm to 50 nm. The structure of the thin-film transistor 10 provided in Example 2 is shown in Figure 5. In Example 2, the average thickness d1 of the first sublayer 121 ranges from 5 nm to 25 nm, and the average thickness d2 of the second sublayer 122 is greater than 50 nm, meaning that the average thickness d2 of the second sublayer 122 is too large. Both Examples 1 and 2 are obtained by testing the basic characteristics of multiple thin-film transistors 10, resulting in multiple graphs.

[0094] As can be seen from Figure 6, there is a difference N between the basic characteristic curves of the thin-film transistor 10 shown in Example 1 and the thin-film transistor 10 shown in Example 2. That is, at the same gate-source voltage, the drain current of the thin-film transistor 10 shown in Example 2 is less than the drain current of the thin-film transistor 10 shown in Example 1. Therefore, as can be seen from Figure 6, the thin-film transistor 10 shown in Example 1 has a higher mobility.

[0095] Figure 7 is an electrical stability curve of the thin-film transistor 10 according to some embodiments, and Figure 8 is another electrical stability curve of the thin-film transistor 10 according to some embodiments. The horizontal axis represents the gate-source voltage of the thin-film transistor 10, denoted as V. GS The unit is V; the vertical axis represents the logarithmic coordinates of the drain current of the thin-film transistor 10, expressed as I. DS The unit is Å. The structure of the thin-film transistor 10 corresponding to Figure 7 is shown in Figure 3, representing Example 1; the structure of the thin-film transistor 10 corresponding to Figure 8 is shown in Figure 5, representing Example 2. Different curves represent the application of V to the gate 141 of the thin-film transistor 10. GS And V obtained over different durations GS The curves have durations of 0s, 100s, 600s, 1800s, and 3600s. When I... DS As the value gradually increases, it indicates that the thin-film transistor 10 is turned on. Different curves represent the V values ​​when the thin-film transistor 10 is turned on. GS The difference is the threshold voltage offset ΔV of the thin-film transistor 10. th .

[0096] As can be seen from Figure 7, the threshold voltage offset ΔV of the thin-film transistor 10 shown in Example 1 th Less than 2V; as can be seen from Figure 8, the threshold voltage offset ΔV of the thin-film transistor 10 shown in Example 2 is... th With a voltage greater than 5V, the thin-film transistor 10 shown in Example 1 has good electrical stability.

[0097] Therefore, as can be seen from Figures 6 to 8, the thin-film transistor 10 provided by the embodiments of this disclosure not only has high mobility, but also good electrical stability.

[0098] In some embodiments, as shown in Figures 2 and 3, the mobility of the first sublayer 121 is greater than or equal to 20 cm⁻¹. 2 / V*s. This is to ensure that the first sublayer 121 has a higher mobility.

[0099] In some embodiments, as shown in Figures 2 and 3, the mobility of the second sublayer 122 ranges from 5 cm. 2 / V*s~15cm2 / V*s.

[0100] For example, the mobility of the second sublayer 122 is 5 cm. 2 / V*s、7cm 2 / V*s、8cm 2 / V*s、10cm 2 / V*s、12cm 2 / V*s、13cm 2 / V*s or 15cm 2 / V*s, etc., are not limited here.

[0101] The mobility range through the second sublayer 122 is 5 cm. 2 / V*s~15cm 2 The / V*s setting ensures that the mobility of the second sublayer 122 is lower than that of the first sublayer 121. The second sublayer 122 can provide carriers to the first sublayer 121, thereby increasing the carrier concentration of the first sublayer 121. Moreover, compared with the first sublayer 121, the second sublayer 122, with its relatively lower mobility, has stable light-transmitting properties, reducing the generation of photogenerated defects and improving the electrical stability of the thin-film transistor 10.

[0102] In some embodiments, as shown in Figures 2 and 3, the optical band gap Eg1 of the material of the first sublayer 121 is smaller than the optical band gap Eg2 of the material of the second sublayer 122, i.e., Eg1 <Eg2。

[0103] For example, the optical band gap Eg1 of the material of the first sublayer 121 is less than or equal to 2.9 eV, that is, Eg1 ≤ 2.9 eV.

[0104] For example, the optical band gap Eg2 of the material of the second sublayer 122 is greater than or equal to 3eV, that is, Eg2≥3eV.

[0105] By setting the optical band gap Eg1 of the material of the first sublayer 121 to be smaller than the optical band gap Eg2 of the material of the second sublayer 122, the second sublayer 122 can have better light-spot stability, which is beneficial to improving the electrical stability of the thin film transistor 10.

[0106] Figure 9 is a cross-sectional microstructure image of a thin-film transistor 10 according to some embodiments, taken using a transmission electron microscope (TEM). Figure 10 is an elemental energy dispersive X-ray spectroscopy (EDX) image of the active layer 12 of the thin-film transistor 10 according to some embodiments. As can be seen from Figure 9, the active layer 12 includes a first sublayer 121 and a second sublayer 122. As shown in Figure 10, the materials of the active layer 12 include indium (In), gallium (Ga), and zinc (Zn). In Figure 10, the reddish-brown color represents indium. The density of indium in the first sublayer 121 is approximately equal to the density of indium in the second sublayer 122; therefore, the indium content in the first sublayer 121 is approximately equal to the indium content in the second sublayer 122. In Figure 10, the purple color represents zinc. The density of zinc in the first sublayer 121 is greater than the density of zinc in the second sublayer 122; therefore, the zinc content in the first sublayer 121 is greater than the zinc content in the second sublayer 122. In Figure 10, blue represents gallium. The gallium density in the first sublayer 121 is less than that in the second sublayer 122. Therefore, the gallium content in the first sublayer 121 is less than that in the second sublayer 122.

[0107] It should be noted that the element content in the embodiments of this disclosure may refer to the mass percentage of the element or the atomic percentage, and may refer to the proportion of the element in the entire film layer.

[0108] For example, the tin content of the first sublayer 121 is greater than the tin content of the second sublayer 122.

[0109] For example, the ratio of the zinc content of the first sublayer 121 to the zinc content of the second sublayer 122 is in the range of 1.1 to 2. For example, the ratio of the zinc content of the first sublayer 121 to the zinc content of the second sublayer 122 is 1.1, 1.2, 1.3, 1.5, 1.5, 1.7, 1.8, 1.9 or 2, etc., and there is no limitation here.

[0110] For example, the ratio of the gallium content of the second sublayer 122 to the gallium content of the first sublayer 121 is in the range of 2 to 5. For example, the ratio of the gallium content of the second sublayer 122 to the gallium content of the first sublayer 121 is 2, 3, 4 or 5, etc., and there is no limitation here.

[0111] By setting different contents of elements such as zinc, gallium, and tin in the first sublayer 121 and the second sublayer 122, the mobility of the first sublayer 121 is set to be higher than that of the second sublayer 122.

[0112] In some examples, as shown in Figure 2, the material of the first sublayer 121 includes at least one of indium gallium oxide, indium tin zinc oxide, and indium gallium zinc tin oxide, and the material of the second sublayer 122 includes indium gallium zinc oxide.

[0113] For example, the atomic ratio of indium gallium zinc oxide in the second sublayer 122 is In:Ga:Zn = 1:1:1.

[0114] When the material of the second sublayer 122 is indium gallium zinc oxide, the material of the second sublayer 122 does not include tin, so that the tin content of the first sublayer 121 is greater than the tin content of the second sublayer 122.

[0115] It should be noted that the material of the second sublayer 122 in the embodiments of this disclosure includes, but is not limited to, indium gallium zinc oxide (IGZO). That is, if there is a material with properties very similar to IGZO, it can also be used to fabricate the second sublayer 122. As long as the second sublayer 122 can work together with the first sublayer 121, which has high mobility, the thin-film transistor 10 can have both high mobility and good electrical stability.

[0116] In some embodiments, as shown in Figures 2, 11, and 12, the thin-film transistor 10 further includes an interlayer dielectric layer 15, which is located on the side of the gate layer 14 away from the substrate 11. The interlayer dielectric layer 15 includes a first interlayer dielectric layer 151 and a second interlayer dielectric layer 152 disposed along a direction away from the substrate 11. The hydrogen atom content of the first interlayer dielectric layer 151 is less than that of the second interlayer dielectric layer 152; the density of the first interlayer dielectric layer 151 is less than that of the second interlayer dielectric layer 152.

[0117] For example, the material of the first interlayer dielectric layer 151 is silicon oxide, and the material of the second interlayer dielectric layer 152 is silicon nitride.

[0118] It should be noted that, as shown in Figure 4, the active layer 12 includes a channel region and a conductive region. For example, the region of the active layer 12 covered by the gate layer 14 is the channel region, and the region of the active layer 12 not covered by the gate layer 14 is the conductive region. By contacting the first interlayer dielectric layer 151, which has a relatively low hydrogen atom content, with the active layer 12, the problem of channel region conductiveization caused by hydrogen atoms entering the active layer 12 can be effectively avoided.

[0119] However, the first interlayer dielectric layer 151, formed by silicon oxide with a relatively low hydrogen atom content, has low density, which can be understood as the first interlayer dielectric layer 151 being porous and easily corroded by water and oxygen. The second interlayer dielectric layer 152, formed by silicon nitride, has better density and stronger barrier ability against water and oxygen. By including the second interlayer dielectric layer 152 in the interlayer dielectric layer 15, the barrier ability of the interlayer dielectric layer 15 against water and oxygen is improved.

[0120] In some embodiments, as shown in FIG12, the thin film transistor 10 further includes: a first via H1, the first via H1 penetrating the interlayer dielectric layer 15; the first via H1 includes: a first hole H11 penetrating the first interlayer dielectric layer 151 and a second hole H12 penetrating the second interlayer dielectric layer 152; wherein, the boundary L1 of the first interlayer dielectric layer 151 surrounding the first hole H1 is located inside the boundary L2 of the second interlayer dielectric layer 152 surrounding the second hole H12.

[0121] In other words, the wall of the first via H1 is stepped at the interlayer dielectric layer 15. Since the second interlayer dielectric layer 152 is easier to etch, when the first interlayer dielectric layer 151 and the second interlayer dielectric layer 152 are formed, the second interlayer dielectric layer 152 will shrink inward relative to the first interlayer dielectric layer 151, so that the wall of the first via H1 is stepped at the interlayer dielectric layer 15.

[0122] As can be seen from the above description of the source / drain metal layer 16, the source 161 and the drain 162 are connected to the active layer 12 through the first via H1 that penetrates the interlayer dielectric layer 15. The wall of the first via H1 is stepped at the interlayer dielectric layer 15, which facilitates the deposition of the source / drain metal layer 16 in the first via H1 and is beneficial to the overlap of the source 161 and the drain 162 with the active layer 12.

[0123] In some examples, as shown in Figures 11 and 12, the distance d7 between the boundary L1 of the first interlayer dielectric layer 151 and the boundary L2 of the second interlayer dielectric layer 152 in the orthographic projection onto the substrate 11 ranges from 0.5 μm to 1.5 μm.

[0124] For example, in the orthographic projection onto the substrate 11, the distance d7 between the boundary L1 of the first interlayer dielectric layer 151 and the boundary L2 of the second interlayer dielectric layer 152 is 0.5μm, 0.6μm, 0.8μm, 0.9μm, 1.0μm, 1.3μm or 1.5μm, etc., and there is no limitation here.

[0125] In the orthographic projection onto the substrate 11, the distance d7 between the boundary L1 of the first interlayer dielectric layer 151 and the boundary L2 of the second interlayer dielectric layer 152 ranges from 0.5 μm to 1.5 μm, which is beneficial for the overlap of the source electrode 161 and the drain electrode 162 with the active layer 12.

[0126] In some embodiments, as shown in Figures 11 and 12, the second interlayer dielectric layer 152 has a first surface m3 close to the substrate 11 and a second surface m4 away from the substrate 11, and the first surface m3 of the second interlayer dielectric layer 152 is recessed relative to the second surface m4 of the second interlayer dielectric layer 152.

[0127] In other words, in the second direction X, the size of the first surface m3 of the second interlayer dielectric layer 152 is smaller than the size of the second surface m4 of the second interlayer dielectric layer 152. The second direction X is parallel to the plane containing the substrate 11.

[0128] For example, the connection between the boundary L2 of the second interlayer dielectric layer 152 and the first surface m3 of the second interlayer dielectric layer 152 is arc-shaped K, that is, the connection between the side surface of the second interlayer dielectric layer 152 and the first surface m3 of the second interlayer dielectric layer 152 is an arc-shaped surface.

[0129] In some embodiments, as shown in FIG2, the gate layer 14 covers the gate insulating layer 13.

[0130] For example, the gate insulating layer 13 can be formed using the gate layer 14 as a mask, and the active layer 12 can be made conductive. For details, please refer to the description of the fabrication method of the array substrate 100, which will not be elaborated here.

[0131] In some embodiments, as shown in FIG2, the source / drain metal layer 16 is located on the side of the active layer 12 away from the substrate 11, and the source / drain metal layer 16 is connected to the second sub-layer 122.

[0132] In other words, the thin-film transistor 10 shown in Figure 2 is a top-gate top-contact thin-film transistor 10.

[0133] In other embodiments, as shown in FIG13, the source / drain metal layer 16 is located on the side of the active layer 12 near the substrate 11, and the source / drain metal layer 16 is connected to the first sublayer 121.

[0134] In other words, the thin-film transistor 10 shown in Figure 2 is a top-gate bottom-contact thin-film transistor 10.

[0135] By configuring the active layer 12 to include a first sub-layer 121 and a second sub-layer 122 located on the side of the first sub-layer 121 away from the substrate 11, and the mobility of the first sub-layer 121 is higher than that of the second sub-layer 122, and the average thickness d1 of the first sub-layer 121 is less than the average thickness d2 of the second sub-layer 122, a thin-film transistor 10 with high mobility and good electrical stability can be obtained. The thin-film transistor 10 can be a top-gate top-contact structure thin-film transistor 10 or a top-gate bottom-contact structure thin-film transistor 10.

[0136] As shown in FIG2, some embodiments of the present disclosure also provide an array substrate 100, the array substrate 100 including: a substrate 11 and a plurality of thin film transistors 10 disposed on the substrate 11, wherein at least one of the plurality of thin film transistors 10 is a thin film transistor 10 as described in any of the above embodiments.

[0137] In some embodiments, as shown in FIG2, the array substrate 100 further includes a light-shielding layer 17 and a buffer layer 18, wherein the light-shielding layer 17 is located on the side of the active layer 12 near the substrate 11, and the buffer layer 18 is located between the active layer 12 and the light-shielding layer 17.

[0138] The light-shielding layer 17 can protect the active layer 12 of the thin-film transistor 10 from the influence of ambient light.

[0139] In some embodiments, as shown in Figures 2 and 3, the thin-film transistor 10 further includes a gate insulating layer 13 located between the active layer 12 and the gate layer 14. The average thickness d8 of the buffer layer 18 between the light-shielding layer 17 and the active layer 12 is greater than the average thickness d9 of the gate insulating layer 13, i.e., d8 > d9.

[0140] It is understood that the thickness of the buffer layer 18 between the light-shielding layer 17 and the active layer 12 is the dimension of the buffer layer 18 between the light-shielding layer 17 and the active layer 12 in the direction Y perpendicular to the substrate 11. The thickness of the gate insulating layer 13 is the dimension of the gate insulating layer 13 in the direction Y perpendicular to the substrate 11.

[0141] The light-shielding layer 17 has an electric field strength, which is less than that of the gate layer 14. By setting the average thickness d8 of the buffer layer 18 between the light-shielding layer 17 and the active layer 12 to be greater than the average thickness d9 of the gate insulating layer 13, the influence of the electric field strength of the light-shielding layer 17 on the position of the first conductive channel 12a is reduced. The position of the first conductive channel 12a is mainly affected by the electric field strength of the gate layer 14 and the mobility and average thickness of the first sub-layer 121 and the second sub-layer 122, thereby maintaining the position of the first conductive channel 12a near the interface between the first sub-layer 121 and the second sub-layer 122, thus improving the mobility and electrical stability of the thin-film transistor 10.

[0142] In some embodiments, as shown in FIG2, the array substrate 100 further includes: a first passivation layer 19, a planarization layer 21, a first electrode layer 22, a second passivation layer 23, and a second electrode layer 24. The first passivation layer 19 is located on the side of the source / drain metal layer 16 away from the substrate 11, and the planarization layer 21 is located on the side of the first passivation layer 19 away from the substrate 11. The first electrode layer 22 is located on the side of the planarization layer 21 away from the substrate 11, and the first electrode layer 22 can be a common electrode. The second passivation layer 23 is located on the side of the first electrode layer 22 away from the substrate 11, and the second electrode layer 24 is located on the side of the second passivation layer 23 away from the substrate 11. The second electrode layer 24 is connected to the drain 162 through a second via H2 penetrating the second passivation layer 23, the planarization layer 21, and the first passivation layer 19.

[0143] In some embodiments, as shown in FIG2, the electrical stability of the thin-film transistor 10 can be improved by enhancing the passivation capability of the gate insulating layer 13.

[0144] Since the gate insulating layer 13 with high passivation capability has relatively few interface defects, the capture of carriers in the first conductive channel 12a by the interface defects of the gate insulating layer 13 can be reduced, so that the first conductive channel 12a maintains a high carrier concentration and improves the electrical stability of the thin film transistor 10.

[0145] In some embodiments, as shown in FIG2, the size of the channel region of the thin-film transistor 10 can be increased by increasing the size of the thin-film transistor 10. Increasing the size of the channel region can reduce the current density and improve the electrical stability of the thin-film transistor 10.

[0146] As shown in Figure 14, an embodiment of this disclosure provides a method for fabricating an array substrate, the method comprising steps R1 to R12.

[0147] R1, as shown in Figure 15, provides a substrate 11.

[0148] For example, the substrate 11 includes, but is not limited to, a glass substrate. The embodiments of this disclosure are described with glass as an example.

[0149] R2, as shown in Figure 15, a light-shielding layer 17 is formed on one side of the substrate 11.

[0150] For example, the step of forming the light-shielding layer 17 includes: forming a light-shielding metal layer on the substrate 11, and patterning the light-shielding metal layer to form the final light-shielding layer 17. The method of forming the light-shielding layer 17 includes, but is not limited to, magnetron sputtering, and the patterning method includes, but is not limited to, photolithography, imprinting, etc. The etching and transfer method is not limited to wet etching, dry reaction, etc.

[0151] It should be noted that, since the thin-film transistor 10 in this embodiment is a top-gate thin-film transistor, a light-shielding layer 17 needs to be fabricated to ensure that the active layer 12 of the thin-film transistor 10 is not affected by ambient light. The material of the light-shielding layer 17 includes, but is not limited to, molybdenum-Mo alloys and corresponding copper-Cu and aluminum-Al composite metal structures.

[0152] R3, as shown in Figure 15, a buffer layer 18 is formed on the side of the light-shielding layer 17 away from the substrate 11.

[0153] For example, the material of the buffer layer 18 is silicon oxide, or a composite film of silicon nitride and silicon oxide, and the thickness of the buffer layer 18 is 200nm to 500nm. For example, the thickness of the buffer layer 18 is 200nm, 300nm, 400nm or 500nm, etc., and there is no limitation here.

[0154] For example, as shown in Figures 11 and 12, the buffer layer 18 includes a first film layer 181 and a second film layer 182, wherein the material of the first film layer 181 is silicon oxide and the material of the second film layer 182 is silicon nitride.

[0155] The first film layer 181 formed of silicon oxide is porous and easily corroded by water and oxygen. The second film layer 182 formed of silicon nitride has a strong barrier to water and oxygen. The buffer layer 18, including the first film layer 181 and the second film layer 182, improves the barrier to water and oxygen.

[0156] R4, as shown in Figure 15, an active layer 12 is formed on the side of the buffer layer 18 away from the substrate 11.

[0157] For example, the active layer 12 includes a first sublayer 121 and a second sublayer 122 located on the side of the first sublayer 121 away from the substrate 11.

[0158] For example, the material of the first sublayer 121 includes at least one of indium gallium oxide, indium tin zinc oxide, and indium gallium zinc tin oxide. The material of the second sublayer 122 is indium gallium zinc oxide, and the atomic ratio of indium gallium zinc oxide is In:Ga:Zn = 1:1:1. The mobility of the first sublayer 121 is greater than that of the second sublayer 122, and the average thickness of the first sublayer 121 is less than that of the second sublayer 122. This improves the mobility of the thin-film transistor 10 while enhancing its stability under electrical stress.

[0159] It should be noted that the material of the second sublayer 122 in this embodiment includes, but is not limited to, indium gallium zinc oxide (IGZO). That is, if there is a material with properties very similar to IGZO, it can also be used to fabricate the second sublayer 122. As long as the second sublayer 122 can work together with the first sublayer 121, which has high mobility, to improve the mobility of the thin-film transistor 10 and enhance the stability of the thin-film transistor 10 under electrical stress, it is acceptable.

[0160] In some examples, the average thickness d1 of the first sublayer 121 ranges from 5 nm to 25 nm. For example, the average thickness of the first sublayer 121 may be 5 nm, 10 nm, 15 nm, 20 nm, or 25 nm, etc., and no limitation is set here. The average thickness d2 of the second sublayer 122 ranges from 30 nm to 50 nm. For example, the average thickness of the second sublayer 122 may be 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm, etc., and no limitation is set here.

[0161] In some examples, the steps of forming the active layer 12 include: forming a first conductive layer and a second conductive layer stacked on the side of the buffer layer 18 away from the substrate 11, patterning the first conductive layer and the second conductive layer to form a first sublayer 121 and a second sublayer 122, wherein the first sublayer 121 and the second sublayer 122 form the final active layer 12.

[0162] In some examples, the step of forming the active layer 12 also includes depositing a channel, which can be achieved by magnetron sputtering to deposit an indium tin zinc oxide layer with an average thickness of 30 nm as the channel of the thin film transistor 10, and then annealing the channel to obtain the active layer 12.

[0163] R5. As shown in Figure 15, a gate insulating layer 13 is formed on the side of the active layer 12 away from the substrate 11, and a gate layer 14 is formed on the side of the gate insulating layer 13 away from the substrate 11.

[0164] For example, the steps of forming the gate insulating layer 13 and the gate layer 14 include: forming a first insulating layer on the side of the active layer 12 away from the substrate 11, forming a gate metal layer on the side of the first insulating layer away from the substrate 11, and patterning the gate metal layer to form the gate layer 14. The first insulating layer is etched using the gate layer 14 as a mask to form the gate insulating layer 13, with the gate insulating layer 13 exposing a portion of the active layer 12. The portion of the active layer 12 exposed by the gate insulating layer 13 is then conductiveized. Specifically, the conductiveization process may be performed using plasma of at least one gas selected from helium (He), argon (Ar), hydrogen (H2), and ammonia (NH3).

[0165] By removing all the gate insulating layer 13 around the gate layer 14 and performing a conductor treatment on the exposed active layer 12, a thin-film transistor 10 with a self-aligned gate layer 14 and conductive channel can be obtained. This simplifies the process steps, improves the reliability of the thin-film transistor 10 fabrication, and helps to reduce the size of the thin-film transistor 10.

[0166] For example, the gate layer 14 may include a buffer dielectric layer, a main conductive layer, and a top protective layer stacked together. Specifically, the buffer dielectric layer is located on the side closest to the substrate 11, and the material of the buffer dielectric layer includes, but is not limited to, titanium (Ti) and molybdenum (Mo) based alloys, the material of the main conductive layer includes, but is not limited to, at least one of aluminum (Al) and copper (Cu), and the material of the top protective layer includes, but is not limited to, titanium (Ti) and molybdenum (Mo) based alloys.

[0167] For example, the material of the gate insulating layer 13 includes silicon oxide, and the average thickness of the gate insulating layer 13 ranges from 10 nm to 30 nm. For example, the average thickness of the gate insulating layer 13 is 10 nm, 15 nm, 20 nm, 25 nm or 30 nm, etc., and there is no limitation here.

[0168] R6. As shown in Figure 15, an interlayer dielectric layer 15 is formed on the side of the gate layer 14 away from the substrate 11.

[0169] For example, an interlayer dielectric layer 15 is deposited on the side of the gate layer 14 away from the substrate 11. The material of the interlayer dielectric layer 15 includes, but is not limited to, silicon oxide, or a composite film of silicon nitride and silicon oxide.

[0170] For example, the average thickness of the interlayer dielectric layer 15 ranges from 300 nm to 600 nm. For instance, the average thickness of the interlayer dielectric layer 15 is 300 nm, 350 nm, 400 nm, 450 nm, or 500 nm, etc., and there is no limitation here.

[0171] For example, photolithography and etching are performed on the interlayer dielectric layer 15 to form a first via H1 that exposes a portion of the active layer 12.

[0172] R7, as shown in Figure 15, forms the source / drain metal layer 16.

[0173] For example, the source 161 and drain 162 of the thin film transistor 10 are located in the source-drain metal layer 16.

[0174] For example, source 161 and drain 162 are connected to active layer 12 through different first vias H1 through interlayer dielectric layer 15.

[0175] R8, as shown in Figure 15, a first passivation layer 19 is formed on the side of the source / drain metal layer 16 away from the substrate 11.

[0176] For example, the material of the first passivation layer 19 includes silicon oxide. The average thickness of the first passivation layer 19 ranges from 300 nm to 400 nm, for example, the average thickness of the first passivation layer 19 is 300 nm, 320 nm, 340 nm, 360 nm or 400 nm, etc., and there is no limitation here.

[0177] R9, as shown in Figure 16, a planarization layer 21 is formed on the side of the first passivation layer 19 away from the substrate 11.

[0178] For example, a second via H21 is provided on the planarization layer 21, and in the orthographic projection onto the substrate 11, the second via H21 overlaps with the drain 162 of the thin film transistor 10.

[0179] R10, as shown in Figure 16, forms a first electrode layer 22 on the side of the planarization layer 21 away from the substrate 11.

[0180] For example, the material of the first electrode layer 22 is a transparent conductive material, such as indium tin oxide.

[0181] For example, the first electrode layer 22 can be a common electrode.

[0182] R11, as shown in Figure 16, a second passivation layer 23 is formed on the side of the first electrode layer 22 away from the substrate 11.

[0183] For example, a second via H2 is formed that penetrates the second passivation layer 23 and the first passivation layer 19, and the second via H2 also penetrates the planarization layer 21. The second via H2 overlaps with the second via H21. The second via H2 exposes a portion of the drain 162.

[0184] R12, as shown in Figure 2, a second electrode layer 24 is formed on the side of the second passivation layer 23 away from the substrate 11 to obtain the array substrate 100.

[0185] For example, the second electrode layer 24 is connected to the drain electrode 162 through a second via H2 that penetrates the second passivation layer 23, the planarization layer 21 and the first passivation layer 19.

[0186] For example, the second electrode layer 24 is a pixel electrode, which is connected to the drain 162 and forms an electric field with the first electrode layer 22 (common electrode) in a slit shape.

[0187] The embodiments of this disclosure fabricate an array substrate 100 comprising a first sublayer 121 and a second sublayer 122 for the active layer 12 of a thin-film transistor 10 through the aforementioned steps R1 to R12. The thin-film transistor 10 is configured such that the mobility of the first sublayer 121 is greater than that of the second sublayer 122, and the average thickness d1 of the first sublayer 121 is less than the average thickness d2 of the second sublayer 122. A portion of the first conductive channel 12a is located in the first sublayer 121 with higher mobility, which facilitates carrier transport. Furthermore, the second sublayer 122 can provide carriers to the first sublayer 121, thereby giving the thin-film transistor 10 a higher mobility. Moreover, the first conductive channel 12a can be relatively far from the gate insulating layer 13, reducing the trapping of carriers in the first conductive channel 12a by interface defects in the gate insulating layer 13, thus maintaining a high carrier concentration in the first conductive channel 12a. This improves the electrical stability of the thin-film transistor 10, thereby extending its switching capability and lifespan. Therefore, the embodiments of this disclosure improve the electrical stability of the thin-film transistor 10 while ensuring that the thin-film transistor 10 has a high mobility, thereby achieving the purpose of extending the switching capability and service life of the thin-film transistor 10.

[0188] The array substrate 100 includes the thin-film transistor 10 provided in any of the above embodiments. Therefore, the array substrate 100 provided in this disclosure has all the beneficial effects of the thin-film transistor 10 provided in any of the above embodiments, which will not be elaborated here.

[0189] As shown in FIG17, some embodiments of the present disclosure also provide a display panel 1000, the display panel 1000 including the array substrate 100 as described in any of the above embodiments, the display panel 1000 also including a plurality of light-emitting devices 200, and the array substrate 100 being used to drive the plurality of light-emitting devices 200 to emit light.

[0190] For example, as shown in FIG17, the array substrate 100 further includes multiple scan signal lines GL and multiple data signal lines DL, which are connected to multiple thin-film transistors 10.

[0191] For example, the array substrate 100 includes a plurality of pixel driving circuits 101, and the pixel driving circuits 101 include a plurality of thin film transistors 10, for example, the thin film transistors 10 include driving transistors. The driving transistors are connected to the light-emitting device 200 and are used to drive the light-emitting device 200 to emit light.

[0192] For example, the array substrate 100 further includes: multiple light emission control lines EL, multiple initialization signal lines Vinit, and multiple first voltage signal lines VDD. The scan signal line GL, data signal line DL, light emission control line EL, initialization signal line Vinit, and first voltage signal line VDD are connected to the pixel driving circuit 101. The scan signal line GL, data signal line DL, light emission control line EL, initialization signal line Vinit, and first voltage signal line VDD are used to provide electrical signals to the pixel driving circuit 101 so that the pixel driving circuit 101 drives the light emission device 200 to emit light.

[0193] The display panel 1000 includes the array substrate 100 provided in any of the above embodiments. Therefore, the display panel 1000 provided in this disclosure has all the beneficial effects of the array substrate 100 provided in any of the above embodiments, which will not be elaborated here.

[0194] As shown in FIG18, some embodiments of the present disclosure also provide another display panel 1000, the display panel 1000 including the array substrate 100 as described in any of the above embodiments, the display panel 1000 further including: a counter substrate 300 and a liquid crystal layer 400, the counter substrate being opposite to and spaced apart from the array substrate 100, and the liquid crystal layer 400 being disposed between the array substrate 100 and the counter substrate 300.

[0195] For example, liquid crystal material is disposed in liquid crystal layer 400. The opposing substrate 300 is, for example, a color filter substrate. The array substrate 100 realizes the display operation of display panel 1000 by controlling the degree of rotation of liquid crystal material.

[0196] The display panel 1000 includes the array substrate 100 provided in any of the above embodiments. Therefore, the display panel 1000 provided in this disclosure has all the beneficial effects of the array substrate 100 provided in any of the above embodiments, which will not be elaborated here.

[0197] As shown in Figure 19, some embodiments of this disclosure provide a display device 2000, which includes a display panel 1000 as described in any of the above embodiments. The display device 2000 also includes a driver chip for driving the display panel 1000 to perform display.

[0198] As shown in Figure 19, the display device 2000 can be any device that displays either moving (e.g., video) or stationary (e.g., still images) text or images. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones (e.g., cell phones), wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 19 illustrates the display device 2000 as a cell phone.

[0199] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A thin film transistor, comprising: an active layer located on one side of a substrate, and a gate layer located on a side of the active layer away from the substrate; wherein the active layer comprises a first sub-layer and a second sub-layer located on a side of the first sub-layer away from the substrate, the first sub-layer has a higher mobility than the second sub-layer, and the first sub-layer has a smaller average thickness than the second sub-layer.

2. The thin film transistor according to claim 1, wherein, The ratio of the average thickness of the first sub-layer to the average thickness of the second sub-layer ranges from 0.1 to 0.

85.

3. The thin film transistor according to claim 2, wherein, The average thickness of the first sub-layer ranges from 5 nm to 25 nm.

4. The thin film transistor according to claim 3, wherein, The average thickness of the second sub-layer ranges from 30 nm to 50 nm.

5. The thin film transistor according to any one of claims 1 to 4, wherein The mobility of the first sub-layer is greater than or equal to 20 cm 2 / V*s.

6. The thin film transistor according to claim 4, wherein, The mobility of the second sub-layer ranges from 5 cm 2 / V*s ~ 15 cm 2 / V*s.

7. The thin film transistor according to any one of claims 1 to 6, wherein The material of the first sub-layer has a smaller optical band gap than the material of the second sub-layer.

8. The thin film transistor according to any one of claims 1 to 7, wherein The material of the first sub-layer has an optical band gap less than or equal to 2.9 eV.

9. The thin film transistor according to claim 8, wherein, The material of the second sub-layer has an optical band gap greater than or equal to 3 eV.

10. The thin film transistor according to any one of claims 1 to 9, wherein The first sub-layer and the second sub-layer satisfy at least one of the following conditions: The first sub-layer has a greater zinc content than the second sub-layer; The first sub-layer has a smaller gallium content than the second sub-layer; The first sub-layer has a greater tin content than the second sub-layer.

11. The thin film transistor according to claim 10, wherein, The ratio of the zinc content of the first sub-layer to the zinc content of the second sub-layer ranges from 1.1 to 2; and / or, the ratio of the gallium content of the second sub-layer to the gallium content of the first sub-layer ranges from 2 to 5.

12. The thin film transistor according to any one of claims 1 to 11, wherein The material of the first sub-layer comprises at least one of indium gallium oxide, indium tin zinc oxide, and indium gallium zinc tin oxide; and / or, the material of the second sub-layer comprises indium gallium zinc oxide.

13. The thin film transistor according to any one of claims 1 to 12, further comprising: an interlayer dielectric layer located on a side of the gate layer away from the substrate; The interlayer dielectric layer comprises a first interlayer dielectric layer and a second interlayer dielectric layer arranged in a direction away from the substrate; wherein the first interlayer dielectric layer has a smaller content of hydrogen atoms than the second interlayer dielectric layer, and the first interlayer dielectric layer has a smaller density than the second interlayer dielectric layer.

14. The thin film transistor of claim 13, further comprising: a first via penetrating the interlayer dielectric layer; The first via comprises a first hole penetrating the first interlayer dielectric layer and a second hole penetrating the second interlayer dielectric layer; wherein the boundary of the first hole formed by the first interlayer dielectric layer is located inside the boundary of the second hole formed by the second interlayer dielectric layer.

15. The thin film transistor according to claim 14, wherein, The distance between the boundary of the first hole formed by the first interlayer dielectric layer and the boundary of the second hole formed by the second interlayer dielectric layer ranges from 0.5 μm to 1.5 μm.

16. The thin film transistor according to any one of claims 1 to 15, further comprising: a source-drain metal layer; The source-drain metal layer is located on a side of the active layer away from the substrate, and the source-drain metal layer is connected to the second sub-layer; or, The source-drain metal layer is located on a side of the active layer close to the substrate, and the source-drain metal layer is connected to the first sub-layer. 17.An array substrate, comprising: a substrate; a plurality of thin film transistors arranged on the substrate, wherein at least one of the plurality of thin film transistors is the thin film transistor according to any one of claims 1 to 16. ​ 18. The array substrate of claim 17, further comprising: A light-blocking layer between the substrate and an active layer of the thin film transistor, and a buffer layer between the light-blocking layer and the active layer; The thin film transistor comprises a gate insulating layer between the active layer and a gate layer of the thin film transistor; The average thickness of the part of the buffer layer between the light-blocking layer and the active layer is greater than the average thickness of the gate insulating layer.

19. A display panel comprising: The array substrate of claim 17 or 18; An opposite substrate arranged opposite and spaced apart from the array substrate; A liquid crystal layer arranged between the array substrate and the opposite substrate.

20. A display panel comprising: The array substrate of claim 17 or 18; A plurality of light emitting devices arranged on the array substrate, the array substrate being configured to drive the plurality of light emitting devices to emit light.

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