Chip and electronic device

Abstract

Provided in the present application are a chip and an electronic device. The chip comprises: at least two power amplification paths, each of the power amplification paths comprising a signal input terminal, a power amplification module, a boost module and a signal output terminal, wherein, in each power amplification path, the signal input terminal is connected to a first input terminal of the power amplification module, the signal output terminal is connected to an output terminal of the power amplification module, an output terminal of the boost module is connected to a second input terminal of the power amplification module, and the boost module is used for supplying power to the power amplification module; and a system control module, a control terminal of the system control module being connected to a control terminal of the power amplification module of each power amplification path, and being used for controlling the power amplification module to amplify an input signal.

Description

Chip and electronic device

[0001] Cross Reference to Related Applications

[0002] The present application claims priority to Chinese Patent Application No. 202410974339.5, filed on July 19, 2024, the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the field of communication technology, and in particular to a chip and an electronic device. BACKGROUND

[0004] With the popularity of electronic devices, the functions of electronic devices are becoming more and more perfect. The power amplifier (PA) is an important module of the electronic device, which can be used to drive passive devices such as loudspeakers. With the increase of devices that need to be driven in the electronic device, multiple PA chips need to be arranged in the electronic device, and each PA chip can be used to drive a passive device. The stacked PA chips in the electronic device occupy a lot of space of the electronic device, so that the available space of the electronic device is small. SUMMARY

[0005] The embodiments of the present application provide a chip and an electronic device, which can solve the problem that the stacked PA chips in the electronic device occupy a lot of space of the electronic device, so that the available space of the electronic device is small.

[0006] In a first aspect, the embodiments of the present application provide a chip, comprising:

[0007] At least two power amplification paths, each of the power amplification paths comprising a signal input end, a power amplification module, a voltage boosting module and a signal output end; wherein in each of the power amplification paths, the signal input end is connected with a first input end of the power amplification module, the signal output end is connected with an output end of the power amplification module, an output end of the voltage boosting module is connected with a second input end of the power amplification module, and the voltage boosting module is used to supply power for the power amplification module;

[0008] A system control module, a control end of the system control module is connected with a control end of the power amplification module of each of the power amplification paths, and the system control module is used to control the power amplification module to amplify the input signal.

[0009] In a second aspect, the embodiments of the present application provide an electronic device, comprising the chip of the first aspect.

[0010] In the embodiment of the present application, the chip comprises: at least two power amplification channels, each of the power amplification channels comprising a signal input end, a power amplification module, a voltage boosting module and a signal output end; wherein in each of the power amplification channels, the signal input end is connected with a first input end of the power amplification module, the signal output end is connected with an output end of the power amplification module, an output end of the voltage boosting module is connected with a second input end of the power amplification module, and the voltage boosting module is used to supply power for the power amplification module; and a system control module, a control end of the system control module being connected with control ends of the power amplification modules of each of the power amplification channels respectively, and used to control the power amplification modules to amplify the input signals. In this way, by integrating at least two power amplification channels, the function of at least two PA chips can be realized by one chip, and compared with stacking multiple PA chips in the electronic device, the available space of the electronic device can be increased; further, at least two power amplification channels share one system control module, and the chip cost can be reduced.

[0011] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0012] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the appended drawings.

[0013] Fig. 1 is one of structural schematic diagrams of a chip provided by an embodiment of the present application;

[0014] Fig. 2 is another of structural schematic diagrams of a chip provided by an embodiment of the present application;

[0015] Fig. 3 is a third of structural schematic diagrams of a chip provided by an embodiment of the present application;

[0016] Fig. 4 is a fourth of structural schematic diagrams of a chip provided by an embodiment of the present application;

[0017] Fig. 5 is one of structural schematic diagrams of an electronic device in the related art;

[0018] Fig. 6 is another of structural schematic diagrams of an electronic device in the related art;

[0019] Fig. 7 is one of structural schematic diagrams of a dual-speaker system in the related art;

[0020] Fig. 8 is another of structural schematic diagrams of a dual-speaker system in the related art;

[0021] Fig. 9 is one of structural schematic diagrams of a chip in the related art;

[0022] FIG. 10 is a structural schematic diagram of a chip in the related art;

[0023] FIG. 11 is a structural schematic diagram of a PA chip provided by an embodiment of the present application;

[0024] FIG. 12 is a voltage schematic diagram of a PVDD power supply provided by an embodiment of the present application;

[0025] FIG. 13 is a schematic diagram of PA output distortion provided by an embodiment of the present application;

[0026] FIG. 14 is a schematic diagram of total PA efficiency provided by an embodiment of the present application;

[0027] FIG. 15 is a structural schematic diagram of a PA chip provided by an embodiment of the present application;

[0028] FIG. 16 is a structural schematic diagram of a PA chip provided by an embodiment of the present application;

[0029] FIG. 17 is a structural schematic diagram of a PA chip provided by an embodiment of the present application;

[0030] FIG. 18 is a voltage schematic diagram of a PVDD power supply provided by an embodiment of the present application;

[0031] FIG. 19 is a schematic diagram of PA output distortion provided by an embodiment of the present application;

[0032] FIG. 20 is a schematic diagram of total PA efficiency provided by an embodiment of the present application;

[0033] FIG. 21 is a structural schematic diagram of a PA chip provided by an embodiment of the present application;

[0034] FIG. 22 is a structural schematic diagram of a PA chip provided by an embodiment of the present application. DETAILED DESCRIPTION

[0035] Embodiments of the present application will be described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application, and cannot be understood as a limitation of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0036] The terms "first", "second" in the description and claims of the present application can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified. In addition, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / ", generally indicates that the front and rear associated objects are in an "or" relationship.

[0037] In the description of the present application, it should be understood that the terms "length", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0038] In the description of the present application, it should be noted that unless otherwise specified and limited, the term "connection" should be understood broadly, for example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above-mentioned terms in the present application can be understood according to the specific circumstances.

[0039] The chip and electronic device provided by the embodiments of the present application will be described in detail below in combination with the drawings and specific embodiments and their application scenarios.

[0040] As shown in FIG. 1, the present application provides a chip, which comprises:

[0041] At least two power amplification paths 10, each of the power amplification paths 10 comprises a signal input end, a power amplification module 101, a voltage boosting module 102 and a signal output end; wherein in each of the power amplification paths 10, the signal input end is connected with a first input end of the power amplification module 101, the signal output end is connected with an output end of the power amplification module 101, an output end of the voltage boosting module 102 is connected with a second input end of the power amplification module 101, and the voltage boosting module 102 is used for supplying power to the power amplification module 101;

[0042] A system control module 11, the control end of the system control module 11 is connected with the control end of the power amplification module 101 of each of the power amplification paths 10, respectively, for controlling the power amplification module 101 to amplify and process the input signal.

[0043] The boost module 102 can include a charge pump boost module, a BOOST boost module, or other types of circuit modules that can implement a boost function, and the embodiments of the present application do not limit the type of the boost module 102. The types of the boost module 102 in the at least two power amplification paths 10 can be the same, or can be partially different, or can all be different, and the embodiments of the present application do not limit this.

[0044] In addition, the power amplification module 101 can be a Class D amplifier, or can be a Class AB amplifier, or can be other types of amplifiers, and the embodiments of the present application do not limit the type of the power amplification module 101.

[0045] In addition, the system control module 11 can control the power amplification module 101 through an Inter-Integrated Circuit (IIC or I2C) or other General-purpose input / output (GPIO) control mode. The control end of the system control module 11 can include at least two first control ends, which correspond one-to-one to the at least two power amplification paths 10. Each first control end is connected to the power amplification module 101 of the corresponding power amplification path 10, for controlling the corresponding power amplification module 101 to amplify the input signal.

[0046] In addition, the chip can also include a power input end, which is connected to the input end of the boost module 102 of each power amplification path 10. One input power is shared by multiple power amplification paths 10 to realize multiplexing of the input power; or each power amplification path 10 can include a power input end, which is connected to the input end of the boost module 102. Each power amplification path 10 uses an independent power input.

[0047] In addition, the chip can also include a reset module, the output end of which is connected to the first input end of the system control module 11. The reset module is used for resetting the at least two power amplification paths 10. One reset module is shared by multiple power amplification paths 10 to realize multiplexing of the reset module; or each power amplification path 10 can include a reset module, and the reset module of each power amplification path 10 is connected to the system control module 11. Each power amplification path 10 uses an independent reset module.

[0048] In addition, the power amplification channel 10 can further comprise an input buffer module, in each of the power amplification channel 10, the signal input end is connected with the first input end of the power amplification module 101 through the input buffer module; or, the signal input end can be directly connected with the first input end of the power amplification module 101; or, the signal input end can be connected with the first input end of the power amplification module 101 through other preprocessing modules; the embodiment is not limited in this regard.

[0049] In addition, the power amplification channel 10 can further comprise an electromagnetic interference (EMI) suppression module, in each of the power amplification channel 10, the output end of the power amplification module 101 is connected with the signal output end through the EMI suppression module; or, the output end of the power amplification module 101 can be directly connected with the signal output end; or, the output end of the power amplification module 101 can be connected with the signal output end through other post-processing modules; the embodiment is not limited in this regard.

[0050] In addition, the chip can further comprise an address configuration module, the output end of the reset module is connected with the first input end of the system control module 11, and the output end of the address configuration module is connected with the second input end of the system control module 11; the address configuration module is used for configuring an integrated circuit bus I2C address for the at least two power amplification channels 10, a plurality of power amplification channels 10 share one address configuration module, and multiplexing of the address configuration module is realized; or, each of the power amplification channels 10 can comprise one address configuration module, the address configuration module of each power amplification channel 10 is connected with the system control module 11, and each power amplification channel 10 uses an independent address configuration module.

[0051] Additionally, the chip can further include an audio digital signal processing module and a digital-to-analog conversion module, an output end of the audio digital signal processing module being connected with an input end of the digital-to-analog conversion module, and an output end of the digital-to-analog conversion module being connected with a first input end of the power amplification module 101 in each of the power amplification channels 10; or, the chip can further include an audio digital signal processing module, a digital-to-analog conversion module, an analog-to-digital conversion module and a data collector, the audio digital signal processing module, the digital-to-analog conversion module, the analog-to-digital conversion module and the data collector being shared by the plurality of power amplification channels 10; or, each of the power amplification channels 10 can include independent audio digital signal processing modules, digital-to-analog conversion modules, analog-to-digital conversion modules and data collectors, in each of the power amplification channels 10, the signal input end being connected with an input end of the audio digital signal processing module, an output end of the audio digital signal processing module being connected with an input end of the digital-to-analog conversion module, an output end of the digital-to-analog conversion module being connected with a first input end of the power amplification module 101, an output end of the power amplification module 101 being connected with an input end of the analog-to-digital conversion module, and an output end of the analog-to-digital conversion module being connected with the data collector.

[0052] In the embodiment of the present application, the chip includes: at least two power amplification channels 10, each of the power amplification channels 10 including a signal input end, a power amplification module 101, a voltage boosting module 102 and a signal output end; wherein, in each of the power amplification channels 10, the signal input end is connected with a first input end of the power amplification module 101, the signal output end is connected with an output end of the power amplification module 101, an output end of the voltage boosting module 102 is connected with a second input end of the power amplification module 101, and the voltage boosting module 102 is used to supply power to the power amplification module 101; a system control module 11, a control end of the system control module 11 being connected with control ends of the power amplification modules 101 of each of the power amplification channels 10 respectively, and being used to control the power amplification modules 101 to amplify and process the input signals. In this way, by integrating at least two power amplification channels, the function of at least two PA chips can be realized by one chip, and compared with stacking multiple PA chips in an electronic device, the available space of the electronic device can be increased; further, at least two power amplification channels share one system control module, and the cost of the chip can be reduced.

[0053] Optionally, the voltage boosting module 102 is a charge pump voltage boosting module or a BOOST voltage boosting module.

[0054] The voltage boosting module 102 can provide voltage for the power amplification module 101, and the voltage boosting module 102 can be used to boost the voltage input by the power supply input end 12 and provide the boosted voltage to the power amplification module 101 to supply power to the power amplification module 101.

[0055] For example, as shown in FIG. 2, the voltage boosting module 102 can be a charge pump voltage boosting module, and each power amplification channel 10 has an independent charge pump voltage boosting module to provide voltage for the power amplification module 101.

[0056] In this embodiment, the voltage boosting module 102 is a charge pump voltage boosting module, which is low in cost and can save cost. In addition, each power amplification channel 10 is provided with a respective charge pump voltage boosting module, which avoids energy loss caused by the need to follow the envelope of multiple outputs at the same time due to adaptive power supply when sharing the charge pump voltage boosting module, improves efficiency, and can avoid distortion caused by sharing the charge pump voltage boosting module.

[0057] For example, as shown in FIG. 3, the voltage boosting module 102 can be a BOOST voltage boosting module, and each power amplification channel 10 has an independent BOOST voltage boosting module to provide voltage for the power amplification module 101.

[0058] In this embodiment, the voltage boosting module 102 is a BOOST voltage boosting module, which can provide a relatively flexible voltage boosting value for the power amplification module 101. In addition, each power amplification channel 10 is provided with a respective BOOST voltage boosting module, which avoids energy loss caused by only being able to boost power supply according to the maximum demand when sharing the BOOST voltage boosting module, improves efficiency, and can avoid distortion caused by sharing the BOOST voltage boosting module.

[0059] Optionally, as shown in FIG. 2, the chip further includes a power input end 12, and the power input end 12 is connected with the input end of the voltage boosting module 102 of each power amplification channel 10.

[0060] The power input end 12 can be connected with a processor chip to provide power supply by the processor chip, or can be connected with a battery to provide power supply by the battery, or can be connected with other power supply networks to provide power supply by the other power supply networks.

[0061] In the embodiment, the chip further comprises a power input end 12, the power input end 12 is connected with the input end of the boost module 102 of each power amplification channel 10 respectively, so that multiple power amplification channels 10 can share one input power, the multiplexing of the input power is realized, the size and cost of the chip can be reduced, further, the peripheral decoupling capacitors that need to be increased due to the use of multiple input powers can be avoided, the peripheral decoupling capacitors and the wiring can be saved, the layout area of the printed circuit board (PCB) and the bill of materials (BOM) cost can be reduced, and the wiring complexity can be reduced.

[0062] Optionally, as shown in FIG. 2, the chip further comprises a reset module 13 (i.e., a RESET module), the output end of the reset module 13 is connected with the first input end of the system control module 11, and the reset module 13 is used for resetting the at least two power amplification channels 10.

[0063] The input end of the reset module 13 can be connected with a reset pin, the reset module 13 can receive a reset signal from the reset pin, transmit a reset request to the first input end of the system control module 11, and control the at least two power amplification channels 10 to reset under the control of the system control module 11.

[0064] In the embodiment, the chip further comprises a reset module 13, the output end of the reset module 13 is connected with the first input end of the system control module 11, and the reset module 13 is used for resetting the at least two power amplification channels 10, so that multiple power amplification channels 10 can share one reset module 13, the multiplexing of the reset module 13 is realized, the size and cost of the chip can be reduced, further, the reset pins and the wiring that need to be increased due to the use of multiple reset modules 13 can be avoided, the reset pins and the wiring can be saved, the layout area of the PCB and the BOM cost can be reduced, and the wiring complexity can be reduced.

[0065] Optionally, as shown in FIG. 2 and FIG. 3, the power amplification channel 10 further comprises an input buffer module 103 (i.e., an INPUT BUFFER module), the signal input end is connected with the first input end of the power amplification module 101 through the input buffer module 103.

[0066] In each power amplification path 10, the first input end of the input buffer module 103 is connected with the signal input end, and the output end of the input buffer module 103 is connected with the first input end of the power amplification module 101. The input buffer module 103 further comprises a control end, and the control end of the input buffer module 103 is connected with the second control end of the system control module 11, which is used to transmit a control signal to the input buffer module 103 to control the working state of the input buffer module 103.

[0067] In this embodiment, the power amplification path 10 further comprises an input buffer module 103, and the signal input end is connected with the first input end of the power amplification module 101 through the input buffer module 103, which can provide buffering for the input signal.

[0068] Optionally, as shown in FIG. 2 and FIG. 3, the power amplification path 10 further comprises an electromagnetic interference (EMI) elimination module 104, and the output end of the power amplification module 101 is connected with the signal output end through the EMI elimination module 104.

[0069] In this embodiment, the output end of the power amplification module 101 is connected with the first input end of the EMI elimination module 104, and the output end of the EMI elimination module 104 is connected with the signal output end. The EMI elimination module 104 further comprises a second input end, and the output end of the voltage boosting module 102 comprises a first output end and a second output end. The first output end of the voltage boosting module 102 is connected with the second input end of the power amplification module 101, and the second input end of the EMI elimination module 104 is connected with the second output end of the voltage boosting module 102, so that the voltage boosting module 102 can provide voltage for the EMI elimination module 104 through the second output end.

[0070] In this embodiment, the power amplification path 10 further comprises an electromagnetic interference (EMI) elimination module 104, and the output end of the power amplification module 101 is connected with the signal output end through the EMI elimination module 104, which can improve the anti-interference performance of the power amplification path 10.

[0071] Optionally, as shown in FIG. 2, the chip further comprises an address configuration module 14, and the output end of the address configuration module 14 is connected with the second input end of the system control module 11, which is used to configure an integrated circuit bus (I2C) address for the at least two power amplification paths 10.

[0072] The address configuration module 14 can configure the same or different I2C addresses for the at least two power amplification paths 10, and the embodiment is not limited in this regard.

[0073] In addition, the input end of the address configuration module 14 can be connected with an address pin, the address configuration module 14 can receive an address signal from the address pin, and transmit an address configuration request to the second input end of the system control module 11 to configure I2C addresses for the at least two power amplification paths 10.

[0074] In this embodiment, the chip further comprises an address configuration module 14, the output end of the address configuration module 14 is connected with the second input end of the system control module 11, and the address configuration module 14 is configured to configure integrated circuit bus (I2C) addresses for the at least two power amplification paths 10, so that the plurality of power amplification paths 10 can share one address configuration module 14, the multiplexing of the address configuration module 14 is realized, the size and cost of the chip can be reduced, further, the address pins and wires that need to be increased due to the use of multiple address configuration modules 14 can be avoided, the address pins and wires can be saved, the PCB layout area and BOM cost can be reduced, and the wire complexity can be reduced.

[0075] Optionally, the address configuration module 14 is configured to configure the same I2C addresses for the at least two power amplification paths 10, and configure different register addresses for the at least two power amplification paths 10.

[0076] It should be noted that different power amplification paths 10 can be distinguished by different register addresses, which facilitates the system control module 11 to control the power amplification paths 10 to work.

[0077] In this embodiment, the at least two power amplification paths 10 share the same I2C address, and the address resources can be saved.

[0078] Optionally, as shown in FIG. 4, the chip further comprises an audio digital signal processing module 15 (i.e., a Digital Audio Process path module), a digital-to-analog conversion module 16 (i.e., a DAC module), an analog-to-digital conversion module 17 (i.e., an ADC module), and a data collector 18 (i.e., a DATA collector module), the output end of the audio digital signal processing module 15 is connected with the input end of the digital-to-analog conversion module 16, the output end of the digital-to-analog conversion module 16 is connected with the first input end of the power amplification module 101 in each power amplification path 10, the signal output end is connected with the input end of the analog-to-digital conversion module 17, and the output end of the analog-to-digital conversion module 17 is connected with the data collector 18.

[0079] The output end of the digital-to-analog conversion module 16 is connected with the first input end of the power amplification module 101 as the signal input end. The data collector 18 can include a first input end and a second input end, and the output end of the analog-to-digital conversion module 17 is connected with the first input end of the data collector 18. The output end of the digital-to-analog conversion module 16 can include at least two first output ends, and at least a first output end of the digital-to-analog conversion module 16 corresponds to at least two power amplification paths 10 one by one. The first output end of each digital-to-analog conversion module 16 is connected with the power amplification module 101 of the corresponding power amplification path 10 as the signal input end to transmit the input signal to be amplified to the power amplification module 101. The output end of the digital-to-analog conversion module 16 can also include a second output end, and the second output end of the digital-to-analog conversion module 16 is connected with the second input end of the data collector 18.

[0080] In addition, the system control module 11 can also be connected with the audio digital signal processing module 15, the digital-to-analog conversion module 16, the analog-to-digital conversion module 17 and the data collector 18 respectively to control the working of the audio digital signal processing module 15, the digital-to-analog conversion module 16, the analog-to-digital conversion module 17 and the data collector 18.

[0081] It should be noted that the chip can also include a digital audio interface, and the digital audio interface is connected with the input end of the audio digital signal processing module 15. For example, the digital audio interface can transmit the input signal to the audio digital signal processing module 15, the audio digital signal processing module 15 analyzes the audio signal in the input signal and transmits it to the digital-to-analog conversion module 16; the digital-to-analog conversion module 16 converts the digital signal into an analog signal for processing by the power amplification module 101; the power amplification module 101 transmits the amplified signal to the signal output end and outputs it to the loudspeaker; the analog-to-digital conversion module 17 collects the signal of the signal output end, converts the collected analog signal into a digital signal, and collects temperature or impedance information, and outputs it to the data collector 18. The data collector 18 collects the signals input to the power amplification module 101 and the signals input to the loudspeaker uniformly and transmits them to the audio digital signal processing module 15, which transmits them to the processor chip for analysis and processing.

[0082] In the embodiment, the signal input end is connected with the input end of the audio digital signal processing module 15, the output end of the audio digital signal processing module 15 is connected with the input end of the digital-to-analog conversion module 16, the output end of the digital-to-analog conversion module 16 is connected with the first input end of the power amplification module 101 in each power amplification channel 10, the signal output end is connected with the input end of the analog-to-digital conversion module 17, the multiplexing of the audio digital signal processing module 15, the digital-to-analog conversion module 16, the analog-to-digital conversion module 17 and the data collector 18 can be realized, the size and cost of the chip can be reduced, further, the pins and wires that need to be increased due to the use of multiple audio digital signal processing modules 15, digital-to-analog conversion modules 16, analog-to-digital conversion modules 17 and data collectors 18 can be saved, the pin and wire can be saved, the PCB layout area and BOM cost can be reduced, and the wire complexity can be reduced.

[0083] With the increasing of mobile phones and tablet computers and other consumer electronic products into people's life, people's life is greatly facilitated. At present, with the improvement of people's demand for video and audio entertainment and other scenes, the sound system of mobile phones and tablet computers and other consumer electronic products gradually increases from a single loudspeaker to a stereo loudspeaker, and even more channels of loudspeakers.

[0084] In the related art, an electronic device (such as a mobile phone, a tablet computer, etc.) generally uses one audio power amplifier (PA) to correspond to drive one loudspeaker or other passive device. Therefore, in order to experience a double loudspeaker or a multi-loudspeaker audio system on a mobile phone or other electronic device, more PAs are needed to achieve. As shown in FIGS. 5-6. The electronic device includes a battery cover 201, a lower loudspeaker 202, a battery 203, a mainboard support 204, a sub-board 205, an upper loudspeaker 206, an FPC 207, a mainboard 208, a camera 209, and a middle frame 210, a platform end 211, an upper loudspeaker PA 212, and a lower loudspeaker PA 213. To match, the internal circuit connection of the double loudspeaker electronic device is shown in FIGS. 7 and 8. The stereo double loudspeaker system shown in FIG. 7 is realized by a charge pump power amplifier, and the stereo double loudspeaker system shown in FIG. 8 is realized by a Boost power amplifier.

[0085] The internal block diagrams of the first PA and the second PA of the stereo double loudspeaker system shown in FIG. 7 are shown in FIGS. 9 and 10. The internal block diagrams of the first PA and the second PA are the same, both of which have an independent system control module SYSCTRL, a reset module RESET, an address configuration module Address, and a charge pump power supply and an audio amplification channel.

[0086] It should be noted that, with each added speaker, a PA is needed to drive, and the PA and its peripheral circuit occupy a large board area, and in the trend of increasingly tight internal space of electronic devices, the promotion of multi-channel systems in electronic devices is limited; in addition, each PA needs a separate control line, and when multiple PAs are combined, it will lead to complex internal wiring of electronic devices and poor convenience; further, the increased PA will lead to higher device and assembly costs.

[0087] In the embodiments of the present application, by redesigning the audio PA, two or more channel driving is integrated in one IC, realizing the function of multiple PAs with a single driving IC, and through the single driving IC, stereo or multi-channel can be realized.

[0088] Compared with driving multiple passive devices by multiple PA chips, the chip in the embodiments of the present application can reduce the board area on the PCB, leaving more space for other modules (such as batteries, sound cavities, etc.) of electronic devices;

[0089] In addition, the chip in the embodiments of the present application combines two or more PAs into one PA, reducing the core area, and when two PAs are combined into one PA, the chip cost can be reduced by about 15%;

[0090] In addition, the chip in the embodiments of the present application combines multiple PAs together, and the peripheral circuit devices can also be reduced, for example, the decoupling capacitor of the power supply end originally needs two decoupling capacitors for each PA, and is reduced to only two decoupling capacitors for all channels, which can further reduce material cost and board area;

[0091] In addition, the chip in the embodiments of the present application integrates multiple driving together, so that the number of control lines is simplified, facilitating PCB wiring design. For example, the PA controlled by I2C originally needs two I2C wires for each PA, and after integrating multiple driving together, only two I2C wires are needed; for example, the PA originally needs a reset wire for each PA, and after integrating multiple driving together, only one reset wire is needed; for example, the PA originally needs to be configured with an I2C address for each PA, and after integrating multiple driving together, only one I2C address is needed.

[0092] The chip in the embodiments of the present application is further described below through several examples:

[0093] Embodiment one:

[0094] As shown in FIG. 2, the embodiment integrates two power amplification paths in an IC. The two power amplification paths 10 are respectively a first power amplification path 111 and a second power amplification path 112. The first power amplification path 111 includes: a first power amplification module 1111, i.e. Class D1; a first charge pump voltage boosting module 1112, i.e. Chargepump1; a first input buffer module 1113, i.e. INPUT BUFFER1; a first EMI suppression circuit 1114, i.e. EMI Eliminate1. The second power amplification path 112 includes: a second power amplification module 1121, i.e. Class D2; a second charge pump voltage boosting module 1122, i.e. Chargepump2; a second input buffer module 1123, i.e. INPUT BUFFER2; a second EMI suppression circuit 1124, i.e. EMI Eliminate2. Among them,

[0095] 1) SYSCTRL is a system control module, which can control the hardware state or register state of the two power amplification paths at the same time. The implementation of SYSCTRL can be IIC or other GPIO control mode, which controls the working state or mode of the power amplification path through high and low level.

[0096] 2) RESET is a reset module, which can reset the two power amplification paths at the same time.

[0097] 3) Address is an address configuration module, mainly to configure the address of I2C. The two power amplification paths share an I2C address, and the register addresses of the two power amplification paths are different.

[0098] 4) VDD is the power supply of the entire system of the IC, which can be introduced from the processor chip of the electronic device, or can be the battery voltage, or can be introduced from other system power supply network.

[0099] 5) Chargepump is a charge pump voltage boosting module, which can provide a high enough voltage for the power amplification module, and increase the VDD voltage to twice or more. The two power amplification paths each have a charge pump, which are Chargepump1 and Chargepump2. Compared with the Boost voltage boosting module, the charge pump voltage boosting module has the advantage of low cost.

[0100] 6) INPUT BUFFER1 and INPUT BUFFER2 respectively receive two input signals and provide buffering.

[0101] 7)Class D1 and Class D2 are two power amplification modules respectively, which can amplify the sine wave signal of the Input Buffer and provide it to the subsequent circuit. It should be noted that the power amplification module can also be a Class AB circuit.

[0102] 8)EMI Eliminate1 and EMI Eliminate2 are EMI suppression circuits, which can be used to improve the anti-interference performance of the power amplification path.

[0103] Compared with the stereo dual-speaker system shown in FIG. 7, since the chip of the embodiment shares SYSCTRL system control module, RESET reset module and Address address configuration module, etc., the chip size and chip cost can be reduced.

[0104] In this embodiment, the processor chip is connected with the chip provided by the embodiment of the application. The processor chip can control the reset pin RSTN of the chip to be pulled low from high, and reset the two power amplification paths at the same time. The processor chip can control the working state of the two power amplification paths respectively through different register configurations according to the I2C address configured for the power amplification path. The two audio signals output by the processor chip are input into the power amplification path through the first input end INP1 and INN1 and the second input end INP2 and INN2 respectively, the first audio signal enters the INPUT BUFFER1, and the second audio signal enters the INPUT BUFFER2. The audio signal output by the INPUT BUFFER1 is amplified by the Class D1, and after passing through the EMI Eliminate1 circuit, the signal is output through the output port VOP1 and VON1 to drive the first speaker. The audio signal output by the INPUT BUFFER2 is amplified by the Class D2, and after passing through the EMI Eliminate2 circuit, the signal is output through the output port VOP2 and VON2 to drive the second speaker. Correspondingly, the peripheral circuit diagram for the first embodiment is shown in FIG. 11.

[0105] The descriptions of some pins are as follows:

[0106] INP1 and INN1: signal input end, used for inputting differential or single-ended signal;

[0107] INP2 and INN2: signal input end, used for inputting differential or single-ended signal;

[0108] CTRL1 and CTRL2: I2C bus, as control line;

[0109] CP1 and CN1: power input port of Chargepump1;

[0110] CP2 and CN2: power input port of Chargepump2;

[0111] PVDD1: power output port of Chargepump1;

[0112] PVDD2: power output port of Chargepump2;

[0113] VOP1 and VON1: signal output port for outputting amplified signal to first speaker;

[0114] VOP2 and VON2: signal output port for outputting amplified signal to second speaker;

[0115] AD: address pin;

[0116] RSTN: reset pin.

[0117] Compared with the stereo dual-speaker system shown in FIG. 7, in the embodiment:

[0118] The two power amplification paths share one input power supply VDD, which can save two peripheral decoupling capacitors;

[0119] The two power amplification paths share one I2C, which can save two I2C wires;

[0120] The two power amplification paths share one reset pin RSTN, which can save one GPIO of the processor chip and its wire;

[0121] The two power amplification paths share one address pin AD, which simplifies the circuit connection.

[0122] Compared with the stereo dual-speaker system shown in FIG. 8, in the embodiment:

[0123] The chip provided by the embodiment of the present application uses ChargePump for power supply inside the chip, saves external inductor devices, saves cost, and reduces the z-direction height of the entire module;

[0124] The chip provided in the embodiment of the application is powered by two paths of ChargePump, which avoids energy loss caused by the envelope of two paths of output that need to be followed simultaneously for adaptive power supply when one path of ChargePump is used for power supply, and improves efficiency. As shown in FIG. 12, line 31 is the output of the first loudspeaker, line 32 is the output of the second loudspeaker, and line 33 is the voltage of the PVDD power supply. Since the output distortion of the PA increases with the increase of the output power, the overall efficiency decreases with the increase of the output power, as shown in FIG. 13 and FIG. 14. Using two paths of ChargePump for driving power supply ensures the driving capability and avoids the distortion and efficiency loss caused by the increase of power when one path of power supply is used.

[0125] The embodiment has the following beneficial effects: reducing the PCB layout area and saving the overall stacking space; the internal modules of the chip provided in the embodiment are reused, which can reduce the size and cost of the chip; the peripheral decoupling capacitors, I2C, reset pins and address configuration pins are reused, which can reduce the peripheral circuit devices and wires, further reduce the PCB layout area and BOM cost, and reduce the complexity of the wires; two paths of charge pump voltage boosting modules are used to drive two paths of output, which is more flexible in adaptive boosting and better in following, and can improve the overall efficiency; under the premise of saving cost and layout area, the distortion performance and overall efficiency of the PA overall output are ensured.

[0126] Embodiment two:

[0127] In the embodiment, three paths of power amplification are integrated in one IC. As shown in FIG. 15, compared with the embodiment one, except that the number of paths is different, other modules and working principles are similar to those of the embodiment one, which will not be described here. Correspondingly, the peripheral circuit diagram for the embodiment two is shown in FIG. 16.

[0128] Compared with the stereo double loudspeaker system shown in FIG. 7, in the embodiment:

[0129] The three paths of power amplification share one input power supply VDD, which can save four peripheral decoupling capacitors;

[0130] The three paths of power amplification share one I2C, which can save four I2C wires;

[0131] The three paths of power amplification share one reset pin RSTN, which can save two GPIOs of the processor chip and the wires thereof;

[0132] The three paths of power amplification share one address pin AD, which simplifies the circuit connection.

[0133] The embodiment has the following beneficial effects: reducing the PCB layout area, saving the whole machine stacking space; the internal module of the chip provided by the embodiment is reused, so that the chip volume and cost can be reduced; the peripheral decoupling capacitor, I2C, reset pin and address configuration pin are reused, so that the peripheral circuit devices and wires can be reduced, the PCB layout area and BOM cost can be further reduced, and the wire complexity can be reduced; compared with the first embodiment, the reused part can save more cost and space.

[0134] Embodiment three:

[0135] As shown in FIG. 3, the embodiment is to integrate two power amplification paths in an analog IC. Among them,

[0136] 1) SYSCTRL is a system control module, which aims to control the hardware state or register state of the power amplifier. The implementation of SYSCTRL can be IIC or other GPIO control mode, which controls the working state or mode of the power amplification path through high and low level.

[0137] 2) VBAT is the power supply of the whole system of the IC, which can be introduced from the processor chip, or can be the battery voltage, or can be introduced from other system power supply network.

[0138] 3) BOOST (i.e. boost) is a boost module, which provides a high enough voltage for the power amplification module, and increases the VBAT voltage, and the boost can be controlled by the duty cycle of the drive waveform. The two power amplification paths each have a boost, which are boost1 and boost2 respectively.

[0139] 4) INPUT BUFFER1 and INPUT BUFFER2 respectively receive two input signals and provide buffering.

[0140] 5) Class D1 and Class D2 are two power amplification modules respectively, which can amplify the signal of Input Buffer and provide it to the subsequent circuit.

[0141] 6) EMI Eliminate1 and EMI Eliminate2 are EMI suppression circuits respectively, which can be used to improve the anti-interference performance of the power amplification path.

[0142] In this embodiment, the two audio signals output by the processor chip are input into the power amplification path through the first input ends INP1 and INN1 and the second input ends INP2 and INN2, the first audio signal enters the INPUT BUFFER1, and the second audio signal enters the INPUT BUFFER2; the audio signal output by the INPUT BUFFER1 is amplified by the Class D1, and after passing through the EMI Eliminate1 circuit, the signal is output through the output ports VOP1 and VON1 to drive the first loudspeaker, and the audio signal output by the INPUT BUFFER2 is amplified by the Class D2, and after passing through the EMI Eliminate2 circuit, the signal is output through the output ports VOP2 and VON2 to drive the second loudspeaker. Correspondingly, the peripheral circuit diagram for the third embodiment is shown in FIG. 17.

[0143] In this embodiment, two BOOSTs are used to supply power to the two internal power amplification modules, when the two signals are different, the required power is different, that is, the required boost voltage is different, and the single boost can only supply power according to the maximum demand, as shown in FIG. 18, the double boost power supply can simultaneously follow the envelope adjustment of the two output voltages to adjust the boost value, which improves the efficiency, line 41 is the output of the first loudspeaker, line 42 is the output of the second loudspeaker, and line 43 is the voltage of the PVDD power supply. The relationship between the single boost power amplifier efficiency and distortion (THD+N) and the output power is shown in FIGS. 19 and 20, the power amplifier efficiency decreases with the increase of the power, and the distortion increases with the increase of the output power, line 51 is the distortion diagram at a frequency f of 6KHZ, line 52 is the distortion diagram at a frequency f of 1KHZ, and line 53 is the distortion diagram at a frequency f of 100KHZ. When the power supply is divided into two boost powers, the two power links are separated, which is equivalent to reducing the power of the single boost circuit, and the distortion can be reduced under the condition of ensuring the driving force.

[0144] Further, the peripheral circuit of the chip provided by the embodiment of the present application saves one I2C signal input compared with the peripheral circuit of the two single analog input single boost chips, only one power supply is needed, and the wiring difficulty is reduced.

[0145] In this embodiment, since the two power amplification paths share the VBAT and the I2C circuit, the peripheral circuit is saved, the circuit is more concise, and the device cost and wiring difficulty can be reduced.

[0146] The embodiment has the following beneficial effects: reducing the PCB layout area, saving the whole machine stacking space; the internal module of the chip provided by the embodiment can be reused, so that the chip cost can be reduced; the peripheral decoupling capacitor and I2C are reused, so that the peripheral circuit device and the wire can be reduced, the PCB layout area and the BOM cost can be further reduced, and the wire complexity can be reduced; two boost paths are used to drive two power amplification module outputs, so that the two paths can be adjusted respectively, the boost path is more flexible than the single boost path, and the overall efficiency is improved; the total output power of the power amplifier is driven by two boost paths, the power required by each boost path is smaller, and the distortion can be effectively reduced.

[0147] Embodiment four:

[0148] As shown in FIG. 4, the embodiment is to integrate two power amplification paths in an intelligent IC.

[0149] Compared with the first embodiment, the output signal of the processor chip is converted from an analog signal to a digital signal, and the implementation of the boost and the amplification output is basically the same as that of the first embodiment.

[0150] The difference is that:

[0151] The digital audio process path is an audio digital signal processing module, and the purpose is to analyze the audio signal in the integrated audio interface (IIS).

[0152] The DAC (Digital to analog converter) is a digital-to-analog conversion module, which converts a digital signal into an analog signal for the power amplification path processing.

[0153] The ADC (Analog to Digital converter) is an analog-to-digital conversion module, which converts an analog signal into a digital signal.

[0154] The intelligent power amplifier integrated circuit (IC) has a collection module, which is used to convert the collected analog signal into a digital signal for analysis and processing.

[0155] To match, the peripheral circuit diagram for the fourth embodiment is shown in FIG. 21. Similar to the third embodiment, since the VBAT and the I2C circuit are shared, the IIS can also be shared, so that the peripheral circuit and the wire are saved.

[0156] The embodiment has the following beneficial effects: reducing the PCB layout area, saving the whole machine stacking space; the internal module of the chip provided by the embodiment can be reused, so that the chip cost can be reduced; the peripheral decoupling capacitor, I2C and I2S, etc. are reused, so that the peripheral circuit devices and the wiring can be reduced, the PCB layout area and the BOM cost can be further reduced, and the wiring complexity can be reduced; two paths of boost are used to drive two paths of power amplification modules to output, which is more flexible than a single path of boost, and the overall efficiency is improved; the total output power of the power amplifier is driven by two paths of boost, and the power required by each path of boost is smaller, so that the distortion can be effectively reduced.

[0157] It should be noted that the two paths of power amplification in the first embodiment can be extended to N paths, N is greater than 2, as shown in FIG. 22. The two paths of power amplification in the third embodiment can also be extended to N paths, and the two paths of power amplification in the fourth embodiment can also be extended to N paths, and the specific implementation can refer to the implementation of the two paths of power amplification, which will not be described here.

[0158] The embodiment of the present application also provides an electronic device, which comprises the chip provided by the embodiment of the present application.

[0159] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in combination with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the exemplary description of the above terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0160] Although the embodiments of the present application have been shown and described, those skilled in the art can understand that various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and purposes of the present application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. A chip comprising: at least two power amplification channels, each of the power amplification channels comprising a signal input end, a power amplification module, a voltage boosting module, and a signal output end; wherein in each of the power amplification channels, the signal input end is connected to a first input end of the power amplification module, the signal output end is connected to an output end of the power amplification module, and an output end of the voltage boosting module is connected to a second input end of the power amplification module, the voltage boosting module being configured to supply power to the power amplification module; a system control module, a control end of the system control module being connected to a control end of the power amplification module of each of the power amplification channels, the system control module being configured to control the power amplification module to amplify an input signal.

2. The chip of claim 1, wherein, The chip further comprises a power supply input end, the power supply input end being connected to an input end of the voltage boosting module of each of the power amplification channels.

3. The chip of claim 1, wherein, The chip further comprises a reset module, an output end of the reset module being connected to a first input end of the system control module, the reset module being configured to reset the at least two power amplification channels.

4. The chip of claim 1, wherein, The power amplification channel further comprises an input buffer module, the signal input end being connected to the first input end of the power amplification module through the input buffer module.

5. The chip of claim 1, wherein, The power amplification channel further comprises an electromagnetic interference (EMI) suppression module, the output end of the power amplification module being connected to the signal output end through the EMI suppression module.

6. The chip of claim 1, wherein, The chip further comprises an address configuration module, an output end of the address configuration module being connected to a second input end of the system control module, the address configuration module being configured to configure an integrated circuit bus (I2C) address for the at least two power amplification channels.

7. The chip of claim 6, wherein, The address configuration module is configured to configure the same I2C address for the at least two power amplification channels and different register addresses for the at least two power amplification channels.

8. The chip of any one of claims 1-7, wherein, The voltage boosting module is a charge pump voltage boosting module or a BOOST voltage boosting module.

9. The chip of claim 8, wherein, The chip further comprises an audio digital signal processing module, a digital-to-analog conversion module, an analog-to-digital conversion module, and a data collector, an output end of the audio digital signal processing module being connected to an input end of the digital-to-analog conversion module, an output end of the digital-to-analog conversion module being connected to the first input end of the power amplification module in each of the power amplification channels, the signal output end being connected to an input end of the analog-to-digital conversion module, and an output end of the analog-to-digital conversion module being connected to the data collector.

10. An electronic device comprising the chip of any one of claims 1-9.

11. The electronic device of claim 10, wherein, The electronic device further comprises at least two loudspeakers, the at least two loudspeakers corresponding to the at least two power amplification channels one-to-one, and the loudspeakers being connected to the signal output ends.

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