Computing-in-memory circuit and control method therefor, and chip

Abstract

Provided are a computing-in-memory circuit and a control method therefor, and a chip. The computing-in-memory circuit comprises: at least two memory arrays, including a first memory array and a second memory array, wherein for each memory array among the at least two memory arrays, each memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell comprises a first transistor and a second transistor, and in each memory cell, a gate terminal of the first transistor is connected one of a source terminal and a drain terminal of the second transistor; and at least one converter, wherein each converter is connected to two memory arrays among the at least two memory arrays, the at least one converter includes a first converter, and the first converter is connected to row input-output terminals of the plurality of rows of the first memory array and row input-output terminals of the plurality of rows of the second memory array.

Description

In-memory computing circuits and their control methods, as well as chips Technical Field

[0001] This disclosure relates to data processing, and in particular to a memory computing circuit and its control method, as well as a chip. Background Technology

[0002] In the traditional von Neumann computing architecture, memory and processor are physically separated and connected by a data bus. When performing related calculations, the vector and matrix data to be processed must first be read from memory, transferred to the processor for calculation, and then the calculation results are stored back in memory. This consumes a lot of data bus bandwidth and transmission power.

[0003] The methods described in this section are not necessarily methods that had been previously conceived or adopted. Unless otherwise specified, no method described in this section should be assumed to be prior art simply because it is included in this section. Similarly, unless otherwise specified, the issues mentioned in this section should not be considered to be accepted in any prior art. Summary of the Invention

[0004] According to one aspect of this disclosure, a memory computing circuit is provided, comprising: at least two memory arrays, including a first memory array and a second memory array, wherein for each of the at least two memory arrays, each memory array includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell including a first transistor and a second transistor, wherein in each memory cell, the gate terminal of the first transistor is connected to one of the source and drain terminals of the second transistor, and each memory cell is configured to store a weight corresponding to that memory cell, and for each memory array, one of the drain and source terminals of the first transistor in the memory cells of the same row is connected to a row input-output terminal corresponding to that row, and the drain and source terminals of the first transistor in the memory cells of the same column are connected to the same row input-output terminal. Another terminal of the terminals is connected to the column input-output terminal corresponding to that column; and at least one converter, each converter being connected to two of the at least two memory arrays, the at least one converter including a first converter, the first converter being connected to the row input-output terminals of a plurality of rows of the first memory array and the row input-output terminals of a plurality of rows of the second memory array, and being configured to: in response to an output from the first memory array to the second memory array, for any row of the first memory array, convert the output signal of the row input-output terminal of any row of the first memory array into an input signal of the corresponding row of the second memory array, and input the input signal of the corresponding row of the second memory array to the row input-output terminal of the corresponding row of the second memory array, wherein the corresponding row of the second memory array is the row of the second memory array corresponding to any row of the first memory array.

[0005] According to another aspect of this disclosure, a method for controlling a memory-based circuit as disclosed herein is provided, the method comprising: in response to an output from a first memory array to a second memory array, inputting an input signal corresponding to a column of each column of the first memory array to a column input-output terminal; for any row of the first memory array, converting the output signal of the row input-output terminal of any row of the first memory array into an input signal for the corresponding row of the second memory array; and inputting the input signal for the corresponding row of the second memory array to a row input-output terminal of the corresponding row of the second memory array, wherein the corresponding row of the second memory array is a row of the second memory array corresponding to any row of the first memory array.

[0006] According to another aspect of this disclosure, a chip is provided, including the memory computing circuitry as described in this disclosure. Attached Figure Description

[0007] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of the claims. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0008] Figure 1 shows a schematic diagram of a memory computing circuit according to an exemplary embodiment of the present disclosure;

[0009] Figures 2A-2B show schematic diagrams of memory cells according to exemplary embodiments of the present disclosure;

[0010] Figures 3A-3D show schematic diagrams of memory arrays in memory computing circuits according to exemplary embodiments of the present disclosure;

[0011] Figure 4 shows a schematic diagram of a memory computing circuit according to an exemplary embodiment of the present disclosure;

[0012] Figure 5 shows a schematic diagram of a memory computing circuit according to an exemplary embodiment of the present disclosure;

[0013] Figure 6 shows a schematic diagram of a converter in a memory computing circuit according to an exemplary embodiment of the present disclosure;

[0014] Figure 7 illustrates a schematic diagram of the forward calculation process performed by the memory computing circuit according to an exemplary embodiment of the present disclosure;

[0015] Figure 8 illustrates a schematic diagram of the reverse computation process performed by the memory circuit according to an exemplary embodiment of the present disclosure;

[0016] Figure 9 shows a flowchart of a method for controlling a memory circuit according to an exemplary embodiment of the present disclosure;

[0017] Figure 10 shows a schematic diagram of a chip according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0018] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to define the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0019] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. Furthermore, the term "and / or" as used in this disclosure covers any one of the listed items and all possible combinations thereof.

[0020] As mentioned above, in the traditional von Neumann computing architecture, due to the separation of memory and processor, a large amount of data bus bandwidth and transmission power consumption are required to perform related calculations.

[0021] To address the aforementioned problems, this disclosure provides a memory computing circuit comprising: at least two memory arrays, including a first memory array and a second memory array, wherein for each of the at least two memory arrays, each memory array includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell including a first transistor and a second transistor, wherein in each memory cell, the gate terminal of the first transistor is connected to one of the source and drain terminals of the second transistor, and each memory cell is configured to store a weight corresponding to that memory cell, and for each memory array, one of the drain and source terminals of the first transistor in the memory cells of the same row is connected to the row input-output terminal corresponding to that row, and the drain and source terminals of the first transistor in the memory cells of the same column are connected to the row input-output terminal corresponding to that row. Another terminal in the source terminal is connected to the column input-output terminal corresponding to that column; and at least one converter, each converter being connected to two of the at least two memory arrays, the at least one converter including a first converter, the first converter being connected to the row input-output terminals of a plurality of rows of the first memory array and the row input-output terminals of a plurality of rows of the second memory array, and being configured to: in response to an output from the first memory array to the second memory array, for any row of the first memory array, convert the output signal of the row input-output terminal of any row of the first memory array into an input signal of the corresponding row of the second memory array, and input the input signal of the corresponding row of the second memory array to the row input-output terminal of the corresponding row of the second memory array, wherein the corresponding row of the second memory array is the row of the second memory array corresponding to any row of the first memory array.

[0022] According to the embodiments described herein, by storing computation-related weights in a memory array within a memory circuit, computations (e.g., multiplication) between the input and the stored weights can be performed, thereby reducing overhead from analog-to-digital conversion, digital-to-analog conversion, data transmission, etc., improving processing performance, simplifying circuit structure, increasing response speed, and reducing power consumption. Furthermore, by using memory arrays with different row input / output configurations, i.e., by coupling the row output memory array to the row input memory array via a converter, a separate component for performing matrix transpose is omitted, improving computational efficiency and further simplifying the circuit structure.

[0023] In the embodiments described in this disclosure, a column in a memory array is a set of memory cells at the same vertical position in the horizontal direction of the memory array, or a column in a memory array is a set of memory cells at the same horizontal position in the vertical direction of the memory array, and a column in a memory array is a set of memory cells at the same vertical position in the horizontal direction of the memory array, and a column in a memory array is a set of memory cells at the same vertical position in the vertical direction of the memory array, and a column in a memory array is a set of memory cells at the same horizontal position in the vertical direction of the memory array.

[0024] Figure 1 shows a schematic diagram of a memory computing circuit 100 according to an exemplary embodiment of the present disclosure.

[0025] According to some embodiments, as shown in FIG1, the in-memory computing circuit 100 includes at least two memory arrays 101-102 and at least one converter 111, wherein each converter is connected to the two memory arrays to perform signal conversion between the two memory arrays (e.g., analog-to-digital conversion, digital-to-analog conversion). It should be understood that although two memory arrays 101-102 and one converter 111 are shown in FIG1, FIG1 is only schematic, and the in-memory computing circuit 100 may include more than two memory arrays and / or more than one converter.

[0026] It should be understood that, in order to clearly show the circuit structure of the entire memory computing circuit, the internal structure of each memory cell is not shown in Figure 1. The internal structure of the memory cell will be described in detail below with reference to Figures 2A-2B and 3A-3D.

[0027] Figures 2A-2B illustrate schematic diagrams of a memory cell 200 according to exemplary embodiments of the present disclosure. According to some embodiments, memory cell 101 in the memory array 101-102 of Figure 1... 1,1 -101 M,N 102 1,1 -102 M,N The structure of each of them may be the same as or similar to that of the memory cell 200 described with reference to Figures 2A-2B.

[0028] According to some embodiments, as shown in Figures 2A-2B, for each of at least two memory arrays 101-102, each memory array includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell including a first transistor and a second transistor, wherein in each memory cell, the gate terminal of the first transistor is connected to one of the source terminal and the drain terminal of the second transistor, and the memory cell is configured to store a weight corresponding to the memory cell.

[0029] According to some embodiments, as shown in FIG2A, in memory cell 200, there is a parasitic capacitance 203 between the gate terminal 201g of the first transistor 201 and the ground point, and the weight stored in memory cell 200 is determined based on the charge stored in the parasitic capacitance 203 in memory cell 200.

[0030] According to some embodiments, as shown in FIG2B, the memory cell 200 further includes a storage capacitor 203, a first terminal of which is connected to the gate terminal 201g of the first transistor 201 of the memory cell 200, and a second terminal of which is connected to a ground point, wherein the weight stored in the memory cell 200 is determined based on the charge stored in the storage capacitor 203 in the memory cell 200.

[0031] According to some embodiments, in the memory cell 200 shown in Figures 2A-2B, the charge stored in the storage capacitor 203 or parasitic capacitor 203 in the memory cell 200 can be controlled by applying a conduction signal (e.g., conduction voltage) to the gate terminal 202g of the second transistor 202 and a write signal (e.g., write voltage) to the other terminal 202b of the source and drain terminals of the second transistor 202, thereby controlling the weight value stored in the memory cell.

[0032] According to some embodiments, in any one of the memory arrays 101-102, one of the drain and source terminals of the first transistor in the memory cell in the same row is connected to the row input-output terminal corresponding to that row, and the other terminal of the drain and source terminals of the first transistor in the memory cell in the same column is connected to the column input-output terminal corresponding to that column.

[0033] Figures 3A-3D show schematic diagrams of a memory array 300 in a memory computing circuit according to exemplary embodiments of the present disclosure.

[0034] According to some embodiments, as shown in Figures 3A-3B, the source terminal of the first transistor in the memory cell in the same row of the memory array 300 is connected to the row input-output terminal corresponding to that row (for example, as shown in Figure 3A, the row input-output terminal is used as the row output terminal, or as shown in Figure 3B, the row input-output terminal is used as the row input terminal), and the drain terminal of the first transistor in the memory cell in the same column is connected to the column input-output terminal corresponding to that column (for example, as shown in Figure 3A, the column input-output terminal is used as the column input terminal, or as shown in Figure 3B, the column input-output terminal is used as the column output terminal).

[0035] According to some embodiments, the first memory array 101 in the in-memory computing circuit 100 of FIG1 is the memory array 300 shown in FIG3A, for example, when the first memory array 101 outputs to the second memory array 102. According to other embodiments, the first memory array 101 in the in-memory computing circuit 100 of FIG1 is the memory array 300 shown in FIG3B, for example, when the second memory array 102 outputs to the first memory array 101.

[0036] According to some embodiments, the second memory array 102 in the in-memory computing circuit 100 of FIG1 is the memory array 300 shown in FIG3B, for example, when the first memory array 101 outputs to the second memory array 102. According to other embodiments, the second memory array 102 in the in-memory computing circuit 100 of FIG1 is the memory array 300 shown in FIG3A, for example, when the second memory array 102 outputs to the first memory array 101.

[0037] It should be understood that the circuit structure of the memory array 300 in Figure 3A and Figure 3B is the same, and the only difference is that in the memory array 300 in Figure 3A, the column input-output terminal is used as the column input terminal and the row input-output terminal is used as the row output terminal, while in the memory array 300 in Figure 3B, the column input-output terminal is used as the column output terminal and the row input-output terminal is used as the row input terminal.

[0038] According to some embodiments, as shown in Figures 3C-3D, the source terminal of the first transistor in the memory cell of the memory array 300 in the same column is connected to the column input-output terminal corresponding to that column (for example, as shown in Figure 3C, the column input-output terminal is used as a column input terminal, or as shown in Figure 3D, the column input-output terminal is used as a column output terminal), and the drain terminal of the first transistor in the memory cell of the same row is connected to the row input-output terminal corresponding to that row (for example, as shown in Figure 3C, the row input-output terminal is used as a row output terminal, or as shown in Figure 3D, the row input-output terminal is used as a row input terminal).

[0039] According to some embodiments, the first memory array 101 in the in-memory computing circuit 100 of FIG1 is the memory array 300 shown in FIG3C, for example, when the first memory array 101 outputs to the second memory array 102. According to other embodiments, the first memory array 101 in the in-memory computing circuit 100 of FIG1 is the memory array 300 shown in FIG3D, for example, when the second memory array 102 outputs to the first memory array 101.

[0040] According to some embodiments, the second memory array 102 in the in-memory computing circuit 100 of FIG1 is the memory array 300 shown in FIG3D, for example, when the first memory array 101 outputs to the second memory array 102. According to other embodiments, the second memory array 102 in the in-memory computing circuit 100 of FIG1 is the memory array 300 shown in FIG3C, for example, when the second memory array 102 outputs to the first memory array 101.

[0041] It should be understood that the circuit structure of the memory array 300 in Figure 3C and Figure 3D is the same, and the only difference is that in the memory array 300 in Figure 3C, the column input-output terminal is used as the column input terminal and the row input-output terminal is used as the row output terminal, while in the memory array 300 in Figure 3D, the column input-output terminal is used as the column output terminal and the row input-output terminal is used as the row input terminal.

[0042] According to some embodiments, in each memory cell, a write operation is performed on the memory cell via a second transistor to change the weight stored in the memory cell. According to some embodiments, as shown in Figures 3A-3D, the gate terminals of the second transistors in memory cells of the same row in the memory array 300 are connected, while the other terminal (i.e., the terminal not connected to the gate terminal of the first transistor) of the source and drain terminals of the second transistors in memory cells of the same column in the memory array 300 is connected. According to other embodiments, the gate terminals of the second transistors in memory cells of the same column in the memory array 300 are connected, while the other terminal (i.e., the terminal not connected to the gate terminal of the first transistor) of the source and drain terminals of the second transistors in memory cells of the same row in the memory array 300 is connected.

[0043] According to some embodiments, for any column of memory cells in the memory array 300, the memory cell is "activated" in response to receiving an input signal (e.g., input voltage) at one terminal of the source and drain terminals of the first transistor (hereinafter referred to as "the first terminal of the first transistor" for simplicity), thereby outputting a corresponding output signal (e.g., output current) at the other terminal of the source and drain terminals of the first transistor of the memory cell (hereinafter referred to as "the second terminal of the first transistor" for simplicity).

[0044] According to some embodiments, the output current of the second terminal of the first transistor of the memory cell in the memory array 300 is the product of the weight stored in the memory cell and the input voltage on the first terminal of the first transistor of the memory cell, that is, I OUT = V IN ×W, where I OUT is the output current of the second terminal of the first transistor of the memory cell, V IN is the input voltage on the first terminal of the first transistor of the memory cell, and W is the value stored in the first transistor of the memory cell.

[0045] According to some embodiments, a vector-matrix multiplication can be implemented by the memory array 300. For example, in FIG. 3A or FIG. 3C, the input signals received by each column of the memory array 300 correspond to the respective components of the input vector of the vector-matrix multiplication, the weights of each memory cell in the memory array 300 correspond to the respective weight values of the matrix of the vector-matrix multiplication, and the output signals of each row of the memory array 300 correspond to the respective components of the output vector of the vector-matrix multiplication. For another example, in FIG. 3B or FIG. 3D, the input signals received by each row of the memory array 300 correspond to the respective components of the input vector of the vector-matrix multiplication, the weights of each memory cell in the memory array 300 correspond to the respective weight values of the matrix of the vector-matrix multiplication, and the output signals of each column of the memory array 300 correspond to the respective components of the output vector of the vector-matrix multiplication.

[0046] According to some embodiments, in FIG. 3A or FIG. 3C, for any row of memory cells in the memory array 300, since the second terminals of the first transistors of the memory cells in this row are connected, the output currents of the first transistors of the memory cells in this row are added up to form the output current of this row.

[0047] According to some embodiments, in FIG. 3B or FIG. 3D, for any column of memory cells in the memory array 300, since the second terminals of the first transistors of the memory cells in this column are connected, the output currents of the first transistors of the memory cells in this column are added up to form the output current of this column.

[0048] Taking the memory array 300 in FIG. 3A as an example, if the weight stored in the memory cell located in the k-th row and the j-th column is W k,j , the output current is I k,j , and the input voltage is V INj , where 0 < k ≤ M, 0 < j ≤ N, then the relationship among the output current, the stored weight, and the input voltage of the memory cell located in the k-th row and the j-th column can be expressed as I k,j = VINj W k,j Furthermore, for the memory cell in the k-th row, according to Kirchhoff's laws, the current I at the output terminal of the k-th row is... OUTk It is the sum of the output currents of all memory cells in that row, that is, For example, if a memory array can be viewed as a storage matrix Furthermore, the input voltages of multiple columns in the memory array can be considered as vectors. Based on the above analysis, the output current of multiple rows of the memory array can be considered as a vector. It should be understood that the memory array 300 in Figures 3B-3D performs similar computations to the memory array 300 in Figure 3A.

[0049] According to the embodiments described herein, by using memory arrays with different row input / output configurations, i.e., by coupling the row output memory array with the row input memory array via a converter, without the need for a separate component for performing matrix transpose, computational efficiency is improved and circuit design is simplified.

[0050] According to some embodiments, a first converter 111 is connected to row input-output terminals of a plurality of rows of a first memory array 101 and row input-output terminals of a plurality of rows of a second memory array 102, and is configured to: in response to an output from the first memory array 101 to the second memory array 102, for any row of the first memory array 101, convert the output signal of the row input-output terminal of any row of the first memory array 101 into an input signal of the corresponding row of the second memory array 102, and input the input signal of the corresponding row of the second memory array 102 to the row input-output terminal of the corresponding row of the second memory array 102, wherein the corresponding row of the second memory array 102 is the row of the second memory array 102 corresponding to any row of the first memory array 101.

[0051] According to some embodiments, the corresponding row of the second memory array 102 is the row in the second memory array 102 with the same row number as the row of the first memory array 101. For example, the i-th row of the first memory array 101 corresponds to the i-th row of the second memory array 102.

[0052] According to some embodiments, as will be described in further detail below, the first converter 111 includes an analog-to-digital converter, a digital-to-analog converter, and a multiplexer, wherein the analog-to-digital converter receives an analog output signal from the first memory array 101 and converts it into a digital intermediate signal, while the digital-to-analog converter converts the digital intermediate signal into an analog input signal provided to the second memory array 102. According to some embodiments, the first converter 111 may also include other components, such as a current-to-voltage converter that converts the output current of the first memory array into a voltage, and / or a voltage-to-current converter that converts the output voltage of the first memory array into a current.

[0053] According to some embodiments, the first converter 111 is further configured to: in response to the second memory array 102 outputting to the first memory array 101, for any row of the second memory array 102, convert the output signal of the row input-output terminal of any row into the input signal of the corresponding row of the first memory array 101, and input the input signal of the corresponding row of the first memory array 101 to the row input-output terminal of the corresponding row of the first memory array 101, wherein the corresponding row of the first memory array 101 is the row of the first memory array 101 corresponding to any row of the second memory array 102.

[0054] According to some embodiments, the operation mode of the in-memory computing circuit 100 determines whether the first memory array 101 outputs to the second memory array 102. For example, when the in-memory computing circuit 100 is in the forward operation mode, the first memory array 101 outputs to the second memory array 102. For example, the calculation result performed by the first memory array 101 is used as the input data of the second memory array 102. As another example, when the in-memory computing circuit 100 is in the reverse operation mode, the second memory array 102 outputs to the first memory array 101. For example, the calculation result performed by the second memory array 102 is used as the input data of the first memory array 101.

[0055] According to the embodiments described herein, when using the in-memory computing circuit 100 to perform calculations in different modes, such as forward calculations output from the first memory array 101 to the second memory array 102 and reverse calculations output from the second memory array 102 to the first memory array 101, it is not necessary to change the circuit structure of the first memory array 101 and the second memory array 102 used to perform the calculations. Instead, it is only necessary to control the converter 111 to change the signal flow direction, thereby improving the utilization rate of the in-memory computing circuit.

[0056] Figure 4 shows a schematic diagram of a memory computing circuit 400 according to an exemplary embodiment of the present disclosure. According to some embodiments, the first memory array 401, the second memory array 402, and the first converter 411 in the memory computing circuit 400 may be the same as or similar to the first memory array 101, the second memory array 102, and the first converter 111 in the memory computing circuit 100 described with reference to Figure 1.

[0057] According to some embodiments, at least two memory arrays in the memory computing circuit 400 further include a third memory array 403. For simplicity, FIG4 does not show the specific structure of memory arrays 401-403. It should be understood that the structure of the third memory array 403 may be the same as or similar to that of the memory array 300 described with reference to FIG3A, FIG3B, FIG3C or FIG3D.

[0058] According to some embodiments, at least one converter further includes a second converter 412 connected to column input-output terminals of a plurality of columns of a second memory array 402 and column input-output terminals of a plurality of columns of a third memory array 403, and configured to: in response to an output from a first memory array 401 to a second memory array 402, for any column of the second memory array 402, convert the output signal of the column input-output terminal of that column into an input signal of the corresponding column of the third memory array 403, and input the input signal of the corresponding column of the third memory array 403 to the column input-output terminal of the corresponding column of the third memory array 403, wherein the corresponding column of the third memory array 403 is the column of the third memory array 403 corresponding to any column of the second memory array 402. According to embodiments as described in this disclosure, the second converter 412 controls the second memory array 402 to further output to the third memory array 403 for forward computation.

[0059] According to the embodiments described herein, by using memory arrays with different column input / output configurations, i.e., by coupling the memory array of column outputs to the memory array of column inputs via a converter, computational efficiency is improved and circuit design is simplified without the need for a separate component for performing matrix transpose.

[0060] According to some embodiments, the second converter 412 is further configured to: in response to the second memory array 402 outputting to the first memory array 401, for any column of the third memory array 403, convert the output signal of the column input-output terminal of any column into the input signal of the corresponding column of the second memory array 402, and input the input signal of the corresponding column of the second memory array 402 to the column input-output terminal of the corresponding column of the second memory array 402, wherein the corresponding column of the second memory array 402 is the column of the second memory array 402 corresponding to any column of the third memory array 403. According to the embodiments described in this disclosure, the second converter 412 controls the third memory array 403 to output to the second memory array 402 for reverse computation.

[0061] According to the embodiments described herein, when using the in-memory computing circuit 400 to perform calculations in different modes, such as forward calculations from the first memory array 401 to the third memory array 403 and reverse calculations from the third memory array 403 to the first memory array 401, it is not necessary to change the circuit structure of the first memory array 401, the second memory array 402, and the third memory array 403 used to perform the calculations. Instead, it is only necessary to control the converters 411 and 412 to change the signal flow direction, thereby improving the utilization rate of the in-memory computing circuit.

[0062] Figure 5 shows a schematic diagram of a memory-based computing circuit 500 according to an exemplary embodiment of the present disclosure. According to some embodiments, the first memory array 501, the second memory array 502, and the first converter 511 in the memory-based computing circuit 500 may be the same as or similar to the first memory array 101, the second memory array 102, and the first converter 111 in the memory-based computing circuit 100 described with reference to Figure 1, respectively. Furthermore, the third memory array 503 and the second converter 512 in the memory-based computing circuit 500 may be the same as or similar to the third memory array 403 and the second converter 412 in the memory-based computing circuit 400 described with reference to Figure 4, respectively.

[0063] According to some embodiments, at least two memory arrays in the memory computing circuit 500 also include a fourth memory array 504. For simplicity, FIG5 does not show the specific structure of memory arrays 501-504. It should be understood that the structure of the fourth memory array 504 may be the same as or similar to that of the memory array 300 described with reference to FIG3A, FIG3B, FIG3C or FIG3D.

[0064] According to some embodiments, at least one converter further includes a third converter 513 and a fourth converter 514. According to some embodiments, the third converter 513 is connected to row input-output terminals of a plurality of rows of the third memory array 503 and row input-output terminals of a plurality of rows of the fourth memory array 504, and is configured to: in response to an output from the first memory array 501 to the second memory array 502, for any row of the third memory array 503, convert the output signal of the row input-output terminal of any row into an input signal of the corresponding row of the fourth memory array 504, and input the input signal of the corresponding row of the fourth memory array 504 to the row input-output terminal of the corresponding row of the fourth memory array 504, wherein the corresponding row of the fourth memory array 504 is the row of the fourth memory array 504 corresponding to any row of the third memory array 503.

[0065] According to some embodiments, a fourth converter 514 is connected to column input-output terminals of a plurality of columns of a fourth memory array 504 and column input-output terminals of a plurality of columns of a first memory array 501, and is configured to: in response to an output from the first memory array 501 to a second memory array 502, for any column of the fourth memory array 504, convert the output signal of the column input-output terminal of any column into an input signal of the corresponding column of the first memory array 501, and input the input signal of the corresponding column of the first memory array 501 to the column input-output terminal of the corresponding column of the first memory array 501, wherein the corresponding column of the first memory array 501 is the column of the first memory array 501 corresponding to any column of the fourth memory array 504.

[0066] According to the embodiments disclosed herein, the third converter 513 controls the third memory array 503 to further output to the fourth memory array 504, and the fourth converter 514 controls the fourth memory array 504 to further output to the first memory array 501 for forward calculation.

[0067] According to some embodiments, the third converter 513 is further configured to: in response to the second memory array 502 outputting to the first memory array 501, for any row of the fourth memory array 504, convert the output signal of the row input-output terminal of any row into the input signal of the corresponding row of the third memory array 503, and input the input signal of the corresponding row of the third memory array 503 to the row input-output terminal of the corresponding row of the third memory array 503, wherein the corresponding row of the third memory array 503 is the row of the third memory array 503 corresponding to any row of the fourth memory array 504.

[0068] According to some embodiments, the fourth converter 514 is further configured to: in response to the second memory array 502 outputting to the first memory array 501, for any column of the first memory array 501, convert the output signal of the column input-output terminal of any column into the input signal of the corresponding column of the fourth memory array 504, and input the input signal of the corresponding column of the fourth memory array 504 to the column input-output terminal of the corresponding column of the fourth memory array 504, wherein the corresponding column of the fourth memory array 504 is the column of the fourth memory array 504 corresponding to any column of the first memory array 501.

[0069] According to an embodiment of the present disclosure, the third converter 513 controls the fourth memory array 504 to output to the third memory array 503, and the fourth converter 514 controls the first memory array 501 to output to the fourth memory array 504 for reverse calculation.

[0070] According to the embodiments described herein, by using memory arrays with different row input / output configurations and different column input / output configurations, i.e., by coupling the column output memory array with the column input memory array via a converter, without the need for a separate component for performing matrix transpose, computational efficiency is improved and circuit design is simplified.

[0071] According to the embodiments described herein, when using the in-memory computing circuit 500 to perform calculations in different modes, such as forward calculations from the first memory array 501 to the fourth memory array 504 and reverse calculations from the fourth memory array 504 to the first memory array 501, there is no need to change the circuit structure of the first memory array 501, the second memory array 502, the third memory array 503, and the fourth memory array 504 used to perform the calculations. Instead, only the converters 511-514 need to be controlled to change the signal flow direction, thereby improving the utilization rate of the in-memory computing circuit.

[0072] Figure 6 shows a schematic diagram of a converter 600 in a memory computing circuit according to an exemplary embodiment of the present disclosure. According to some embodiments, the converter 600 may be the same as or similar to the converter 111 described with reference to FIG1, the converters 411-412 described with reference to FIG4, and the converters 511-514 described with reference to FIG5.

[0073] According to some embodiments, converter 600 includes: an analog-to-digital converter 601 configured to generate a digital output signal of the analog-to-digital converter 601 based on the output signal of one of the two memory arrays connected to the converter 600; a digital-to-analog converter 602 configured to generate an analog output signal of the converter 600 and output the analog output signal to the other of the two memory arrays connected to the converter 600; and a multiplexer 603 configured to control the analog-to-digital converter 601 to receive the output signal of one of the two memory arrays connected to the converter 600, and to control the digital-to-analog converter 602 to output the analog output signal of the converter 600 to the other of the two memory arrays connected to the converter.

[0074] According to some embodiments, converter 600 may further include other components, such as a current-to-voltage converter for converting the received output current of the memory array into a voltage. According to some embodiments, converter 600 also includes intermediate circuitry between analog-to-digital converter 601 and digital-to-analog converter 602, wherein analog-to-digital converter 601 outputs a generated digital output signal to the intermediate circuitry, the intermediate circuitry generates an intermediate signal based on the digital output signal from analog-to-digital converter 601, and digital-to-analog converter 602 generates an analog output signal from converter 600 based on the received intermediate signal from the intermediate circuitry.

[0075] According to embodiments described in this disclosure, the direction of signal flow in a memory circuit can be controlled by a converter including a multiplexer.

[0076] Figure 7 illustrates a schematic diagram of a memory-based circuit 500 performing forward computation according to an exemplary embodiment of the present disclosure. According to some embodiments, the memory-based circuit 500 in Figure 7 may be the same as or similar to the memory-based circuit described with reference to Figure 5, the only difference being that Figure 7 shows the internal structure of converters 511-514. It should be understood that, for simplicity, Figure 7 only shows the analog-to-digital converters and digital-to-analog converters of converters 511-514, omitting the multiplexer; however, in practice, converters 511-514 include a multiplexer to control the direction of signal flow.

[0077] According to some embodiments, the first analog-to-digital converter 5111 in the first converter 511 receives the output signal from the first memory array 501, and the first digital-to-analog converter 5112 generates an analog output signal and outputs the generated analog output signal to the second memory array 502.

[0078] According to some embodiments, the second analog-to-digital converter 5121 in the second converter 512 receives the output signal from the second memory array 502, and the second digital-to-analog converter 5122 generates an analog output signal and outputs the generated analog output signal to the third memory array 503.

[0079] According to some embodiments, the third analog-to-digital converter 5131 in the third converter 513 receives the output signal from the third memory array 503, and the third digital-to-analog converter 5132 generates an analog output signal and outputs the generated analog output signal to the fourth memory array 504.

[0080] According to some embodiments, the fourth analog-to-digital converter 5141 in the fourth converter 514 receives the output signal from the fourth memory array 504, and the fourth digital-to-analog converter 5142 generates an analog output signal and outputs the generated analog output signal to the first memory array 501.

[0081] Figure 8 illustrates a schematic diagram of the in-memory circuit 500 performing reverse computation according to an exemplary embodiment of the present disclosure. According to some embodiments, the in-memory circuit 500 in Figure 8 may be the same as or similar to the in-memory circuit described with reference to Figure 5, the only difference being that Figure 8 shows the internal structure of converters 511-514. It should be understood that, for simplicity, only the analog-to-digital converters and digital-to-analog converters of converters 511-514 are shown in Figure 8, while the multiplexer is omitted. However, in practice, converters 511-514 may include a multiplexer to control the direction of signal flow.

[0082] According to some embodiments, the first analog-to-digital converter 5111 in the first converter 511 receives the output signal from the second memory array 502, and the first digital-to-analog converter 5112 generates an analog output signal and outputs the generated analog output signal to the first memory array 501.

[0083] According to some embodiments, the second analog-to-digital converter 5121 in the second converter 512 receives the output signal from the third memory array 503, and the second digital-to-analog converter 5122 generates an analog output signal and outputs the generated analog output signal to the second memory array 502.

[0084] According to some embodiments, the third analog-to-digital converter 5131 in the third converter 513 receives the output signal from the fourth memory array 504, and the third digital-to-analog converter 5132 generates an analog output signal and outputs the generated analog output signal to the third memory array 503.

[0085] According to some embodiments, the fourth analog-to-digital converter 5141 in the fourth converter 514 receives the output signal from the first memory array 501, and the fourth digital-to-analog converter 5142 generates an analog output signal and outputs the generated analog output signal to the fourth memory array 504.

[0086] According to some embodiments, the first transistor is a silicon transistor (e.g., a complementary metal-oxide-semiconductor (CMOS) transistor), and the second transistor is an indium gallium zinc oxide (IGZO) transistor. According to the embodiments described in this disclosure, since IGZO transistors have good leakage current performance, using IGZO transistors as write transistors can better prevent memory cell leakage (e.g., leakage of storage capacitance or parasitic capacitance connected to the source or drain terminals of the IGZO transistor). Furthermore, since the gate of a silicon transistor is typically oxide, there is not much leakage current, and using a silicon transistor as a read transistor will not cause excessive memory cell leakage (e.g., leakage of storage capacitance or parasitic capacitance).

[0087] According to other embodiments, the first transistor may also be configured as an IGZO transistor to improve write speed.

[0088] According to some embodiments, the in-memory computing circuit may also include programming circuitry to control the process of writing to the memory array in the in-memory computing circuit.

[0089] Figure 9 shows a flowchart of a method 900 for controlling a memory circuit (e.g., memory circuit 100 described with reference to Figure 1, memory circuit 400 described with reference to Figure 4, and memory circuit 500 described with reference to Figure 5) according to an exemplary embodiment of the present disclosure. According to some embodiments, features and / or technical effects of the memory circuits and their components described above with reference to Figures 1-8 can be applied accordingly to method 900, and are therefore omitted here. As shown in Figure 9, method 900 includes:

[0090] Step S901: In response to the first memory array outputting to the second memory array, input signal corresponding to that column is input to the column input-output terminal of each column of the first memory array;

[0091] Step S902: For any row of the first memory array, convert the output signal of the row input-output terminal of any row into the input signal of the corresponding row of the second memory array; and

[0092] Step S903: Input the input signal of the corresponding row of the second memory array to the row input-output terminal of the corresponding row of the second memory array, wherein the corresponding row of the second memory array is the row of the second memory array corresponding to any row of the first memory array.

[0093] According to some embodiments, the method described in this disclosure further includes: in response to the second memory array outputting to the first memory array, inputting an input signal corresponding to the column to the column input-output terminal of each column of the second memory array; for any row of the second memory array, converting the output signal of the row input-output terminal of any row into an input signal of the corresponding row of the first memory array; and inputting the input signal of the corresponding row of the first memory array to the row input-output terminal of the corresponding row of the first memory array, wherein the corresponding row of the first memory array is the row of the first memory array corresponding to any row of the second memory array.

[0094] According to some embodiments, at least two memory arrays further include a third memory array, and at least one converter further includes a second converter connected to column input-output terminals of a plurality of columns of the second memory array and column input-output terminals of a plurality of columns of the third memory array. The method as disclosed herein further includes: in response to the first memory array outputting to the second memory array, for any column of the second memory array, converting the output signal of the column input-output terminal of any column of the second memory array into an input signal of the corresponding column of the third memory array; and inputting the input signal of the corresponding column of the third memory array to the column input-output terminal of the corresponding column of the third memory array, wherein the corresponding column of the third memory array is the column of the third memory array corresponding to any column of the second memory array.

[0095] According to some embodiments, the method described in this disclosure further includes: in response to the second memory array outputting to the first memory array, inputting an input signal corresponding to the row to the row input-output terminal of each row of the third memory array; for any column of the third memory array, converting the output signal of the column input-output terminal of any column into an input signal of the corresponding column of the second memory array; and inputting the input signal of the corresponding column of the second memory array to the column input-output terminal of the corresponding column of the second memory array, wherein the corresponding column of the second memory array is the column of the second memory array corresponding to any column of the third memory array.

[0096] According to some embodiments, at least two memory arrays further include a fourth memory array, and at least one converter further includes a third converter and a fourth converter. The third converter is connected to row input-output terminals of a plurality of rows of the third memory array and row input-output terminals of a plurality of rows of the fourth memory array. The fourth converter is connected to column input-output terminals of a plurality of columns of the fourth memory array and column input-output terminals of a plurality of columns of the first memory array. Furthermore, the method as described in this disclosure further includes: in response to the first memory array outputting to the second memory array, for any row of the third memory array, converting the output signal of the row input-output terminal of any row into an input signal of the corresponding row of the fourth memory array; and inputting the fourth memory array signal to the row input-output terminal of the corresponding row of the fourth memory array. The input signal for the corresponding row of the memory array, wherein the corresponding row of the fourth memory array is the row of the fourth memory array corresponding to any row of the third memory array, and in response to the first memory array being in output mode, inputting the input signal corresponding to the column to the column input-output terminal of each column of the first memory array includes: in response to the first memory array outputting to the second memory array, for any column of the fourth memory array, converting the output signal of the column input-output terminal of any column into the input signal of the corresponding column of the first memory array; and inputting the input signal of the corresponding column of the first memory array to the column input-output terminal of the corresponding column of the first memory array, wherein the corresponding column of the first memory array is the column of the first memory array corresponding to any column of the fourth memory array.

[0097] According to some embodiments, the method described in this disclosure further includes: in response to the second memory array outputting to the first memory array, for any column of the first memory array, converting the output signal of the column input-output terminal of any column into the input signal of the corresponding column of the fourth memory array, and inputting the input signal of the corresponding column of the fourth memory array to the column input-output terminal of the corresponding column of the fourth memory array, wherein the corresponding column of the fourth memory array is the column of the fourth memory array corresponding to any column of the first memory array; and in response to the second memory array outputting to the first memory array, converting the output signal of the column input-output terminal of any column of the second memory array into the input signal of the corresponding column of the third memory array for any column of the third memory array includes: in response to the second memory array outputting to the first memory array, for any row of the fourth memory array, converting the output signal of the row input-output terminal of any row into the input signal of the corresponding row of the third memory array; and inputting the input signal of the corresponding row of the third memory array to the row input-output terminal of the corresponding row of the third memory array, wherein the corresponding row of the third memory array is the row of the third memory array corresponding to any row of the fourth memory array.

[0098] Figure 10 shows a schematic diagram of a chip 1000 according to an exemplary embodiment of the present disclosure. According to some embodiments, the chip 1000 includes a memory computing circuit 1001 as described in the present disclosure.

[0099] The memory computing circuit and its control method described in this disclosure, as well as the chip, can be used in terminals such as computers, mobile phones, and tablet computers to perform related calculations. Other essential components of the memory computing circuit are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the present invention.

[0100] By adjusting the voltage at the gate terminal of the first transistor in the memory cell, each memory cell is regarded as a variable equivalent analog weight, which is equivalent to analog matrix data. Furthermore, by applying analog voltage to the memory cell, matrix multiplication is achieved. The circuit structure is simple, the number of components is small, the response speed is fast, and the power consumption is low, which greatly reduces the overhead caused by analog-to-digital conversion, digital-to-analog conversion, and data transmission, and effectively improves the processing performance of the memory computing circuit.

[0101] Furthermore, the memory array provided by the present invention can be used as a dynamic random access memory (DRAM) when it is in an idle state, thereby enabling the reuse of electrical components, improving component utilization efficiency, and saving hardware costs of integrated circuits.

[0102] The storage device provided by this invention integrates in-memory computing circuitry, enabling calculations to be performed directly within the storage device. This achieves in-memory computing integration, eliminating the need for data transfer between the memory and the processor, thereby improving processing performance and reducing power consumption and cost.

[0103] While embodiments or examples of this disclosure have been described with reference to the accompanying drawings, it should be understood that the methods, systems, and devices described above are merely exemplary embodiments or examples, and the scope of the invention is not limited by these embodiments or examples, but only by the granted claims and their equivalents. Various elements in the embodiments or examples may be omitted or replaced by their equivalents. Furthermore, the steps may be performed in a different order than that described in this disclosure. Further, various elements in the embodiments or examples may be combined in various ways. Importantly, as the technology evolves, many elements described herein can be replaced by equivalents that appear after this disclosure.

Claims

1. A compute-in-memory circuit, comprising: at least two memory arrays, including a first memory array and a second memory array, wherein, for each of the at least two memory arrays, each memory array includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell includes a first transistor and a second transistor, in each memory cell, a gate terminal of the first transistor is connected to one of a source terminal and a drain terminal of the second transistor, and each memory cell is configured to store a weight corresponding to that memory cell, and for each memory array, one of the drain terminal and the source terminal of the first transistor in the memory cells in a same row is connected to a row input-output terminal corresponding to that row, and the other of the drain terminal and the source terminal of the first transistor in the memory cells in a same column is connected to a column input-output terminal corresponding to that column; and at least one converter, each converter connected to two memory arrays of the at least two memory arrays, the at least one converter includes a first converter connected to row input-output terminals of a plurality of rows of the first memory array and row input-output terminals of a plurality of rows of the second memory array, and configured to, when the compute-in-memory circuit is in a forward computation mode, for any row of the first memory array, convert an output signal of the row input-output terminal of the any row to an input signal of a corresponding row of the second memory array, and input the input signal of the corresponding row of the second memory array to the row input-output terminal of the corresponding row of the second memory array, wherein the corresponding row of the second memory array is a row of the second memory array corresponding to the any row of the first memory array.

2. The compute-in-memory circuit of claim 1, wherein, the first converter is further configured to: when the compute-in-memory circuit is in a reverse computation mode, for any row of the second memory array, convert an output signal of the row input-output terminal of the any row to an input signal of a corresponding row of the first memory array, and input the input signal of the corresponding row of the first memory array to the row input-output terminal of the corresponding row of the first memory array, wherein the corresponding row of the first memory array is a row of the first memory array corresponding to the any row of the second memory array.

3. The compute-in-memory circuit of claim 1 or 2, wherein, the at least two memory arrays further include a third memory array, and the first converter is further configured to: when the compute-in-memory circuit is in a forward computation mode, for any row of the first memory array, convert an output signal of the row input-output terminal of the any row to an input signal of a corresponding row of the third memory array, and input the input signal of the corresponding row of the third memory array to the row input-output terminal of the corresponding row of the third memory array, wherein the corresponding row of the third memory array is a row of the third memory array corresponding to the any row of the first memory array. The at least one converter further includes a second converter connected to column input-output terminals of a plurality of columns of the second memory array and column input-output terminals of a plurality of columns of the third memory array and configured to, when the memory-compute circuit is in the forward mode of operation, for any column of the second memory array, convert an output signal of the column input-output terminal of the any column to an input signal of a corresponding column of the third memory array and input the input signal of the corresponding column of the third memory array to the column input-output terminal of the corresponding column of the third memory array, wherein the corresponding column of the third memory array is a column of the third memory array corresponding to the any column of the second memory array.

4. The compute-in-memory circuit of any one of claims 1-3, wherein, The at least two memory arrays further include a third memory array, and The at least one converter further includes a second converter further configured to, when the memory-compute circuit is in the reverse mode of operation, for any column of the third memory array, convert an output signal of a column input-output terminal of the any column to an input signal of a corresponding column of the second memory array and input the input signal of the corresponding column of the second memory array to the column input-output terminal of the corresponding column of the second memory array, wherein the corresponding column of the second memory array is a column of the second memory array corresponding to the any column of the third memory array.

5. The compute-in-memory circuit of claim 3 or 4, wherein, The at least two memory arrays further include a fourth memory array, and The at least one converter further includes a third converter and a fourth converter, wherein The third converter is connected to row input-output terminals of a plurality of rows of the third memory array and row input-output terminals of a plurality of rows of the fourth memory array and configured to, when the memory-compute circuit is in the forward mode of operation, for any row of the third memory array, convert an output signal of the row input-output terminal of the any row to an input signal of a corresponding row of the fourth memory array and input the input signal of the corresponding row of the fourth memory array to the row input-output terminal of the corresponding row of the fourth memory array, wherein the corresponding row of the fourth memory array is a row of the fourth memory array corresponding to the any row of the third memory array, and The fourth converter is connected to column input-output terminals of a plurality of columns of the fourth memory array and column input-output terminals of a plurality of columns of the first memory array and configured to, when the memory-compute circuit is in the forward mode of operation, for any column of the fourth memory array, convert an output signal of the column input-output terminal of the any column to an input signal of a corresponding column of the first memory array and input the input signal of the corresponding column of the first memory array to the column input-output terminal of the corresponding column of the first memory array, wherein the corresponding column of the first memory array is a column of the first memory array corresponding to the any column of the fourth memory array.

6. The compute-in-memory circuit of any one of claims 3-5, wherein, The at least two memory arrays further include a fourth memory array, and The at least one converter further includes a third converter and a fourth converter, wherein The third converter is connected to row input-output terminals of a plurality of rows of the third memory array and row input-output terminals of a plurality of rows of the fourth memory array and configured to, when the memory-compute circuit is in the forward mode of operation, for any row of the third memory array, convert an output signal of the row input-output terminal of the any row to an input signal of a corresponding row of the fourth memory array and input the input signal of the corresponding row of the fourth memory array to the row input-output terminal of the corresponding row of the fourth memory array, wherein the corresponding row of the fourth memory array is a row of the fourth memory array corresponding to the any row of the third memory array, and The fourth converter is connected to column input-output terminals of a plurality of columns of the fourth memory array and column input-output terminals of a plurality of columns of the first memory array and configured to, when the memory-compute circuit is in the forward mode of operation, for any column of the fourth memory array, convert an output signal of the column input-output terminal of the any column to an input signal of a corresponding column of the first memory array and input the input signal of the corresponding column of the first memory array to the column input-output terminal of the corresponding column of the first memory array, wherein the corresponding column of the first memory array is a column of the first memory array corresponding to the any column of the fourth memory array. The at least one converter further comprises a third converter and a fourth converter, wherein the third converter is connected to row input-output terminals of a plurality of rows of the third memory array and row input-output terminals of a plurality of rows of the fourth memory array, and is configured to: when the memory-compute circuit is in the reverse operation mode, for any row of the fourth memory array, convert an output signal of the row input-output terminal of the any row into an input signal of a corresponding row of the third memory array, and input the input signal of the corresponding row of the third memory array to the row input-output terminal of the corresponding row of the third memory array, wherein the corresponding row of the third memory array is a row of the third memory array corresponding to the any row of the fourth memory array, and the fourth converter is connected to column input-output terminals of a plurality of columns of the fourth memory array and column input-output terminals of a plurality of columns of the first memory array, and is configured to: when the memory-compute circuit is in the reverse operation mode, for any column of the first memory array, convert an output signal of the column input-output terminal of the any column into an input signal of a corresponding column of the fourth memory array, and input the input signal of the corresponding column of the fourth memory array to the column input-output terminal of the corresponding column of the fourth memory array, wherein the corresponding column of the fourth memory array is a column of the fourth memory array corresponding to the any column of the first memory array.

7. The compute-in-memory circuit of any one of claims 1-6, wherein, Each of the at least one converter comprises: an analog-to-digital converter configured to generate a digital output signal of the analog-to-digital converter based on an output signal of one of the two memory arrays connected to the converter; a digital-to-analog converter configured to generate an analog output signal of the converter and output the analog output signal to the other of the two memory arrays connected to the converter; and a multiplexer configured to control the analog-to-digital converter to receive the output signal of the one of the two memory arrays connected to the converter, and control the digital-to-analog converter to output the analog output signal of the converter to the other of the two memory arrays connected to the converter.

8. The compute-in-memory circuit of any one of claims 1-7, wherein, Each memory cell further comprises a storage capacitor, a first terminal of the storage capacitor is connected to a gate terminal of the first transistor of the memory cell, and a second terminal of the storage capacitor is connected to the ground, wherein the weight stored by each memory cell is determined based on a charge stored by the storage capacitor in the memory cell.

9. The compute-in-memory circuit of any one of claims 1-7, wherein, In each memory cell, there is a parasitic capacitor between the gate terminal of the first transistor and the ground, and the weight stored by each memory cell is determined based on a charge stored by the parasitic capacitor in the memory cell.

10. The compute-in-memory circuit of any one of claims 1-9, wherein, The first transistor is a silicon transistor, and the second transistor is an indium gallium zinc oxide transistor.

11. A control method for controlling the compute-in-memory circuit of any one of claims 1-10, the control method comprising: when the compute-in-memory circuit is in a forward mode of operation, inputting to the column input-output terminals of each column of the first memory array an input signal corresponding to the column; for any row of the first memory array, converting an output signal of the row input-output terminals of the any row to an input signal of a corresponding row of the second memory array; and inputting to the row input-output terminals of the corresponding row of the second memory array the input signal of the corresponding row of the second memory array, wherein the corresponding row of the second memory array is a row of the second memory array corresponding to the any row of the first memory array.

12. The control method of claim 11, further comprising: when the compute-in-memory circuit is in a reverse mode of operation, inputting to the column input-output terminals of each column of the second memory array an input signal corresponding to the column; for any row of the second memory array, converting an output signal of the row input-output terminals of the any row to an input signal of a corresponding row of the first memory array; and inputting to the row input-output terminals of the corresponding row of the first memory array the input signal of the corresponding row of the first memory array, wherein the corresponding row of the first memory array is a row of the first memory array corresponding to the any row of the second memory array.

13. The control method according to claim 11 or 12, wherein the at least two memory arrays further comprise a third memory array, and the at least one converter further comprises a second converter connected to the column input-output terminals of a plurality of columns of the second memory array and the column input-output terminals of a plurality of columns of the third memory array, the control method further comprising: when the compute-in-memory circuit is in the forward mode of operation, for any column of the second memory array, converting an output signal of the column input-output terminals of the any column to an input signal of a corresponding column of the third memory array; and inputting to the column input-output terminals of the corresponding column of the third memory array the input signal of the corresponding column of the third memory array, wherein the corresponding column of the third memory array is a column of the third memory array corresponding to the any column of the second memory array.

14. The control method according to any one of claims 11 to 13, wherein the at least two memory arrays further comprise a third memory array, and the at least one converter further comprises a second converter connected to the column input-output terminals of a plurality of columns of the second memory array and the column input-output terminals of a plurality of columns of the third memory array, the control method further comprising: when the compute-in-memory circuit is in the reverse mode of operation, inputting to the row input-output terminals of each row of the third memory array an input signal corresponding to the row; for any column of the third memory array, converting an output signal of the column input-output terminals of the any column to an input signal of a corresponding column of the second memory array; and inputting to the row input-output terminals of the corresponding row of the second memory array the input signal of the corresponding row of the second memory array, wherein the corresponding row of the second memory array is a row of the second memory array corresponding to the any row of the first memory array. inputting, to column input-output terminals of corresponding columns of the second memory array, input signals of the corresponding columns of the second memory array, wherein the corresponding columns of the second memory array are columns of the second memory array that correspond to any column of the third memory array.

15. The control method according to claim 13 or 14, wherein The at least two memory arrays further include a fourth memory array, the at least one translator further includes a third translator and a fourth translator, the third translator is connected to row input-output terminals of a plurality of rows of the third memory array and row input-output terminals of a plurality of rows of the fourth memory array, the fourth translator is connected to column input-output terminals of a plurality of columns of the fourth memory array and column input-output terminals of a plurality of columns of the first memory array, and, The control method further includes: when the memory-compute circuit is in the forward operation mode, for any row of the third memory array, converting output signals of row input-output terminals of the any row into input signals of a corresponding row of the fourth memory array; and inputting, to row input-output terminals of the corresponding row of the fourth memory array, the input signals of the corresponding row of the fourth memory array, wherein the corresponding row of the fourth memory array is a row of the fourth memory array that corresponds to the any row of the third memory array, and The inputting, to column input-output terminals of each column of the first memory array, input signals corresponding to the column includes: for any column of the fourth memory array, converting output signals of column input-output terminals of the any column into input signals of a corresponding column of the first memory array; and inputting, to column input-output terminals of the corresponding column of the first memory array, the input signals of the corresponding column of the first memory array, wherein the corresponding column of the first memory array is a column of the first memory array that corresponds to the any column of the fourth memory array. 16.The control method of any one of claims 13 to 15, the at least two memory arrays further include a fourth memory array, the at least one translator further includes a third translator and a fourth translator, the third translator is connected to row input-output terminals of a plurality of rows of the third memory array and row input-output terminals of a plurality of rows of the fourth memory array, the fourth translator is connected to column input-output terminals of a plurality of columns of the fourth memory array and column input-output terminals of a plurality of columns of the first memory array, the control method further includes: when the storage-computation circuit is in the reverse operation mode, for any column of the first memory array, converting an output signal of a column input-output terminal of the any column into an input signal of a corresponding column of the fourth memory array, and inputting the input signal of the corresponding column of the fourth memory array to a column input-output terminal of the corresponding column of the fourth memory array, wherein the corresponding column of the fourth memory array is a column of the fourth memory array corresponding to the any column of the first memory array; for any row of the fourth memory array, converting an output signal of a row input-output terminal of the any row into an input signal of a corresponding row of the third memory array; and inputting the input signal of the corresponding row of the third memory array to a row input-output terminal of the corresponding row of the third memory array, wherein the corresponding row of the third memory array is a row of the third memory array corresponding to the any row of the fourth memory array.

17. A chip comprising the storage-computation circuit according to any one of claims 1-10.

Images